Memory circuit and operating method thereof

Abstract

Embodiments of the invention provide a memory circuit including a first memory cell operable to access through a first access line and a second access line; a first read pass gate transistor and a second read pass gate transistor coupled to the first access line and the second access line, respectively; a first sense amplifier coupled to the first access line and the second access line; a first read enable control circuit configured to generate a first read enable signal based on the clock signal; and a second read enable control circuit configured to generate a second read enable signal. The first read enable signal selectively transitions to a different logic state based on the first sense enable signal. The second read enable signal is configured to activate or deactivate the first and second read pass gate transistors, and the first sense enable signal is set to activate or deactivate the first sense amplifier. The embodiment of the invention also provides an operation method of the memory circuit.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of electronic circuits, and more particularly, to memory circuits and methods of operating the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In large part, the improvement in integration density comes from the repeated reduction of minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0003] An embodiment of the present invention provides a memory circuit, comprising: a first memory cell, which is operably accessed through a first access line and a second access line; a first read pass gate transistor and a second read pass gate transistor, respectively coupled to the first access line and the second access line; a first sense amplifier, coupled to the first access line and the second access line; a first read enable control circuit, configured to generate a first read enable signal based on a clock signal; and a second read enable control circuit, configured to generate a second read enable signal by logically inverting the first read enable signal, wherein the first read enable signal is selectively converted to a different logic state based on the first sense enable signal; wherein the second read enable signal is configured to activate or deactivate the first read pass gate transistor and the second read pass gate transistor, and the first sense enable signal is configured to activate or deactivate the first sense amplifier.

[0004] Another embodiment of the present invention provides a memory circuit, comprising: a memory array comprising a plurality of memory cells; an input / output (I / O) circuit operably coupled to the memory array and physically disposed adjacent to the memory array along a first horizontal direction, wherein the I / O circuit comprises a plurality of read transfer gate circuits and a plurality of sense amplifiers, the read transfer gate circuits being operably coupled to different groups of memory cells, and the sense amplifiers being operably coupled to different groups of memory cells; and a control circuit operably coupled to the memory array and physically disposed adjacent to the I / O circuit along a second horizontal direction perpendicular to the first horizontal direction; wherein the control circuit comprises a global read enable control circuit, and the I / O circuit comprises a plurality of local read enable control circuits, each of the local read enable control circuits being operably coupled to a corresponding one of the plurality of read transfer gate circuits; and wherein the global read enable control circuit is configured to generate a first read enable signal based on a sense enable control signal, and each of the local read enable control circuits is configured to generate a corresponding second read enable signal for a corresponding read transfer gate circuit based on the sense enable control signal.

[0005] Yet another embodiment of the present invention provides a method for operating a memory circuit, comprising: determining a sensing enable control signal according to a transition edge of a clock signal; determining a sensing enable signal after the sensing enable control signal; canceling a global read enable signal in response to the sensing enable control signal being determined; deactivating a read transfer gate circuit by transitioning a local read enable signal from a first logic state to a second logic state after the sensing enable signal is determined; and activating the read transfer gate circuit by transitioning the local read enable signal from the second logic state to the first logic state after the sensing enable signal is deactivated. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 An example block diagram of a memory circuit according to some embodiments is shown.

[0008] Figure 2 According to some embodiments Figure 1 An example schematic diagram of a portion of a memory circuit.

[0009] Figure 3 According to some embodiments Figure 2An example circuit diagram of a portion of a memory circuit is shown in FIG.

[0010] Figure 4 shows the operation according to some embodiments Figure 1 Example waveforms of various signals when using a memory circuit.

[0011] Figure 5 According to some embodiments Figure 1 Another example schematic diagram of a portion of a memory circuit.

[0012] Figure 6 According to some embodiments Figure 5 An example circuit diagram of a portion of a memory circuit is shown in FIG.

[0013] Figure 7 According to some embodiments Figure 5 Another example circuit diagram of the memory circuit portion is shown.

[0014] Figure 8 An example circuit diagram of a sense amplifier according to some embodiments is shown.

[0015] Figure 9 An example flow chart for operating a memory circuit according to some embodiments is shown. DETAILED DESCRIPTION

[0016] The present invention provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another (or more) elements or components as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0018] A static random access memory (SRAM) device is a volatile semiconductor memory that uses a bistable circuit to store data bits. The bistable circuit will maintain the integrity of the stored bit without refreshing. A single SRAM cell is often referred to as a bit cell because a single SRAM cell stores one bit of information, represented by the logic state of two cross-coupled inverters. The memory array includes a plurality of bit cells arranged in rows and columns. In some methods, each bit cell in the memory array includes a connection to a power supply voltage and a connection to a reference voltage. A logic signal on a first access line (e.g., a bit line) controls the reading and writing of the bit cell, and a second access line (e.g., a word line) controls the connection of the bit line to the cross-coupled inverters through a pass-gate. When the pass-gate is in a non-conducting state, the bit cell floats.

[0019] Over the past few decades, the scaling of semiconductor devices (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) has led to continuous improvements in the speed, performance, density, and cost per function of integrated circuits. With this scaling trend, the number of bit cells in an SRAM circuit has grown exponentially, resulting in relatively long connection lines between different components of the SRAM circuit. Generally, these extended connection lines adversely affect the performance (e.g., speed) of the SRAM circuit due to various limited clock paths, such as a bit line precharge path, a write clock path, a word line path, a sense amplifier precharge path, and a read clock path. Among them, the performance of existing SRAM circuits is generally limited by their read clock paths, wherein, with the scaling trend, the contention between a read enable signal configured to enable reading of a data bit stored in a bit cell and a sense enable signal configured to amplify the read data bit appears to become more severe. Therefore, existing SRAM circuits are not entirely satisfactory in some aspects.

[0020] The present disclosure provides various embodiments of a memory circuit including one or more memory arrays (or memory banks), each memory array being operably coupled to a local read enable control circuit. The local read enable control circuit is typically coupled to a global read enable control circuit, and each local read enable control circuit is configured to provide a read enable (READB) signal for activating / deactivating a corresponding read pass gate circuit based on a sense enable (SAE) signal. By directly controlling the local read enable control circuit by the SAE signal, various time margins for distinguishing between read operations and sense operations of the memory circuit can be advantageously optimized. For example, a first time margin (between the pulled-up SAE signal and the pulled-up READB signal) and a second time margin (between the pulled-down SAE signal and the pulled-down READB signal) can be ensured to be greater than a specific threshold. When the first time margin is sufficiently large, it can be ensured that the bit line of the corresponding sense amplifier does not float; and when the second time margin is sufficiently large, it can be ensured that the bit line of the sense amplifier is not disturbed by the bit line precharge circuit. In various embodiments, the memory circuit may include control circuitry and input / output (I / O) circuitry physically disposed next to the memory array. The control circuitry may include a global read enable control circuit, and the I / O circuitry may include a read enable control circuit.

[0021] Figure 1 1 shows an example block diagram of a memory circuit 100 according to various embodiments of the present disclosure. Typically, the memory circuit 100 includes a plurality of SRAM cells. However, the memory cells of the memory circuit 100 may be applicable to other semiconductor memories, including but not limited to dynamic random access memory ("DRAM"), erasable programmable read-only memory ("EPROM"), and electrically erasable programmable read-only memory ("EEPROM"), as well as other read-only memories ("ROM"), random access memories, and flash memories. It should be understood that for the purpose of illustration, Figure 1 The block diagram has been simplified, and thus, the memory circuit 100 may include any of a variety of other components or circuits while remaining within the scope of the present disclosure. For example, the memory circuit 100 may include one or more tracking circuits.

[0022] As shown, the memory circuit 100 includes a plurality of memory banks 102, a plurality of local input / output (LIO) blocks 104, a plurality of local control (LCTRL) blocks 106, a plurality of word line (WL) driver blocks 108, a global control block 110 (GCTRL), and a global input / output (GIO) block 112. Each memory bank 102 may include a plurality of memory arrays, each of which may include a plurality of SRAM cells. Each memory bank 102 may be operably coupled to a corresponding LIO block 104, a corresponding LCTRL block 106, and a corresponding WL driver block 108. Different LIO blocks 104 may be operably coupled to the GIO block 112, and different LCTRL blocks 106 and different WL driver blocks 108 may be operably connected to the GCTRL block 110.

[0023] For example, the GCTRL block 110 may include a clock generator (or two clock generators, one for read operations and the other for write operations) to generate an internal clock (ICLK) signal. The ICLK signal can control the reading and writing of the SRAM cells of the memory bank 102. The GCTRL block 110 may include at least one X-bit address decoder and one Y-bit address decoder, which are configured to decode the first part and the second part of the address, respectively. The first part of the address can be sent to the LIO block 104 through the LCTRL block 106 after decoding to identify one or more bit lines (BL) of the memory bank 102; and the second part of the address can be sent to the WL driver block 108 after being decoded to determine (assert) one or more word lines (WL) of the memory bank 102.

[0024] In various embodiments of the present disclosure, the LCTRL block 106 may include a global read enable control circuit configured to generate a global read enable (READ) signal based on an ICLK signal (provided by the GCTRL block 110). The LIO block 104 may include a plurality of local read enable control circuits, each operably coupled to a corresponding SRAM cell group of a corresponding memory bank 102. The local read enable control circuit (of the LIO block 104) may generally receive a READ signal (provided by the LCTRL block 106) to generate a corresponding local read enable (READB) signal for the corresponding SRAM cell group. Each local read enable control circuit may also be controlled by a sense enable (SAE) signal generated by the LCTRL block 106. The READB signal may be configured to activate / deactivate at least one read transmission gate circuit coupled to the corresponding SRAM cell group, and the SAE signal may be configured to activate / deactivate at least one sense amplifier circuit coupled to the corresponding group of SRAM cells. The local READB signal is logically opposite to the global READ signal and may be selectively grounded based on the SAE signal. Advantageously, it can be ensured that the time margin between the reading and sensing operations is sufficiently large. The details of these signals will be discussed further below.

[0025] In various embodiments, such as Figure 1 As shown in the example of FIG, each memory bank 102 may have a corresponding LIO block 104 disposed adjacent thereto along the Y direction, and its corresponding LCTRL block 106 may be positioned adjacent to the LIO block 104 along the X direction. Furthermore, the GIO block 112 may be spaced apart from the memory bank 102 along the Y direction, with at least one LIO block 104 interposed between the GIO block and the memory bank 102; and the GCTRL block 110 may be disposed adjacent to the GIO block 112 along the X direction. However, it should be understood that the arrangement of the blocks of the memory circuit 100 may be configured differently while remaining within the scope of the present disclosure.

[0026] Figure 2 1 shows an example schematic diagram of a portion of a memory circuit 100 according to various embodiments of the present disclosure. For example, Figure 2 The schematic diagram includes the GCTRL block 110 and the GIO block 112, as well as a group of SRAM cells 210 of a memory array of a memory bank 102, and corresponding LIO block 104, LCTRL block 106 and WL driver block 108. The group of SRAM cells 210 can be coupled (e.g., through) between a pair of bit lines, such as Figure 2 For clarity, other groups of SRAM cells of the same memory array coupled between BL2 and BLB2, between BL1 and BLB1, and between BL0 and BLB0 are not shown.

[0027] The SRAM cells 210 can be implemented as six-transistor (6T) SRAM cells, respectively. However, the SRAM cells 210 can be implemented as any of a variety of other configurations, such as an eight-transistor (8T) SRAM cell, a ten-transistor (10T) SRAM cell, etc., while still within the scope of the present disclosure. The 6T SRAM cell generally includes a first pass-gate transistor configured to selectively connect a pair of cross-coupled inverters to a first bit line (e.g., BL3), and a second pass-gate transistor configured to selectively connect the cross-coupled inverters to a second bit line (e.g., BLB3). Both the first pass-gate transistor and the second pass-gate transistor are configured to be activated based on a signal provided by a word line (e.g., one of WL0 to WLTOP) to enable access (e.g., reading, writing) of the SRAM cell.

[0028] The GCTRL block 110 may include an X-bit address decoder 220, a write enable latch 222, a clock generator 224, and a Y-bit address decoder 226. The clock generator 224 may receive a clock source (CLK) to provide an internal clock (ICLK) signal to the LCTRL block 106 and the WL driver block 108. The write enable latch 222 may receive a write enable (WE) signal having a logic state that indicates whether a write or read operation is initiated on the SRAM cell 210. For example, when the WE signal is a logic 0, the SRAM cell is configured for reading; when the WE signal is a logic 1, the SRAM cell is configured for writing. The write enable latch 222 may then provide a latched write enable (LWE) signal to the global read enable control circuit 230 included in the LCTRL block 106, which will be discussed below.

[0029] In some embodiments, the X-bit address decoder 220 and the Y-bit address decoder 226 can receive different portions (e.g., different bits) of the address signal, such as A[0:7]. Furthermore, the X-bit address decoder 220 can provide a decoded X signal for identifying one or more selected access lines extending in the X direction (e.g., WL), and the Y-bit address decoder 226 can provide a decoded Y signal for identifying one or more selected access lines extending in the Y direction (e.g., BL). For example, the X-bit address decoder 220 can decode the first portion of the address signal, such as A[3:7], and provide decoded X signals, such as XC[0:3] and XD[0:7], to the WL driver block 108 to identify the corresponding WL. The WL driver block 108 can include a plurality of WL drivers 254 corresponding to WL0 through WLTOP, respectively. The Y bit address decoder 226 can decode the second portion of the address signal (e.g., A[0:2]) and provide the decoded Y signal (e.g., Y[0:3]) to the LCTRL block 106 to select at least one pair of BL / BLB. The decoded Y signal can be logically inverted to YB[0:3] by the inverter of the LCTRL block 106. The YB[0:3] signal can be used to activate at least one pair of Y multiplexers (Y MUX) 262 coupled to the selected BL / BLB pair. In an example where the Y MUX 262 is implemented as a p-type metal oxide semiconductor (PMOS) field effect transistor (FET), when bit YB[3] is set to logic 0 and the other bits YB[0], YB[1], and YB[2] are set to logic 1, the Y MUX 262 connected to BL3 and BLB3, respectively, can be activated, thereby selecting the BL3 and BL23 pairs.

[0030] The LCTRL block 106 may include a sense amplifier enable / sense amplifier precharge bit line (SA / SAPRB) driver 228 and a BL precharge driver 232. In some embodiments, the SA / SAPRB driver 228 may provide different control signals based on the ICLK signal to control (e.g., activate or deactivate) corresponding circuits included in the LIO block 104. Similarly, the BL precharge driver 232 may provide at least one control signal based on the ICLK signal to control (e.g., activate or deactivate) circuits included in the LIO block 104.

[0031] For example, the SA / SAPRB driver 228 is configured to receive an ICLK signal. When the ICLK signal transitions to a different logic state (e.g., logic 1), the SA / SAPRB driver 228 can pull up the sense enable control (SAE_LCTRL) signal and the sense precharge bit line (SAPRB) signal. Therefore, both the SAE_LCTRL signal and the SAPRB signal can follow the ICLK signal. In some embodiments, the SAE_LCTRL signal can propagate through a first inverter to become a sense enable inverted (SAEB) signal, and then propagate through a second inverter to become a sense enable (SAE) signal. The SAE signal can be received by the sense amplifier 244 of the LIO block 104. The sense amplifier 244 (an example implementation of which is shown in FIG. Figure 8 ) can be activated by pulling up the SAE signal. Once activated by the SAE signal (e.g., when the SAE signal is pulled up), the sense amplifier 244 can amplify the latched input value, which is the voltage of one of the read bit lines (e.g., RBL or RBLB) sensed from the corresponding SRAM cell 210 and coupled to the sense amplifier 224. In some embodiments, the SAPRB signal can be received by the sense amplifier precharge (SAPCH) circuit 246 of the LIO block 104. Once activated by the SAPRB signal (e.g., the SAPRB signal is pulled down), which typically occurs before the sense amplifier 244 is activated, the SAPCH circuit 246 can precharge the read bit lines RBL and RBLB to a common mid-range voltage, such as VDD / 2.

[0032] The BL precharge driver 232 is configured to receive the ICLK signal. When the ICLK signal transitions to a different logic state (e.g., a logic 1), the BL precharge driver 232 can pull up the BL precharge inverted (BLPCHB) signal. The BLPCHB signal can be received by the precharge (PRCH) circuit 260 of the LIO block 104. The PRCH circuit 260 can be activated by pulling down the BLPCHB signal. Once activated by the BLPCHB signal (e.g., the BLPCHB signal is pulled down), the PRCH circuit 260 can generally pull up the coupled BL / BLB pair (e.g., Figure 2 BL3 and BLB3 in the example are precharged to VDD.

[0033] According to various embodiments of the present disclosure, the global read enable control circuit 230 may include a NOR logic gate having a first input, a second input, and an output. The first input is configured to receive (couple to) the LWE signal, and the second input is configured to receive (connect to) the SAE_LCTRL signal. Thus, the global read enable control circuit 230 can provide a local READB signal as an XOR of the LWE signal and the SAE_LCTRL signal. In a read or sense operation, the LWE signal can be provided at a logic 0, which makes the global READ signal logically opposite to the SAE_LCTRL signal. As will be discussed below, the global READ signal is received by a local read enable control circuit 242 included in the LIO block 104, which also receives the SAE signal. The local read enable control circuit 242 can logically invert the global READ signal and further adjust the corresponding timing of the rising and falling edges of the local READB signal based on the SAE signal.

[0034] The local READ signal may be received by a read pass gate circuit included in the LIO block 104. In some embodiments, the read pass gate circuit may include a pair of PMOS FETs 250 and 252 configured to selectively couple a selected pair of BL / BLB (e.g., BL3 and BLB3) to the sense amplifier 244. The PMOS FETs 250 and 252, when activated, may couple the selected BL / BLB pair to the sense amplifier 244. Figure 2 In the example of FIG, when PMOS FETs 250 and 252 are activated or turned on, the selected BL / BLB pair on one side of the PMOS FETs 250 and 252 (e.g., their source terminals) can become the RBL / RBLB pair on the other side of the PMOS FETs 250 and 252 (e.g., their drain terminals). The gate terminals of the PMOS FETs 250 and 252 can be commonly coupled to the local READB signal. Therefore, when the local READB signal is at a logic 0, the read pass gate circuit (PMOS FETs 250 and 252) can be activated; and when the local READB signal is at a logic 1, the read pass gate circuit (PMOSFETs 250 and 252) can be deactivated.

[0035] The LIO block 104 may be coupled to a memory bank and may include Figure 2 One or more groups of circuit components (e.g., 240, 244, 246, 250, 252, 260, and 262) shown in FIG. Figure 2, a group 240, 244, 246, 250, 252, 260, and 262 are shown as being operably coupled to a corresponding group of SRAM cells 210 of a first memory array that may belong to a memory bank. In some implementations, other groups of SRAM cells 210 in the same first memory array, coupled to (or through) other BL / BLB pairs (e.g., BL2 / BLB2, BL1 / BLB1, BL0 / BLB0), may have their own PRCH circuits 260, but share the same YMUX 262, read pass gate circuits 250 / 252, SAPCH circuits 246, and sense amplifiers 244. Thus, the LIO block 104 may have other groups of circuit components 240 to 262 that are respectively coupled to other memory arrays of the same memory bank.

[0036] Figure 3 Various embodiments according to the present disclosure are shown Figure 2 An example circuit diagram of a portion of a memory circuit 100 is shown in FIG. Figure 3 Also shown are some circuit components, such as a pair of Y MUXes 262, which are selected by the YB[3] signal, a read transmission gate circuit (PMOS FETs 250 and 252), and a sense amplifier 244. It should be understood that for illustration purposes, Figure 3 The circuit diagram has been simplified.

[0037] like Figure 3As shown, global read enable control circuit 230 includes a NOR gate 310; local read enable control circuit 240 includes an inverter 320 and an NMOS FET 330; SAPCH circuit 246 includes a pair of PMOS FETs 340 and 342; and PRCH circuit 260 includes a pair of PMOS FETs 350 and 352. Specifically, NOR gate 310 can perform a NOR operation on the SAE_LCTRL signal and the LWE signal to provide a global READ signal. The global READ signal is received by inverter 320 and further received at the drain terminal of transistor 330, where transistor 330 is gated by the SAE signal and grounded. Inverter 320 can provide a local READB signal as an inverted global READ signal, the timing of which can be adjusted by transistor 330, which is gated by the SAE signal. In some embodiments, the sense amplifier 246 is activated for a sensing operation that is subsequent to a previous read operation performed on the selected SRAM cell, and during the sensing operation, no precharge operation is performed on BL3 / BLB3 or RBL / RBLB. In addition, the next read operation. For example, during the sensing operation, the PRCH circuit 260 (or PMOS FETs 350 and 352) can be disabled by holding the BLPCHB signal at logic 1; and the SAPCH circuit 246 (or PMOS FETs 340 and 342) can be disabled by holding the SAPRB signal at logic 1. Example waveforms of the local READB signal, the SAE signal, the BLPCHB signal, and the SAPRB signal are shown in FIG. Figure 4 provided and discussed in.

[0038] Figure 4 1 shows a method for operating the memory circuit 100 (according to the embodiment of the present disclosure) in a sensing operation. Figure 3 For example, example waveforms of the BLPCH signal, the SAE_LCTRL signal, the SAEB signal, the global READ signal, the SAE signal, the local READB signal, the SAPRB signal, and the voltages presented on BL3 / BLB3 / RBL / RBLB that vary over time (e.g., during a sensing operation) are shown. Figure 4 Typically, a sensing operation is performed after a first read operation performed on the memory circuit 100, and a second, next read operation is not performed until the sensing operation is fully completed.

[0039] As shown in the figure, the BLPCHB signal, the SAE_LCTRL signal, and the SAPRB signal are pulled up after the rising edge of the ICLK signal. When the BLPCH signal and the SAPRB signal are pulled up to logic 1, the PRCH circuit 260 and the SAPCH circuit 246 are disabled. When the SAE_LCTRL signal is pulled up to logic 1, the SAEB signal is pulled down, and then the SAE signal will be pulled up. Since the SAE_LCTRL signal is at logic 1 (the LWE signal remains at logic 0), the global READ signal is output at logic 0 by the NOR gate 310 of the global read enable control circuit 230. At the same time, the global READ signal is also pulled down to logic 0 by the transistor 330 of the local read enable control circuit 240. The transistor 330 is activated or turned on by the SAE signal, and therefore the local read READB signal is pulled high to logic 1. In other words, the global READ signal is coupled to ground by activating transistor 330. The timing of the rising edge ("t2") of the local READB signal can be controlled based on the timing of the rising edge ("t1") of the SAE signal. Once the SAE signal is pulled up to logic 1, the sense amplifier 244 is activated to perform the sensing (and amplification) operation, and when completed, the SAE_LCTRL signal is pulled down to logic 0, which causes the SAE signal to transition to logic 0 at "t3." With the SAE signal pulled down to logic 0, the transistor 330 of the local read enable control circuit 240 is deactivated or turned off. As a result, the global READ signal is decoupled from ground, which can advantageously extend the timing of the falling edge ("t4") of the local READB signal.

[0040] In some implementations, the first timing margin is determined as t2-t1 (i.e., the timing of the rising edge of the local READB signal minus the timing of the rising edge of the SAE signal), and the second timing margin is determined as t4-t3 (i.e., the timing of the falling edge of the READB signal minus the timing of the falling edge of the SAE signal). The local READB signal, which is controlled by the SAE signal via the local read enable control circuit 240, can ensure that both the first and second timing margins are sufficiently large (e.g., greater than 10%), regardless of the RC mismatch between the propagation paths of the received SAE_LCTRL signal and the LWE signal. Given a sufficiently large first timing margin, the RBL and RBLB of the sense amplifier 244 can be advantageously ensured to not float. Furthermore, given a sufficiently large second timing margin, the PRCH circuit 260 can be advantageously ensured to not interfere with the RBL and RBLB of the sense amplifier 244.

[0041] Figure 5 Another example schematic diagram of a portion of a memory circuit 100 according to various embodiments of the present disclosure is shown. Figure 5 Schematic diagram, Figure 6 and Figure 7 Shown respectively Figure 5 An example circuit diagram of a portion of a memory circuit 100 is shown in FIG.

[0042] First reference Figure 5 , memory bank 102 includes two different groups of SRAM cells 510 and 520. The two groups of SRAM cells 510 and 520 can each belong to different memory arrays of a memory bank, or to different sub-arrays of a memory array. Typically, groups 510 and 520 are coupled to corresponding BL and BLB groups or corresponding RBL and RBLB groups. In some embodiments, groups 510 and 520 can share the same GCTRL block 110, the same LCTRL block 106, the same WL driver block 108, the same LIO block 104, and the same GIO block 112, but the LIO block 103 and the GIO block 104 each have components for groups 510 and 510.

[0043] For example, the LIO block 104 includes an LIO block 104[0] coupled to the SRAM cell group 510 and an LIO module 104[1] coupled to the SRAM cell group 520. Each of the LIO blocks 104[0] and 104[1] is substantially the same as the LIO block 104 described above and, therefore, will be briefly described below. Each of the LIO blocks 104[0] and 104[1] may include a BLPCH circuit, a plurality of Y MUXs, a local read enable control circuit (e.g., 240[0], 240[1]), a read transmission gate circuit, a SAPCH circuit, and a sense amplifier. The read transmission gate circuit is activated / deactivated by a local READB signal generated by a corresponding local read enable control circuit and may selectively couple a selected BL / BLB pair to a corresponding RBL / RBLB pair. The sense amplifier is activated / deactivated by a SAE signal generated globally by the LCTRL block 106 and may selectively couple the RBL / RBLB pair to a corresponding output latch (e.g., Q[0], Q[1]).

[0044] exist Figure 6 In the example of FIG, in addition to the local read enable control circuits 240[0] and 240[1], two other local read enable control circuits 240[2] and 240[3] are shown. Each of the local read enable control circuits 240[0] to 240[3] is connected to Figure 3 The local read enable control circuit shown is substantially similar, for example, including an inverter 320 and a transistor 330. Figure 5 , local read enable control circuits 240[0] to 240[3] are respectively coupled to different SRAM cell groups. In some implementations, local read enable control circuits 240[0] to 240[3] can receive a common SAE signal and provide corresponding local READB signals.

[0045] exist Figure 7 In the example of FIG. 1 , four local read enable control circuits 240 [ 0 ] to 240 [ 3 ] are shown, which are connected to Figure 6 Substantially similar, except that each local read enable control circuit 240[0] to 240[3] further includes a switch. Local read enable control circuit 240[0] includes a switch SW1 coupled between the global READ signal and the drain terminal of its transistor 330; local read enable control circuit 240[1] includes a switch SW2 coupled between the global READ signal and the drain terminal of its transistor 330; local read enable control circuit 240[2] includes a switch SW3 coupled between the global READ signal and the drain terminal of its transistor 330; and local read enable control circuit 240[3] includes a switch SW4 coupled between the global READ signal and the drain terminal of its transistor 330. In some implementations, local read enable control circuits 240[0] to 240[3] can receive a common SAE signal and provide a corresponding local READB signal. In addition, switches SW1 and SW3 can be activated simultaneously, while switches SW2 and SW4 can be deactivated simultaneously. Local read enable control circuits 240[0] and 240[2] may be coupled to corresponding even-numbered output latches, while local read enable control circuits 240[1] and 240[3] may be coupled to respective odd-numbered output latches.

[0046] Figure 8 An example circuit diagram of a sense amplifier 800 according to various embodiments of the present disclosure is shown. The sense amplifier 800 can be a non-limiting implementation of the sense amplifier 244 described above. Thus, the sense amplifier 800 can be coupled to a pair of RBL and RBLB that can be precharged by a SAPCH circuit (e.g., 246), and the RBL and RBCB can be coupled from a selected BL and a selected BLB through an activated read pass gate circuit before a sensing operation.

[0047] The sense amplifier 800 includes transistors 810, 820, 830, 840, and 850, wherein transistors 810 and 820 are each implemented as a PMOS FET, and transistors 830 to 850 are each implemented as an NMOS FET. Transistors 810 and 830 may form a first inverter, and transistors 820 and 840 may form a second inverter, wherein the first inverter and the second inverter are cross-coupled to each other to be operable as a latch. Transistor 850 is gated by a sense enable signal (e.g., an SAE signal) and may serve as a switch for the sense amplifier 800. For example, the sense amplifier 800 may be activated to sense and amplify an input value only when transistor 850 is activated or turned on.

[0048] Prior to the sensing operation, nodes DL_IN and DLB_IN are typically precharged by the corresponding SAPCH circuit to a voltage below the power supply voltage VDD, such as VDD / 2. After both nodes DL_IN and DLB_IN are precharged, the small voltage sensed from the selected memory cell is coupled to the sensing node DL_IN or DLB_IN; the other node will remain at its precharged voltage. Next, the sense amplifier 800 can be enabled by the SAE signal, which causes transistor 850 to couple the latch (formed by the cross-coupled first and second inverters) to ground or other voltage source (for example, this can also be negative) to allow current to flow through transistors 810 to 840. Since one of the inputs DL_IN or DLB_IN will be greater than or less than the threshold potential of one of the transistors, and the other input is at an intermediate value, the latch will latch that input value. Due to the gain of the transistors in the latch, the latch can amplify the input value, and the sensed small signal voltage will be amplified to the full logic value for output to the corresponding output latch.

[0049] Figure 9 1 is a flow chart illustrating an example method 900 for operating a memory circuit according to various embodiments of the present disclosure. The operations of the method 900 may be performed by the components described above (e.g., Figures 2 to 8 ) is performed, therefore, some of the reference numbers used above may be reused in the following discussion of method 900. In addition, it is understood that method 900 has been simplified, therefore, in Figure 9 Additional operations may be provided before, during, and after method 900, and some other operations may only be briefly described herein.

[0050] The method 900 begins with operation 910 by asserting a sensing enable control signal based on a transition edge of a clock signal. Figure 2 Schematic diagram and Figure 3 As a representative example, once the clock signal (e.g., ICLK signal) is pulled up to logic 1, the sense enable control signal (e.g., SAE_LCTRL signal) is asserted by the pull-up. In some embodiments, the clock generator 224 may pull up the ICLK signal, which causes the SAE / SAPRB circuit 228 to pull up the SAE_LCTRL signal.

[0051] Method 900 continues to operation 920, where a sense enable signal is determined immediately following the sense enable control signal. For the same example as above, when the SAE_LCTRL (sense enable control) signal is pulled up, the sense enable signal (e.g., the SAE signal) can be determined by the pull-up. In some embodiments, the SAE_LCTRL signal is logically inverted to the SAEB signal by a first inverter, and the SAE signal is logically inverted from the SAEB signal by a second inverter.

[0052] The method 900 continues to operation 930 where the global read enable signal is deasserted in response to the assertion of the sense enable control signal. Furthermore, when the SAE_LCTRL (sense enable control) signal is pulled up, the global read enable signal (e.g., READ) can be deasserted by pulling down the global read enable control circuit 230. The global read enable control circuit 230 includes a NOR gate that receives the SAE_LCTRL signal and the LWE signal as inputs.

[0053] Method 900 continues with operation 940 by transitioning the local read enable signal from a first logic state to a second logic state to disable the read pass gate circuit after the first transition of the sense enable signal. Continuing with the same example, after the SAE signal transitions to logic 1 to turn on transistor 330 of local read enable control circuit 240, the global READ signal is pulled down to ground, which causes the local read enable signal (e.g., READB signal) to be asserted, e.g., transition to logic 1. Consequently, the read pass gate circuit (e.g., PMOS FETs 250 and 252) is disabled to decouple the selected BL / BLB pair from the RBL / RBLB pair of the sense amplifier.

[0054] Method 900 continues with operation 950, where the local read enable signal is transitioned from the second logic state to the first logic state to activate the read pass gate circuit after the second transition of the sense enable signal. Continuing with the same example, after the SAE signal transitions to logic 0 (e.g., after the sensing operation is completed), transistor 330 of local read enable control circuit 240 is turned off, which disconnects the output node of the NOR gate (of global read enable control circuit 230) from ground. Thus, it is ensured that the READB signal has a sufficient time margin to transition to logic 0 after the SAE signal transitions to logic 0. Consequently, the read pass gate circuit (e.g., PMOS FETs 250 and 252) is activated to couple the selected BL / BLB pair to the RBL / RBLB pair of the sense amplifier, enabling the next read operation.

[0055] In some embodiments, a signal is said to be asserted when it is pulled up from a logic 0 to a logic 1. Similarly, a signal is said to be deasserted when it is pulled down from a logic 1 to a logic 0. However, in some other embodiments, the polarity of a circuit component (e.g., one or more transistors) controlled (e.g., gated) by a signal may change. Thus, it should be understood that a signal may be said to be asserted and deasserted when it is pulled down and pulled up, respectively, while still within the scope of the present disclosure.

[0056] In one aspect of the present disclosure, a memory circuit is disclosed. The memory circuit includes a first memory cell that is accessible via a first access line and a second access line; a first read pass-gate transistor and a second read pass-gate transistor coupled to the first access line and the second access line, respectively; a first sense amplifier coupled to the first access line and the second access line; a first read enable control circuit configured to generate a first read enable signal based on a clock signal; and a second read enable control circuit configured to generate a second read enable signal by logically inverting the first read enable signal, wherein the first read enable signal selectively transitions to a different logic state based on the first sense enable signal. The second read enable signal is configured to activate or deactivate the first and second read pass-gate transistors, and the first sense enable signal is configured to activate or deactivate the first sense amplifier.

[0057] In some embodiments, the first read enable control circuit includes a NOR gate, and the second read enable control circuit includes an inverter and a transistor.

[0058] In some embodiments, the NOR gate has a first input terminal configured to receive a write enable signal, a second input terminal configured to receive a sense enable control signal generated according to the clock signal, and an output terminal configured to output the first read enable signal, and the sense enable signal follows the sense enable control signal.

[0059] In some embodiments, the inverter has an input terminal configured to receive the first read enable signal and an output terminal configured to provide the second read enable signal, and the transistor has a gate terminal connected to the first sense enable signal, a drain terminal connected to the first read enable signal, and a source terminal connected to ground.

[0060] In some embodiments, the second read enable control circuit is configured to deactivate the first read pass-gate transistor and the second read pass-gate transistor based on coupling the first read enable signal to ground only after the first sense enable signal transitions from a first logic state to a second logic state to activate the first sense amplifier.

[0061] In some embodiments, only after the first sense enable signal transitions from the second logic state to the first logic state to disable the first sense amplifier, the second read enable control circuit is configured to keep the first read pass-gate transistor and the second read pass-gate transistor disabled for a period of time based on decoupling the first read enable signal from ground.

[0062] In some embodiments, the memory circuit further includes: a second memory cell operably accessible via a third access line and a fourth access line; a third read pass-gate transistor and a fourth read pass-gate transistor, respectively coupled to the third access line and the fourth access line; a second sense amplifier coupled to the third access line and the fourth access line; and a third read enable control circuit configured to generate a third read enable signal by logically inverting the first read enable signal, the first read enable signal selectively transitioning to a different logic state based on the second sense enable signal; wherein the third read enable signal is configured to activate or deactivate the third read pass-gate transistor and the fourth read pass-gate transistor, and the second sense enable signal is configured to activate or deactivate the second sense amplifier.

[0063] In some embodiments, the second read enable control circuit is physically positioned next to the first memory cell along a first horizontal direction, the third read enable control circuit is physically positioned next to the second memory cell along the first horizontal direction, and the first read enable controller circuit is physically arranged next to the second read enable control circuit and the third read enable control circuit along a second horizontal direction perpendicular to the first horizontal direction.

[0064] In some embodiments, the first access line and the second access line belong to a first array, and the third access line and the fourth access line belong to a second array.

[0065] In some embodiments, the second read enable control circuit and the third read enable control circuit are activated alternately.

[0066] In another aspect of the present disclosure, a memory circuit is disclosed. The memory circuit includes a memory array comprising a plurality of memory cells; an input / output (I / O) circuit operably coupled to the memory array and physically disposed adjacent to the memory array along a first lateral direction, wherein the I / O circuit includes a plurality of read pass gate circuits and a plurality of sense amplifiers, the read pass gate circuits being operably coupled to different groups of memory cells, and the sense amplifiers being operably coupled to different groups of memory cells; and a control circuit operably coupled to the memory array and physically disposed adjacent to the I / O circuit along a second lateral direction perpendicular to the first lateral direction. The control circuit includes a global read enable control circuit, and the I / O circuit includes a plurality of local read enable signal control circuits, each of which is operably coupled to a corresponding one of a plurality of read pass gate circuits. The global read enable control circuit is configured to generate a first read enable signal based on a sense enable control signal, and each local read enable control circuit is configured to generate a corresponding second read enable signal for a corresponding read pass gate circuit based on the sense enable control signal.

[0067] In some embodiments, the global read enable control circuit includes a NOR gate, and each of the local read enable control circuits includes an inverter and a transistor.

[0068] In some embodiments, the NOR gate has a first input terminal configured to receive a write enable signal, a second input terminal configured to receive the sense enable control signal generated according to a clock signal, and an output terminal configured to output the first read enable signal.

[0069] In some embodiments, the inverter has an input terminal configured to receive the first read enable signal and an output terminal configured to provide the second read enable signal, and the transistor has a gate terminal connected to the corresponding sense enable signal, a drain terminal connected to the first read enable signal, and a source terminal connected to ground.

[0070] In some embodiments, the sense enable signal follows the sense enable control signal to selectively activate corresponding sense amplifiers.

[0071] In some embodiments, after the sense enable signal activates the corresponding sense amplifier, the local read enable control circuit is configured to disable the corresponding read pass gate circuit by turning on the corresponding transistor to couple the first read enable signal to ground.

[0072] In some embodiments, after the sense enable signal disables the corresponding sense amplifier, the local read enable control circuit is configured to keep the corresponding read pass gate circuit disabled for a period of time by turning off the corresponding transistor to decouple the first read enable signal from ground.

[0073] In some embodiments, the global read enable control circuit includes a NOR gate, and each of the local read enable control circuits includes an inverter, a switch, and a transistor.

[0074] In another aspect of the present disclosure, a method for operating a memory circuit is disclosed. The method includes determining a sense enable control signal based on a transition edge of a clock signal. The method includes asserting the sense enable signal after the sense enable control signal is asserted. The method includes deactivating a global read enable signal in response to the sense enable control signal being asserted. The method includes deactivating a read pass gate circuit by transitioning a local read enable signal from a first logic state to a second logic state after the sense enable signal is asserted. The method includes activating the read pass gate circuit by transitioning the local read enable signal from the second logic state to the first logic state after the sense enable signal is deactivated.

[0075] In some embodiments, the local read enable signal is pulled up based on coupling the global read enable signal to ground, and the local read enable signal is pulled down based on decoupling the global read enable signal from ground.

[0076] As used herein, the terms "about" and "approximately" generally refer to a value of a given quantity that may vary depending on the particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "approximately" may refer to a value of a given quantity that varies, for example, within a range of 10-30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0077] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may undergo various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A memory circuit comprising: a first memory cell operatively accessible via a first access line and a second access line; a first read pass-gate transistor and a second read pass-gate transistor, coupled to the first access line and the second access line, respectively; a first sense amplifier coupled to the first access line and the second access line; a first read enable control circuit configured to generate a first read enable signal based on a clock signal; as well as a second read enable control circuit configured to generate a second read enable signal by logically inverting the first read enable signal, wherein the first read enable signal selectively transitions to a different logic state based on the first sense enable signal; The second read enable signal is configured to activate or deactivate the first read pass-gate transistor and the second read pass-gate transistor, and the first sense enable signal is configured to activate or deactivate the first sense amplifier.

2. The memory circuit according to claim 1, wherein The first read enable control circuit includes a NOR gate, and the second read enable control circuit includes an inverter and a transistor.

3. The memory circuit according to claim 2, wherein: The NOR gate has a first input terminal configured to receive a write enable signal, a second input terminal configured to receive a sense enable control signal generated according to the clock signal, and an output terminal configured to output the first read enable signal, and the first sense enable signal follows the sense enable control signal.

4. The memory circuit according to claim 3, wherein: The inverter has an input terminal configured to receive the first read enable signal and an output terminal configured to provide the second read enable signal, and the transistor has a gate terminal connected to the first sense enable signal, a drain terminal connected to the first read enable signal, and a source terminal connected to ground.

5. A memory circuit comprising: a memory array comprising a plurality of memory cells; an input / output (I / O) circuit operatively coupled to the memory array and physically disposed adjacent to the memory array along a first lateral direction, wherein the input / output circuit comprises a plurality of read transfer gate circuits and a plurality of sense amplifiers, wherein the read transfer gate circuits are operatively coupled to different memory cell groups, and the sense amplifiers are operatively coupled to different memory cell groups; and a control circuit operatively coupled to the memory array and physically disposed adjacent to the input / output circuit along a second lateral direction perpendicular to the first lateral direction; wherein the control circuit comprises a global read enable control circuit, and the input / output circuit comprises a plurality of local read enable control circuits, each local read enable control circuit being operatively coupled to a corresponding one of the plurality of read pass gate circuits; and The global read enable control circuit is configured to generate a first read enable signal based on a sense enable control signal, and each of the local read enable control circuits is configured to generate a corresponding second read enable signal for the corresponding read transfer gate circuit based on the sense enable control signal. The memory circuit according to claim 5 , wherein: The global read enable control circuit includes a NOR gate, and each of the local read enable control circuits includes an inverter and a transistor.

7. The memory circuit according to claim 6, wherein: The NOR gate has a first input terminal configured to receive a write enable signal, a second input terminal configured to receive the sense enable control signal generated according to a clock signal, and an output terminal configured to output the first read enable signal.

8. The memory circuit according to claim 7, wherein: The inverter has an input terminal configured to receive the first read enable signal and an output terminal configured to provide the second read enable signal, and the transistor has a gate terminal connected to a corresponding sense enable signal, a drain terminal connected to the first read enable signal, and a source terminal connected to ground.

9. A method for operating a memory circuit, comprising: determining a sensing enable control signal according to a transition edge of a clock signal; determining a sensing enable signal after the sensing enable control signal; in response to the sense enable control signal being asserted, canceling a global read enable signal; disabling a read pass-gate circuit by transitioning a local read enable signal from a first logic state to a second logic state after the sense enable signal is asserted; as well as After the sense enable signal is deactivated, the read pass-gate circuit is activated by transitioning the local read enable signal from the second logic state to the first logic state.

10. The method according to claim 9, wherein: The local read enable signal is pulled up based on coupling the global read enable signal to ground, and the local read enable signal is pulled down based on decoupling the global read enable signal from ground.

Images