Voltage control and data reading method and device of phase change memory, storage medium and program product

Abstract

The embodiment of the invention provides a voltage control and data reading method and device of a phase change memory, a storage medium and a program product. In the method, writing and reading interval description information when an application performs data writing-first and reading-second operation on the PCM can be obtained, an initial voltage gear and a gear switching strategy required when data is read from a storage unit of the PCM are determined according to the description information, and the data are read from the PCM based on the initial voltage gear and the gear switching strategy. Due to the fact that writing and reading interval description information is considered in the initial voltage gear and the gear switching strategy, the voltage drift factor can be reflected, the initial voltage gear is determined, the corresponding gear switching strategy is determined, data can be read from the PCM on the basis of the initial voltage gear, and data reading efficiency is improved. And when the reading of the initial voltage gear fails, reasonable voltage gear switching is carried out based on the gear switching strategy, so that the probability of successfully reading data from the PCM is improved, and the overall data reading efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of cloud computing technology, and in particular to a voltage control and data reading method, device, storage medium, and program product of a phase change memory. Background Art

[0002] With the development of cloud computing and cloud storage technologies, the exploration of persistent memory application architectures has deepened, creating an urgent need for storage suitable for persistent memory. Phase change memory (PCM) offers advantages such as high read / write speed, non-volatility, and byte addressability, along with the potential to serve as both main and external memory, thus meeting this requirement.

[0003] PCM uses the difference in conductivity exhibited by a special material when transitioning between its crystalline and amorphous states to store data. In the amorphous state, the resistance is higher, representing a stored logic "0," while in the crystalline state, the resistance is lower, representing a stored logic "1." To read data, a read voltage is applied to the PCM. Since this read voltage is relatively small, it does not change the stored state.

[0004] In practical applications, PCM has a voltage drift issue. That is, after writing data to the PCM storage cell, as the data retention time increases, the voltage actually required to read the data will continue to increase. This may cause the read voltage originally applied to the PCM to fail to successfully read the data from the PCM, reducing data reading efficiency. Summary of the Invention

[0005] Multiple aspects of the present application provide a phase change memory voltage control and data reading method, device, storage medium and program product, which are used to reasonably configure the initial voltage level required for reading data from PCM and the corresponding voltage level adjustment strategy, thereby increasing the probability of successfully reading data from PCM and thereby improving data reading efficiency.

[0006] An embodiment of the present application provides a voltage control method for a PCM, which is applied to a host. The method includes: responding to a preset trigger event, predicting write-read interval description information when a target application performs a write-first-then-read operation on the PCM in a future time period, wherein the target application is an application on the host that uses the PCM to access data; and sending the write-read interval description information to a storage controller in the PCM, so that the storage controller configures an initial voltage level and a corresponding target level switching strategy required for reading data from a storage unit in the PCM according to the write-read interval description information.

[0007] An embodiment of the present application also provides a method for reading data from a PCM, which is applied to a storage controller in the PCM, the method comprising: receiving write-read interval description information sent by a host when a target application performs a write-first-then-read operation on the PCM in a future time period, the target application being an application on the host that uses the PCM to access data; configuring an initial voltage level and a corresponding target level switching strategy required for reading data from a storage unit in the PCM according to the write-read interval description information; and upon receiving a read command from the target application, reading data from the storage unit of the PCM based on the initial voltage level and the corresponding target level switching strategy.

[0008] An embodiment of the present application further provides a host, comprising: a memory and a processor; the memory is used to store a computer program, and the processor is coupled to the memory and is used to execute the computer program to implement the steps in the PCM voltage control method provided in the embodiment of the present application.

[0009] An embodiment of the present application also provides a phase change memory, comprising: a storage unit for storing data and a storage controller for performing storage control on the storage unit; the storage controller comprises: a processor and a memory, wherein the memory stores a firmware program of the phase change memory, and the processor is configured to execute the firmware program to implement the steps in the data reading method of the PCM.

[0010] An embodiment of the present application also provides a storage controller, which is applied to a phase change memory and is used to control the storage of storage units in the phase change memory. The storage controller includes: a processor and a memory, wherein the memory stores a firmware program of the phase change memory, and the processor is used to execute the firmware program to implement the steps in the data reading method of the PCM.

[0011] An embodiment of the present application further provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor implements the steps of the PCM voltage control method and / or the PCM data reading method provided in the embodiment of the present application.

[0012] An embodiment of the present application further provides a computer program product, comprising: a computer program / instruction, which, when executed by a processor, causes the processor to implement the steps of the PCM voltage control method and the PCM data reading method provided in the embodiment of the present application.

[0013] In this embodiment, write-read interval description information can be obtained when an application performs a write-first-then-read data operation on a PCM. The initial voltage level and level switching strategy required for reading data from the PCM's storage cells are determined based on this description information, and data is read from the PCM based on the initial voltage level and level switching strategy. Because the initial voltage level and level switching strategy take into account the write-read interval description information, and because the write-read interval description information can reflect voltage drift factors, not only the initial voltage level is determined, but also the level switching strategy corresponding to the initial voltage level is determined. This allows data to be read from the PCM's storage cells based on the initial voltage level. If the initial voltage level reading fails, a reasonable voltage level switching is performed based on the level switching strategy, which helps increase the probability of successfully reading data from the PCM's storage cells and improves overall data reading efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0015] Figure 1a A system architecture diagram of a host system 100 provided in an exemplary embodiment of the present application;

[0016] Figure 1b An interactive flow chart within the host system 100 provided for an exemplary embodiment of the present application;

[0017] Figure 2 A schematic flow chart of a voltage control method for a phase change memory provided in yet another exemplary embodiment of the present application;

[0018] Figure 3 A flowchart of a method for reading data from a phase change memory provided by another exemplary embodiment of the present application;

[0019] Figure 4 A flowchart of an actual scenario provided for another exemplary embodiment of the present application;

[0020] Figure 5 A schematic structural diagram of a voltage control device for a phase change memory provided by another exemplary embodiment of the present application;

[0021] Figure 6 A schematic structural diagram of a data reading device for a phase change memory provided by another exemplary embodiment of the present application;

[0022] Figure 7 A schematic structural diagram of a host device provided as another exemplary embodiment of the present application;

[0023] Figure 8A schematic structural diagram of a PCM provided as another exemplary embodiment of the present application. DETAILED DESCRIPTION

[0024] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the specific embodiments of this application and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0025] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation portals for users to choose to authorize or refuse. In addition, the various models involved in this application (including but not limited to language models or large models) are in compliance with relevant laws and standards.

[0026] PCM consists of multiple memory cells, each of which stores a single piece of data, either a logical "0" or a logical "1." A memory cell is also called a storage bit, and in PCM, these cells are organized and managed in rows and columns. When reading data from PCM, the memory cell to be read is determined, and a corresponding read voltage is applied to that cell. However, in practical applications, PCM suffers from voltage drift. After data is written to a PCM memory cell, the voltage required to read the data increases as the data retention time increases. This can cause the read voltage originally applied to the PCM to fail to successfully read the data, reducing data reading efficiency.

[0027] In response to the above technical problems, in an embodiment of the present application, based on the principle of voltage drift, for a target application (i.e., an application using PCM for data access), the write-read interval description information is obtained when the target application performs a data write-first-then-read operation on the PCM. The write-read interval description information is used to describe the interval time between the data write operation and the data read operation corresponding to the data write operation. In other words, the write-read interval description information is used to describe the time difference between the write time and the read time for any data. For example, if the target application writes some data to the PCM at time T1 and reads the data from the PCM at time T2, then the write-read interval between T1 and T2 is T2-T1. The write-read interval description information refers to information that can describe or reflect the write-read interval T2-T1 to a certain extent. Optionally, the write-read interval description information can be the write-read interval T2-T1 itself, or other information that can reflect the write-read interval T2-T1, such as the average write-read interval of the target application, or the write-read interval gear to which the write-read interval T2-T1 belongs, etc. Different write-read interval gears correspond to different write-read interval ranges. It should be noted that, due to different types or applicable scenarios of different applications, the write and read intervals of the applications and the write and read interval description information used may be different.

[0028] The initial voltage level and the corresponding level switching strategy required for reading data from the storage unit of the PCM are determined based on the write-read interval description information, and data is read from the PCM based on the initial voltage level and the corresponding level switching strategy. Since the initial voltage level and the level switching strategy take into account the write-read interval description information, and the write-read interval description information can reflect the voltage drift factor, and not only the initial voltage level is determined, but also the level switching strategy corresponding to the initial voltage level is determined, data can be read from the storage unit of the PCM based on the initial voltage level, and when the initial voltage level reading fails, a reasonable voltage level switching can be performed based on the level switching strategy, which is conducive to increasing the probability of successfully reading data from the storage unit of the PCM, thereby improving the overall data reading efficiency.

[0029] In the embodiments of the present application, there is no limitation on the implementation method for obtaining the write-read interval description information when the application performs a write-first-then-read operation on the PCM, nor is there any limitation on the implementation method for determining the initial voltage level and the corresponding level switching strategy required for reading data from the storage unit of the PCM based on the write-read interval description information. The embodiments of the present application provide several implementation methods, in which different implementation methods can be used to determine the write-read interval description information, and different implementation methods can be used to determine the initial voltage level and the corresponding level switching strategy required for reading data from the storage unit of the PCM based on the write-read interval description information.

[0030] The following is a schematic illustration of several implementation methods provided in the embodiments of the present application in conjunction with a host system architecture that uses PCM as a storage medium.

[0031] Figure 1a The system architecture diagram of the host system 100 provided in the embodiment of the present application is as follows: Figure 1a As shown, the host system 100 may include: a host 10 and a phase change memory 20. The phase change memory 20 may be implemented as an extended memory of the host 10 or as an external memory of the host 10, without limitation. The host 10 and the phase change memory 20 are interconnected. The phase change memory 20 may be integrated into the host 10 or plugged into the host 10 in a plug-and-play manner, without limitation in this embodiment. Regardless of the interconnection method adopted, the host 10 and the phase change memory 20 may be interconnected using a bus, such as, but not limited to, a DDR (Double Data Rate Synchronous Dynamic Random Access) bus or a PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) bus.

[0032] In addition, when different buses are used for interconnection between the host 10 and the phase change memory 20, the transmission protocol between the host 10 and the phase change memory 20 will also be different. For example, when using a DDR bus for interconnection, the DDR protocol can be used. Among them, the DDR protocol includes multiple generations, such as DDR1, DDR2, DDR3, DDR4, DDR5, etc. In addition, from the perspective of the topology of the DDR bus, the DDR protocol is also divided into a DDR protocol that supports a T-type topology (abbreviated as DDR-T) and a DDR protocol that supports a daisy chain topology, etc., and the appropriate DDR protocol can be flexibly selected according to needs, for example, the DDR-T protocol can be selected. For example, when using a PCIE bus for interconnection, the CXL (Compute Express Link) protocol or the Nvme (Non-volatile memory express) protocol can be used. Among them, the CXL protocol is a cache consistency interconnection protocol for processors, memory extensions and accelerators, which enables high-speed and efficient interconnection between the processor of the host 10 and the phase change memory 20.

[0033] In this embodiment, at least one application can be run on the host 10, and the phase change memory 20 can provide storage services for one or more applications on the host. It is explained here that the host 10 can use the phase change memory 20 to provide storage services for one or several applications, or can flexibly and dynamically allocate the phase change memory 20 to different applications according to application requirements. For ease of description, the application currently using the phase change memory 20 to provide storage services is called the target application, and the target application can be fixed or dynamically changing. Figure 1a As shown, the host 10 may include: a first memory 101 and a first CPU 102 (Central Processing Unit). The first CPU 102 is the CPU on the host 10. In order to distinguish it from the CPU in the phase change memory 20, the CPU in the host 10 is referred to as the first CPU. The first memory 101 is the memory in the host 10, which is used to store various software codes such as various applications, operating systems, etc. on the host 10. Figure 1a In the figure, the program code of the target application is stored in the first memory 101 as an example, and the target application is at least one application that currently uses the phase change memory 20 for data access; the first CPU 102 serves as the control brain of the host 10 and is used to execute some operations on the host 10 such as calculation, control and data processing.

[0034] like Figure 1a As shown, the phase change memory 20 may include a memory controller 201 and a memory cell array 202. The memory cell array 202 includes a plurality of memory cells organized and managed in a row and column manner. The memory controller 201 and the memory cell array 202 may be interconnected via an internal bus. Figure 1a As shown, the storage controller 201 includes: a second CPU 2012, a second memory 2011, a reading circuit 2016 and various related hardware registers. The second CPU refers to the CPU in the storage controller 201, which is used to perform some operations such as calculation, control and data processing on the storage controller 201; the second memory 2011 refers to the memory in the storage controller 201, mainly refers to the internal memory of the storage controller 201, and is mainly used to store the firmware program of the phase change memory 20. The firmware program can be understood as the program code solidified in the second memory 2011 for controlling the phase change memory 20, which is used to drive the phase change memory 20 to run. In the embodiment of the present application, whether it is a CPU or a memory, the use of "first" and "second" is only used to distinguish different CPUs or memories, and does not limit the function, model and order of the CPU or memory. As Figure 1aAs shown, the registers in the memory controller 201 include at least: a voltage level register 2014, a voltage strategy selection register 2013, a vector register, and a count register 2015. These registers are used to store parameters or data related to reading and controlling the phase change memory 20. For details, please refer to the description of the subsequent method embodiments. These registers are connected to a read circuit 2016. The read circuit 2016 can read data from the memory cell array 202 based on the parameters or data stored in these registers, and can also write data related to the read and write operations back to the relevant registers, such as writing various read failure counts to the count register 2015.

[0035] Based on the above architecture, several solutions provided in the embodiments of this application are briefly described:

[0036] In solution A, to obtain write-read interval description information, the memory controller 201 of the PCM 20 can record the write address and write time of each memory cell. During each read operation, the write time of the memory cell involved in the read operation is queried. Based on the current time and the write time, the data retention time is determined as the write-read interval description information. Furthermore, based on the data retention time, a suitable read voltage is determined for the read operation. This read voltage is provided to the read circuit 2016, which then reads data from the corresponding memory cell in the memory cell array 202 based on the read voltage. This solution can use an appropriate read voltage for data read operations, which helps increase the probability of successfully reading data from the memory cells of the PCM 20. Since the number of erroneous rereads is reduced, the overall data read efficiency can be improved to a certain extent. However, recording information at the memory cell granularity and querying operations at the read operation granularity pose a significant challenge to the memory controller 201, both in terms of required storage space and computing resources.

[0037] In Solution B, host 10 is responsible for predicting and maintaining the write / read interval description information when the target application performs a write-first, read-later operation on PCM 20. Each time data needs to be read from the PCM, host 10 provides both the read instruction and the write / read interval description information to storage controller 201 in PCM 20. Based on this write / read interval description information, storage controller 201 determines the initial voltage level and corresponding level switching strategy required for reading data from storage cell array 202. It then reads data from storage cell array 202 based on the initial voltage level and corresponding level switching strategy. By maintaining the write / read interval description information when the target application performs a write-first, read-later operation on PCM 20, host 10 can promptly update this information based on actual application conditions. This allows for more accurate write / read interval description information to be provided to storage controller 201, facilitating more accurate determination of the initial voltage level and corresponding level switching strategy by storage controller 201. This improves the probability of successfully reading data from PCM 20's storage cells and, by reducing the number of erroneous rereads, improves overall data read efficiency to a certain extent. However, each time the storage controller 201 reads data, there will be a certain delay in determining the initial voltage level and the corresponding level switching strategy in real time. Therefore, this solution B is suitable for some application scenarios that do not have high requirements for data reading delay.

[0038] In Solution C, the host 10 can predict the write / read interval description information that will be used when the target application performs a write-first-then-read operation on the PCM 20 in a future time period, and pre-send the write / read interval description information to the storage controller 201. Based on this write / read interval description information, the storage controller 201 determines the initial voltage level and corresponding level switching strategy required for reading data. Subsequently, when data needs to be read from the storage cell array 202, the storage controller 201 can read data from the PCM 20 based on the initial voltage level and corresponding level switching strategy. In this approach, the host 10 predicts the write / read interval description information that will be used when the target application performs a write-first-then-read operation on the PCM 20 in a future time period, and pre-sends the information to the storage controller 201. Without performing any data write / read operations, the storage controller 201 pre-configures the initial voltage level and level switching strategy. When subsequently reading data, the storage controller 201 can directly read data based on the pre-configured initial voltage level and level switching strategy. This not only increases the probability of successfully reading data from the storage cells of the PCM 20, but also improves the efficiency of each data read, thereby improving overall data read efficiency. In addition, Solution C has good universal adaptability and is suitable for both application scenarios with low requirements for data reading latency and application scenarios with high requirements for data reading latency.

[0039] It is noted that in the above-mentioned solutions B and C, the logic for the storage controller 201 to set the initial voltage level and the level switching strategy can be pre-set in the firmware program of the phase-change memory, and the storage controller can execute the firmware program to set the initial voltage level and the level switching strategy according to the logic in solution B or solution C. The logic for the storage controller to set the initial voltage level and the level switching strategy can be changed or updated by upgrading the firmware program.

[0040] Of course, in solution C, the write-read interval description information when the target application performs a write-first-then-read operation on PCM20 may change. For example, if the application mode has changed significantly or in a special period, it may be necessary to change from the original low-frequency data reading to frequent data reading and writing, or from the original high-frequency data reading to low-frequency data reading. The host 10 can sense the change in the write-read interval description information when the target application performs a write-first-then-read operation on PCM20, and re-predict the latest write-read interval description information, and provide the latest write-read interval description information to the storage controller 201, so that the storage controller 201 can reset the initial voltage gear and gear switching strategy. In the following embodiments of this application, the focus will be on solution C, combined with the attached Figure 1a The host system architecture shown and Figure 1b The interactive flowchart shown in FIG. 1 illustrates the implementation process of Solution C in detail.

[0041] like Figure 1b As shown, the process of the host 10 interacting with the storage controller to set the initial voltage level and level switching strategy includes the following steps:

[0042] Step 11: The host 10 may respond to a preset trigger event and predict the write-read interval description information when the target application performs a data write-first-then-read operation on the PCM 20 in a future time period.

[0043] Step 14: The host 10 sends the write-read interval description information to the storage controller in the PCM 20 based on the interconnection bus between the host 10 and the PCM 20.

[0044] Step 15: After receiving the write / read interval description information sent by the host 10, the storage controller configures the initial voltage level and the corresponding target level switching strategy required for reading data from the storage unit in the PCM 20 according to the write / read interval description information.

[0045] Step 16: The host 10 responds to the read command initiated by the target application and sends the read command to the storage controller based on the interconnection bus between the host 10 and the PCM 20.

[0046] Step 17: When receiving the read command from the target application, the storage controller reads data from the storage unit of the PCM based on the configured initial voltage level and the corresponding target level switching strategy.

[0047] Step 18: When the data is successfully read, the storage controller sends the read data to the host 10, so that the host 10 provides the data to the target application for processing.

[0048] In this way, because the initial voltage level and level-switching strategy take into account the write-read interval description information, which reflects voltage drift, and not only the initial voltage level is determined, but also the level-switching strategy corresponding to that initial voltage level is determined, data can be read from the PCM storage cells based on the initial voltage level. This solution rationally configures the initial voltage level and the corresponding voltage level adjustment strategy required for reading data from the PCM, which helps increase the probability of successfully reading data from the PCM storage cells, thereby improving overall data reading efficiency.

[0049] In the embodiments of the present application, there is no limitation on the prediction triggering event, and it can be flexibly set according to the application requirements. The following examples illustrate:

[0050] ①: Resource scheduling event that allocates PCM20 to the target application, i.e., an event that allocates PCM20 to the target application for use. The host 10 can autonomously detect the storage resources required by the target application. When it detects that the current storage space is insufficient to accommodate the storage resources, it can expand the target application's capacity. At this time, PCM20 can be allocated to the target application, triggering the prediction of the target application's write and read interval description information. Alternatively, the target application can send a request to the host 10 for the use of PCM20 based on its own storage resource usage. The host 10 can respond to the request, allocate PCM20 to the target application, and trigger the prediction of the target application's write and read interval description information.

[0051] ②: The target application switches its operating mode while using PCM20. If the target application switches its operating mode while using PCM20, this may cause its data writing and reading mode to change, meaning that the write and read interval description information will also change. In this case, the host 10 can predict the target application's write and read interval description information. For example, if the target application switches from a slow read and write operating mode (which can be understood as a power-saving mode) to a high-speed read and write operating mode while using PCM20, the read and write frequencies in these two operating modes are different. The host 10 can respond to this preset trigger event and predict the target application's write and read interval description information.

[0052] ③: The target application uses PCM20 for a duration greater than the set duration threshold. This event occurs when the target application writes and reads historical data generated by the PCM20 for a duration greater than the preset time interval threshold. This event is considered a preset trigger event because, over time, a large amount of written data is read again after a time exceeding the set time threshold.

[0053] In this way, by presetting a relatively rich set of trigger events, the host can timely and accurately predict the write and read interval description information of the target application.

[0054] In some optional embodiments, when the host 10 responds to a preset trigger event and predicts the write-read interval description information of the target application performing a data write-first-then-read operation on the PCM in a future time period, it can be implemented based on the following implementation methods:

[0055] Implementation method A: respond to a preset trigger event and predict the write-read interval description information according to the application type of the target application. The application type of the target application may include: video production, video playback, game, navigation, etc. For example, for video production applications, such as short video publishing applications in short video scenarios and anchor-side applications in live broadcast scenarios, these video production applications mainly upload videos for storage, and are an application type with more write operations and fewer read operations. For video playback applications, such as short video publishing applications in short video scenarios and anchor-side applications in live broadcast scenarios, these video playback applications mainly read videos for playback, and are an application type with more read operations and fewer write operations.

[0056] Since different application types have different data read and write modes, and there is a certain correspondence between data read and write modes and read and write intervals, the write and read interval description information corresponding to different application types will also be different. Based on this, the host 10 can more accurately determine the write and read interval description information of the target application based on the application type of the target application. Further, optionally, the host 10 can pre-maintain the correspondence between the application type and the data read and write mode, and can determine the target data read and write mode based on the application type of the target application, and then determine the corresponding write and read interval description information based on the target data read and write mode.

[0057] Implementation method B: responding to a preset trigger event, predicting write / read interval description information based on the application scenario of the target application, wherein the application scenarios may include: data backup scenario, gaming scenario, and vehicle navigation scenario.

[0058] For example, in a database backup scenario, assuming PCM is used as persistent memory on the primary database, the PCM in the primary database primarily performs read operations, reading data from the PCM in the primary database and writing it to the backup database. In everyday applications, the primary database provides both storage and query functions, so both writes and reads are involved, potentially in a full-disk sequential write-followed-by-read mode. This means that the corresponding write-read interval description information may vary depending on the application scenario. For another example, in gaming scenarios, where user interaction with the application is frequent and the target application requires immediacy, the write-read interval can be relatively small when performing write-first-then-read operations on the PCM.

[0059] Since different application scenarios have different data read and write modes, and there is a certain correspondence between the data read and write modes and the write and read intervals, the write and read interval description information corresponding to different application scenarios will also be different. Based on this, the host 10 can more accurately determine the write and read interval description information of the target application based on the application scenario of the target application. Further, optionally, the host 10 can pre-maintain the correspondence between the application scenario and the data read and write mode, and can determine the target data read and write mode based on the application scenario of the target application, and then determine the corresponding write and read interval description information based on the target data read and write mode.

[0060] Implementation method C: In response to a preset trigger event, predict the write-read interval description information based on the historical write-read operation information of the target application. The historical write-read operation information of the target application is used to describe the detailed information of the read and write operations of the target application within a preset historical time range. The detailed information may include: the bandwidth consumed by reading data, the bandwidth consumed by writing data, the read time, the write time, the number of read operations, the number of write operations, the time interval between read operations, and the time interval between write operations, etc. The historical time range can be any range, for example, 30s, 1min, 30min, or 1h, etc. This historical read-write operation information can reflect the data read and write pattern of the target application within the historical time period. There is a certain correspondence between the data read and write pattern and the write-read interval. If the data read and write pattern of the target application is relatively stable, the data read and write pattern of the target application in the future time period can be predicted based on this historical read and write operation information. Then, based on the data read and write pattern of the target application in the future time period, the write-read interval description information when the target application performs data write-first and then read operations on the PCM 20 in the future time period can be determined.

[0061] It should be noted that the above implementation modes A to C can be implemented individually or in combination, and this embodiment does not limit them.

[0062] The above-mentioned embodiment C will be further described in detail below. When the host 10 responds to a preset trigger event and predicts the write-read interval description information based on the historical write and read operation information of the target application, it can be implemented based on the following embodiments C1 to C3:

[0063] Implementation method C1, in response to a preset trigger event, count the first bandwidth ratio of the historical write operations of the target application in the historical write and read operations within the first set time range. Based on the first bandwidth ratio, predict the write and read interval description information. For example, the bandwidth of the historical write operations of the target application within the first set time range is A (bps), and the bandwidth of the historical write and read operations of the target application within the first set time range is B (bps), then the first bandwidth ratio is A / B. Among them, the host 10 can determine the write and read interval description information based on the correspondence between the preset first bandwidth ratio and the write and read interval description information, as well as the first bandwidth ratio. For example, the correspondence between the preset first bandwidth ratio and the write and read interval description information includes: first bandwidth ratio 80% - write and read interval 50s, first bandwidth ratio 70% - write and read interval 40s, and first bandwidth ratio 60% - write and read interval 30s, etc. If the calculated first bandwidth ratio is 70%, the write and read interval description information can be determined to be a write and read interval 40s based on the correspondence.

[0064] Implementation method C2, in response to a preset trigger event, count the second bandwidth ratio of the historical read operations of the target application in the historical write and read operations within the first set time range; predict the write and read interval description information based on the second bandwidth ratio. For example, the bandwidth of the historical read operations of the target application within the first set time range is C (bps), and the bandwidth of the historical write and read operations of the target application within the first set time range is D (bps), then the second bandwidth ratio is C / D. Among them, the host 10 can determine the write and read interval description information based on the correspondence between the preset second bandwidth ratio and the write and read interval description information, as well as the second bandwidth ratio. For example, the correspondence between the preset second bandwidth ratio and the write and read interval description information includes: second bandwidth ratio 20% - write and read interval 50s, second bandwidth ratio 30% - write and read interval 40s, and second bandwidth ratio 40% - write and read interval 30s, etc. If the calculated second bandwidth ratio is 40%, the write and read interval description information can be determined as a write and read interval 30s based on the correspondence.

[0065] Implementation method C3, in response to a preset trigger event, count the time intervals between the historical write operation and the first historical read operation of the target application for the same data within the second preset time range, and predict the write-read interval description information based on the time interval. Among them, the host 10 can count the time intervals between the historical write operation and the first historical read operation of the target application for each data within the second preset time range. For example, the time interval for data M1 can be counted as T10, the time interval for data M2 can be T20, and the time interval for data M3 can be T30. Based on this, when predicting the write-read interval description information based on the time interval, the host 10 can perform an averaging operation, a maximum value operation, a minimum value operation, or a weighted summation operation on multiple time intervals, and use the operation result as the write-read interval description information, which is not limited in this embodiment. Among them, the weights of the host 10 when performing the weighted summation on multiple time intervals can be pre-configured, or can be set according to the early or late time of the historical write operation, wherein the earlier the time, the smaller the weight. For example, if the time of the historical write operation of the data M1 is earlier than the time of the historical write operation of the data M2, the weight of the time interval of the data M1 may be smaller than the weight of the time interval of the data M2.

[0066] In the above manner, the host 10 can respond to a preset trigger event and more accurately predict the write-read interval description information when the target application performs a write-first-then-read operation on the PCM in a future time period.

[0067] In some optional embodiments, such as Figure 1b As shown, before the host 10 sends the write-read interval description information to the storage controller 201 in the PCM 20, the host 10 further includes:

[0068] Step 12: The host 10 sends a first mode command to the storage controller 201 in the PCM 20 based on the interconnection bus between the host 10 and the PCM 20;

[0069] Step 13: The storage controller 201 may respond to the first mode command and set the voltage strategy selection register 2013 to the first gear management mode.

[0070] It should be noted that Figure 1b The above steps 12 and 13 are illustrated with dotted lines to indicate that these two steps are optional operations.

[0071] Specifically, the host 10 can send various mode commands to the storage controller 201 to control the storage controller 201 to switch between different gear management modes. This can be implemented based on the following implementations:

[0072] In the first embodiment, the host 10 may issue a first mode command to the storage controller 201. Accordingly, the storage controller 201 may respond to the first mode command and set the voltage policy selection register to the first gear management mode. The first gear management mode refers to a mode that relies on the write-read interval description information to configure the initial voltage gear and target gear switching strategy. In other words, in this gear management mode, the host 10 can indirectly control the storage controller 201 to perform voltage control by sending the write-read interval description information to the storage controller 201. The first gear management module can be referred to as a firmware model (FM).

[0073] In the second embodiment, the host 10 can issue a second mode command to the storage controller 201. Accordingly, the storage controller 201 can respond to the second mode command by setting the voltage policy selection register 2013 to the second gear management mode. The second gear management mode is a mode that does not rely on the write-read interval description information to configure the initial voltage gear and target gear switching strategy. In other words, in this gear management mode, the host 10 cannot indirectly control the storage controller 201 to perform voltage control by sending the write-read interval description information to the storage controller 201. Instead, the storage controller 201 performs voltage control autonomously. The second gear management module can be referred to as a hardware model (HM).

[0074] Implementation method three: The host 10 can also send a mode recovery command to the storage controller 201. Correspondingly, the storage controller 201 can respond to the mode recovery command to restore the second gear management mode of the PCM20 power-on initialization configuration and the default voltage gear under the second gear management mode and the corresponding default gear switching strategy.

[0075] In this way, the host 10 can flexibly control the storage controller 201 to switch between different gear management modes by sending commands to the PCM 20.

[0076] In some optional embodiments, PCM20 may support multiple write-read interval gears, with different write-read interval gears corresponding to different gear commands. A write-read interval gear may correspond to a voltage gear range, with different write-read interval gears corresponding to different voltage gear ranges. The number of write-read interval gears supported by PCM20, as well as the gear commands and voltage gear ranges corresponding to different write-read interval gears, may be pre-set before PCM20 leaves the factory and written into the corresponding firmware program of PCM20. Of course, the number of write-read interval gears supported by PCM20, as well as the gear commands and voltage gear ranges corresponding to different write-read interval gears, may also be updated through firmware upgrades. The voltage gear range corresponding to each write-read interval gear may include multiple voltage gears. For example, if the voltage gear range corresponding to the write-read interval gear is 1V-10V, the voltage gear range may include four voltage gears, with voltages of 2V, 4V, 6V, and 8V, respectively. The voltage level in the embodiment of the present application refers to the amplitude of each adjustment of the read voltage. For example, when the voltage level is 2V, it means that when the read voltage is adjusted according to the voltage level, the read voltage will be increased by 2V each time; other voltage levels are similar.

[0077] Based on this, when the host 10 sends the write-read interval description information to the storage controller in the PCM20, it can determine the target write-read interval gear that is compatible with the write-read interval description information from multiple write-read interval gears. Among them, the host 10 can determine the target voltage gear range in which the write-read interval description information is located from the voltage gear range corresponding to each write-read interval gear, and use the write-read interval gear corresponding to the target voltage gear range as the target write-read interval gear that is compatible with the write-read interval description information. After determining the target write-read interval gear that is compatible with the write-read interval description information, the host 10 can send a target gear command corresponding to the target write-read interval gear to the storage controller. Among them, the target write-read interval gear represents the write-read interval description information, and the target gear command represents the target write-read interval gear. Therefore, the target gear command represents the write-read interval description information.

[0078] Correspondingly, when receiving the write / read interval description information sent by the host 10, the storage controller 201 may receive a target gear command issued by the host 10. Furthermore, the storage controller 201 may respond to the target gear command and configure the initial voltage gear and corresponding gear switching strategy required for reading data from the storage unit in the PCM 20 based on the target voltage gear range corresponding to the target write / read interval gear.

[0079] Specifically, the storage controller 201 configures the initial voltage level and the corresponding level switching strategy according to the target voltage level range corresponding to the target write / read interval level, which can be implemented in the following manner:

[0080] Method 1: The storage controller 201 can respond to the standard gear command and determine the initial voltage gear and the corresponding target gear switching strategy based on the multiple voltage gears in the target voltage gear range corresponding to the target write-read interval gear. Among them, the storage controller 201 can randomly select a voltage gear from multiple voltage gears as the initial voltage gear, or can select the largest voltage gear or the smallest voltage gear from multiple voltage gears as the initial voltage gear; or can select the voltage gear located in the middle position or the voltage gear close to the middle position as the initial voltage gear, which is not limited in this embodiment. After determining the initial voltage gear, the storage controller 201 can generate a switching strategy between the initial voltage gear and the voltage gear connected to it. Among them, the switching strategy can be: switch to the adjacent gear first, and then switch to other larger gears; the switching strategy can also be: switch directly to the gear with one interval; the switching strategy can also be: switch directly to the larger gear; which is not limited in this embodiment.

[0081] After the storage controller 201 determines the initial voltage level and the corresponding target level switching strategy, it can write the initial voltage level and the corresponding target level switching strategy into the storage controller 201. Figure 1a The voltage level register 2014 is shown as a read circuit 2016 for reading data from a memory cell in the PCM. When reading data from a memory cell, the read circuit 2016 can read the initial voltage level and the target level switching strategy from the voltage level register 2014 and attempt to read data starting from the initial voltage level. If the read fails during the data reading process, and the read failure meets the set level switching condition, the read circuit can switch levels according to the target level switching strategy and continue to attempt to read data at the switched voltage level.

[0082] Method 2: Each voltage range can be configured with a default voltage range, and each default voltage range can correspond to a range switching strategy. Based on this, the storage controller 201 can use the default voltage range within the target voltage range and the range switching strategy corresponding to the default voltage range as the initial voltage range and the target range switching strategy, respectively. The voltage range, the default voltage range within the voltage range, and the corresponding range switching strategy can be pre-configured in the PCM firmware and dynamically updated through PCM firmware upgrades.

[0083] Specifically, in the second embodiment, a voltage range may include multiple first-level voltage ranges. Each first-level voltage range is the maximum value of any of the multiple voltage ranges obtained by dividing the voltage range, and is used to adjust the voltage of the storage cells in the PCM 20. The value of each first-level voltage range can be understood as the adjustment value for adjusting the reference voltage of the storage cells in the PCM 20.

[0084] For example, the voltage range of 1V-20V may include: a first-level voltage level D1 (5V), a first-level voltage level D2 (10V), and a first-level voltage level D3 (15V). When the configured initial voltage level is the first-level voltage level D1 (5V), the storage controller 201 may superimpose a 5V voltage on the reference voltage (e.g., 2V) applied to the PCM 20, thereby adjusting the 2V reference voltage to 7V.

[0085] In addition, a primary voltage level may also include multiple secondary voltage levels, where the secondary voltage level is smaller than the primary voltage level to which it belongs, and is any voltage value in any of the multiple voltage ranges obtained by dividing the voltage level range. The arbitrary voltage value can be customized according to actual design requirements, as long as it is smaller than the primary voltage level to which it belongs. This is not limited in this embodiment. The value of any secondary voltage level can be understood as the adjustment value when adjusting the sum of the reference voltage of the storage unit in PCM20 and the primary voltage level to which it belongs. Continuing with the above example, the primary voltage level D1 (5V) may include the secondary voltage level D11 (1V) and the secondary voltage level D12 (3V). The secondary voltage level D11 (1V) can be used to superimpose 1V on the basis of 7V, thereby adjusting the sum of the reference voltage of the storage unit in PCM20 and the primary voltage level to which it belongs (7V) to 8V.

[0086] Based on this, when the storage controller 201 uses the default voltage gear in the target voltage gear range and its corresponding gear switching strategy as the initial voltage gear and the target gear switching strategy respectively, the default first-level voltage gear in the target voltage gear range and the default second-level voltage gear below the default first-level voltage gear can be used as the initial voltage gear; and the gear switching strategy corresponding to the default first-level voltage gear and the gear switching strategy corresponding to the default second-level voltage gear can be used as the target gear switching strategy.

[0087] Through the first and second methods, the storage controller 201 can more accurately configure the initial voltage level and the corresponding level switching strategy required when reading data from the storage unit in the PCM according to the write-read interval description information.

[0088] In some optional embodiments, when the storage controller 201 receives a read command from a target application, the storage controller 201 may read data from the storage unit of the PCM based on the initial voltage level and the corresponding target level switching strategy in the following manner:

[0089] When the storage controller 201 receives a read command from the target application, it controls the read circuit 2016 to read data from the storage cells of the PCM based on the initial voltage level. The storage controller 201 then interacts with the registers on the PCM 20 to determine whether the number of read failures meets the policy switching condition.

[0090] During the data reading process, the read circuit 2016 can write relevant count information to at least one of the first count register, the second count register, and the third count register. Accordingly, the storage controller 201 can obtain the count information written by the read circuit 2016 to at least one of the first count register, the second count register, and the third count register. The first count register records the total number of read operations, the second count register records the number of successful rereads after N rereads, and the third count register records the number of successful rereads after M rereads. N and M are positive integers, and N is less than M. In an optional embodiment, N = 1 and M = 2, but this is not limited to this. Furthermore, based on this count information, the storage controller 201 can determine whether the number of read failures meets the switching condition.

[0091] When the number of read failures meets the switching conditions, the storage controller 201 can switch a new initial voltage level from the target voltage level range according to the target level switching strategy, and control the read circuit 2016 to continue reading data from the storage unit of the PCM based on the new initial voltage level.

[0092] The following examples illustrate the switching conditions and target gear switching strategies under different switching conditions.

[0093] From the perspective of a single read operation, a single read of a certain data from the storage unit of PCM 20 may fail. In this case, the read circuit 2016 can re-read the data. Based on this, the switching condition can be that the number of read failures of the read circuit 2016 for a certain data is greater than a positive integer N (for example, 1). In other words, for a piece of data, when a read failure occurs, it can be determined that the number of read failures meets the switching condition, and the current initial voltage level (a secondary voltage level under a primary voltage level) is switched to a higher secondary voltage level within the target voltage level range.

[0094] Furthermore, when the reading circuit 2016 fails to read a certain data for a number of times that is not less than a positive integer M (for example, 2), the current first-level voltage level in the target voltage level range can be switched to another first-level voltage level. That is, the reading circuit 2016 will continue to try to read a certain data after failing to read it N times. If the reading still fails after M times, the current first-level voltage level can be switched to another first-level voltage level.

[0095] From the perspective of global read operations, the switching conditions may include that the frequency of read failures within a set time period is higher than a preset frequency threshold. The storage controller 201 may write the number information in at least one of the first number register, the second number register, and the third number register through the reading circuit 2016, count the frequency of read failures within the preset time period, and determine whether the number of read failures within the preset time period meets the switching condition. If the switching condition is met, the current initial voltage level (a secondary voltage level under a certain primary voltage level) is switched to a larger secondary voltage level from the target voltage level range.

[0096] Furthermore, the switching condition may also include that the number of reread failures M times is greater than a set threshold number (for example, 5). If the switching condition is met, the storage controller 201 may switch the current initial voltage level (a certain first-level voltage) to a larger first-level voltage level from the target voltage level range when the number of read failures meets the switching condition.

[0097] Furthermore, the switching condition may also include the number of times multiple data are reread M times and all fail. For example, if five data are reread M times (for example, twice) and all fail, and the reading is successful only after switching to a higher voltage level, the voltage level may be switched to a higher voltage level.

[0098] Through the above method, when the number of read failures meets the switching conditions, the storage controller 201 can flexibly switch the first-level voltage level and the second-level voltage level in the target voltage level range according to the target level switching strategy, so that the reading circuit 2016 can be more accurately controlled based on the adjusted voltage level.

[0099] Figure 2 This is a flow chart of a voltage control method for a phase change memory PCM provided by another exemplary embodiment of the present application. When the method is executed on the host side, it may include the following steps: Figure 2 Steps shown:

[0100] Step 201 : In response to a preset trigger event, predict the write-read interval description information of a target application performing a write-first-then-read operation on a PCM in a future period of time, where the target application is an application on a host that uses the PCM for data access.

[0101] Step 202: Send the write / read interval description information to the storage controller in the PCM, so that the storage controller configures the initial voltage level and the corresponding target level switching strategy required for reading data from the storage unit in the PCM according to the write / read interval description information.

[0102] In this way, because the initial voltage level and level-switching strategy take into account the write-read interval description information, which reflects voltage drift, and not only the initial voltage level is determined, but also the level-switching strategy corresponding to that initial voltage level is determined, data can be read from the PCM storage cells based on the initial voltage level. This solution rationally configures the initial voltage level and the corresponding voltage level adjustment strategy required for reading data from the PCM, which helps increase the probability of successfully reading data from the PCM storage cells, thereby improving overall data reading efficiency.

[0103] Optionally, in response to a preset trigger event, the write-read interval description information of the target application when performing a write-first-then-read operation on the PCM in a future time period is predicted, including: responding to the preset trigger event, predicting the write-read interval description information based on the application type, application scenario and / or historical write-read operation information of the target application.

[0104] Optionally, in response to a preset trigger event, based on the historical write and read operation information of the target application, write and read interval description information is predicted, including: in response to the preset trigger event, counting a first bandwidth ratio of the historical write operations of the target application within a first set time range in the historical write and read operations; predicting the write and read interval description information based on the first bandwidth ratio; and / or, in response to the preset trigger event, counting a second bandwidth ratio of the historical read operations of the target application within the first set time range in the historical write and read operations; predicting the write and read interval description information based on the second bandwidth ratio; and / or, in response to the preset trigger event, counting the time interval between the historical write operations and the first historical read operations of the target application for the same data within a second preset time range, and predicting the write and read interval description information based on the time interval.

[0105] Optionally, the preset trigger events include: a resource scheduling event that allocates PCM to the target application; and / or an event in which the target application switches the working mode during the use of PCM; and / or an event in which the target application uses PCM for a time greater than a set time threshold.

[0106] Optionally, the PCM supports multiple write-read interval gears, different write-read interval gears correspond to different gear commands, and one write-read interval gear corresponds to a voltage gear range; the write-read interval description information is sent to the storage controller in the PCM, so that the storage controller configures the initial voltage gear required to read data from the storage unit in the PCM and the corresponding target gear switching strategy according to the write-read interval description information, including: determining a target write-read interval gear that is compatible with the write-read interval description information from multiple write-read interval gears; and sending a target gear command corresponding to the target write-read interval gear to the storage controller, so that the storage controller configures the initial voltage gear and the corresponding target gear switching strategy according to the voltage gear range corresponding to the target write-read interval gear.

[0107] Optionally, before sending the write-read interval description information to the storage controller in the PCM, it also includes: sending a first mode command to the storage controller to make the storage controller operate in a first gear management mode. The first gear management mode refers to a mode that relies on the write-read interval description information to configure the initial voltage gear and target gear switching strategy.

[0108] Optionally, it also includes: sending a second mode command to the storage controller to make the storage controller operate in the second gear management mode, the second gear management mode refers to a mode that does not rely on write-read interval description information to configure the initial voltage gear and target gear switching strategy; or, sending a mode recovery command to the storage controller to make the storage controller restore the second gear management mode of the PCM power-on initialization configuration and the default voltage gear and the corresponding default gear switching strategy under the second gear management mode.

[0109] The detailed implementation and beneficial effects of each step in the method of this embodiment have been described in detail in the aforementioned embodiments and will not be elaborated here.

[0110] Figure 3 This is a flow chart of a data reading method for a phase change memory provided by another exemplary embodiment of the present application. When the method is executed by a memory controller in a PCM, it may include the following steps: Figure 3 Steps shown:

[0111] Step 301: Receive, from a host, description information of a write-read interval when a target application performs a write-first-then-read operation on a PCM in a future period of time. The target application is an application on the host that uses the PCM for data access.

[0112] Step 302: Configure the initial voltage level and the corresponding target level switching strategy required when reading data from the storage unit in the PCM according to the write-read interval description information;

[0113] Step 303: upon receiving a read command from the target application, data is read from the storage unit of the PCM based on the initial voltage level and the corresponding target level switching strategy.

[0114] In this way, because the initial voltage level and level-switching strategy take into account the write-read interval description information, which reflects voltage drift, and not only the initial voltage level is determined, but also the level-switching strategy corresponding to that initial voltage level is determined, data can be read from the PCM storage cells based on the initial voltage level. This solution rationally configures the initial voltage level and the corresponding voltage level adjustment strategy required for reading data from the PCM, which helps increase the probability of successfully reading data from the PCM storage cells, thereby improving overall data reading efficiency.

[0115] Optionally, the PCM supports multiple write-read interval gears, and different write-read interval gears correspond to different gear commands; the write-read interval description information sent by the receiving host when the target application performs a write-first-then-read operation on the PCM in a future time period includes: receiving the target gear command sent by the host, the target gear command corresponds to the target write-read interval gear, and the target write-read interval gear is a write-read interval gear among multiple write-read interval gears that is adapted to the write-read interval description information.

[0116] Optionally, a write-read interval gear corresponds to a voltage gear range, and the voltage gear range includes multiple voltage gears. Then, according to the write-read interval description information, the initial voltage gear and the corresponding gear switching strategy required for reading data from the storage unit in the PCM are configured, including: determining the initial voltage gear and the corresponding target gear switching strategy based on the multiple voltage gears in the target voltage gear range corresponding to the target write-read interval gear; writing the initial voltage gear and the corresponding target gear switching strategy into the voltage gear register to provide them to the read circuit responsible for reading data from the storage unit in the PCM.

[0117] Optionally, a default voltage gear is set in a voltage gear range, and the default voltage gear corresponds to a gear switching strategy; according to multiple voltage gears in the target voltage gear range corresponding to the target write-read interval gear, the initial voltage gear and the corresponding gear switching strategy are configured, including: using the default voltage gear in the target voltage gear range and its corresponding gear switching strategy as the initial voltage gear and the target gear switching strategy, respectively.

[0118] Optionally, a voltage gear range includes multiple first-level voltage gears, a first-level voltage gear includes multiple second-level voltage gears, and the second-level voltage gear is smaller than the first-level voltage gear to which it belongs; the default voltage gear in the target voltage gear range and its corresponding gear switching strategy are respectively used as the initial voltage gear and the target gear switching strategy, including: the default first-level voltage gear in the target voltage gear range and the default second-level voltage gear below the default first-level voltage gear are used as the initial voltage gear; the gear switching strategy corresponding to the default first-level voltage gear and the gear switching strategy corresponding to the default second-level voltage gear are used as the target gear switching strategy.

[0119] Optionally, when a read command from a target application is received, data is read from the storage cell of the PCM based on the initial voltage level and the corresponding target level switching strategy, including: when a read command from a target application is received, controlling the read circuit to read data from the storage cell of the PCM based on the initial voltage level; and, when the number of read failures meets the switching condition, switching a new initial voltage level from the target voltage level range according to the target level switching strategy, and controlling the read circuit to continue reading data from the storage cell of the PCM based on the new initial voltage level.

[0120] Optionally, it also includes: obtaining the number information written by the reading circuit in the first number register, the second number register and / or the third number register; judging whether the number of read failures meets the switching condition based on the number information; wherein, the number of read operations recorded in the first number register, the number of successful rereads N times recorded in the second number register, and the number of successful rereads M times recorded in the third number register; N and M are positive integers, and N is less than M.

[0121] Optionally, before receiving the write-read interval description information sent by the host, it also includes: receiving the first mode command sent by the host, and setting the voltage strategy selection register to the first gear management mode. The first gear management mode refers to a mode that relies on the write-read interval description information to configure the initial voltage gear and target gear switching strategy.

[0122] Optionally, it also includes: receiving a second mode command sent by the host, and setting the voltage strategy selection register to the second gear management mode, the second gear management mode refers to a mode that does not rely on write-read interval description information to configure the initial voltage gear and target gear switching strategy; or receiving a mode recovery command sent by the host, and setting the voltage strategy selection register to the second gear management mode, and setting the voltage gear register to the default voltage gear and the corresponding default gear switching strategy under the second gear management mode.

[0123] The detailed implementation and beneficial effects of each step in the method of this embodiment have been described in detail in the aforementioned embodiments and will not be elaborated here.

[0124] The voltage control and data reading method of the present application will be further described below from the host side and the PCM side in combination with actual application scenarios.

[0125] The host can control the storage controller to enter different modes by issuing the following commands to the storage controller:

[0126] L1 command (i.e., the first mode command mentioned above): This command switches the host firmware control strategy to the controller logic control strategy, i.e., the firmware switching strategy becomes invalid, and the storage controller performs voltage control based on the interval description information.

[0127] L2 command (i.e., the second mode command mentioned above): This command switches the controller logic control strategy to the host firmware control strategy, that is, the storage controller no longer performs voltage control based on the interval description information.

[0128] L0 command (also referred to as the mode restore command above): When the storage controller receives this command, all adjustment commands previously issued by the host to the storage controller are invalid. The storage controller can select the gear strategy according to the power-on initialization configuration. That is, the storage controller restores the second gear management mode configured at power-on initialization of the PCM, as well as the default voltage gear and corresponding default gear switching strategy under the second gear management mode.

[0129] In addition, this solution can also divide the gears into multiple different types according to the write and read interval description information. Different types of gears can correspond to different commands, such as the following commands:

[0130] L3 command corresponds to the write-read cold mode. This mode is suitable for read-after-write scenarios with a latency of 100 seconds or more. This mode can be proactively switched to when data is mostly read with little write activity, or when write bandwidth usage remains low for an extended period. This mode is typically beneficial in long-term stability testing or post-launch scenarios with low load. The write-read hot mode is suitable for read-after-write scenarios with a latency of 300ms or less.

[0131] L4 command: corresponds to the write-read hot gear. This gear is suitable for write-after-read scenarios with a latency of 300ms or less. When data scenarios are mostly write-intensive or when write bandwidth usage is very high for a long time, it can be considered to be actively switched to this scenario. It is usually more advantageous in stress testing or performance comparison scenarios.

[0132] L5 command: corresponds to the write-read temperature range. This range is suitable for write-then-read scenarios with a 300ms to 100s write-read interval. When data scenarios have regular sequential write and read scenarios, the software can determine whether the write-read interval is within this range based on calculations. If so, this range can be set.

[0133] The three gears corresponding to the above L3-L4 commands are only examples of the write-read interval gears mentioned above. In addition, the write-read intervals and application scenarios corresponding to the three gears are only examples and are not limited to this.

[0134] The following describes the host's gear determination process from the host's perspective: In the default state, no operation or cmd (Command Prompt) command is required on the host side. In subsequent processes, the host can send corresponding commands to the storage controller according to the gear adjustment requirements. For example, if it is necessary to return to the firmware default configuration, the host can send the target gear command cmd L0 to the storage controller to adjust the storage controller's control logic to L0. If it is necessary to switch to the L1 policy, the host can send the target gear command cmd L1 to the storage controller to adjust the storage controller's control logic to L1. If it is necessary to switch to the L2 policy, the host can send the target gear command cmd L2 to the storage controller to adjust the storage controller's control logic to L2. If the write bandwidth usage ratio is lower than 5% of the rated bandwidth within 10 minutes, the host can send the target gear command cmd L3 to the storage controller to adjust the storage controller's control logic to L3. If the write bandwidth usage exceeds 60% of the rated bandwidth within 10 minutes, the host can send the target gear command cmdL4 to the storage controller to adjust the storage controller's control logic to L4. If the read interval after a full-disk sequential write is 300ms to 100s, the host can send the target gear command cmdL5 to the storage controller to adjust the storage controller's control logic to L5. If the read interval after a full-disk sequential write is less than 300ms, the host can send the target gear command cmdL4 to the storage controller to adjust the storage controller's control logic to L5. If the read interval after a full-disk sequential write is more than 100s, the host can send the target gear command cmdL3 to the storage controller to adjust the storage controller's control logic to L3.

[0135] The following will be combined Figure 4 From the perspective of the storage controller, the processing logic of the storage controller for the voltage level is explained: In the following embodiment, it is assumed that the PCM supports two-level voltage levels, and the first-level voltage level includes five, namely Va, Vb, Vc, Vd, and Ve; each first-level voltage level includes three second-level voltage levels, which are represented by adding subscripts x, y, and z under the first-level voltage level. Taking the first-level voltage level Vb as an example, it includes second-level voltage levels Vbx, Vby, and Vbz, and others are similar.

[0136] ① The storage controller can power on and check endurance information, selecting any primary voltage level Vb from multiple primary voltage levels (Va, Vb, Vc, Vd, Ve). During operation, if the endurance indicator exceeds the switching threshold specified by the media management policy, the primary voltage level Vb can be switched to the primary voltage level Vd. The switching method described here is only an example, primarily indicating the ability to switch to other voltage levels. ② Based on the media management policy, the default secondary voltage level Vbx is selected from the secondary voltage levels (Vbx, Vby, Vbz) under the default primary voltage level Vb.

[0137] ③When the storage controller receives the host cmd L* command, it can update the firmware policy or switch the first-level voltage gear according to the * value. Specifically, the * in the cmd L* command can be any number from 1 to 5. The number * refers to is different, and the command is also different. For example, when * is 1, the cmd L1 command is the first mode command, which is used to set the read mode to the first gear management mode (firmware mode, FM). Among them, before the gear switching policy takes effect in FM mode, the media management policy adopts the gear switching policy defined in HW mode. After the gear switching policy takes effect in FM mode, the media management policy adopts the gear switching policy defined in FM mode. The gear switching policy defines the switching method between the second-level voltage gears, from the second-level voltage gear to the first-level voltage gear, and between the first-level voltage gears.

[0138] ④ For a single read operation, when rereading after a read failure occurs, the storage controller can switch the current secondary voltage gear to the subsequent secondary voltage gear according to the gear switching strategy defined in the media management strategy, for example, switching from Vbx to Vby and then to Vbz in sequence.

[0139] ⑤ If the read fails twice, switch to the first-level voltage level and try again according to the media management strategy; if this happens more than 5 times, update the first-level voltage level to be used subsequently.

[0140] ⑥ When the reread probability is higher than the preset threshold, the current secondary voltage level can be switched to the subsequent default secondary voltage level according to the media management strategy, or the subsequent primary voltage level can be updated.

[0141] ⑦Logic voltage gear adaptive function switch. When turned on (receiving host cmd L1 or L2), the logic determines the subsequent default gear based on the last successful gear, and the firmware gear configuration register is closed at this time; when turned off, the logic no longer actively updates the gear, but reads the firmware gear configuration register to determine the subsequent voltage gear.

[0142] Among them, the registers in the PCM may include: ① voltage gear register reg_VreadLevel, which is readable and writable by the firmware and is used by the firmware to control the size gear used by the current system. ② voltage strategy selection register reg_VreadHw, which is readable and writable by the firmware and is used to select from two logics of autonomous control voltage and firmware control voltage during firmware initialization. ③ reading count register group, including the following three registers reg_ReadCount (i.e. the first count register in the previous article), reg_ReadRetry1Count (i.e. the second count register in the previous article), reg_ReadRetry2Count (i.e. the third count register in the previous article), which are readable and writable by the firmware and are used to record the total number of reads, the number of successful rereads, and the number of successful rereads; after the firmware reads, the firmware can choose to actively clear this register.

[0143] Here, for write operations, data can be written directly to the memory cell array. Optionally, to facilitate subsequent read operations, it is also possible to detect whether the read mode is FW mode; if so, the relevant registers are set according to the FW mode; if not, the relevant registers can be set according to the HW mode to facilitate subsequent data reading.

[0144] In this embodiment, write-read interval description information can be obtained when an application performs a write-first-then-read data operation on a PCM. The initial voltage level and level switching strategy required for reading data from the PCM's storage cells are determined based on this description information, and data is read from the PCM based on the initial voltage level and level switching strategy. Because the initial voltage level and level switching strategy take into account the write-read interval description information, and because the write-read interval description information can reflect voltage drift factors, not only the initial voltage level is determined, but also the level switching strategy corresponding to the initial voltage level is determined. This allows data to be read from the PCM's storage cells based on the initial voltage level. If the initial voltage level reading fails, a reasonable voltage level switching is performed based on the level switching strategy, which helps increase the probability of successfully reading data from the PCM's storage cells and improves overall data reading efficiency.

[0145] It should be noted that the execution entity of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution entity of steps 301 to 303 can be device A; for another example, the execution entity of steps 301 and 302 can be device A, and the execution entity of step 303 can be device B; and so on.

[0146] In addition, in some of the processes described in the above embodiments and the accompanying drawings, multiple operations that appear in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this article or may be executed in parallel. The sequence numbers of the operations, such as 301, 302, etc., are only used to distinguish between different operations, and the sequence numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this article are used to distinguish different messages, devices, modules, etc., and do not represent the order of precedence, nor do they limit "first" and "second" to be different types.

[0147] Figure 5 FIG1 is a structural diagram of a voltage control device of a phase change memory provided by another exemplary embodiment of the present application. Figure 5 As shown, the device includes: a prediction module 501, configured to, in response to a preset trigger event, predict write / read interval description information for a target application performing a write-first-then-read operation on a PCM within a future time period, where the target application is an application on the host that uses the PCM for data access. A delivery module 502, configured to deliver the write / read interval description information to a storage controller in the PCM, so that the storage controller configures the initial voltage level required to read data from the storage cells in the PCM and the corresponding target level switching strategy based on the write / read interval description information.

[0148] Optionally, the prediction module 501 responds to a preset trigger event and predicts the write-read interval description information of the target application when performing a write-first-then-read operation on the PCM in a future time period. It is used to: respond to the preset trigger event and predict the write-read interval description information based on the application type, application scenario and / or historical write-read operation information of the target application.

[0149] Optionally, when the prediction module 501 responds to a preset trigger event and predicts the write-read interval description information based on the historical write-read operation information of the target application, it is specifically used to: respond to the preset trigger event, count the first bandwidth ratio of the historical write operations of the target application within the first set time range in the historical write-read operations; predict the write-read interval description information based on the first bandwidth ratio; and / or, respond to the preset trigger event, count the second bandwidth ratio of the historical read operations of the target application within the first set time range in the historical write-read operations; predict the write-read interval description information based on the second bandwidth ratio; and / or, respond to the preset trigger event, count the time interval between the historical write operation and the first historical read operation of the target application for the same data within the second preset time range, and predict the write-read interval description information based on the time interval.

[0150] Optionally, the preset trigger events include: a resource scheduling event that allocates PCM to the target application; and / or an event in which the target application switches the working mode during the use of PCM; and / or an event in which the target application uses PCM for a time greater than a set time threshold.

[0151] Optionally, the PCM supports multiple write-read interval gears, different write-read interval gears correspond to different gear commands, and one write-read interval gear corresponds to a voltage gear range; the sending module 502 sends the write-read interval description information to the storage controller in the PCM, so that the storage controller configures the initial voltage gear required to read data from the storage unit in the PCM and the corresponding target gear switching strategy according to the write-read interval description information, specifically used for: determining the target write-read interval gear that is compatible with the write-read interval description information from multiple write-read interval gears; sending the target gear command corresponding to the target write-read interval gear to the storage controller, so that the storage controller configures the initial voltage gear and the corresponding target gear switching strategy according to the voltage gear range corresponding to the target write-read interval gear.

[0152] Optionally, before sending the write-read interval description information to the storage controller in the PCM, the sending module 502 is also used to: send a first mode command to the storage controller to make the storage controller operate in the first gear management mode. The first gear management mode refers to a mode that relies on the write-read interval description information to configure the initial voltage gear and target gear switching strategy.

[0153] Optionally, the sending module 502 is also used to: send a second mode command to the storage controller to make the storage controller operate in the second gear management mode, the second gear management mode refers to a mode that does not rely on write-read interval description information to configure the initial voltage gear and target gear switching strategy; or, send a mode recovery command to the storage controller to make the storage controller restore the second gear management mode of the PCM power-on initialization configuration and the default voltage gear and the corresponding default gear switching strategy under the second gear management mode.

[0154] In this embodiment, write-read interval description information can be obtained when an application performs a write-first-then-read data operation on a PCM. The initial voltage level and level switching strategy required for reading data from the PCM's storage cells are determined based on this description information, and data is read from the PCM based on the initial voltage level and level switching strategy. Because the initial voltage level and level switching strategy take into account the write-read interval description information, and because the write-read interval description information can reflect voltage drift factors, not only the initial voltage level is determined, but also the level switching strategy corresponding to the initial voltage level is determined. This allows data to be read from the PCM's storage cells based on the initial voltage level. If the initial voltage level reading fails, a reasonable voltage level switching is performed based on the level switching strategy, which helps increase the probability of successfully reading data from the PCM's storage cells and improves overall data reading efficiency.

[0155] Figure 6 This is a structural diagram of a data reading device for a phase change memory provided by another exemplary embodiment of the present application. Figure 6 As shown, the device includes: a receiving module 601, used to receive write-read interval description information sent by a host when a target application performs a write-first-then-read operation on a PCM in a future time period, and the target application is an application on the host that uses the PCM to access data; a configuration module 602, used to configure the initial voltage level and the corresponding target level switching strategy required when reading data from a storage unit in the PCM according to the write-read interval description information; a reading module 603, used to read data from the storage unit of the PCM based on the initial voltage level and the corresponding target level switching strategy when receiving a read command from the target application.

[0156] Optionally, PCM supports multiple write-read interval gears, and different write-read interval gears correspond to different gear commands; when the receiving module 601 receives the write-read interval description information sent by the host when the target application performs a write-first-then-read operation on the PCM in a future time period, it is specifically used to: receive the target gear command issued by the host, the target gear command corresponds to the target write-read interval gear, and the target write-read interval gear is a write-read interval gear among multiple write-read interval gears that is adapted to the write-read interval description information.

[0157] Optionally, a write-read interval gear corresponds to a voltage gear range, and the voltage gear range includes multiple voltage gears. The configuration module 602 configures the initial voltage gear and the corresponding gear switching strategy required when reading data from the storage unit in the PCM according to the write-read interval description information. It is specifically used to: determine the initial voltage gear and the corresponding target gear switching strategy according to the multiple voltage gears in the target voltage gear range corresponding to the target write-read interval gear; write the initial voltage gear and the corresponding target gear switching strategy into the voltage gear register to provide them to the read circuit responsible for reading data from the storage unit in the PCM.

[0158] Optionally, a default voltage gear is set in a voltage gear range, and the default voltage gear corresponds to a gear switching strategy; when the configuration module 602 configures the initial voltage gear and the corresponding gear switching strategy according to multiple voltage gears in the target voltage gear range corresponding to the target write-read interval gear, it is specifically used to: use the default voltage gear in the target voltage gear range and its corresponding gear switching strategy as the initial voltage gear and the target gear switching strategy, respectively.

[0159] Optionally, a voltage gear range includes multiple first-level voltage gears, a first-level voltage gear includes multiple second-level voltage gears, and the second-level voltage gear is smaller than the first-level voltage gear to which it belongs; when the configuration module 602 uses the default voltage gear in the target voltage gear range and its corresponding gear switching strategy as the initial voltage gear and the target gear switching strategy, respectively, it is specifically used to: use the default first-level voltage gear in the target voltage gear range and the default second-level voltage gear below the default first-level voltage gear as the initial voltage gear; use the gear switching strategy corresponding to the default first-level voltage gear and the gear switching strategy corresponding to the default second-level voltage gear as the target gear switching strategy.

[0160] Optionally, when the read module 603 receives a read command from the target application, it reads data from the storage unit of the PCM based on the initial voltage level and the corresponding target level switching strategy. Specifically, it is used to: when the read command from the target application is received, control the read circuit to read data from the storage unit of the PCM based on the initial voltage level; and, when the number of read failures meets the switching condition, switch to a new initial voltage level from the target voltage level range according to the target level switching strategy, and control the read circuit to continue to read data from the storage unit of the PCM based on the new initial voltage level.

[0161] Optionally, the reading module 603 is also used to: obtain the number information written by the reading circuit in the first number register, the second number register and / or the third number register; based on the number information, determine whether the number of read failures meets the switching condition; wherein, the number of read operations recorded in the first number register, the number of successful rereads N times recorded in the second number register, and the number of successful rereads M times recorded in the third number register; N and M are positive integers, and N is less than M.

[0162] Optionally, before receiving the write-read interval description information sent by the host, the receiving module 601 is also used to: receive the first mode command issued by the host, and set the voltage strategy selection register to the first gear management mode. The first gear management mode refers to a mode that relies on the write-read interval description information to configure the initial voltage gear and target gear switching strategy.

[0163] Optionally, the receiving module 601 is also used to: receive a second mode command sent by the host, and set the voltage strategy selection register to the second gear management mode, where the second gear management mode refers to a mode that does not rely on write-read interval description information to configure the initial voltage gear and target gear switching strategy; or receive a mode recovery command sent by the host, and set the voltage strategy selection register to the second gear management mode, and set the voltage gear register to the default voltage gear and the corresponding default gear switching strategy under the second gear management mode.

[0164] In this embodiment, write-read interval description information can be obtained when an application performs a write-first-then-read data operation on a PCM. The initial voltage level and level switching strategy required for reading data from the PCM's storage cells are determined based on this description information, and data is read from the PCM based on the initial voltage level and level switching strategy. Because the initial voltage level and level switching strategy take into account the write-read interval description information, and because the write-read interval description information can reflect voltage drift factors, not only the initial voltage level is determined, but also the level switching strategy corresponding to the initial voltage level is determined. This allows data to be read from the PCM's storage cells based on the initial voltage level. If the initial voltage level reading fails, a reasonable voltage level switching is performed based on the level switching strategy, which helps increase the probability of successfully reading data from the PCM's storage cells and improves overall data reading efficiency.

[0165] The above describes the internal function and structure of the voltage control device of the phase change memory. Figure 7 As shown, in practice, the voltage control device of the phase change memory can be implemented as a host device, which includes: a memory 701 , a processor 702 and a communication component 703 .

[0166] Memory 701 is used to store computer programs and can be configured to store various other data to support operations on the host device. Examples of such data include instructions for any application or method operating on the host device, contact data, phone book data, messages, pictures, videos, etc.

[0167] The memory 701 can be implemented by any type of volatile or non-volatile memory device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0168] The processor 702 is coupled to the memory 701 and is used to execute a computer program in the memory 701, so as to: respond to a preset trigger event, predict write-read interval description information when a target application performs a write-first-then-read operation on the PCM in a future time period, wherein the target application is an application on the host that uses the PCM to access data; and send the write-read interval description information to a storage controller in the PCM, so that the storage controller configures an initial voltage level and a corresponding target level switching strategy required for reading data from a storage unit in the PCM according to the write-read interval description information.

[0169] Optionally, when the processor 702 responds to a preset trigger event and predicts the write-read interval description information of the target application when performing a write-first-then-read operation on the PCM in a future time period, it is used to: respond to the preset trigger event and predict the write-read interval description information based on the application type, application scenario and / or historical write-read operation information of the target application.

[0170] Optionally, when the processor 702 responds to a preset trigger event and predicts the write-read interval description information based on the historical write-read operation information of the target application, it is specifically used to: respond to the preset trigger event, count the first bandwidth ratio of the historical write operations of the target application within a first set time range in the historical write-read operations; predict the write-read interval description information based on the first bandwidth ratio; and / or, respond to the preset trigger event, count the second bandwidth ratio of the historical read operations of the target application within the first set time range in the historical write-read operations; predict the write-read interval description information based on the second bandwidth ratio; and / or, respond to the preset trigger event, count the time interval between the historical write operations and the first historical read operations of the target application for the same data within a second preset time range, and predict the write-read interval description information based on the time interval.

[0171] Optionally, the preset trigger events include: a resource scheduling event that allocates PCM to the target application; and / or an event in which the target application switches the working mode during the use of PCM; and / or an event in which the target application uses PCM for a time greater than a set time threshold.

[0172] Optionally, the PCM supports multiple write-read interval gears, different write-read interval gears correspond to different gear commands, and one write-read interval gear corresponds to a voltage gear range; the processor 702 sends the write-read interval description information to the storage controller in the PCM, so that the storage controller configures the initial voltage gear required to read data from the storage unit in the PCM and the corresponding target gear switching strategy according to the write-read interval description information, specifically used to: determine the target write-read interval gear that is compatible with the write-read interval description information from multiple write-read interval gears; send the target gear command corresponding to the target write-read interval gear to the storage controller, so that the storage controller configures the initial voltage gear and the corresponding target gear switching strategy according to the voltage gear range corresponding to the target write-read interval gear.

[0173] Optionally, before sending the write-read interval description information to the storage controller in the PCM, the processor 702 is also used to: send a first mode command to the storage controller to make the storage controller operate in a first gear management mode, and the first gear management mode refers to a mode that relies on the write-read interval description information to configure the initial voltage gear and target gear switching strategy.

[0174] Optionally, the processor 702 is also used to: send a second mode command to the storage controller to enable the storage controller to operate in the second gear management mode, where the second gear management mode refers to a mode that does not rely on write-read interval description information to configure the initial voltage gear and target gear switching strategy; or, send a mode recovery command to the storage controller to enable the storage controller to restore the second gear management mode of the PCM power-on initialization configuration and the default voltage gear and the corresponding default gear switching strategy under the second gear management mode.

[0175] Further, if Figure 7 As shown, the host device also includes: a display 704, a power supply component 705 and other components. Figure 7 Only some components are shown schematically, which does not mean that the host device only includes Figure 7 In addition, Figure 7 The components in the dotted box are optional components, not mandatory components, and the specific components may depend on the product form of the host device. The host device of this embodiment can be implemented as a terminal device such as a desktop computer, laptop computer, smart phone or IOT device, or a server device such as a conventional server, cloud server or server array. If the host device of this embodiment is implemented as a terminal device such as a desktop computer, laptop computer, smart phone, etc., it can include Figure 7 If the host device of this embodiment is implemented as a conventional server, cloud server or server array and other server-side devices, it may not include Figure 7 Components within the dotted box.

[0176] In this embodiment, write-read interval description information can be obtained when an application performs a write-first-then-read data operation on a PCM. The initial voltage level and level switching strategy required for reading data from the PCM's storage cells are determined based on this description information, and data is read from the PCM based on the initial voltage level and level switching strategy. Because the initial voltage level and level switching strategy take into account the write-read interval description information, and because the write-read interval description information can reflect voltage drift factors, not only the initial voltage level is determined, but also the level switching strategy corresponding to the initial voltage level is determined. This allows data to be read from the PCM's storage cells based on the initial voltage level. If the initial voltage level reading fails, a reasonable voltage level switching is performed based on the level switching strategy, which helps increase the probability of successfully reading data from the PCM's storage cells and improves overall data reading efficiency.

[0177] The above describes the internal function and structure of the data reading device of the phase change memory. Figure 8 As shown, in practice, the data reading device of the phase change memory PCM can be implemented as a PCM, including: a storage unit 801 for storing data and a storage controller 802 for performing storage control on the storage unit; the storage controller 802 includes: a processor 8021 and a memory 8022, the memory storing the firmware program of the phase change memory, and the processor for executing the firmware program to implement the steps in the data reading method of the phase change memory PCM.

[0178] The memory 8022 is used to store computer programs and can be configured to store various other data to support operations on the computing platform. Examples of such data include instructions for any application or method operating on the computing platform, contact data, phone book data, messages, images, videos, etc.

[0179] The processor 8021 and the memory 8022 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0180] The processor 8021 is coupled to the memory 8022 and is used to execute a computer program in the memory 8022, so as to: receive write-read interval description information sent by a host when a target application performs a write-first-then-read operation on the PCM in a future time period, wherein the target application is an application on the host that uses the PCM to access data; configure an initial voltage level and a corresponding target level switching strategy required when reading data from a storage unit in the PCM according to the write-read interval description information; and upon receiving a read command from the target application, read data from the storage unit of the PCM based on the initial voltage level and the corresponding target level switching strategy.

[0181] Optionally, PCM supports multiple write-read interval gears, and different write-read interval gears correspond to different gear commands; when the processor 8021 receives the write-read interval description information sent by the host when the target application performs a write-first-then-read operation on the PCM in a future time period, it is specifically used to: receive the target gear command sent by the host, the target gear command corresponds to the target write-read interval gear, and the target write-read interval gear is a write-read interval gear among multiple write-read interval gears that is adapted to the write-read interval description information.

[0182] Optionally, a write-read interval gear corresponds to a voltage gear range, and the voltage gear range includes multiple voltage gears. When the processor 8021 configures the initial voltage gear and the corresponding gear switching strategy required when reading data from the storage unit in the PCM according to the write-read interval description information, it is specifically used to: determine the initial voltage gear and the corresponding target gear switching strategy according to the multiple voltage gears in the target voltage gear range corresponding to the target write-read interval gear; write the initial voltage gear and the corresponding target gear switching strategy into the voltage gear register to provide them to the read circuit responsible for reading data from the storage unit in the PCM.

[0183] Optionally, a default voltage gear is set in a voltage gear range, and the default voltage gear corresponds to a gear switching strategy; when the processor 8021 configures the initial voltage gear and the corresponding gear switching strategy according to multiple voltage gears in the target voltage gear range corresponding to the target write-read interval gear, it is specifically used to: use the default voltage gear in the target voltage gear range and its corresponding gear switching strategy as the initial voltage gear and the target gear switching strategy, respectively.

[0184] Optionally, a voltage gear range includes multiple first-level voltage gears, a first-level voltage gear includes multiple second-level voltage gears, and the second-level voltage gear is smaller than the first-level voltage gear to which it belongs; when the processor 8021 uses the default voltage gear in the target voltage gear range and its corresponding gear switching strategy as the initial voltage gear and the target gear switching strategy, respectively, it is specifically used to: use the default first-level voltage gear in the target voltage gear range and the default second-level voltage gear below the default first-level voltage gear as the initial voltage gear; use the gear switching strategy corresponding to the default first-level voltage gear and the gear switching strategy corresponding to the default second-level voltage gear as the target gear switching strategy.

[0185] Optionally, when the processor 8021 receives a read command from the target application, it reads data from the storage unit of the PCM based on the initial voltage level and the corresponding target level switching strategy. Specifically, it is used to: when receiving a read command from the target application, control the read circuit to read data from the storage unit of the PCM based on the initial voltage level; and, when the number of read failures meets the switching condition, switch to a new initial voltage level from the target voltage level range according to the target level switching strategy, and control the read circuit to continue to read data from the storage unit of the PCM based on the new initial voltage level.

[0186] Optionally, the processor 8021 is also used to: obtain the number information written by the reading circuit in the first number register, the second number register and / or the third number register; based on the number information, determine whether the number of read failures meets the switching condition; wherein, the number of read operations recorded in the first number register, the number of successful rereads N times recorded in the second number register, and the number of successful rereads M times recorded in the third number register; N and M are positive integers, and N is less than M.

[0187] Optionally, before receiving the write-read interval description information sent by the host, the processor 8021 is also used to: receive the first mode command issued by the host, and set the voltage strategy selection register to the first gear management mode. The first gear management mode refers to a mode that relies on the write-read interval description information to configure the initial voltage gear and target gear switching strategy.

[0188] Optionally, the processor 8021 is also used to: receive a second mode command sent by the host, and set the voltage strategy selection register to the second gear management mode, where the second gear management mode refers to a mode that does not rely on write-read interval description information to configure the initial voltage gear and target gear switching strategy; or receive a mode recovery command sent by the host, and set the voltage strategy selection register to the second gear management mode, and set the voltage gear register to the default voltage gear and the corresponding default gear switching strategy under the second gear management mode.

[0189] Further, if Figure 8 As shown, the PCM further includes: a power supply component 804 and other components. Figure 8 Only some components are shown schematically, which does not mean that the host only includes Figure 8 In addition, Figure 8 The components in the dotted box are optional components, not mandatory components, and the specific components depend on the product form of the working node. The working node of this embodiment can be implemented as a terminal device such as a desktop computer, laptop computer, smart phone or IOT device, or a server device such as a conventional server, cloud server or server array. If the working node of this embodiment is implemented as a terminal device such as a desktop computer, laptop computer, smart phone, etc., it can include Figure 8 If the working node of this embodiment is implemented as a server device such as a conventional server, a cloud server or a server array, it may not include Figure 8 Components within the dotted box.

[0190] In this embodiment, write-read interval description information can be obtained when an application performs a write-first-then-read data operation on a PCM. The initial voltage level and level switching strategy required for reading data from the PCM's storage cells are determined based on this description information, and data is read from the PCM based on the initial voltage level and level switching strategy. Because the initial voltage level and level switching strategy take into account the write-read interval description information, and because the write-read interval description information can reflect voltage drift factors, not only the initial voltage level is determined, but also the level switching strategy corresponding to the initial voltage level is determined. This allows data to be read from the PCM's storage cells based on the initial voltage level. If the initial voltage level reading fails, a reasonable voltage level switching is performed based on the level switching strategy, which helps increase the probability of successfully reading data from the PCM's storage cells and improves overall data reading efficiency.

[0191] An embodiment of the present application also provides a storage controller, which is applied to a phase change memory and is used to control the storage of storage units in the phase change memory. The storage controller includes: a processor and a memory, wherein the memory stores a firmware program of the phase change memory, and the processor is used to execute the firmware program to implement the steps in the data reading method of the phase change memory PCM.

[0192] Accordingly, an embodiment of the present application further provides a computer-readable storage medium storing a computer program, which, when executed, can implement the steps that can be executed by the host and / or PCM in the above method embodiment.

[0193] An embodiment of the present application further provides a computer program product, comprising: a computer program / instruction, which, when executed by a processor, causes the processor to implement the steps in the data reading method and / or voltage control method of a phase change memory.

[0194] The above-mentioned memory can be implemented by any type of volatile or non-volatile memory device or a combination thereof, such as static random-access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0195] The above-mentioned communication component is configured to facilitate wired or wireless communication between the device where the communication component is located and other devices. The device where the communication component is located can access a wireless network based on a communication standard, such as WiFi, 2G, 3G, 4G / LTE, 5G and other mobile communication networks, or a combination thereof. In an exemplary embodiment, the communication component receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra wide band (UWB) technology, Bluetooth (BT) technology and other technologies.

[0196] The above-mentioned display includes a screen, which may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor can not only sense the boundary of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation.

[0197] The power supply assembly provides power to various components of the device in which the power supply assembly is located. The power supply assembly may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which the power supply assembly is located.

[0198] The above-mentioned audio component can be configured to output and / or input audio signals. For example, the audio component includes a microphone (MIC), and when the device where the audio component is located is in an operating mode, such as call mode, recording mode, and voice recognition mode, the microphone is configured to receive external audio signals. The received audio signal can be further stored in a memory or sent via a communication component. In some embodiments, the audio component also includes a speaker for outputting audio signals.

[0199] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to magnetic disk storage, compact disc read-only memory (CD-ROM), optical storage, etc.) that contain computer-usable program code.

[0200] The present application is described with reference to the flow chart and / or block diagram of the method, device (system), and computer program product according to the embodiment of the present application. It should be understood that each flow process and / or box in the flow chart and / or block diagram and the combination of the flow process and / or box in the flow chart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processing machine or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for realizing the function specified in one flow chart flow or multiple flows and / or one box or multiple boxes of the block diagram.

[0201] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0202] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0203] In a typical configuration, a computing device includes one or more processors (Central Processing Unit, CPU), input / output interfaces, network interfaces, and memory.

[0204] Memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0205] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be used to store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change random access memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media such as modulated data signals and carrier waves.

[0206] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0207] The above are merely embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A voltage control method for a phase change memory (PCM), characterized in that: Applied to a host, the method includes: In response to a preset trigger event, predicting description information of a write-read interval when a target application performs a data write-then-read operation on a PCM in a future time period, wherein the target application is an application on the host that uses the PCM to access data; The write-read interval description information is sent to the storage controller in the PCM, so that the storage controller configures the initial voltage level and the corresponding target level switching strategy required for reading data from the storage unit in the PCM according to the write-read interval description information.

2. The method according to claim 1, characterized in that In response to a preset trigger event, the target application is predicted to write and read data to the PCM in the future. The interval description information includes: In response to a preset trigger event, the write-read interval description information is predicted according to the application type, application scenario and / or historical write-read operation information of the target application.

3. The method according to claim 2, characterized in that In response to a preset trigger event, predicting the write-read interval description information based on historical write-read operation information of the target application includes: In response to a preset trigger event, counting a first bandwidth proportion of historical write operations of the target application in historical write and read operations within a first set time range; and predicting the write-read interval description information based on the first bandwidth proportion; and / or In response to a preset trigger event, counting a second bandwidth ratio of historical read operations of the target application in historical write and read operations within a first set time range; and predicting the write-read interval description information based on the second bandwidth ratio; and / or In response to a preset trigger event, the time interval between the historical write operation and the first historical read operation of the target application for the same data within a second preset time range is counted, and the write-read interval description information is predicted based on the time interval.

4. The method according to claim 1, wherein The preset triggering events include: A resource scheduling event in which the PCM is allocated to the target application; and / or an event in which the target application switches its working mode during use of the PCM; and / or an event in which the target application uses the PCM for a time greater than a set duration threshold.

5. The method according to any one of claims 1 to 4, characterized in that The PCM supports multiple write and read interval gears, different write and read interval gears correspond to different gear commands, and one write and read interval gear corresponds to one voltage gear range; Sending the write-read interval description information to a storage controller in the PCM so that the storage controller configures an initial voltage level and a corresponding target level switching strategy required for reading data from a storage unit in the PCM according to the write-read interval description information, including: Determining a target write-read interval gear adapted to the write-read interval description information from the plurality of write-read interval gears; A target gear command corresponding to the target write-read interval gear is issued to the storage controller, so that the storage controller configures an initial voltage gear and a corresponding target gear switching strategy according to a voltage gear range corresponding to the target write-read interval gear.

6. The method according to any one of claims 1 to 4, characterized in that Before sending the write-read interval description information to the storage controller in the PCM, the method further includes: A first mode command is issued to the storage controller to enable the storage controller to operate in a first gear management mode, wherein the first gear management mode refers to a mode for configuring an initial voltage gear and a target gear switching strategy based on write-read interval description information.

7. The method according to claim 6, characterized in that Also includes: issuing a second mode command to the storage controller to enable the storage controller to operate in a second gear management mode, wherein the second gear management mode is a mode in which the initial voltage gear and the target gear switching strategy are configured without relying on the write-read interval description information; or A mode recovery command is issued to the storage controller to enable the storage controller to restore the second gear management mode configured by the PCM power-on initialization, the default voltage gear in the second gear management mode, and the corresponding default gear switching strategy.

8. A method for reading data from a phase change memory (PCM), characterized in that: Applied to a storage controller in the PCM, the method comprises: receiving, from a host, description information of a write-read interval when a target application performs a data write-first-then-read operation on a PCM in a future time period, the target application being an application on the host that uses the PCM to access data; According to the write-read interval description information, configuring the initial voltage level and the corresponding target level switching strategy required when reading data from the storage unit in the PCM; and When a read command of the target application is received, data is read from a storage unit of the PCM based on the initial voltage level and the corresponding target level switching strategy.

9. The method according to claim 8, characterized in that The PCM supports multiple write and read interval gears, and different write and read interval gears correspond to different gear commands; The host receives the write-read interval description information of the target application when performing a write-first-then-read operation on the PCM data in the future period, including: A target gear command sent by the host is received, where the target gear command corresponds to a target write-read interval gear, and the target write-read interval gear is a write-read interval gear among the multiple write-read interval gears that is adapted to the write-read interval description information.

10. The method according to claim 9, characterized in that A write / read interval gear corresponds to a voltage gear range, and the voltage gear range includes multiple voltage gears. Then, according to the write / read interval description information, the initial voltage gear required for reading data from the storage unit in the PCM and the corresponding gear switching strategy are configured, including: Determining an initial voltage level and a corresponding target level switching strategy according to a plurality of voltage levels in a target voltage level range corresponding to the target write / read interval level; The initial voltage gear and the corresponding target gear switching strategy are written into a voltage gear register to be provided to a reading circuit responsible for reading data from a storage unit in the PCM.

11. The method according to claim 10, characterized in that A default voltage gear is set in a voltage gear range, and the default voltage gear corresponds to a gear switching strategy; Configuring an initial voltage level and a corresponding level switching strategy according to a plurality of voltage levels in a target voltage level range corresponding to the target write / read interval level includes: The default voltage level in the target voltage level range and its corresponding level switching strategy are used as the initial voltage level and the target level switching strategy, respectively.

12. The method according to claim 11, characterized in that A voltage range includes multiple first-level voltage ranges, and a first-level voltage range includes multiple second-level voltage ranges. The second-level voltage range is smaller than the first-level voltage range to which it belongs. The default voltage level in the target voltage level range and its corresponding level switching strategy are used as the initial voltage level and the target level switching strategy, respectively, including: The default first voltage level and the default second voltage level below the default first voltage level in the target voltage level range are used as the initial voltage level; The gear switching strategy corresponding to the default first-level voltage gear and the gear switching strategy corresponding to the default second-level voltage gear are used as the target gear switching strategy.

13. The method according to any one of claims 10 to 12, characterized in that: Upon receiving a read command from the target application, reading data from a storage unit of the PCM based on the initial voltage level and the corresponding target level switching strategy includes: Upon receiving a read command from the target application, controlling the read circuit to read data from a storage unit of the PCM based on the initial voltage level; and When the number of read failures meets the switching condition, a new initial voltage level is switched from the target voltage level range according to the target level switching strategy, and the reading circuit is controlled to continue reading data from the storage unit of the PCM based on the new initial voltage level.

14. The method according to claim 13, wherein: Also includes: Acquire the number of times information written by the reading circuit into the first number register, the second number register and / or the third number register; According to the number information, determining whether the number of read failures meets the switching condition; Among them, the number of read operations recorded in the first number register, the number of successful reads after N rereads recorded in the second number register, and the number of successful reads after M rereads recorded in the third number register; N and M are positive integers, and N is less than M.

15. A host, characterized in that: include: memory and processor; The memory is used to store a computer program, and the processor is coupled to the memory and is used to execute the computer program to implement the steps in the method according to any one of claims 1 to 7.

16. A phase change memory, characterized in that: include: A storage unit for storing data and a storage controller for performing storage control on the storage unit; The storage controller includes: a processor and a memory, wherein the memory stores a firmware program of the phase change memory, and the processor is configured to execute the firmware program to implement the steps of the method according to any one of claims 8 to 14.

17. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the processor is caused to implement the steps of the method according to any one of claims 1 to 7 and claims 8 to 14.

18. A computer program product, characterized in that include: A computer program / instruction, when executed by a processor, causes the processor to implement the steps of the method according to any one of claims 1 to 7 and claims 8 to 14.

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