A multi-scale cue fusion device and multi-stimulus competition system based on memristor

Abstract

This invention belongs to the technical field of biomimetic circuit design, and discloses a multi-scale cue fusion device and a multi-stimulus competition system based on memristors. The fusion device includes: a state generation module, which includes a volatile memristor, a positive correlation mapping circuit, and a state comparison circuit; a stimulus intensity processing module, which includes a memristor circuit, a subtraction circuit, and a stimulus comparison circuit; a context-related processing module, which includes a context gating circuit, a memristor, a context comparison circuit, a latch, and a shaping circuit; a state feedback module, which includes a state gating circuit; and a fusion module, which is used to perform weighted summation of voltages and output a fusion significance voltage. Based on the above design, it can more realistically reflect the biological process of processing multi-scale information, obtain the true perception of stimuli by the biological body under the comprehensive influence of multi-scale information, and provide biomimetic accuracy. Moreover, the introduction of memristors in this invention can improve the processing speed of the device.

Description

Technical Field

[0001] This invention belongs to the technical field of biomimetic circuit design, and more specifically, relates to a multi-scale cue fusion device and a multi-stimulus competition system based on memristors. Background Technology

[0002] In complex and dynamic environments, organisms rely on information at multiple scales (such as the intensity of physical stimuli, contextual relevance, and internal state) to selectively process information and thus make adaptive behaviors. This adaptive sensory processing mechanism is an important part of the cognitive process and has important implications for artificial systems simulating biological intelligence. However, traditional artificial circuits often struggle to process multi-scale, multi-dimensional input information simultaneously and make choices quickly and accurately with limited resources. Furthermore, while existing digital logic-based systems have high accuracy in information processing, they are limited in terms of energy consumption, integration, and real-time adaptability to dynamic information. Summary of the Invention

[0003] To address the aforementioned deficiencies or improvement needs of existing technologies, this invention provides a multi-scale cue fusion device and a multi-stimulus competition system based on memristors. Its purpose is to rapidly and accurately simulate the real perception of stimuli by organisms under the comprehensive influence of multi-scale information, thereby providing biomimetic accuracy.

[0004] To achieve the above objectives, according to a first aspect of the present invention, a memristor-based multi-scale clue fusion device is provided, comprising:

[0005] The state generation module includes a volatile memristor VM1, a positive correlation mapping circuit, and a state comparison circuit. The memristor VM1 receives a reward voltage; it is in a high-resistance state when no reward voltage is applied and its resistance gradually decreases during the application of the reward voltage. The positive correlation mapping circuit maps the resistance of VM1 to a voltage. The comparison circuit compares the mapped voltage with a state threshold voltage and outputs a starvation state voltage. When the mapped voltage exceeds the state threshold voltage, the output is high; otherwise, it is low.

[0006] The stimulation intensity processing module includes a memristor circuit, a subtraction circuit, and a stimulation comparison circuit. The memristor circuit adjusts memristor M1 based on the hunger state voltage. When the hunger state voltage is high, M1 is set to a low-impedance state to output a high level; otherwise, M1 is reset to a high-impedance state to output a low level. The subtraction circuit calculates the voltage difference between the set voltage and the output voltage of M1. The adjustable threshold voltage of the stimulation comparison circuit is positively correlated with the voltage difference and is used to receive the stimulation voltage and compare it with the adjustable threshold voltage. When the stimulation voltage is greater than the adjustable threshold voltage, a physical intensity voltage positively correlated with the stimulation voltage is output; otherwise, the physical intensity voltage remains low.

[0007] The context-dependent processing module includes a context gating circuit, a memristor M2, a context comparator circuit, a latch, and a shaping circuit. Specifically: the context gating circuit receives the context voltage and is controlled by the physical strength voltage; the context comparator circuit compares the output voltage of M2 with a set context threshold voltage; when the context gating circuit is on, the context voltage is applied to M2; if the context voltage does not reach the set threshold, M2 is in a high-impedance state, and the context comparator outputs a low level; otherwise, M2 is set to a low-impedance state, and the context comparator outputs a high level; the latch latches the output voltage of the context comparator; and the shaping circuit performs a logical AND operation on the latch output voltage and the physical strength voltage to output the context-dependent voltage.

[0008] The state feedback module includes a state gate circuit that receives physical strength voltage and is controlled by a starvation state voltage, and outputs an internal state voltage when the state gate circuit is turned on.

[0009] The fusion module is used to perform a weighted summation of physical strength voltage, context-dependent voltage, and internal state voltage, and output the fusion significance voltage.

[0010] Optionally, in the state generation module, the positive correlation mapping circuit includes operational amplifier OP3, resistor R7, and voltage calculation module ABM1, which is used to calculate the voltage difference between different input voltages; the state comparison circuit includes operational amplifier OP4; wherein,

[0011] The first terminal of memristor VM1 and the second terminal of voltage calculation module ABM1 are respectively used to connect the reward voltage V. i The second terminal of memristor VM1 is connected to the first terminal of resistor R7 and the negative input terminal of operational amplifier OP3. The positive input terminal of operational amplifier OP3 is grounded. The output terminal of operational amplifier OP3 is connected to the second terminal of resistor R7 and the first terminal of voltage calculation module ABM1. The output terminal of voltage calculation module ABM1 is connected to the positive input terminal of operational amplifier OP4. The negative input terminal of operational amplifier OP4 is connected to the state threshold voltage V. th s When connected, the output of operational amplifier OP4 outputs a starved state voltage.

[0012] Optionally, in the stimulus intensity processing module, the memristor circuit includes an adder A1, a logic gate D1, a memristor M1, and an NMOS transistor N1; the logic gate D1 is an NOT gate; wherein,

[0013] The first input terminal of adder A1 and the input terminal of logic gate D1 are respectively connected to the starvation state voltage. The output terminal of logic gate D1 is connected to the gate of NMOS transistor N1, and the drain of NMOS transistor N1 is connected to the memristor reset voltage V. rThe source of NMOS transistor N1 is connected to the second input terminal of adder A1, the output terminal of adder A1 is connected to the first terminal of memristor M1, and the second terminal of memristor M1 is connected to the subtraction circuit.

[0014] Optionally, in the stimulus intensity processing module, the subtraction circuit includes resistors R1, R2, and R3, and operational amplifier OP1; the stimulus comparison circuit includes NMOS transistor N2, resistors R4 and R5, and PMOS transistor P1; wherein,

[0015] The second terminal of memristor M1 and the first terminal of resistor R1 are connected to the negative input terminal of operational amplifier OP1, respectively. The second terminal of resistor R1 is connected to the output terminal of operational amplifier OP1. The second terminal of resistor R2 and the first terminal of resistor R3 are both connected to the positive input terminal of the first amplifier OP1. The first terminal of resistor R2 is used to connect the stimulation threshold voltage V. th_p The second terminal of resistor R3 is grounded;

[0016] The source of NMOS transistor N2 is connected to the output of operational amplifier OP1. The gate of NMOS transistor N2 and the source of PMOS transistor P1 are used to connect the stimulation voltage V. s1 The drain of N2, the gate of P1, and the first terminal of R4 are connected, and the second terminal of R4 is grounded. The drain of P1 is connected to the first terminal of R5, and the second terminal of R5 is grounded. The drain of P1 outputs a physical strength voltage.

[0017] Optionally, in the context-related processing module, the context gating circuit includes logic gate D2, PMOS transistor P2, and NMOS transistor N3; logic gate D2 is an NOT gate; the context comparison circuit includes resistor R6 and operational amplifier OP2; wherein,

[0018] The input of logic gate D2 and the gate of NMOS transistor N3 are both connected to the physical strength voltage. The output of logic gate D2 is connected to the gate of PMOS transistor P2. The drain of NMOS transistor N3 and the source of PMOS transistor P2 are respectively connected to the application voltage V. c The source of NMOS transistor N3 and the drain of PMOS transistor P2 are connected to the first terminal of memristor M2. The second terminal of memristor M2 and the first terminal of resistor R6 are connected to the positive input terminal of operational amplifier OP2. The second terminal of resistor R6 is grounded. The negative input terminal of operational amplifier OP2 is used to connect the scenario threshold voltage V. th_c The output of operational amplifier OP2 is connected to a latch.

[0019] Optionally, in the state feedback module, the state gating circuit includes logic gate D6, NMOS transistor N4, and PMOS transistor P3; logic gate D6 is an NOT gate; wherein,

[0020] The input of logic gate D6 and the gate of NMOS transistor N4 are both connected to the starvation state voltage. The gate of PMOS transistor P3 is connected to the output of logic gate D6. The drain of NMOS transistor N4 and the source of PMOS transistor P3 are respectively connected to the physical strength voltage. The source of NMOS transistor N4 and the drain of PMOS transistor P3 are connected and output the internal state voltage.

[0021] According to a second aspect of the present invention, a memristor-based multi-stimulus competition system is provided, comprising at least two multi-scale cue fusion devices and a comparison device, wherein...

[0022] The multi-scale cue fusion device is the multi-scale cue fusion device as described in any of the preceding claims, and different multi-scale cue fusion devices share the same state generation module;

[0023] The comparison device is used to perform pairwise comparisons of the fusion significance voltages output by each multi-scale cue fusion device and output the comparison results.

[0024] Optionally, the comparison device includes a subtractor, a window comparator module, and a result output module; wherein,

[0025] The subtractor is used to subtract the first fusion significance voltage from the second fusion significance voltage; the first fusion significance voltage and the second fusion significance voltage are the fusion significance voltages output by any two multi-scale cue fusion devices;

[0026] The window comparator module receives the output voltage of the subtractor and identifies the range in which the output voltage of the subtractor is located. Based on the different ranges, it outputs the corresponding range level signal.

[0027] The output module receives the interval level signal and generates a voltage signal that reflects the voltage difference between the two fusion significance levels.

[0028] Optionally, the window comparator module includes NMOS transistors N9 to NMOS transistor N. 13 Resistance R 14 ~Resistance R 17 and PMOS transistor P7; where,

[0029] The output of the subtractor is connected to the gate of NMOS transistor N9 and the gate of NMOS transistor N. 11 The gate of NMOS transistor N9 is connected to the source of NMOS transistor N9, which is connected to a -1V voltage. The drain of NMOS transistor N9 is connected to resistor R. 14 The first terminal and NMOS transistor N 10 The gate is connected, and the resistor R 14 The second terminal, resistor R 16 The first terminal, resistor R 15The second terminal and the source of PMOS transistor P7 are both used to connect to a 1V voltage, and the NMOS transistor N... 10 Drain and resistor R 16 The second terminal is connected, NMOS transistor N 10 The source of the NMOS transistor 11 The source of the NMOS transistor 12 The source of the NMOS transistor 13 The sources of all NMOS transistors are grounded. 11 Drain, resistor R 15 The first terminal, the gate of PMOS transistor P7, and the NMOS transistor N 12 The gates of PMOS transistor P7 and NMOS transistor N are connected. 12 The drain of the NMOS transistor N 13 The gate of the NMOS transistor is connected to the gate of the NMOS transistor. 13 Drain and resistor R 17 The second terminal is connected to the resistor R. 17 The first terminal is used to connect to a 1V voltage; resistor R 16 The second terminal outputs the first level signal of the interval, resistor R 17 The second terminal outputs the second level signal of the interval.

[0030] Optionally, the result output module includes logic gate D. 13 ~Logic gate D 18 NMOS transistor 14 ~NMOS transistor N 16 Resistance R 18 ~Resistance R 20 ; Logic gate D 13 ~Logic gate D 16 For AND gates, logic gate D 17 D 18 NOT gate; among which,

[0031] Logic gate D 13 The two input terminals are respectively connected to the first level signal of the interval and the second level signal of the interval, and the logic gate D 17 The input terminal is connected to the first level signal of the interval, and the logic gate D 18 The input terminal is connected to the second level signal of the interval, and the logic gate D 14 The first input terminal and logic gate D 13 The output of logic gate D is connected to the logic gate D. 14 The second and third input terminals are respectively connected to the physical intensity voltages generated in the two multi-scale cue fusion devices currently performing pairwise comparisons, logic gate D. 15 The first input terminal and logic gate D 17 The output of logic gate D is connected to the logic gate D. 15The second and third input terminals are respectively connected to the physical intensity voltages generated in the two multi-scale cue fusion devices currently performing pairwise comparisons, logic gate D. 16 The first input terminal and logic gate D 18 The output of logic gate D is connected to the logic gate D. 16 The second and third input terminals are respectively connected to the physical intensity voltages generated in the two multi-scale cue fusion devices currently performing pairwise comparisons, logic gate D. 14 The output terminal is connected to the NMOS transistor N 14 The gates are connected, logic gate D 15 The output terminal is connected to the NMOS transistor N 15 The gates are connected, logic gate D 16 The output terminal is connected to the NMOS transistor N 16 The gate of the NMOS transistor is connected to the gate of the NMOS transistor. 14 The drain of the NMOS transistor is used to connect to the first drive voltage V1. 15 The drain of the NMOS transistor is used to connect to the second drive voltage V2. 16 The drain of the NMOS transistor is used to connect to the third drive voltage V3. 14 The source and resistor R 18 The second terminal is connected to the resistor R. 18 The first terminal is grounded, and the NMOS transistor N 15 The source and resistor R 19 The second terminal is connected to the resistor R. 19 The first terminal is grounded, and the NMOS transistor N 16 The source and resistor R 20 The second terminal is connected to the resistor R. 20 The first terminal is grounded, and the NMOS transistor N 14 The source output first suppression output voltage V inhibition NMOS transistor N 15 The source output second winning output voltage V win_2 NMOS transistor N 16 The source output first winning output voltage V win_1 If the first suppression output voltage V inhibition A high level indicates that the difference between the second fusion significance voltage and the first fusion significance voltage is within the set range [-V]. l V h Within, if the second winning output voltage V win_2 A high level indicates that the second fusion significance voltage is greater than the first fusion significance voltage +V. h If the first winning output voltage V win_1 A high level indicates that the first fusion significance voltage is greater than the second fusion significance voltage +V. l V l Vh These are the interval division values ​​determined by the window comparator module.

[0032] In summary, compared with the prior art, the technical solutions conceived in this invention have the following main advantages:

[0033] 1. This invention provides a multi-scale cue fusion device based on memristors, comprising a state generation module, a stimulus intensity processing module, a context-related processing module, a state feedback module, and a fusion module. The state generation module primarily simulates the influence of reward on internal states; different internal states result in different levels of perception of external stimuli by the organism. The stimulus intensity processing module primarily simulates the influence of internal states on the organism's perception of the intensity of external physical stimuli. The context-related processing module primarily simulates context-related factors, thereby simulating the influence of different environments on the organism's perception of external stimuli. The state feedback module primarily simulates the superimposed influence of internal states on the organism's final perception of stimulus intensity. Based on the above design, the mutual influence of multi-scale signals can be reflected, thus more realistically reflecting the organism's processing of multi-scale information, obtaining the organism's true perception of stimuli under the comprehensive influence of multi-scale information, and providing biomimetic accuracy. Moreover, this invention introduces memristors, whose superior in-memory computing capabilities can accelerate the device's signal processing, thereby improving the device's processing speed.

[0034] 2. This invention provides a memristor-based multi-stimulus competition system that simulates which type of stimulus an organism tends to respond to under various different stimuli. This allows it to be applied to different scenarios, greatly improving the adaptability and anti-interference capability of biomimetic sensing circuits. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the framework of a memristor-based multi-scale clue fusion device in one embodiment of the present invention;

[0036] Figure 2 This is a circuit diagram of a state generation module in one embodiment of the present invention;

[0037] Figure 3 This is a circuit diagram of the stimulation intensity processing module in one embodiment of the present invention;

[0038] Figure 4 This is a circuit diagram of the context-related processing module in one embodiment of the present invention;

[0039] Figure 5 This is a circuit diagram of a state feedback module in one embodiment of the present invention;

[0040] Figure 6 This is a schematic diagram of the framework of a memristor-based multi-stimulus competition system in one embodiment of the present invention;

[0041] Figure 7 This is a circuit diagram of a comparison device according to an embodiment of the present invention;

[0042] Figure 8 This is a detailed circuit connection diagram of a memristor-based multi-stimulus competition system according to one embodiment of the present invention;

[0043] Figure 9 These are the stimulus voltage and situational voltage input under two different stimuli in one embodiment of the present invention;

[0044] Figure 10 Is the input as follows Figure 9 The signal shown corresponds to the multi-scale signal generated inside the multi-scale cue fusion device.

[0045] Figure 11 Is the input as follows Figure 9 The signal is shown as the competitive output of the multi-stimulus competitive system. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0047] This invention provides a multi-scale cue fusion device based on memristors. This device comprehensively considers the interaction of external physical stimuli, situational stimuli, and internal states to simulate the intensity of stimuli ultimately perceived by an organism under multiple signals. External physical stimuli refer to signals in the environment that directly act on the organism's senses and elicit a response, such as ringing, food, or electric shocks. Situational stimuli are stimuli associated with a specific scene or background, which typically do not directly elicit a single response but provide contextual cues for behavior or memory, such as a familiar room layout. Internal states refer to the physiological or psychological states within the organism, which influence responses to external stimuli, such as hunger, anxiety, and fatigue.

[0048] like Figure 1 The diagram shown is a schematic of the framework of a memristor-based multi-scale cue fusion device according to an embodiment of the present invention, which mainly includes a state generation module, a stimulus intensity processing module, a context relevance processing module, a state feedback module, and a fusion module.

[0049] The state generation module includes a volatile memristor VM1, a positive correlation mapping circuit, and a state comparison circuit. VM1 receives a reward voltage; it is in a high-resistance state when no reward voltage is applied and its resistance gradually decreases during the application of the reward voltage. The positive correlation mapping circuit maps the resistance of VM1 to a voltage. The comparison circuit compares the mapped voltage with a state threshold voltage and outputs a starvation state voltage. When the mapped voltage exceeds the state threshold voltage, the output is high; otherwise, it is low.

[0050] Specifically, the state generation module mainly simulates the effect of rewards on internal states. Different internal states result in different levels of perception of external stimuli by the organism. Among them, the reward voltage is a signal that can weaken the organism's sensitivity to external stimuli. When the reward voltage lasts long enough, the organism may not even perceive the external stimuli.

[0051] The working mechanism of the state generation module is as follows: when there is no reward, the hunger state voltage output by the module is high level. When a sufficiently large reward voltage is input and the duration of the reward voltage reaches a certain level, the hunger state voltage will change from high level to low level. The high and low levels reflect whether the reward is effective.

[0052] In the state generation module, a volatile memristor VM1 is specifically introduced, and a positive correlation mapping circuit and a state comparison circuit are designed. The volatile memristor VM1 is in a high-resistance state (reset state) when there is no reward voltage, and it can spontaneously reset to its original high-resistance state when the reward voltage is removed. When a reward voltage is applied, the resistance of the volatile memristor VM1 gradually decreases to reflect the cumulative effect of continuous rewards. The positive correlation mapping circuit maps the resistance of VM1 to a voltage, meaning the voltage and resistance are positively correlated. As the resistance of the volatile memristor VM1 gradually decreases, the mapped voltage output by the positive correlation mapping circuit also gradually decreases. The comparator circuit compares the mapped voltage and the state threshold voltage and outputs the starvation state voltage. When there is no reward voltage, the volatile memristor VM1 is in a high-resistance state, the mapped voltage is higher than the state threshold voltage, and the starvation state voltage is high. Only when a reward is applied and lasts for a certain period, until the resistance of the volatile memristor VM1 gradually decreases so that the mapped voltage gradually decreases below the state threshold voltage, does the starvation state voltage switch from high to low. Once the reward voltage is removed, the starvation state voltage jumps back from low to high. A high level indicates that no effective reward has been generated, and a low level indicates that an effective reward has been generated. Whether the reward is effective represents the internal state of the organism, which will affect the organism's final stimulus perception.

[0053] The stimulation intensity processing module includes a memristor circuit, a subtraction circuit, and a stimulation comparison circuit. The memristor circuit adjusts memristor M1 based on the hunger state voltage. When the hunger state voltage is high, M1 is set to a low-impedance state to output a high level; otherwise, M1 is reset to a high-impedance state to output a low level. The subtraction circuit calculates the voltage difference between the set voltage and the output voltage of M1. The adjustable threshold voltage of the stimulation comparison circuit is positively correlated with the voltage difference and is used to receive the stimulation voltage and compare it with the adjustable threshold voltage. When the stimulation voltage is greater than the adjustable threshold voltage, a physical intensity voltage positively correlated with the stimulation voltage is output; otherwise, the physical intensity voltage remains low.

[0054] Specifically, the stimulus intensity processing module mainly simulates the influence of internal state on the organism's perception of the intensity of external physical stimuli.

[0055] The working mechanism of the stimulus intensity processing module is as follows: when there is no effective reward, the internal state of the organism does not affect the organism's perception of external physical stimuli. The physical intensity voltage output by the stimulus intensity processing module is basically equal to the stimulus voltage it receives. When there is an effective reward, the organism's perception of external physical stimuli is suppressed by the organism's internal state. The physical intensity voltage output by the stimulus intensity processing module is small or even non-existent.

[0056] The stimulus intensity processing module specifically incorporates a memristor circuit, a subtraction circuit, and a stimulus comparison circuit. The memristor circuit adjusts the output voltage of memristor M1 based on the hunger state voltage, thereby adjusting the voltage difference between the set voltage and the output voltage of M1, which in turn adjusts the adjustable threshold voltage of the comparison circuit, ultimately outputting different physical intensity voltages.

[0057] When there is no effective reward, the hunger state voltage is high. At this time, M1 is set to a low-impedance state, and its output voltage is high. The subtraction circuit subtracts the output voltage of M1 from the set voltage. Therefore, the voltage difference output by the subtraction circuit is small. The adjustable threshold voltage is positively correlated with the voltage difference. The smaller the voltage difference, the smaller the adjustable threshold voltage. Therefore, when the adjustable threshold voltage is small, even a small stimulus voltage can pass through the stimulus intensity processing module and output a physical intensity voltage that is basically the same as the received stimulus voltage intensity.

[0058] When a valid reward is present, the hunger state voltage is low. At this time, M1 is reset to a high-impedance state, and its output voltage is low. The subtraction circuit subtracts the output voltage of M1 from the set voltage. Therefore, the voltage difference output by the subtraction circuit is large. The adjustable threshold voltage is positively correlated with the voltage difference. The larger the voltage difference, the larger the adjustable threshold voltage. Therefore, when the adjustable threshold voltage is large, a small stimulus voltage cannot pass through the stimulus intensity processing module. That is, when a valid reward is present, it will affect the organism's perception of external stimuli. Only when the external stimulus is large enough will the stimulus intensity processing module output a physical intensity voltage.

[0059] The context-dependent processing module includes a context gating circuit, a memristor M2, a context comparator circuit, a latch, and a shaping circuit. Specifically: the context gating circuit receives the context voltage and is controlled by the physical strength voltage; the context comparator circuit compares the output voltage of M2 with a set context threshold voltage; when the context gating circuit is on, the context voltage is applied to M2; if the context voltage does not reach the set threshold, M2 is in a high-impedance state, and the context comparator outputs a low level; otherwise, M2 is set to a low-impedance state, and the context comparator outputs a high level; the latch latches the output voltage of the context comparator; and the shaping circuit performs a logical AND operation on the latch output voltage and the physical strength voltage to output the context-dependent voltage.

[0060] Specifically, the context-related processing module mainly simulates context-related factors, thereby simulating the influence of organisms' perception of external stimuli in different environments.

[0061] The working mechanism of the context-related processing module is that when the stimulus intensity processing module can generate physical intensity voltage, the organism's final perception of the stimulus will also be superimposed with the influence of the context signal. That is, the context-related processing module will generate a context-related voltage as a perception gain.

[0062] The context-related processing module incorporates a context gating circuit, memristor M2, a context comparator circuit, a latch, and a shaping circuit. The context gating circuit receives the context voltage and is controlled by the physical intensity voltage. When both the physical intensity voltage and the context voltage are present, the context gating circuit is activated, applying the context voltage to memristor M2, setting it to a low resistance state. Memristor M2 outputs a high level, and since its output voltage exceeds the context threshold voltage, the context comparator outputs a high level. This high level is then latched and ANDed with the original physical intensity voltage to shape the waveform, resulting in a context-related voltage with the same waveform as the original physical intensity voltage. If the stimulus intensity processing module does not detect the physical intensity voltage, the context-related processing module will not output a context-related voltage. It should be noted that because the context signal is typically long-lasting, memristor M2 can be a non-volatile memristor with long-term memory capabilities; its state remains unchanged after the context voltage sets it to a low resistance state.

[0063] The state feedback module includes a state gating circuit that receives physical strength voltage and is controlled by a starvation state voltage. When the state gating circuit is turned on, it outputs an internal state voltage.

[0064] Specifically, the state feedback module mainly simulates the superimposed influence of internal state on the organism's final perception of stimulus intensity.

[0065] The working mechanism of the state feedback module is as follows: when there is no effective reward, the state feedback module generates an internal state voltage that enhances the perception of the final stimulus; when there is an effective reward, the state feedback module will not enhance the perception of the final stimulus.

[0066] The state feedback module incorporates a state gating circuit. When no valid reward exists, the starvation state voltage is high, the state gating circuit is activated, and the state feedback module outputs an internal state voltage positively correlated with the physical strength voltage. When a valid reward exists, the starvation state voltage is low, the state gating circuit is deactivated, and the state feedback module has no output.

[0067] The fusion module is used to perform a weighted summation of physical strength voltage, context-dependent voltage, and internal state voltage, and output the fusion significance voltage.

[0068] Specifically, the fusion module mainly fuses the voltages output by the above modules to obtain the final fusion significance voltage, which reflects the intensity of the external physical stimulus ultimately perceived by the organism under certain circumstances and reward conditions.

[0069] In one embodiment, such as Figure 2As shown, in the state generation module, its positive correlation mapping circuit includes operational amplifier OP3, resistor R7, and voltage calculation module ABM1. Voltage calculation module ABM1 is used to calculate the voltage difference between different input voltages; its state comparison circuit includes operational amplifier OP4.

[0070] The specific circuit connection is as follows: the first terminal of the memristor VM1 and the second terminal of the voltage calculation module ABM1 are respectively used to connect the reward voltage V. i The second terminal of memristor VM1 is connected to the first terminal of resistor R7 and the negative input terminal of operational amplifier OP3. The positive input terminal of operational amplifier OP3 is grounded. The output terminal of operational amplifier OP3 is connected to the second terminal of resistor R7 and the first terminal of voltage calculation module ABM1. The output terminal of voltage calculation module ABM1 is connected to the positive input terminal of operational amplifier OP4. The negative input terminal of operational amplifier OP4 is connected to the state threshold voltage V. th_s When connected, the output of operational amplifier OP4 outputs a starved state voltage.

[0071] Its specific working principle is as follows: If there is no reward voltage V i When memristor VM1 is in a high-impedance state, its output voltage is high, operational amplifier OP3 outputs a low level, voltage calculation module ABM1 outputs a high level, and operational amplifier OP4 outputs a high level; if a bonus voltage V is applied... i As the resistance of memristor VM1 gradually decreases, its output voltage gradually decreases until operational amplifier OP3 outputs a high level, voltage calculation module ABM1 outputs a low level, and operational amplifier OP4 outputs a low level. If the reward is cancelled, memristor VM1 spontaneously returns to a high-resistance state, its output voltage is relatively high, operational amplifier OP3 outputs a low level, voltage calculation module ABM1 outputs a high level, and operational amplifier OP4 outputs a high level.

[0072] In one embodiment, such as Figure 3 As shown, in the stimulus intensity processing module, the memristor circuit includes an adder A1, a logic gate D1, a memristor M1, and an NMOS transistor N1; the logic gate D1 is an NOT gate.

[0073] The specific circuit connection is as follows: the first input terminal of adder A1 and the input terminal of logic gate D1 are respectively connected to the starvation state voltage; the output terminal of logic gate D1 is connected to the gate of NMOS transistor N1; and the drain of NMOS transistor N1 is connected to the memristor reset voltage V. r The source of NMOS transistor N1 is connected to the second input terminal of adder A1, the output terminal of adder A1 is connected to the first terminal of memristor M1, and the second terminal of memristor M1 is connected to the subtraction circuit.

[0074] Its specific working principle is as follows: when the starvation state voltage is high, NMOS transistor N1 is turned off, and the reset voltage V is not applied.r When the starvation voltage is low, the memristor M1 is set to a low-impedance state, and its output voltage is high. When the starvation voltage is low, the NMOS transistor N1 is turned on, and the reset voltage V is applied. r (Negative voltage) When memristor M1 is reset to a high-impedance state, its output voltage is low.

[0075] In one embodiment, continue as follows Figure 3 As shown, in the stimulus intensity processing module, the subtraction circuit includes resistors R1, R2, R3 and operational amplifier OP1, and the stimulus comparison circuit includes NMOS transistor N2, resistors R4 and R5 and PMOS transistor P1.

[0076] The specific circuit connection is as follows: the second terminal of memristor M1 and the first terminal of resistor R1 are connected to the negative input terminal of operational amplifier OP1, the second terminal of resistor R1 is connected to the output terminal of operational amplifier OP1, the second terminal of resistor R2 and the first terminal of resistor R3 are both connected to the positive input terminal of the first amplifier OP1, and the first terminal of resistor R2 is used to connect the stimulation threshold voltage V. th_p The second terminal of resistor R3 is grounded; the source of NMOS transistor N2 is connected to the output of operational amplifier OP1, and the gate of NMOS transistor N2 and the source of PMOS transistor P1 are used to connect the stimulation voltage V. s1 The drain of N2, the gate of P1, and the first terminal of R4 are connected, and the second terminal of R4 is grounded. The drain of P1 is connected to the first terminal of R5, and the second terminal of R5 is grounded. The drain of P1 outputs a physical strength voltage.

[0077] Its specific working principle is as follows: When the memristor M1 outputs a low level, the voltage difference output by the operational amplifier OP1 is large, resulting in a high source potential of the NMOS transistor N2. Consequently, the adjustable threshold voltage of the NMOS transistor N2 is large. Therefore, only a large stimulation voltage can turn on the NMOS transistor N2 and output a positively correlated physical strength voltage. A small stimulation voltage cannot stimulate the generation of a positively correlated physical strength voltage. When the memristor M1 outputs a high level, the voltage difference output by the operational amplifier OP1 is small, resulting in a low source potential of the NMOS transistor N2. Consequently, the adjustable threshold voltage of the NMOS transistor N2 is small. Therefore, a small stimulation voltage can also turn on the NMOS transistor N2 and output a positively correlated physical strength voltage.

[0078] In one embodiment, such as Figure 4 As shown, in the context correlation processing module, the context gating circuit includes logic gate D2, PMOS transistor P2, and NMOS transistor N3; logic gate D2 is an NOT gate; the context comparison circuit includes resistor R6 and operational amplifier OP2.

[0079] The specific circuit connection is as follows: the input terminal of logic gate D2 and the gate of NMOS transistor N3 are both connected to the physical strength voltage; the output terminal of logic gate D2 is connected to the gate of PMOS transistor P2; and the drain of NMOS transistor N3 and the source of PMOS transistor P2 are respectively connected to the application voltage V. c1 The source of NMOS transistor N3 and the drain of PMOS transistor P2 are connected to the first terminal of memristor M2. The second terminal of memristor M2 and the first terminal of resistor R6 are connected to the positive input terminal of operational amplifier OP2. The second terminal of resistor R6 is grounded. The negative input terminal of operational amplifier OP2 is used to connect the scenario threshold voltage V. th c The output of operational amplifier OP2 is connected to a latch.

[0080] Its specific working principle is as follows: the initial state of memristor M2 is the reset state, that is, the high impedance state, and its output is low level. The operational amplifier OP2 outputs a low level. When the physical strength voltage turns on the situation gate circuit, the situation voltage V... c When memristor M2 is set to low impedance, its output is high, and operational amplifier OP2 outputs a high level.

[0081] Furthermore, in the context-dependent processing module, the latch uses an SR flip-flop, which includes logic gates D3 and D4, and the shaping circuit includes logic gate D5; logic gates D3 and D4 are both NOR gates, and logic gate D5 is an AND gate. The output of operational amplifier OP2 is connected to the first input of logic gate D3; the second input of logic gate D3 is connected to the output of logic gate D4 and the second input of logic gate D5, the second input of logic gate D5 obtains the physical strength voltage, the output of logic gate D3 is connected to the first input of logic gate D4, and the second input of logic gate D4 is connected to the flip-flop reset voltage V. rst Connected, the output of logic gate D5 outputs a context-dependent voltage.

[0082] In one embodiment, such as Figure 5 As shown, in the state feedback module, the state gating circuit includes logic gate D6, NMOS transistor N4 and PMOS transistor P3; logic gate D6 is an NOT gate.

[0083] The specific circuit connection is as follows: the input terminal of logic gate D6 and the gate of NMOS transistor N4 are both connected to the starvation state voltage. The gate of PMOS transistor P3 is connected to the output terminal of logic gate D6. The drain of NMOS transistor N4 and the source of PMOS transistor P3 are respectively connected to the physical strength voltage. The source of NMOS transistor N4 and the drain of PMOS transistor P3 are connected and output the internal state voltage.

[0084] Its specific working principle is as follows: when the hunger state voltage is high, the state gate circuit is turned on, the physical strength voltage passes through the state gate circuit, and outputs an internal state voltage that is positively correlated with it. When the hunger state voltage is low, the state gate circuit is turned off, and at this time the internal state voltage is empty.

[0085] In one embodiment, the fusion module can specifically be a weighted adder A3. The physical strength voltage, the context-related voltage, and the internal state voltage are respectively input to the three input terminals of the adder A3, and the fusion significance voltage is output after weighted summation.

[0086] This invention also provides a memristor-based multi-stimulus competition system. This system can simulate which type of stimulus an organism tends to respond to when faced with a variety of different external stimuli.

[0087] like Figure 6 The diagram shows a framework of a memristor-based multi-stimulus competition system according to an embodiment of the present invention, which includes at least two multi-scale cue fusion devices as described above and a comparison device. Different multi-scale cue fusion devices share the same state generation module. The comparison device is used to perform pairwise comparisons of the fusion significance voltages output by each multi-scale cue fusion device and output the comparison results.

[0088] In one embodiment, it is possible to determine only the magnitude relationship of the fusion significance voltage, that is, only their relative magnitudes need to be determined. In this case, only a simple comparison circuit needs to be set up.

[0089] Considering that in real-world situations, when the fusion significance voltages obtained from two stimuli are relatively close, there is a certain degree of randomness in which stimulus a response is made, in some embodiments, a subtractor, a window comparator module, and a result output module are set in the comparison device to obtain three comparison results: the two fusion significance voltages are close, the first fusion significance voltage is significantly larger, or the second fusion significance voltage is significantly larger.

[0090] Specifically, the subtractor is used to subtract the first fusion significance voltage from the second fusion significance voltage; the first fusion significance voltage and the second fusion significance voltage are the fusion significance voltages output by any two multi-scale cue fusion devices; the window comparator module receives the output voltage of the subtractor and identifies the interval in which the output voltage of the subtractor is located, and outputs the interval level signal of the corresponding interval according to the different intervals in which it is located; the result output module receives the interval level signal and generates a voltage signal that reflects the difference between the two fusion significance voltages.

[0091] For details, please refer to Figure 7 As shown, the window comparator module includes NMOS transistors N9 to NMOS transistor N 13 Resistance R 14~Resistance R 17 And PMOS transistor P7.

[0092] The specific circuit connection is as follows: the output of the subtractor is connected to the gate of NMOS transistor N9, and the NMOS transistor N... 11 The gate of NMOS transistor N9 is connected to the source of NMOS transistor N9, which is connected to a -1V voltage. The drain of NMOS transistor N9 is connected to resistor R. 14 The first terminal and NMOS transistor N 10 The gate is connected, and the resistor R 14 The second terminal, resistor R 16 The first terminal, resistor R 15 The second terminal and the source of PMOS transistor P7 are both used to connect to a 1V voltage, and the NMOS transistor N... 10 Drain and resistor R 16 The second terminal is connected, NMOS transistor N 10 The source of the NMOS transistor 11 The source of the NMOS transistor 12 The source of the NMOS transistor 13 The sources of all NMOS transistors are grounded. 11 Drain, resistor R 15 The first terminal, the gate of PMOS transistor P7, and the NMOS transistor N 12 The gates of PMOS transistor P7 and NMOS transistor N are connected. 12 The drain of the NMOS transistor N 13 The gate of the NMOS transistor is connected to the gate of the NMOS transistor. 13 Drain and resistor R 17 The second terminal is connected to the resistor R. 17 The first terminal is used to connect to a 1V voltage; resistor R 16 The second terminal outputs the first level signal of the interval, resistor R 17 The second terminal outputs the second level signal of the interval.

[0093] Its specific working principle is as follows: by adjusting the resistor R 14 and resistance R 15 The value of V can be adjusted to control the interval division value. l V h Let ΔV = the difference between the second fusion significance voltage and the first fusion significance voltage. If -V l ≤△V≤V h This indicates that the two are relatively close, so the first level signal in the interval is high and the second level signal in the interval is high; if ΔV < -V l This indicates that the first fusion significance voltage is significantly larger, therefore the first level signal in the interval is low, and the second level signal in the interval is high; if ΔV > -V hThis indicates that the second fusion significance voltage is significantly larger, so the second level signal in the interval is low, and the first level signal in the interval is high. The difference in the interval level signals reflects the competition result.

[0094] In one embodiment, reference continues Figure 7 As shown, the result output module includes logic gate D. 13 ~Logic gate D 18 NMOS transistor 14 ~NMOS transistor N 16 Resistance R 18 ~Resistance R 20 ; Logic gate D 13 ~Logic gate D 16 For AND gates, logic gate D 17 D 18 NOT gate.

[0095] Its specific circuit connection is as follows: Logic gate D 13 The two input terminals are respectively connected to the first level signal of the interval and the second level signal of the interval, and the logic gate D 17 The input terminal is connected to the first level signal of the interval, and the logic gate D 18 The input terminal is connected to the second level signal of the interval, and the logic gate D 14 The first input terminal and logic gate D 13 The output of logic gate D is connected to the logic gate D. 14 The second and third input terminals are respectively connected to the physical intensity voltages generated in the two multi-scale cue fusion devices currently performing pairwise comparisons, logic gate D. 15 The first input terminal and logic gate D 17 The output of logic gate D is connected to the logic gate D. 15 The second and third input terminals are respectively connected to the physical intensity voltages generated in the two multi-scale cue fusion devices currently performing pairwise comparisons, logic gate D. 16 The first input terminal and logic gate D 18 The output of logic gate D is connected to the logic gate D. 16 The second and third input terminals are respectively connected to the physical intensity voltages generated in the two multi-scale cue fusion devices currently performing pairwise comparisons, logic gate D. 14 The output terminal is connected to the NMOS transistor N 14 The gates are connected, logic gate D 15 The output terminal is connected to the NMOS transistor N 15 The gates are connected, logic gate D 16 The output terminal is connected to the NMOS transistor N 16 The gate of the NMOS transistor is connected to the gate of the NMOS transistor. 14 The drain of the NMOS transistor is used to connect to the first drive voltage V1. 15The drain of the NMOS transistor is used to connect to the second drive voltage V2. 16 The drain of the NMOS transistor is used to connect to the third drive voltage V3. 14 The source and resistor R 18 The second terminal is connected to the resistor R. 18 The first terminal is grounded, and the NMOS transistor N 15 The source and resistor R 19 The second terminal is connected to the resistor R. 19 The first terminal is grounded, and the NMOS transistor N 16 The source and resistor R 20 The second terminal is connected to the resistor R. 20 The first terminal is grounded, and the NMOS transistor N 14 The source output first suppression output voltage V inhibition NMOS transistor N 15 The source output second winning output voltage V win_2 NMOS transistor N 16 The source output first winning output voltage V win_1 If the first suppression output voltage V inhibition A high level indicates that the difference between the second fusion significance voltage and the first fusion significance voltage is within the set range [-V]. l V h Within, if the second winning output voltage V win_2 A high level indicates that the second fusion significance voltage is greater than the first fusion significance voltage +V. h If the first winning output voltage V win_1 A high level indicates that the first fusion significance voltage is greater than the second fusion significance voltage +V. l V l V h These are the interval division values ​​determined by the window comparator module.

[0096] Its specific working principle is as follows: If -V l ≤△V≤V h This indicates that the two are relatively close; the first level signal in the interval is high, and the second level signal in the interval is high. At this time, logic gate D... 13 Output high level, through logic gate D 14 Shaping is performed to output the first suppression output voltage V. inhibition At this time, the other two output terminals have no output; if ΔV < -V l This indicates that the first fusion significance voltage is significantly larger, the first level signal in the interval is low, and the second level signal in the interval is high. At this time, logic gate D... 18 Output high level, through logic gate D 16 Perform shaping to output the first winning output voltage V. win_1At this time, the other two output terminals have no output; if ΔV > -V h This indicates that the second fusion significance voltage is significantly larger, the second level signal in the interval is low, and the first level signal in the interval is high. At this time, logic gate D... 17 Output high level, through logic gate D 15 Perform shaping to output the second winning output voltage V. win_2 At this point, the other two output terminals have no output.

[0097] like Figure 8 The diagram shown is a detailed circuit connection diagram of a memristor-based multi-stimulus competition system according to an embodiment of the present invention. Different labels are used for the components in the two multi-scale cue fusion devices to distinguish them.

[0098] like Figure 9 The figure shows the stimulus voltage and situation voltage input under two different stimuli in one embodiment of the present invention, wherein V s1 V is the stimulation voltage input under the first stimulus. c1 V represents the situational voltage associated with the first stimulus. s2 V is the stimulation voltage input under the second type of stimulus. c2 The situational voltage associated with the second stimulus.

[0099] like Figure 10 The input is shown below. Figure 9 The signal shown corresponds to the multi-scale signal generated inside the multi-scale cue fusion device, where V s1_p and V s2_p V represents the physical stimulus intensity signals of the first stimulus and the second stimulus, respectively. s1_c and V s2_c V represents the context-relevance signal of the first stimulus and the second stimulus, respectively. s1_s and V s2_s These are the internal state signals of the first stimulus and the second stimulus, respectively.

[0100] like Figure 11 The input is shown below. Figure 9 The competitive output of the multi-stimulus competitive system shown in the figure indicates that, within 0 to 3 seconds, the first stimulus wins, and the organism tends to respond to the first stimulus. Within 3 to 4 seconds, the two stimuli are relatively close, and the organism's response has a certain degree of randomness. Within 4 to 8 seconds, the second stimulus wins, and the organism tends to respond to the second stimulus.

[0101] The technical features of the embodiments described above can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. It should be noted that the terms "in one embodiment," "for example," and "again" in this invention are intended to illustrate the invention and are not intended to limit the invention.

[0102] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A multi-scale cue fusion device based on memristors, characterized in that, include; The state generation module includes a volatile memristor VM1, a positive correlation mapping circuit, and a state comparison circuit. The memristor VM1 receives a reward voltage; it is in a high-resistance state when no reward voltage is applied and its resistance gradually decreases during the application of the reward voltage. The positive correlation mapping circuit maps the resistance of VM1 to a voltage. The comparison circuit compares the mapped voltage with a state threshold voltage and outputs a starvation state voltage. When the mapped voltage exceeds the state threshold voltage, the output is high; otherwise, it is low. The stimulation intensity processing module includes a memristor circuit, a subtraction circuit, and a stimulation comparison circuit. The memristor circuit adjusts memristor M1 based on the hunger state voltage. When the hunger state voltage is high, M1 is set to a low-impedance state to output a high level; otherwise, M1 is reset to a high-impedance state to output a low level. The subtraction circuit calculates the voltage difference between the set voltage and the output voltage of M1. The adjustable threshold voltage of the stimulation comparison circuit is positively correlated with the voltage difference and is used to receive the stimulation voltage and compare it with the adjustable threshold voltage. When the stimulation voltage is greater than the adjustable threshold voltage, a physical intensity voltage positively correlated with the stimulation voltage is output; otherwise, the physical intensity voltage remains low. The context-dependent processing module includes a context gating circuit, a memristor M2, a context comparator circuit, a latch, and a shaping circuit. Specifically: the context gating circuit receives the context voltage and is controlled by the physical strength voltage; the context comparator circuit compares the output voltage of M2 with a set context threshold voltage; when the context gating circuit is on, the context voltage is applied to M2; if the context voltage does not reach the set threshold, M2 is in a high-impedance state, and the context comparator outputs a low level; otherwise, M2 is set to a low-impedance state, and the context comparator outputs a high level; the latch latches the output voltage of the context comparator; and the shaping circuit performs a logical AND operation on the latch output voltage and the physical strength voltage to output the context-dependent voltage. The state feedback module includes a state gate circuit that receives physical strength voltage and is controlled by a starvation state voltage, and outputs an internal state voltage when the state gate circuit is turned on. The fusion module is used to perform a weighted summation of physical strength voltage, context-dependent voltage, and internal state voltage, and output the fusion significance voltage.

2. The memristor-based multi-scale clue fusion device as described in claim 1, characterized in that, In the state generation module, the positive correlation mapping circuit includes operational amplifier OP3, resistor R7, and voltage calculation module ABM1, which calculates the voltage difference between different input voltages; the state comparison circuit includes operational amplifier OP4; wherein, The first terminal of memristor VM1 and the second terminal of voltage calculation module ABM1 are respectively used to connect the reward voltage V. i The second terminal of memristor VM1 is connected to the first terminal of resistor R7 and the negative input terminal of operational amplifier OP3. The positive input terminal of operational amplifier OP3 is grounded. The output terminal of operational amplifier OP3 is connected to the second terminal of resistor R7 and the first terminal of voltage calculation module ABM1. The output terminal of voltage calculation module ABM1 is connected to the positive input terminal of operational amplifier OP4. The negative input terminal of operational amplifier OP4 is connected to the state threshold voltage V. th_s When connected, the output of operational amplifier OP4 outputs a starved state voltage.

3. The memristor-based multi-scale clue fusion device as described in claim 1, characterized in that, In the stimulus intensity processing module, the memristor circuit includes an adder A1, a logic gate D1, a memristor M1, and an NMOS transistor N1; the logic gate D1 is an NOT gate; among which, The first input terminal of adder A1 and the input terminal of logic gate D1 are respectively connected to the starvation state voltage. The output terminal of logic gate D1 is connected to the gate of NMOS transistor N1, and the drain of NMOS transistor N1 is connected to the memristor reset voltage V. r The source of NMOS transistor N1 is connected to the second input terminal of adder A1, the output terminal of adder A1 is connected to the first terminal of memristor M1, and the second terminal of memristor M1 is connected to the subtraction circuit.

4. The memristor-based multi-scale clue fusion device as described in claim 3, characterized in that, In the stimulus intensity processing module, the subtraction circuit includes resistors R1, R2, and R3, and operational amplifier OP1; the stimulus comparison circuit includes NMOS transistor N2, resistors R4 and R5, and PMOS transistor P1; wherein, The second terminal of memristor M1 and the first terminal of resistor R1 are connected to the negative input terminal of operational amplifier OP1, respectively. The second terminal of resistor R1 is connected to the output terminal of operational amplifier OP1. The second terminal of resistor R2 and the first terminal of resistor R3 are both connected to the positive input terminal of the first amplifier OP1. The first terminal of resistor R2 is used to connect the stimulation threshold voltage V. th_p The second terminal of resistor R3 is grounded; The source of NMOS transistor N2 is connected to the output of operational amplifier OP1. The gate of NMOS transistor N2 and the source of PMOS transistor P1 are used to connect the stimulation voltage V. s1 The drain of N2, the gate of P1, and the first terminal of R4 are connected, and the second terminal of R4 is grounded. The drain of P1 is connected to the first terminal of R5, and the second terminal of R5 is grounded. The drain of P1 outputs a physical strength voltage.

5. The memristor-based multi-scale clue fusion device as described in claim 1, characterized in that, In the context-dependent processing module, the context gating circuit includes logic gate D2, PMOS transistor P2, and NMOS transistor N3; logic gate D2 is an NOT gate; the context comparison circuit includes resistor R6 and operational amplifier OP2; wherein, The input of logic gate D2 and the gate of NMOS transistor N3 are both connected to the physical strength voltage. The output of logic gate D2 is connected to the gate of PMOS transistor P2. The drain of NMOS transistor N3 and the source of PMOS transistor P2 are respectively connected to the application voltage V. c The source of NMOS transistor N3 and the drain of PMOS transistor P2 are connected to the first terminal of memristor M2. The second terminal of memristor M2 and the first terminal of resistor R6 are connected to the positive input terminal of operational amplifier OP2. The second terminal of resistor R6 is grounded. The negative input terminal of operational amplifier OP2 is used to connect the scenario threshold voltage V. th_c The output of operational amplifier OP2 is connected to a latch.

6. The memristor-based multi-scale clue fusion device as described in claim 1, characterized in that, In the state feedback module, the state gating circuit includes logic gate D6, NMOS transistor N4, and PMOS transistor P3; logic gate D6 is an NOT gate; where, The input of logic gate D6 and the gate of NMOS transistor N4 are both connected to the starvation state voltage. The gate of PMOS transistor P3 is connected to the output of logic gate D6. The drain of NMOS transistor N4 and the source of PMOS transistor P3 are respectively connected to the physical strength voltage. The source of NMOS transistor N4 and the drain of PMOS transistor P3 are connected and output the internal state voltage.

7. A memristor-based multi-stimulus competition system, characterized in that, It includes at least two multi-scale cue fusion devices and a comparison device, wherein, The multi-scale cue fusion device is the multi-scale cue fusion device as described in any one of claims 1 to 6, and different multi-scale cue fusion devices share the same state generation module; The comparison device is used to perform pairwise comparisons of the fusion significance voltages output by each multi-scale cue fusion device and output the comparison results.

8. The memristor-based multi-stimulus competition system as described in claim 7, characterized in that, The comparison device includes a subtractor, a window comparator module, and a result output module; wherein, The subtractor is used to subtract the first fusion significance voltage from the second fusion significance voltage; the first fusion significance voltage and the second fusion significance voltage are the fusion significance voltages output by any two multi-scale cue fusion devices; The window comparator module receives the output voltage of the subtractor and identifies the range in which the output voltage of the subtractor is located. Based on the different ranges, it outputs the corresponding range level signal. The output module receives the interval level signal and generates a voltage signal that reflects the voltage difference between the two fusion significance levels.

9. The memristor-based multi-stimulus competition system as described in claim 8, characterized in that, The window comparator module includes NMOS transistors N9 to NMOS transistor N 13 Resistance R 14 ~resistance R 17 and PMOS transistor P7; where, The output of the subtractor is connected to the gate of NMOS transistor N9 and the gate of NMOS transistor N. 11 The gate of NMOS transistor N9 is connected to the source of NMOS transistor N9, which is connected to a -1V voltage. The drain of NMOS transistor N9 is connected to resistor R. 14 The first terminal and NMOS transistor N 10 The gate is connected, and the resistor R 14 The second terminal, resistor R 16 The first terminal, resistor R 15 The second terminal and the source of PMOS transistor P7 are both used to connect to a 1V voltage, and the NMOS transistor N... 10 Drain and resistor R 16 The second terminal is connected, NMOS transistor N 10 The source of the NMOS transistor 11 The source of the NMOS transistor 12 The source of the NMOS transistor 13 The sources of all NMOS transistors are grounded. 11 Drain and resistor R 15 The first terminal, the gate of PMOS transistor P7, and the NMOS transistor N 12 The gates of PMOS transistor P7 and NMOS transistor N are connected. 12 The drain of the NMOS transistor N 13 The gate of the NMOS transistor is connected to the gate of the NMOS transistor. 13 Drain and resistor R 17 The second terminal is connected to the resistor R. 17 The first terminal is used to connect to a 1V voltage; resistor R 16 The second terminal outputs the first level signal of the interval, resistor R 17 The second terminal outputs the second level signal of the interval.

10. The memristor-based multi-stimulus competition system as described in claim 9, characterized in that, The output module includes logic gate D. 13 ~Logic gate D 18 NMOS transistor 14 ~NMOS transistor N 16 Resistance R 18 ~resistance R 20 ; Logic gate D 13 ~Logic gate D 16 For AND gates, logic gate D 17 D 18 NOT gate; among which, Logic gate D 13 The two input terminals are respectively connected to the first level signal of the interval and the second level signal of the interval, and the logic gate D 17 The input terminal is connected to the first level signal of the interval, and the logic gate D 18 The input terminal is connected to the second level signal of the interval, and the logic gate D 14 The first input terminal and logic gate D 13 The output of logic gate D is connected to the logic gate D. 14 The second and third input terminals are respectively connected to the physical intensity voltages generated in the two multi-scale cue fusion devices currently performing pairwise comparisons, logic gate D. 15 The first input terminal and logic gate D 17 The output of logic gate D is connected to the logic gate D. 15 The second and third input terminals are respectively connected to the physical intensity voltages generated in the two multi-scale cue fusion devices currently performing pairwise comparisons, logic gate D. 16 The first input terminal and logic gate D 18 The output of logic gate D is connected to the logic gate D. 16 The second and third input terminals are respectively connected to the physical intensity voltages generated in the two multi-scale cue fusion devices currently performing pairwise comparisons, logic gate D. 14 The output terminal is connected to the NMOS transistor N 14 The gates are connected, logic gate D 15 The output terminal is connected to the NMOS transistor N 15 The gates are connected, logic gate D 16 The output terminal is connected to the NMOS transistor N 16 The gate of the NMOS transistor is connected to the gate of the NMOS transistor. 14 The drain of the NMOS transistor is used to connect to the first drive voltage V1. 15 The drain of the NMOS transistor is used to connect to the second drive voltage V2. 16 The drain of the NMOS transistor is used to connect to the third drive voltage V3. 14 The source and resistor R 18 The second terminal is connected to the resistor R. 18 The first terminal is grounded, and the NMOS transistor N 15 The source and resistor R 19 The second terminal is connected to the resistor R. 19 The first terminal is grounded, and the NMOS transistor N 16 The source and resistor R 20 The second terminal is connected to the resistor R. 20 The first terminal is grounded, and the NMOS transistor N 14 The source output first suppression output voltage V inhibition NMOS transistor N 15 The source output second winning output voltage V win_2 NMOS transistor N 16 The source output first winning output voltage V win_1 If the first suppression output voltage V inhibition A high level indicates that the difference between the second fusion significance voltage and the first fusion significance voltage is within the set range [-V]. l V h Within, if the second winning output voltage V win_2 A high level indicates that the second fusion significance voltage is greater than the first fusion significance voltage +V. h If the first winning output voltage V win_1 A high level indicates that the first fusion significance voltage is greater than the second fusion significance voltage +V. l V l V h These are the interval division values ​​determined by the window comparator module.

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