Semiconductor device and cutting method thereof, and semiconductor chip

Abstract

The invention provides a semiconductor device, a cutting method thereof and a semiconductor chip, relates to the technical field of semiconductor chips, and aims to solve the technical problem that the packaging yield of the semiconductor chip is low. The semiconductor device comprises a substrate, a plurality of semiconductor units and a plurality of test structures, wherein the plurality of semiconductor units and the plurality of test structures are located on one side of the substrate. The plurality of semiconductor units are distributed in an array, and at least part of the plurality of test structures is located between two adjacent semiconductor units. In the two adjacent semiconductor units and the test structure between the two adjacent semiconductor units, the distance between one semiconductor unit and the test structure is smaller than the distance between the other semiconductor unit and the test structure. The semiconductor chip obtained by cutting the semiconductor device is applied to a three-dimensional memory so as to realize data reading and writing operation.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor chips, and in particular to a semiconductor device and a cutting method thereof, and a semiconductor chip. Background Art

[0002] Before existing three-dimensional NAND memory (3D NAND) can be used in electronic products, the die must be separated from the wafer. However, the wafer cannot be split in the specified direction during dicing, which can easily lead to chip cracking, edge collapse, or damage, affecting the subsequent die packaging yield.

[0003] Therefore, how to improve the packaging yield of semiconductor chips obtained by cutting semiconductor devices is a technical problem that needs to be solved urgently. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor device, a cutting method thereof, and a semiconductor chip.

[0005] The embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a semiconductor device is provided, comprising: a substrate, and a plurality of semiconductor units and a plurality of test structures located on one side of the substrate. The plurality of semiconductor units are arranged in an array, and at least some of the plurality of test structures are located between two adjacent semiconductor units. In each of the two adjacent semiconductor units and the test structure located between the two adjacent semiconductor units, the distance between one semiconductor unit and the test structure is smaller than the distance between another semiconductor unit and the test structure.

[0007] In some embodiments, the plurality of test structures are arranged in an array, with a row of test structures and a row of semiconductor units arranged alternately along a first direction, which is the arrangement direction of a column of semiconductor units.

[0008] In some embodiments, a row of test structures includes a first side and a second side in a first direction. Of the two rows of semiconductor units adjacent to each row of test structures, the row of semiconductor units with the smallest distance from the test structure is located on the first side of the test structure.

[0009] In some embodiments, the plurality of test structures are arranged in an array, and along a second direction, a row of test structures and a row of semiconductor units are alternately arranged. The second direction is the arrangement direction of a row of semiconductor units.

[0010] In some embodiments, in the second direction, a column of test structures includes a third side and a fourth side. Of the two adjacent columns of semiconductor units of each column of test structures, the column of semiconductor units with a smaller distance from the test structure is located on the third side of the test structure.

[0011] In some embodiments, the plurality of semiconductor units are divided into a plurality of groups, each group including two rows of semiconductor units. A plurality of test structures are arranged in an array, with two rows of test structures disposed between two rows of semiconductor units in a group of semiconductor units, and no test structures disposed between two adjacent groups of semiconductor units.

[0012] In some embodiments, a distance between two rows of semiconductor units in a group of semiconductor units is greater than a distance between two adjacent groups of semiconductor units.

[0013] In some embodiments, in two rows of test structures disposed between two rows of semiconductor cells in a group of semiconductor cells, the distance between one row of test structures and its adjacent row of semiconductor cells is equal to the distance between another row of test structures and another row of semiconductor cells.

[0014] In some embodiments, the plurality of semiconductor units are divided into a plurality of groups, each group including two columns of semiconductor units. A plurality of test structures are arranged in an array, with two columns of test structures disposed between two columns of semiconductor units in a group of semiconductor units, and no test structures disposed between two adjacent groups of semiconductor units.

[0015] In some embodiments, a distance between two rows of semiconductor units in a group of semiconductor units is greater than a distance between two adjacent groups of semiconductor units.

[0016] In some embodiments, the two columns of test structures disposed between two columns of semiconductor units in a group of semiconductor units have equal spacing to the two rows of semiconductor units on both sides.

[0017] On the other hand, a method for cutting a semiconductor device is provided, comprising: forming a plurality of semiconductor units and a plurality of test structures on one side of a substrate. The plurality of semiconductor units are arranged in an array, and at least some of the plurality of test structures are located between two adjacent groups of semiconductor units. In the case of two adjacent semiconductor units and the test structure located between the two adjacent semiconductor units, the distance between one semiconductor unit and the test structure is smaller than the distance between the other semiconductor unit and the test structure. Cutting is performed in the area between the test structure and the semiconductor unit farther from the test structure, thereby cutting the semiconductor device into a plurality of semiconductor chips. The semiconductor chip includes a substrate to be cut and semiconductor units located on the cut substrate.

[0018] In some embodiments, cutting a semiconductor device into a plurality of semiconductor chips includes forming a mask layer on a surface of the plurality of semiconductor units and the plurality of test structures that is remote from the substrate, the mask layer including a plurality of openings that expose areas between two adjacent semiconductor units and between a test structure and a semiconductor unit that is further away from the test structure. Etching the semiconductor device through the plurality of openings to obtain the plurality of semiconductor chips.

[0019] In some embodiments, a row of test structures and a row of semiconductor units are arranged alternately, and a column of test structures and a column of semiconductor units are arranged alternately. The multiple openings in the mask layer expose the areas between two adjacent rows of semiconductor units, between a row of test structures and a row of semiconductor units farther from a row of test structures, and between two adjacent columns of semiconductor units, and between a column of test structures and a column of semiconductor units farther from a column of test structures.

[0020] In some embodiments, the plurality of semiconductor units are divided into a plurality of first groups, each of which includes two rows of semiconductor units, two rows of test structures are disposed between the two rows of semiconductor units in the first group, and no test structures are disposed between two adjacent first groups. Furthermore, the plurality of semiconductor units are divided into a plurality of second groups, each of which includes two columns of semiconductor units, two columns of test structures are disposed between the two columns of semiconductor units in the second group, and no test structures are disposed between two adjacent second groups. The plurality of openings in the mask layer expose an area between the two rows of test structures between the two rows of semiconductor units in the first group, an area between the two columns of test structures between the two columns of semiconductor units in the second group, an area between two adjacent first groups, and an area between two adjacent second groups.

[0021] In another aspect, a semiconductor chip is provided, comprising: a substrate, a semiconductor unit and a plurality of test structures disposed on the substrate, wherein the plurality of test structures are disposed along a portion of a side edge of the semiconductor unit.

[0022] In some embodiments, a distance between a side of the test structure away from the semiconductor unit and the semiconductor unit is smaller than a distance between an edge of the substrate located on a side of the test structure away from the semiconductor unit and the semiconductor unit.

[0023] In some embodiments, the semiconductor unit includes a first side and a second side arranged opposite to each other in a first direction, and a third side and a fourth side arranged opposite to each other in a second direction, wherein the first direction intersects the second direction and is parallel to the substrate. The distance between the first side and the edge of the substrate adjacent to it in the first direction is smaller than the distance between the second side and the edge of the substrate adjacent to it in the first direction. The distance between the third side and the edge of the substrate adjacent to it in the second direction is smaller than the distance between the fourth side and the edge of the substrate adjacent to it in the second direction. A plurality of test structures are arranged along the second side and the fourth side. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0025] Figure 1 A top view of a semiconductor device in an embodiment provided by the present disclosure;

[0026] Figure 2 for Figure 1 A top view of a minimal repeating unit of a provided semiconductor device;

[0027] Figure 3 for Figure 1 A cross-sectional view of a semiconductor device is provided;

[0028] Figure 4 for Figure 1 A cross-sectional view of another semiconductor device is provided;

[0029] Figure 5 A top view of a semiconductor device in another embodiment provided by the present disclosure;

[0030] Figure 6 for Figure 5 A top view of a minimal repeating unit of a provided semiconductor device;

[0031] Figure 7 A top view of a semiconductor device in yet another embodiment provided by the present disclosure;

[0032] Figure 8 for Figure 7 A top view of a minimal repeating unit of a provided semiconductor device;

[0033] Figure 9 A top view of a semiconductor device in yet another embodiment provided by the present disclosure;

[0034] Figure 10 for Figure 9 A top view of a minimal repeating unit of a provided semiconductor device;

[0035] Figure 11 A flow chart of a method for cutting a semiconductor device in an embodiment provided by the present disclosure;

[0036] Figure 12 A flow chart of a method for cutting a semiconductor device in another embodiment provided by the present disclosure;

[0037] Figure 13 For Figure 12 A cross-sectional view of a semiconductor device corresponding to the provided cutting method;

[0038] Figure 14 For Figure 12 A cross-sectional view of another semiconductor device corresponding to the provided cutting method;

[0039] Figure 15 For Figure 12 A cross-sectional view of another semiconductor device corresponding to the provided cutting method;

[0040] Figure 16 A cross-sectional view of a semiconductor device according to an embodiment of the present disclosure;

[0041] Figure 17 A cross-sectional view of another semiconductor device in an embodiment provided by the present disclosure;

[0042] Figure 18 A cross-sectional view of another semiconductor device in an embodiment provided by the present disclosure;

[0043] Figure 19 A cross-sectional view of another semiconductor device in an embodiment provided by the present disclosure;

[0044] Figure 20 A cross-sectional view of another semiconductor device in an embodiment provided by the present disclosure;

[0045] Figure 21 A cross-sectional view of another semiconductor device in an embodiment provided by the present disclosure;

[0046] Figure 22 A cross-sectional view of another semiconductor device in an embodiment provided by the present disclosure;

[0047] Figure 23 A cross-sectional view of another semiconductor device in an embodiment provided by the present disclosure;

[0048] Figure 24 A cross-sectional view of another semiconductor device in an embodiment provided by the present disclosure;

[0049] Figure 25 A cross-sectional view of another semiconductor device in an embodiment provided by the present disclosure;

[0050] Figure 26 A cross-sectional view of another semiconductor device in an embodiment provided by the present disclosure;

[0051] Figure 27A schematic structural diagram of a semiconductor chip in an embodiment provided by the present disclosure. DETAILED DESCRIPTION

[0052] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0053] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0054] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0055] As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0056] Figure 1 A top view of a semiconductor device 10 according to an embodiment of the present disclosure is provided; Figure 2 for Figure 1 A top view of a minimal repeating unit 20 of a semiconductor device 10 is provided.

[0057] See Figure 1 and Figure 2 In one embodiment, the semiconductor device 10 may be a wafer, wherein the wafer may have undergone a certain processing process. For example, the processing process may be a memory array process integration process, a peripheral circuit process integration process, etc.

[0058] The semiconductor device 10 may include a substrate 101 , a plurality of semiconductor units 400 arranged in an array and disposed on the substrate 101 , and a test structure 300 disposed between two adjacent semiconductor units 400 .

[0059] Exemplarily, the semiconductor unit 400 may include a device structure and an interconnection structure of the device structure. The device structure may include at least one of an active device and a passive device. The active device may, for example, include a MOS device, a memory device, or other semiconductor device, wherein the memory device may, for example, include a non-volatile memory or a random access memory device. The non-volatile memory may, for example, include at least one field effect transistor of a three-dimensional NAND memory and a three-dimensional NOR memory, or a ferroelectric memory. The passive device may, for example, include a resistor, a capacitor, or an inductor. The device structure may be a planar device or a three-dimensional device, wherein the three-dimensional device may, for example, be a fin field effect transistor (FIN-FET) and a three-dimensional memory.

[0060] In some examples, the semiconductor units 400 may be arranged in rows and columns. However, when the semiconductor device 10 is a wafer, since the wafer substrate 101 is generally circular, the number of semiconductor chips 200 arranged in each row or column may be the same or different.

[0061] In some examples, the test structure 300 can be centrally located between two adjacent semiconductor units 400 to test the electrical specifications of the semiconductor device 10, determine whether the semiconductor device 10 meets process requirements, and evaluate the quality and stability of the semiconductor device 10. For example, the test structure 300 can include structures such as pads and pins required for testing.

[0062] During the packaging process, it is necessary to perform a dicing operation on the semiconductor unit 400 to achieve the division of the semiconductor device 10 into multiple semiconductor chips. The path of the dicing knife for cutting is the dicing lane. In some examples, the dicing lane can be a preset path before the dicing knife cuts, which is a non-physical device structure. The dicing lanes can be arranged horizontally or vertically, that is, in the semiconductor units 400 arranged in an array, dicing lanes can be set between two adjacent rows of semiconductor units 400 and two adjacent columns of semiconductor units 400.

[0063] In some examples, the scribe lines can be designed on the test structures 300 and extend along the arrangement direction of the test structures 300. A buffer distance is provided between the test structures 300 and the semiconductor units 400 on both sides thereof to protect the semiconductor units 400 on both sides during the dicing operation.

[0064] Figure 3 for Figure 1 A cross-sectional view of a semiconductor device 10 is provided, Figure 4 for Figure 1 A cross-sectional view of another semiconductor device 10 is provided.

[0065] See Figure 3 and Figure 4 When the dicing lanes are designed on the test structure 300, because the test structure 300 may be made of metal, the resulting cut surface during the dicing operation is less flat and contains foreign particles, which can affect the subsequent hybrid bonding process. Furthermore, the material characteristics of the test structure 300 pose a risk of lateral cracks during dicing, which in turn affects the packaging yield of the resulting semiconductor chips.

[0066] The hybrid bonding process may include bonding between two semiconductor chips, bonding between a semiconductor chip and the wafer 100 , and the like.

[0067] Based on this, an embodiment of the present disclosure provides a semiconductor device 10 , which improves the packaging yield of semiconductor chips obtained after cutting the semiconductor device 10 by changing the layout of the semiconductor device 10 .

[0068] The specific structures of the semiconductor device and semiconductor chip provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0069] Figure 5 A top view of a semiconductor device 10 in another embodiment provided by the present disclosure is shown. Figure 6 for Figure 5 A top view of a minimal repeating unit 20 of a semiconductor device 10 is provided.

[0070] See Figure 5 and Figure 6In one embodiment, a semiconductor device includes a substrate 101, and a plurality of semiconductor units 400 and a plurality of test structures 300 located on one side of the substrate 101. The plurality of semiconductor units 400 are arranged in an array, and at least some of the plurality of test structures 300 are located between two adjacent semiconductor units 400. Among the two adjacent semiconductor units 400 and the test structures 300 located between the two adjacent semiconductor units 400, the distance between one semiconductor unit 400 and one test structure 300 is smaller than the distance between another semiconductor unit 400 and the test structure 300.

[0071] In some examples, by arranging the test structure 300 between two adjacent semiconductor units 400 close to any one of the two semiconductor units 400, sufficient layout space can be provided for setting the cutting lanes, so that the layout position of the cutting lanes does not need to pass through the test structure 300.

[0072] In the embodiment of the present disclosure, since the layout position of the cutting path does not need to pass through the test structure 300, during the scribing operation, the problem of lateral cracks or impurity particles caused by the presence of the test structure 300 can be avoided, thereby improving the packaging yield of the semiconductor chip obtained by cutting the semiconductor device 10.

[0073] Among them, the cutting path can be set between the test structure 300 and the semiconductor unit 400 which is relatively far away from the test structure 300, so that during the scribing process, the test structure 300 can be used as a buffer area for the semiconductor unit 400 adjacent to the test structure 300, thereby saving the layout area of the substrate 101 and avoiding the waste of the layout area of the substrate 101, thereby improving the layout utilization rate of the substrate 101.

[0074] Please continue reading Figure 5 and Figure 6 In one embodiment, the plurality of test structures 300 are arranged in an array, with a row of test structures 300 and a row of semiconductor units 400 arranged alternately along a first direction Y. The first direction Y is the arrangement direction of a column of semiconductor units 400.

[0075] In the disclosed embodiment, the layout positions of the multiple rows of test structures 300 and the multiple rows of semiconductor units 400 in the first direction Y can ensure a uniform and neat layout of the overall semiconductor device 10 in the first direction Y. This facilitates the subsequent layout of saw streets on the substrate 101 along the first direction Y, thereby reducing the difficulty of subsequent sawing of the semiconductor device 10 along the saw streets. Furthermore, the uniform and neat layout of the semiconductor device 10 helps improve the layout utilization of the substrate 101 and avoids waste of the layout area of the substrate 101.

[0076] Please continue reading Figure 5 and Figure 6 In one embodiment, in the first direction Y, a row of test structures 300 includes a first side 301 and a second side 302. Of the two rows of semiconductor units 400 adjacent to each row of test structures 300, the row of semiconductor units 400 with the smallest distance from the test structure 300 is located on the first side 301 of the test structure 300.

[0077] In the semiconductor device 10 of this embodiment, by arranging a row of test structures 300 close to the semiconductor units 400 on the same side, the area for laying out the cutting paths can be set on the same side of the row of test structures 300. Therefore, during the scribing operation, the cutting paths can be located on the same side of the row of test structures 300 and extend in a straight line.

[0078] By setting a cutting road extending in a straight line, the process difficulty of the dicing operation can be reduced, and multiple semiconductor chips with relatively uniform sizes can be obtained, which is conducive to the implementation of subsequent hybrid bonding and packaging processes of the semiconductor chips.

[0079] Please continue reading Figure 5 and Figure 6 In one embodiment, the plurality of test structures 300 are arranged in an array, and along the second direction X, a row of test structures 300 and a row of semiconductor units 400 are alternately arranged. The second direction X is the arrangement direction of a row of semiconductor units 400.

[0080] In the disclosed embodiment, the distribution of the multiple rows of test structures 300 and the multiple rows of semiconductor units 400 in the second direction X allows for a uniform and neat layout of the overall semiconductor device 10 in the second direction X. This facilitates the subsequent layout of saw streets on the substrate 101 along the second direction X, thereby reducing the difficulty of subsequently cutting the semiconductor device 10 along the saw streets. Furthermore, the neat and uniform layout of the semiconductor device 10 helps improve the layout utilization of the substrate 101, thereby increasing the array density of the semiconductor units 400 on the semiconductor device 10.

[0081] Please continue reading Figure 5 and Figure 6 In one embodiment, in the second direction X, a column of test structures 300 includes a third side 303 and a fourth side 304. Of the two adjacent columns of semiconductor units 400 of each column of test structures 300, the column of semiconductor units 400 that is closer to the test structure 300 is located on the third side 303 of the test structure 300.

[0082] In the semiconductor device 10 of this embodiment, by arranging a column of test structures 300 close to the semiconductor units 400 on the same side, the area for laying out the cutting paths can be arranged on the same side of the column of test structures 300. Therefore, during the scribing operation, the cutting paths can be located on the same side of the column of test structures 300 and extend in a straight line.

[0083] By setting a cutting path extending in a straight line, the difficulty of the dicing operation can be reduced, and after the dicing operation is completed, semiconductor chips with relatively uniform sizes can be obtained, which is conducive to the implementation of subsequent hybrid bonding and packaging processes of the semiconductor chips.

[0084] Figure 7 A top view of a semiconductor device 10 in another embodiment provided by the present disclosure is shown. Figure 8 for Figure 7 A top view of a minimal repeating unit 20 of a semiconductor device 10 is provided.

[0085] See Figure 7 and Figure 8 In one embodiment, the plurality of semiconductor units 400 are divided into a plurality of groups, each group including two rows of semiconductor units 400. The plurality of test structures 300 are arranged in an array, with two rows of test structures 300 disposed between two rows of semiconductor units 400 in a group of semiconductor units 400, and no test structure 300 disposed between two adjacent groups of semiconductor units 400.

[0086] The disclosed embodiment groups multiple semiconductor units 400 and adjusts the layout of the multiple groups of semiconductor units 400 and the test structures 300 on the substrate 101. For example, the entire structure formed by two rows of test structures 300 can be centered between the two rows of semiconductor units 400 in each group, or can be offset toward the semiconductor units 400 on either side.

[0087] The dicing line may be disposed between two rows of test structures 300 . For example, the dicing line may be disposed in the center between the two rows of test structures 300 , or may be offset toward the test structures 300 on either side.

[0088] With this arrangement, the cutting path can avoid the test structure 300 , thereby preventing the occurrence of lateral cracks or foreign particles due to the presence of the test structure 300 during the scribing operation, thereby improving the subsequent packaging yield of the semiconductor chip 200 .

[0089] Figure 9 A top view of a semiconductor device 10 in another embodiment provided by the present disclosure is shown. Figure 10 for Figure 9 A top view of a minimal repeating unit 20 of a semiconductor device 10 is provided.

[0090] See Figure 9 and Figure 10 In some examples, since the cutting lanes within each group of semiconductor units 400 are arranged between two rows of test structures 300, during the dicing operation, the two rows of test structures 300 can be used to protect the semiconductor units 400 on both sides respectively, so that there is no need to set an additional buffer distance between the test structure 300 and the semiconductor unit 400 on its adjacent side.

[0091] Such an arrangement can reduce the waste of the layout area on the substrate 101 and fully utilize the layout area of the substrate 101, thereby improving the layout utilization rate of the substrate 101.

[0092] Please continue reading Figure 7 and Figure 8 In one embodiment, the distance between two rows of semiconductor units 400 in a group of semiconductor units 400 is greater than the distance between two adjacent groups of semiconductor units 400.

[0093] In the semiconductor device 10 of this embodiment, no test structure 300 is provided between two adjacent groups of semiconductor units 400. Therefore, the distance between the two adjacent groups of semiconductor units 400 can be shortened to reduce the waste of layout area on the substrate 101, thereby improving the layout utilization of the substrate 101, and further increasing the number of semiconductor units 400 on the substrate 101 of the same size, thereby improving the array density of the semiconductor units 400.

[0094] In some examples, the scribe line can be centered between two adjacent groups of semiconductor units 400. Therefore, only a buffer distance is required between the two adjacent groups of semiconductor units 400 to protect the semiconductor units 400 on both sides of the scribe line during the dicing operation. This arrangement can further reduce the distance between the two adjacent groups of semiconductor units 400.

[0095] Please continue reading Figure 7 and Figure 8 In one embodiment, in two rows of test structures 300 arranged between two rows of semiconductor units 400 in a group of semiconductor units 400, the distance between one row of test structures 300 and its adjacent row of semiconductor units 400 is equal to the distance between another row of test structures 300 and the other row of semiconductor units 400.

[0096] In the semiconductor device 10 of this embodiment, the whole formed by the two rows of test structures 300 can be centrally arranged between the two rows of semiconductor units 400 in each group, so that the layout of the test structures 300 and the semiconductor units 400 on the semiconductor device 10 can be more uniform, which facilitates subsequent cutting operations.

[0097] Please continue to see Figure 9 and Figure 10 By reducing the distance between each row of test structures 300 and its adjacent row of semiconductor units 400, the layout area occupied by the semiconductor device 10 can be further reduced, thereby improving the layout utilization of the semiconductor device 10 and further improving the device density of the semiconductor device 10.

[0098] Please continue reading Figure 7 and Figure 8 In one embodiment, the plurality of semiconductor units 400 are divided into a plurality of groups, each group including two columns of semiconductor units 400. The plurality of test structures 300 are arranged in an array, with two columns of test structures 300 disposed between two columns of semiconductor units 400 within a group of semiconductor units 400, and no test structure 300 disposed between two adjacent groups of semiconductor units 400.

[0099] The disclosed embodiment groups multiple semiconductor units 400 and adjusts the layout of the multiple groups of semiconductor units 400 and the test structures 300 on the substrate 101. For example, the entire structure consisting of two columns of test structures 300 can be centered between the two columns of semiconductor units 400 within each group, or can be offset toward the semiconductor units 400 on either side.

[0100] The cutting line may be disposed between two columns of test structures 300 . For example, the cutting line may be disposed in the center between the two columns of test structures 300 , or may be offset toward the test structure 300 on either side.

[0101] With this arrangement, the cutting path can avoid the test structure 300 , thereby preventing the occurrence of lateral cracks or foreign particles due to the presence of the test structure 300 during the scribing operation, thereby improving the subsequent packaging yield of the semiconductor chips.

[0102] Please continue reading Figure 9 and Figure 10 In some examples, because the scribe lines within each group of semiconductor cells 400 are located between two rows of test structures 300, the two rows of test structures 300 can be used to protect the semiconductor cells 400 on either side during the dicing process, eliminating the need for a buffer distance between the test structure 300 and the adjacent semiconductor cell 400. This arrangement reduces waste of layout area on the substrate 101, fully utilizing the layout area of the substrate 101 and improving the layout utilization rate of the substrate 101.

[0103] Please continue reading Figure 7 and Figure 8 In one embodiment, the distance between two columns of semiconductor units 400 in a group of semiconductor units 400 is greater than the distance between two adjacent groups of semiconductor units 400.

[0104] In the semiconductor device 10 of this embodiment, no test structure 300 is provided between two adjacent groups of semiconductor units 400. Therefore, the distance between the two adjacent groups of semiconductor units 400 can be reduced to avoid wasting the layout area of the substrate 101, thereby improving the layout utilization of the substrate 101, and further increasing the number of semiconductor units 400 on the wafer 100 of the same size, thereby improving the device density.

[0105] In some examples, the cutting path can be centered between two adjacent groups of semiconductor units 400, so only a buffer distance needs to be set between the two adjacent groups of semiconductor units 400 to protect the semiconductor units 400 on both sides of the cutting path during the dicing operation. Such a setting can further reduce the distance between the two adjacent groups of semiconductor units 400 and improve the device density.

[0106] Please continue reading Figure 7 and Figure 8 In one embodiment, in two columns of test structures 300 arranged between two columns of semiconductor units 400 in a group of semiconductor units 400, the distance between one column of test structures 300 and its adjacent column of semiconductor units 400 is equal to the distance between the other column of test structures 300 and the other column of semiconductor units 400.

[0107] In the semiconductor device 10 of this embodiment, the entirety formed by the two rows of test structures 300 can be centrally disposed between the two rows of semiconductor units 400 in each group. This can make the layout of the test structures 300 and the semiconductor units 400 on the semiconductor device 10 more uniform, thereby reducing the difficulty of subsequent cutting operations.

[0108] Please continue to see Figure 9 and Figure 10 By reducing the distance between each column of test structures 300 and its adjacent column of semiconductor units 400, the layout area occupied by the semiconductor device 10 can be further reduced, thereby improving the layout utilization of the semiconductor device 10, increasing the number of semiconductor units 400, and further improving the array density of the semiconductor units 400.

[0109] Based on the semiconductor devices 10 provided in some of the above embodiments, an embodiment of the present disclosure further provides a method for cutting the semiconductor device 10 . The method for cutting the semiconductor device 10 can be used to cut the above-mentioned semiconductor devices 10 .

[0110] Figure 11 This is a flow chart of a method for cutting a semiconductor device 10 in an embodiment provided by the present disclosure.

[0111] See Figure 11 The method for cutting the semiconductor device 10 includes the following steps S1 to S2.

[0112] S1. Form a plurality of semiconductor units 400 and a plurality of test structures 300 on one side of a substrate 101. The plurality of semiconductor units 400 are arranged in an array, and at least some of the plurality of test structures 300 are located between two adjacent groups of semiconductor units 400. For two adjacent semiconductor units 400 and a test structure 300 located between the two adjacent semiconductor units 400, the distance between one semiconductor unit 400 and the test structure 300 is smaller than the distance between another semiconductor unit 400 and the test structure 300.

[0113] In step S1, a substrate 101 is provided. The substrate 101 may be a single crystal silicon (Si) substrate, a single crystal germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate material may also be a compound semiconductor. For example, the substrate may be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, or a silicon carbide (SiC) substrate. The substrate disclosed herein may also be prepared from other semiconductor materials commonly used in the art.

[0114] A plurality of semiconductor units 400 and a plurality of test structures 300 are formed on one side of the substrate 101. The semiconductor units 400 may include three-dimensional memory devices, such as DRAM or 3D NAND memory arrays, and may also include peripheral circuits, CMOS image sensors, etc. The test structures 300 may include structures such as pads and pins.

[0115] In the semiconductor device 10 formed in the embodiment of the present disclosure, the test structure 300 between two adjacent semiconductor units 400 is offset toward the semiconductor unit 400 on either side, thereby providing a layout area for setting scribe lines on the substrate 101. By setting the scribe lines directly on the substrate 101, the test structure 300 can be avoided during the dicing operation, thereby preventing the generation of lateral cracks or foreign particles, thereby improving the packaging yield of the diced semiconductor chips.

[0116] In addition, the test structure 300 can directly serve as a buffer structure for the semiconductor unit 400 adjacent thereto, thereby preventing the dicing process from affecting the semiconductor unit 400 .

[0117] S2. Cutting is performed in the region between the test structure 300 and the semiconductor unit 400 which is farther from the test structure 300 to cut the semiconductor device 10 into a plurality of semiconductor chips. The semiconductor chip includes a cut substrate 101 and semiconductor units 400 located on the cut substrate 101.

[0118] In step S2, a dicing line is set between the test structure 300 and the semiconductor unit 400. During the dicing operation, any dicing method such as laser dicing, knife dicing or etching dicing can be used to dicing the semiconductor device 10 into multiple semiconductor chips 200.

[0119] Figure 12 This is a flow chart of a method for cutting a semiconductor device 10 in another embodiment provided by the present disclosure. Figure 13 For Figure 12 A cross-sectional view of a semiconductor device 10 corresponding to the cutting method provided, Figure 14 For Figure 12 A cross-sectional view of another semiconductor device 10 corresponding to the cutting method provided, Figure 15 For Figure 12 A cross-sectional view of another semiconductor device 10 corresponding to the cutting method provided, Figure 16 FIG. 1 is a cross-sectional view of a semiconductor device 10 in yet another embodiment of the present disclosure.

[0120] See Figure 12 The above step S2 of cutting the semiconductor device 10 into a plurality of semiconductor chips further includes the following steps S21 to S22.

[0121] S21. A mask layer 102 is formed on a surface of the plurality of semiconductor units 400 and the plurality of test structures 300 that is away from the substrate 101. The mask layer 102 includes a plurality of openings 103. The plurality of openings 103 expose the areas between two adjacent semiconductor units 400 and between a test structure 300 and a semiconductor unit 400 that is farther away from the test structure 300.

[0122] In this step S21, refer to Figure 13 A photoresist layer is formed on a surface of the semiconductor units 400 and the test structures 300 that is away from the substrate 101, and the photoresist layer is patterned to obtain a mask layer 102 having a plurality of openings 103. The locations on the semiconductor device 10 exposed by the openings 103 are the locations where the dicing streets are set.

[0123] S22 , etching the semiconductor device 10 through the plurality of openings 103 to obtain a plurality of semiconductor chips.

[0124] For example, dry etching can be used to etch the semiconductor device 10 exposed by the plurality of openings 103, thereby dividing the semiconductor device 10 into a plurality of semiconductor chips. The substrate 101 can be made of a single material or two or more materials.

[0125] See Figure 14 and Figure 15Since the etching process requires the etched medium to be uniform, when the substrate 101 is composed of two different materials stacked together, the etching process of the substrate 101 can be completed in two steps. Figure 14 The stacking interface 800 of two different materials is shown, that is, the stacking interface 800 is set at the position where the first etching stops.

[0126] Due to the size limitation of the semiconductor device 10, the size of the cutting road arranged on the semiconductor device 10 is relatively small. The etching process is used to divide the semiconductor device 10, which has good directionality. It can reduce the process difficulty while improving the accuracy of division and realizing narrow pitch cutting.

[0127] In addition, the cutting surface formed by the etching process has a high surface flatness and does not produce impurity particles, which can improve the cleanliness of the semiconductor chip and thereby improve the packaging yield of the subsequent packaging of the semiconductor chip.

[0128] The above embodiment is a preferred embodiment of the method for cutting the semiconductor device 10 provided by the present disclosure. Figure 16 In other embodiments, the semiconductor device 10 can be directly cut into multiple semiconductor chips using a cutting tool, laser, or other cutting methods.

[0129] In some examples, before cutting the semiconductor device 10 into a plurality of semiconductor chips in step S2 , the substrate 101 of the semiconductor device 10 needs to undergo a thinning process.

[0130] Figure 17 is a cross-sectional view of yet another semiconductor device 10 in an embodiment provided by the present disclosure, Figure 18 is a cross-sectional view of yet another semiconductor device 10 in an embodiment provided by the present disclosure, Figure 19 is a cross-sectional view of yet another semiconductor device 10 in an embodiment provided by the present disclosure, Figure 20 FIG. 1 is a cross-sectional view of another semiconductor device 10 according to an embodiment of the present disclosure.

[0131] See Figures 17-20 In the aforementioned step S1 , the thickness of the provided substrate 101 is generally greater than the thickness of the substrate 101 required by the semiconductor device 10 , and therefore the substrate 101 needs to be thinned.

[0132] For example, a protective film 700 is provided on the side of the substrate 101 where the semiconductor unit 400 is provided, thereby protecting the semiconductor unit 400 and the test structure 300 during the polishing process of the substrate 101. Alternatively, chemical mechanical polishing (CMP) can be used to thin the side of the substrate 101 away from the semiconductor unit 400.

[0133] After the CMP process is completed, the protection film 700 on the side of the substrate 101 where the semiconductor unit 400 is disposed is removed, thereby completing the thinning process of the substrate 101 .

[0134] In some embodiments, a row of test structures 300 and a row of semiconductor cells 400 are arranged alternately, and a column of test structures 300 and a column of semiconductor cells 400 are arranged alternately. The plurality of openings 103 in the mask layer 102 expose the regions between two adjacent rows of semiconductor cells 400, between a row of test structures 300 and a row of semiconductor cells 400 farther from the row of test structures 300, and between two adjacent columns of semiconductor cells 400, and between a column of test structures 300 and a column of semiconductor cells 400 farther from the column of test structures 300.

[0135] The semiconductor device 10 of this embodiment can be divided into multiple independent semiconductor chips by providing dicing lanes between the multiple semiconductor units 400 arranged in an array. Since multiple test structures 300 are interspersed between the multiple semiconductor units 400 arranged in an array, the dicing lanes need to be arranged to avoid the test structures 300 and instead be located between each row of test structures 300 and a row of semiconductor units 400 farther from that row of test structures 300, as well as between each column of test structures 300 and a column of semiconductor units 400 farther from that column of test structures 300. This arrangement avoids problems such as lateral cracks or foreign particles caused by cutting the test structures 300, thereby improving the subsequent packaging yield of the semiconductor chips.

[0136] In the step of cutting the semiconductor device 10 , the plurality of openings 103 provided in the mask layer 102 expose the cutting street area at one time, which is beneficial to simplifying the cutting process and improving the accuracy of cutting the semiconductor device 10 .

[0137] In some embodiments, the plurality of semiconductor cells 400 are divided into a plurality of first groups 500, each of which includes two rows of semiconductor cells 400. Two rows of test structures 300 are disposed between the two rows of semiconductor cells 400 in the first group 500, and no test structure 300 is disposed between two adjacent first groups 500. Furthermore, the plurality of semiconductor cells 400 are divided into a plurality of second groups 600, each of which includes two columns of semiconductor cells 400. Two columns of test structures 300 are disposed between the two columns of semiconductor cells 400 in the second group 600, and no test structure 300 is disposed between two adjacent second groups 600. The plurality of openings 103 in the mask layer 102 expose the region between the two rows of test structures 300 between the two rows of semiconductor cells 400 in the first group 500, the region between the two columns of test structures 300 between the two columns of semiconductor cells 400 in the second group 600, the region between two adjacent first groups 500, and the region between two adjacent second groups 600.

[0138] The semiconductor device 10 in this embodiment groups the plurality of semiconductor units 400 so that cutting lanes are provided between two adjacent groups and between two rows or two columns of semiconductor units 400 in each group, thereby cutting the semiconductor device 10 into a plurality of independent semiconductor chips.

[0139] Among them, since the test structure 300 is arranged between two rows or two columns of semiconductor units 400 in each group, and is arranged in two rows or two columns side by side, the cutting path can be arranged between the two rows or two columns of test structures 300 arranged side by side, so as to avoid the cutting path in the subsequent cutting process, thereby improving the subsequent packaging yield of semiconductor chips and obtaining multiple semiconductor chips with relatively uniform sizes.

[0140] In the step of cutting the semiconductor device 10 , the plurality of openings 103 provided in the mask layer 102 expose the cutting street area at one time, which is beneficial to simplifying the cutting process and improving the accuracy of cutting the semiconductor device 10 .

[0141] Figure 21 is a cross-sectional view of yet another semiconductor device 10 in an embodiment provided by the present disclosure, Figure 22 is a cross-sectional view of yet another semiconductor device 10 in an embodiment provided by the present disclosure, Figure 23 is a cross-sectional view of yet another semiconductor device 10 in an embodiment provided by the present disclosure, Figure 24 is a cross-sectional view of yet another semiconductor device 10 in an embodiment provided by the present disclosure, Figure 25 is a cross-sectional view of yet another semiconductor device 10 in an embodiment provided by the present disclosure, Figure 26 FIG. 1 is a cross-sectional view of another semiconductor device 10 according to an embodiment of the present disclosure.

[0142] See also Figures 21-26 ,in, Figure 21-23 The cross-sectional view of the semiconductor device 10 corresponding to the cutting method of the semiconductor device 10 is shown in an example where the semiconductor device 10 groups the plurality of semiconductor units 400 and sets cutting streets between two rows or two columns of the semiconductor units 400 in each group.

[0143] Figure 24-26 The cross-sectional view of the semiconductor device 10 corresponding to the cutting method of the semiconductor device 10 is shown in an example in which a cutting street is provided between two adjacent groups of semiconductor units 400 after the semiconductor device 10 groups the plurality of semiconductor units 400 .

[0144] Based on the cutting methods of the semiconductor device 10 provided in some of the above embodiments, an embodiment of the present disclosure further provides a semiconductor chip. The semiconductor chip can be obtained by cutting the semiconductor device 10 using the above-mentioned cutting method of the semiconductor device 10 .

[0145] Figure 27 A schematic structural diagram of a semiconductor chip 200 in an embodiment provided by the present disclosure.

[0146] See Figure 27 In some embodiments, the semiconductor chip 200 includes a substrate 101, a semiconductor unit 400 and a plurality of test structures 300 disposed on the substrate 101. The plurality of test structures 300 are disposed along a portion of a side edge of the semiconductor unit 400.

[0147] The semiconductor chip 200 in this embodiment changes the layout of the multiple test structures 300 and the semiconductor unit 400 on the substrate 101, so that the multiple test structures 300 are arranged on part of the side of the semiconductor unit 400. This ensures the structural integrity of the test structure 300 within the limited layout area of the semiconductor chip 200, thereby providing a feasible implementation method for subsequent preparation processes that may be applied to the test structure 300.

[0148] In some embodiments, the distance between the semiconductor unit 400 and the side of the test structure 300 away from the semiconductor unit 400 is smaller than the distance between the semiconductor unit 400 and the edge of the substrate 101 located on the side of the test structure 300 away from the semiconductor unit 400 .

[0149] Please continue reading Figure 27 In the semiconductor chip 200 of this embodiment, there is a certain distance between the test structure 300 and the edge of the substrate 101. This distance can protect the test structure 300 during the cutting operation, avoiding damage to the test structure 300 during the cutting process of the semiconductor device 10, thereby ensuring the integrity of the test structure 300.

[0150] With such configuration, the semiconductor chip 200 can provide a feasible implementation method for a subsequent fabrication process that may be applied to the test structure 300 .

[0151] In some embodiments, the semiconductor unit 400 includes a first side 401 and a second side 402 disposed opposite to each other in a first direction Y, and a third side 403 and a fourth side 404 disposed opposite to each other in a second direction X, wherein the first direction Y intersects the second direction X and is parallel to the substrate 101. The distance between the first side 401 and its adjacent edge of the substrate 101 in the first direction Y is smaller than the distance between the second side 402 and its adjacent edge of the substrate 101 in the first direction Y. The distance between the third side 403 and its adjacent edge of the substrate 101 in the second direction X is smaller than the distance between the fourth side 404 and its adjacent edge of the substrate 101 in the second direction X. A plurality of test structures 300 are disposed along the second side 402 and the fourth side 404.

[0152] Please continue reading Figure 27 In the semiconductor chip 200 of this embodiment, by reducing the distance between the first side 401 and the third side 403 where the test structure 300 is not provided and the corresponding adjacent edges of the substrate 101, the size of the semiconductor chip 200 can be reduced, thereby increasing the number of semiconductor units 400 on the semiconductor device 10, improving the array density of the semiconductor units 400, and thus reducing production costs.

[0153] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: a substrate, and a plurality of semiconductor units and a plurality of test structures located on one side of the substrate; The plurality of semiconductor units are distributed in an array, and at least part of the plurality of test structures are located between two adjacent semiconductor units; In the two adjacent semiconductor units and the test structure located between the two adjacent semiconductor units, a distance between one of the semiconductor units and one of the test structures is smaller than a distance between another of the semiconductor units and the test structure.

2. The semiconductor device according to claim 1, wherein The plurality of test structures are distributed in an array, and along a first direction, a row of the test structures and a row of the semiconductor units are alternately arranged; the first direction is the arrangement direction of a column of the semiconductor units.

3. The semiconductor device according to claim 2, wherein In the first direction, a row of the test structures includes a first side and a second side; in the two rows of semiconductor units adjacent to each row of the test structures, the row of semiconductor units with a smaller distance from the test structures is located on the first side of the test structures.

4. The semiconductor device according to claim 2 or 3, characterized in that The plurality of test structures are distributed in an array, and along a second direction, a column of the test structures and a column of the semiconductor units are alternately arranged; the second direction is the arrangement direction of a row of the semiconductor units.

5. The semiconductor device according to claim 4, wherein In the second direction, a column of the test structures includes a third side and a fourth side; in each column of the test structures, of the two adjacent columns of semiconductor units, the column of semiconductor units that is at a smaller distance from the test structure is located on the third side of the test structure. The semiconductor device according to claim 1 , wherein: The plurality of semiconductor units are divided into a plurality of groups, each group including two rows of semiconductor units; The multiple test structures are distributed in an array, two rows of the test structures are arranged between two rows of the semiconductor units in one group of the semiconductor units, and no test structure is arranged between two adjacent groups of the semiconductor units.

7. The semiconductor device according to claim 6, wherein: The distance between two rows of semiconductor units in one group of semiconductor units is greater than the distance between two adjacent groups of semiconductor units.

8. The semiconductor device according to claim 6 or 7, wherein: In the two rows of test structures disposed between two rows of semiconductor units in a group of semiconductor units, the distance between one row of test structures and its adjacent row of semiconductor units is equal to the distance between the other row of test structures and the other row of semiconductor units.

9. The semiconductor device according to claim 8, wherein The plurality of semiconductor units are divided into a plurality of groups, each group including two columns of the semiconductor units; The multiple test structures are distributed in an array, two columns of the test structures are arranged between two columns of the semiconductor units in one group of the semiconductor units, and no test structure is arranged between two adjacent groups of the semiconductor units.

10. The semiconductor device according to claim 9, wherein The distance between two columns of semiconductor units in one group of semiconductor units is greater than the distance between two adjacent groups of semiconductor units.

11. The semiconductor device according to claim 10, wherein: The two columns of the test structures arranged between the two columns of semiconductor units in a group of the semiconductor units have equal spacing to the two rows of semiconductor units on both sides.

12. A method for cutting a semiconductor device, characterized in that: include: forming a plurality of semiconductor units and a plurality of test structures on one side of the substrate; The plurality of semiconductor units are arranged in an array, at least some of the plurality of test structures are located between two adjacent groups of the semiconductor units; and among the two adjacent semiconductor units and the test structures located between the two adjacent semiconductor units, the distance between one semiconductor unit and the test structure is smaller than the distance between another semiconductor unit and the test structure. Cutting is performed in a region between the test structure and the semiconductor unit which is farther from the test structure, so as to cut the semiconductor device into a plurality of semiconductor chips; the semiconductor chips include a cut substrate and semiconductor units located on the cut substrate.

13. The cutting method according to claim 12, characterized in that: Cutting the semiconductor device into a plurality of semiconductor chips comprises: forming a mask layer on a surface of the plurality of semiconductor units and the plurality of test structures away from the substrate, the mask layer comprising a plurality of openings, the plurality of openings exposing an area between two adjacent semiconductor units and an area between a test structure and a semiconductor unit farther from the test structure; The semiconductor device is etched through the plurality of openings to obtain the plurality of semiconductor chips.

14. The cutting method according to claim 13, characterized in that: A row of test structures and a row of semiconductor units are arranged alternately, and a column of test structures and a column of semiconductor units are arranged alternately; The multiple openings of the mask layer expose the areas between two adjacent rows of semiconductor units, between a row of test structures and a row of semiconductor units farther away from the row of test structures, and between two adjacent columns of semiconductor units, and between a column of test structures and a column of semiconductor units farther away from the column of test structures.

15. The cutting method according to claim 13, characterized in that: The plurality of semiconductor units are divided into a plurality of first groups, each first group including two rows of semiconductor units, two rows of test structures are provided between the two rows of semiconductor units of the first group, and no test structure is provided between two adjacent first groups; and the plurality of semiconductor units are divided into a plurality of second groups, each second group including two columns of semiconductor units, two columns of test structures are provided between the two columns of semiconductor units of the second group, and no test structure is provided between two adjacent second groups; The multiple openings of the mask layer expose the area between the two rows of test structures between the two rows of semiconductor units of the first group, the area between the two columns of test structures between the two columns of semiconductor units of the second group, the area between two adjacent first groups, and the area between two adjacent second groups.

16. A semiconductor chip, characterized in that: The invention comprises: a substrate, and a semiconductor unit and a plurality of test structures arranged on the substrate; The plurality of test structures are arranged along a portion of a side edge of the semiconductor unit.

17. The semiconductor chip according to claim 16, wherein: The distance between the semiconductor unit and a side of the test structure away from the semiconductor unit is smaller than the distance between the semiconductor unit and an edge of the substrate located on a side of the test structure away from the semiconductor unit.

18. The semiconductor chip according to claim 17, wherein: The semiconductor unit includes a first side and a second side arranged opposite to each other in a first direction, and a third side and a fourth side arranged opposite to each other in a second direction, wherein the first direction intersects the second direction and is parallel to the substrate; The distance between the first side and the edge of the substrate adjacent to it in the first direction is smaller than the distance between the second side and the edge of the substrate adjacent to it in the first direction; the distance between the third side and the edge of the substrate adjacent to it in the second direction is smaller than the distance between the fourth side and the edge of the substrate adjacent to it in the second direction; The plurality of test structures are arranged along the second side and the fourth side.

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