Semiconductor device

Abstract

This semiconductor device is provided with: an interlayer insulating film that is provided between the upper surface of a semiconductor substrate and an upper surface electrode, and that has a first contact hole that connects the semiconductor substrate and the upper surface electrode; the protective film is arranged on the upper surface of the upper surface electrode; and a plating layer provided in a region of the upper surface of the upper surface electrode that is not covered by the protective film, the semiconductor substrate having a first end side in plan view, the first contact hole having a first outer hole end portion closest to the first end side, and the second contact hole having a second outer hole end portion closest to the first end side in plan view. The plating layer is formed on a portion of the upper surface electrode that overlaps an end portion of the first outer hole.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Conventionally, there is known a semiconductor device provided with a protective film such as a polyimide film covering an emitter (for example, see Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2022-059487 Summary of the Invention

[0004] Technical issues It is preferable that a semiconductor device have small temporal variation in characteristics.

[0005] Technical Solution To solve the above-mentioned problems, in a first embodiment of the present invention, a semiconductor device is provided. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface. Any of the semiconductor devices may include a top electrode comprising aluminum. Any of the semiconductor devices may include an interlayer insulating film disposed between the upper surface of the semiconductor substrate and the top electrode, and having a first contact hole connecting the semiconductor substrate and the top electrode. Any of the semiconductor devices may include a protective film disposed on the upper surface of the top electrode. Any of the semiconductor devices may include a plating layer disposed in an area of the top surface of the top electrode that is not covered by the protective film. In any of the semiconductor devices, the semiconductor substrate may have a first end side when viewed from above. In any of the semiconductor devices, the first contact hole may have a first outer hole end portion closest to the first end side. In any of the semiconductor devices, the plating layer may be formed on a portion of the top electrode that overlaps with the first outer hole end portion.

[0006] In any of the above-mentioned semiconductor devices, the protection film may include an outer protection portion provided between the first outer hole end portion and the first end side in a plan view.

[0007] In any of the above-mentioned semiconductor devices, an inner protection end portion of the outer protection portion closest to the first contact hole may be provided between the first outer hole end portion and the first end side.

[0008] In any of the above-mentioned semiconductor devices, the protection film may further include an inner protection portion that is arranged farther from the first edge than the outer protection portion in a plan view and that overlaps with the first contact hole.

[0009] In any of the aforementioned semiconductor devices, the semiconductor substrate may include an active portion having a semiconductor element formed thereon. In any of the aforementioned semiconductor devices, the first contact hole may include an active hole end portion closest to the first end edge of the portion connecting the active portion to the top surface electrode. In any of the aforementioned semiconductor devices, the plating layer may be formed on a portion of the top surface electrode that overlaps with the active hole end portion.

[0010] In any of the above-mentioned semiconductor devices, the semiconductor substrate may have a drift region of the first conductivity type provided in the active portion. In any of the above-mentioned semiconductor devices, the semiconductor substrate may have a well region of the second conductivity type provided so as to surround the active portion when viewed from above. In any of the above-mentioned semiconductor devices, the first contact hole may have a well hole end portion closest to the first end edge in the portion connecting the well region to the upper surface electrode. In any of the above-mentioned semiconductor devices, the plating layer may be formed on the portion of the upper surface electrode overlapping with the well hole end portion.

[0011] In any of the above semiconductor devices, the semiconductor substrate may have a groove portion extending from the upper surface to the interior of the semiconductor substrate and having a length along the first direction on the upper surface. In any of the above semiconductor devices, the first outer hole end portion may be an end portion of the first contact hole in the first direction.

[0012] In any of the above-mentioned semiconductor devices, the semiconductor substrate may have a groove portion extending from the upper surface to the interior of the semiconductor substrate and having a length along the first direction on the upper surface. In any of the above-mentioned semiconductor devices, the outer protective portion may be provided between the first outer hole end and the first end side in the first direction.

[0013] In any of the above-mentioned semiconductor devices, the semiconductor substrate may have a groove portion, which is arranged from the upper surface to the inside of the semiconductor substrate and has a length along the first direction on the upper surface. In any of the above-mentioned semiconductor devices, the semiconductor substrate may have a drift region of the first conductivity type arranged in the active portion. In any of the above-mentioned semiconductor devices, the semiconductor substrate may have a base region of the second conductivity type, which is arranged between the drift region and the upper surface and is connected to the groove portion. In any of the above-mentioned semiconductor devices, the semiconductor substrate may have an accumulation region of the first conductivity type, which is arranged between the drift region and the base region and has a concentration higher than that of the drift region. In any of the above-mentioned semiconductor devices, in the first direction, the inner protective end portion may be arranged between the accumulation region and the first end side.

[0014] In any of the aforementioned semiconductor devices, the semiconductor substrate may have a plurality of grooves arranged in the second direction on the upper surface. In any of the aforementioned semiconductor devices, the plurality of grooves may extend from the upper surface to the interior of the semiconductor substrate and have a length along the first direction on the upper surface. In any of the aforementioned semiconductor devices, the first outer hole end may be an end of the first contact hole in the second direction.

[0015] In any of the above-mentioned semiconductor devices, the semiconductor substrate may include an active portion in which a semiconductor element is formed. In any of the above-mentioned semiconductor devices, the semiconductor substrate may include a plurality of trench portions arranged along a second direction on the upper surface. In any of the above-mentioned semiconductor devices, the semiconductor substrate may include a drift region of a first conductivity type disposed in the active portion. In any of the above-mentioned semiconductor devices, the semiconductor substrate may include a base region of a second conductivity type disposed between the drift region and the upper surface and in contact with the trench portion. In any of the above-mentioned semiconductor devices, the semiconductor substrate may include an accumulation region of a first conductivity type disposed between the drift region and the base region and having a higher concentration than that of the drift region. In any of the above-mentioned semiconductor devices, the plurality of trench portions may each extend from the upper surface to within the semiconductor substrate and have a length along the first direction on the upper surface. In any of the above-mentioned semiconductor devices, the inner protective end portion may be disposed between the accumulation region and the first end side in the second direction.

[0016] In any of the above-mentioned semiconductor devices, the semiconductor substrate may include an active portion in which a semiconductor element is formed. In any of the above-mentioned semiconductor devices, the semiconductor substrate may include a plurality of trench portions arranged along a second direction on the upper surface. In any of the above-mentioned semiconductor devices, the semiconductor substrate may include a drift region of a first conductivity type disposed in the active portion. In any of the above-mentioned semiconductor devices, the semiconductor substrate may include a base region of a second conductivity type disposed between the drift region and the upper surface and in contact with the trench portion. In any of the above-mentioned semiconductor devices, the semiconductor substrate may include a contact region of a second conductivity type disposed between the upper surface and the base region, connected to the upper surface electrode, and having a higher concentration than that of the base region. In any of the above-mentioned semiconductor devices, the plurality of trench portions may each extend from the upper surface to within the semiconductor substrate and have a length along the first direction on the upper surface. In any of the above-mentioned semiconductor devices, the inner protective end portion may be disposed between the contact region and the first end edge in the second direction.

[0017] In any of the above-mentioned semiconductor devices, the semiconductor substrate may further have a second end side and a third end side when viewed from above. In any of the above-mentioned semiconductor devices, the first contact hole may have a second outer hole end closest to the second end side and a third outer hole end closest to the third end side. In any of the above-mentioned semiconductor devices, the plating layer may be formed on a portion of the top surface electrode overlapping with the second outer hole end side and a portion of the top surface electrode overlapping with the third outer hole end side.

[0018] In any of the above-mentioned semiconductor devices, the plating layer may contain at least one of nickel and copper.

[0019] The above summary of the invention does not list all the necessary features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 1 is a plan view showing an example of a semiconductor device 100 according to an embodiment of the present invention.

[0021] Figure 2 yes Figure 1 Magnified view of area A.

[0022] Figure 3 It shows Figure 2 FIG. 1 is a diagram showing an example of an X1-X1' cross section.

[0023] Figure 4 It shows Figure 2 FIG. 1 is a diagram showing an example of a Y1-Y1' cross section.

[0024] Figure 5 It is a figure which shows an example of the Y2-Y2' cross section.

[0025] Figure 6 This is a diagram showing another example of the Y2-Y2' cross section.

[0026] Figure 7 It is a diagram illustrating the path of the hole current from the outer hole end portion 281 of the comparative example.

[0027] Figure 8 1 and 2 are diagrams illustrating the path of hole current from the outer hole end portion 281 according to the embodiment.

[0028] 10…semiconductor substrate, 11…well region, 12…emitter region, 14…base region, 15…contact region, 16…accumulation region, 18…drift region, 20…buffer region, 21…upper surface, 22…collector region, 23…lower surface, 24…collector electrode, 30…dummy trench portion, 32…dummy insulating film, 34…dummy conductive portion, 38…interlayer insulating film, 40…gate trench portion, 42…gate insulating film, 44…gate conductive portion, 50…first gate wiring, 51…second gate wiring, 52…upper surface electrode Pole, 53…upper surface, 54…first contact hole, 55…second contact hole, 57…pad, 100…semiconductor device, 111…center, 160…active portion, 201, 202…well hole end portion, 204…outer connection portion, 210…plating layer, 211, 222…active hole end portion, 231…end side, 251, 252, 253, 254, 255…protective film, 261, 262…inner protection end portion, 270…insulating film, 280…pad electrode, 281…outer hole end portion. DETAILED DESCRIPTION

[0029] The present invention will be described below by way of embodiments of the invention, but the following embodiments do not limit the invention of the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the technical solution of the invention.

[0030] In this specification, one side parallel to the depth direction of a semiconductor substrate is referred to as "upper," and the other side is referred to as "lower." Of the two principal surfaces of a substrate, layer, or other component, one is referred to as the upper surface, and the other is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the orientation of the semiconductor device during installation.

[0031] In this specification, technical matters are sometimes described using the orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. These axes merely determine the relative positions of components and do not define specific directions. For example, the Z-axis does not necessarily indicate the height relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is not indicated, it means a direction parallel to the +Z and -Z axes.

[0032] In this specification, the axes perpendicular to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and the Y-axis. Furthermore, the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and the Y-axis, is sometimes referred to as the horizontal direction.

[0033] The region from the center in the depth direction of the semiconductor substrate to the upper surface of the semiconductor substrate is sometimes referred to as the upper surface side. Similarly, the region from the center in the depth direction of the semiconductor substrate to the lower surface of the semiconductor substrate is sometimes referred to as the lower surface side.

[0034] In this specification, the term "same" or "equal" may include a case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0035] In this specification, the conductivity type of a doped region doped with impurities is described as P-type or N-type. In this specification, an impurity may specifically refer to either an N-type donor or a P-type acceptor, and may also be referred to as a dopant. In this specification, doping refers to the introduction of donors or acceptors into a semiconductor substrate to form a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.

[0036] In this specification, when described as P+ type or N+ type, it means that the doping concentration is higher than that of P type or N type, and when described as P- type or N- type, it means that the doping concentration is lower than that of P type or N type. In addition, when described as P++ type or N++ type in this specification, it means that the doping concentration is higher than that of P+ type or N+ type.

[0037] Figure 1 FIG. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Figure 1 , the positions of the components projected onto the upper surface of the semiconductor substrate 10 are shown. Figure 1 , semiconductor substrate 10, upper surface electrode 52, active portion 160, protective films 251, 252, 253, and 254 of semiconductor device 100 are shown, and other components are omitted. Protective films 251, 252, 253, and 254 may be insulating films formed of a polymer compound such as polyimide.

[0038] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate, but may also be a compound semiconductor substrate such as silicon carbide, gallium nitride, or gallium arsenide.

[0039] In this specification, the term "top view" refers to viewing from the upper surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has a plurality of edge sides 231 when viewed from the top. Figure 1 In FIG. 2 , the X-axis and the Y-axis are parallel to one of the end sides 231 . In addition, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10 .

[0040] The semiconductor substrate 10 of this embodiment may have two sets of end edges facing each other (at Figure 1 In this specification, each end side 231 is sometimes referred to as a first end side, a second end side, a third end side, or a fourth end side. Any end side 231 can function as a first end side. Any end side 231 can function as a second end side, a third end side, or a fourth end side.

[0041] In several figures of this specification, the cross-sectional structure near a particular edge 231 is described. The structure near another edge 231 opposite to the aforementioned edge 231 can also be similar to that near the aforementioned edge 231. For example, the structure near edge 231-1 and the structure near edge 231-3 can be similar. The structure near edge 231-2 and the structure near edge 231-4 can also be similar. However, pad 57 and protective film 252 are not provided near edge 231-4.

[0042] An upper surface electrode 52 is provided above the upper surface of the semiconductor substrate 10. Figure 1 In the figure, the region where the upper surface electrode 52 is provided is surrounded by a dotted line. The upper surface electrode 52 is an electrode through which the main current of the semiconductor element provided on the semiconductor substrate 10 flows. If the semiconductor element is an IGBT (Insulated Gate Bipolar Transistor), the upper surface electrode 52 can be an emitter electrode. If the semiconductor element is a MOSFET, the upper surface electrode 52 can be a source electrode. If the semiconductor element is a diode, the upper surface electrode 52 can be an anode electrode.

[0043] The top electrode 52 is formed of metal. At least a portion of the top electrode 52 may be formed of aluminum or an aluminum-silicon alloy. The top electrode 52 may include a barrier metal formed of titanium, a titanium compound, or the like, beneath the aluminum region. Furthermore, a plug formed by embedding tungsten or the like in contact with the barrier metal and the aluminum may be included in the contact hole.

[0044] An active portion 160 having a semiconductor element formed therein is provided on semiconductor substrate 10. As described above, the semiconductor element may include at least one of an IGBT, a MOSFET, or a diode. This specification describes an example in which an IGBT is provided on semiconductor substrate 10. Semiconductor substrate 10 may include either a reverse-conducting IGBT (RC-IGBT) or a reverse-blocking IGBT (RB-IGBT). Furthermore, when a MOSFET is provided on semiconductor substrate 10, the term "emitter" in this specification may be replaced with "source," and the term "collector" may be replaced with "drain."

[0045] The active portion 160 is a region where the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor element is in operation. The active portion 160 in this example refers to the region surrounded by the well region 11 described later when viewed from above. An upper surface electrode 52 is provided above the active portion 160. Figure 1 In the embodiment, the range of the active portion 160 and the range of the upper surface electrode 52 are made the same, but the range of the active portion 160 may be different from the range of the upper surface electrode 52 .

[0046] The semiconductor device 100 may have one or more solder pads 57 above the semiconductor substrate 10. The one or more solder pads 57 may include a solder pad insulated from the upper surface electrode 52, or may include a solder pad connected to the upper surface electrode 52. The one or more solder pads 57 may include, for example, a gate solder pad connected to the gate electrode of an IGBT or MOSFET. The one or more solder pads 57 may also include a solder pad for temperature detection, a solder pad for current detection, a solder pad for potential detection of the upper surface electrode 52, and the like. Each solder pad 57 in this example is arranged near the end edge 231-2. The vicinity of the end edge 231-2 refers to the area between the end edge 231-2 and the upper surface electrode 52 when viewed from above, or between the end edge 231-2 and the active portion 160 when viewed from above. When the semiconductor device 100 is installed, the upper surface electrode 52 and the solder pad 57 may be connected to an external circuit via wiring such as a wire.

[0047] At least a portion of each of the protective film 251, the protective film 252, the protective film 253, and the protective film 254 is disposed above the upper surface electrode 52 or the pad 57. Figure 1 In the figure, the areas where the protective films are formed are hatched with oblique lines. Each protective film exposes at least a portion of the upper surface 53 of the upper surface electrode 52. The exposed upper surface 53 can be connected to wiring such as a wire. Furthermore, each protective film exposes at least a portion of the upper surface of each pad 57. Wiring such as a wire can also be connected to the upper surface of each pad 57.

[0048] The protective film 251 is provided in contact with the edge 231 when viewed from above. In this embodiment, the protective film 251 is provided in a ring shape along the edge 231 of the semiconductor substrate 10. The protective film 251 can be provided to extend from each edge 231 to a position overlapping with the upper surface electrode 52 or to a position overlapping with the pad 57. In this embodiment, the protective film 251 extends from the edge 231-1, 231-3, and 231-4 to a position overlapping with the upper surface electrode 52. In addition, the protective film 251 extends from the edge 231-2 to a position overlapping with the pad 57.

[0049] The protective film 252 is provided so as to extend from the pad 57 to the upper surface electrode 52 when viewed from above. The protective film 252 is connected to the protective film 251. The protective film 251 may be provided between the two pads 57. When viewed from above, a portion of the upper surface 53 of the upper surface electrode 52 is surrounded by the protective film 251 and the protective film 252. In addition, when viewed from above, a portion of the upper surface of each pad is surrounded by the protective film 251 and the protective film 252.

[0050] The protective film 253 is provided so as to extend from the end of the protective film 251 toward the inner side of the active portion 160. The inner side of the active portion 160 refers to a direction toward the center of the active portion 160 when viewed from above. The protective film 253 may overlap with the gate wiring arranged in the active portion 160. The gate wiring is a wiring that transmits the gate voltage. The gate wiring may include metal wiring formed from a metal such as aluminum, semiconductor wiring formed from a semiconductor such as polysilicon doped with impurities, or a stack of metal wiring and semiconductor wiring.

[0051] The gate wiring may include an annular portion disposed outside the upper surface electrode 52 in a plan view, and an inner portion extending from the annular portion toward the inside of the active portion 160. The annular portion of the gate wiring is connected to a gate pad (e.g., pad 57-3). The annular portion of the gate wiring may be disposed below the protective film 251 or the protective film 252. The annular portion and the inner portion of the gate wiring are connected to the gate electrode of the semiconductor element provided in the active portion 160. This structure enables the application of a gate voltage to the gate electrode at various locations on the semiconductor substrate 10.

[0052] Protective film 254 extends from the end of protective film 251 or protective film 252 toward the inside of active portion 160. Protective film 254 may overlap a temperature detection diode disposed above active portion 160 and wiring connected to the diode. The temperature detection diode is, for example, a PN junction diode formed of polycrystalline silicon.

[0053] A well region 11, described later, may be formed in the semiconductor substrate 10 below each protective film. Well region 11 is a P+ type region exposed on the upper surface of semiconductor substrate 10. The doping concentration of well region 11 may be higher than that of base region 14, described later. Well region 11 may be formed deeper than base region 14.

[0054] The semiconductor substrate 10 may include an edge termination structure between the well region 11 and the edge 231. The edge termination structure mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure may include at least one of a guard ring provided in an annular shape to surround the active portion 160, a field plate, and a surface electric field reduction device.

[0055] Figure 2 yes Figure 1 The enlarged view of the region A in FIG. The region A is a region including the upper surface electrode 52, the active portion 160, the well region 11, the protective film 251, and the protective film 252. In this example, the upper surface electrode 52 is provided in a wider range than the active portion 160. An interlayer insulating film is provided between the semiconductor substrate 10 and the upper surface electrode 52, but Figure 2 The interlayer insulating film is provided with a first contact hole 54 for electrically connecting the semiconductor substrate 10 and the upper surface electrode 52 .

[0056] exist Figure 2 , solid lines indicate various regions such as the well region 11 provided within the semiconductor substrate 10 and exposed on the upper surface of the semiconductor substrate 10. Furthermore, solid lines indicate the first contact hole 54. Dashed lines and arrows indicate the region where the reservoir region 16 is provided, which is provided within the semiconductor substrate 10 and not exposed on the upper surface of the semiconductor substrate 10. Furthermore, dashed lines and arrows indicate the region where the upper surface electrode 52, the active portion 160, the protective film 251, and the protective film 252 are provided.

[0057] The well region 11 is provided so as to surround the active portion 160 and the upper surface electrode 52. A portion of the well region 11 may overlap with the upper surface electrode 52. The gate wiring described above is provided above the well region 11, but Figure 2 The gate wiring is arranged at a position further outward than the upper surface electrode 52 when viewed from above. The outer side refers to the side close to the end edge 231 of the semiconductor substrate 10. The gate wiring can be arranged in a range that overlaps with the well region 11 when viewed from above. The well region 11 can be arranged in a range wider than the gate wiring. The N-type drift region 18 can be exposed on the upper surface of the semiconductor substrate 10 outside the well region 11.

[0058] The protective film 251 and the protective film 252 are arranged outside the active portion 160 in a plan view. A portion of the protective film 251 overlaps with the upper surface electrode 52 in a plan view. Figure 2 In the example, the inner end of the protective film 251 in the X-axis direction is arranged above the upper surface electrode 52. The inner side refers to the side away from the edge 231 of the semiconductor substrate 10 (that is, the side close to the center of the active portion 160). A portion of the protective film 252 overlaps with the upper surface electrode 52 when viewed from above. Figure 2 In the example, the inner end portion of the protective film 252 in the Y-axis direction is arranged above the upper surface electrode 52 .

[0059] In this example, an IGBT is formed as a semiconductor element in the active portion 160. Figure 2 The active portion 160 is provided with a gate trench portion 40 , a dummy trench portion 30 , an emitter region 12 , a contact region 15 , and an accumulation region 16 .

[0060] The gate trench 40 and the dummy trench 30 are each an example of a trench. Each trench comprises a groove portion provided on the upper surface of the semiconductor substrate 10, a conductive portion provided within the groove portion, and an insulating film that insulates the semiconductor substrate 10 from the conductive portion. A gate voltage is applied to the conductive portion of the gate trench 40, while a voltage different from the gate voltage is applied to the conductive portion of the dummy trench 30. The conductive portion of the dummy trench 30 in this example is connected to the upper surface electrode 52 via a contact hole provided in the interlayer insulating film.

[0061] Each groove portion is provided from the upper surface of the semiconductor substrate 10 to the inside of the semiconductor substrate 10. Figure 2 As shown, each trench portion extends along the Y-axis direction (first direction) on the upper surface 21 of the semiconductor substrate 10 and has a length. The trench portions are arranged along a second direction (X-axis direction) that is different from the Y-axis direction. In this example, the first and second directions are orthogonal to each other, but the first and second directions do not necessarily need to be orthogonal to each other.

[0062] In the X-axis direction, one or more dummy trenches 30 are provided between two gate trenches 40. Figure 2 In the example shown in FIG, one gate trench 40 and two dummy trenches 30 are repeatedly arranged in the X-axis direction. In another example, more gate trenches 40 may be arranged continuously in the X-axis direction, or more dummy trenches 30 may be arranged continuously in the X-axis direction. Furthermore, the active portion 160 may be provided with only gate trenches 40, without dummy trenches 30.

[0063] like Figure 2As shown, a curved gate trench 40 can be used to connect the ends of two gate trenches 40 in the Y-axis direction. Similarly, a curved dummy trench 30 can be used to connect the ends of two dummy trenches 30 in the Y-axis direction. This shape can alleviate electric field concentration at the Y-axis front ends of the trenches. In this specification, the straight line portion extending in the Y-axis direction in each trench is sometimes referred to as a single trench.

[0064] The gate trench portion 40 is electrically connected to the gate wiring. The gate trench portion 40 extends into the interior of the well region 11 in the Y-axis direction. The dummy trench portion 30 may also extend into the interior of the well region 11. The end of the gate trench portion 40 is electrically connected to the gate wiring provided above the well region 11. The front end of the gate trench portion 40 can be connected to the gate wiring via a contact hole provided in the interlayer insulating film, etc.

[0065] The well region 11 can be formed deeper than each trench. With this structure, the Y-axis tip of each trench is surrounded by the P+ type well region 11. This can alleviate the electric field concentration at the tip of each trench, thereby improving the withstand voltage.

[0066] In the X-axis direction, a mesa portion is provided between each groove portion. The mesa portion refers to an area inside the semiconductor substrate 10 that is sandwiched between two adjacent groove portions in the X-axis direction. A mesa portion is provided between each of the two groove portions. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the groove portion. The mesa portion in this example is provided on the upper surface of the semiconductor substrate 10 and extends along the groove in the Y-axis direction. Each mesa portion can be connected to the upper surface electrode 52 through the first contact hole 54.

[0067] A P-type base region is provided in each mesa portion, but Figure 2 The base region has a portion that is in contact with the gate trench 40. When a predetermined gate voltage is applied to the gate trench 40, a channel is formed in the base region, and the IGBT turns on. The base region can be provided throughout the mesa portion within the semiconductor substrate 10. The base region may or may not be exposed on the upper surface of the mesa portion.

[0068] Each mesa portion has an emitter region 12 that is in contact with (ie, exposed on) the upper surface of the semiconductor substrate 10. The emitter region 12 is provided between the base region and the upper surface of the semiconductor substrate 10. At least a portion of the emitter region 12 is provided in contact with the gate trench portion 40.

[0069] Each mesa portion may include a contact region 15 exposed on the upper surface of semiconductor substrate 10. Contact region 15 is a P+ type region with a higher concentration than that of the base region. Contact region 15 is provided between the base region and the upper surface of semiconductor substrate 10. The provision of contact region 15 reduces the contact resistance with upper surface electrode 52. Emitter region 12 and contact region 15 are connected to upper surface electrode 52 via first contact hole 54.

[0070] The contact regions 15 and emitter regions 12 in the mesa portion of this embodiment are respectively provided from one groove portion to another groove portion adjacent in the X-axis direction. The contact regions 15 and emitter regions 12 are alternately arranged along the Y-axis direction.

[0071] The contact region 15-e is a contact region located at the end of the plurality of contact regions 15 discretely arranged in the Y-axis direction. The contact region 15-e can be connected to the well region 11. The base region can be exposed on the upper surface of the semiconductor substrate 10 instead of the contact region 15-e.

[0072] In another example, the contact regions 15 and emitter regions 12 of the mesa portion can be arranged in stripes along the Y-axis direction. For example, the emitter regions 12 can be arranged in regions adjacent to the grooves, and the contact regions 15 can be arranged in regions sandwiched between the emitter regions 12.

[0073] exist Figure 2 , the structure near one end of the trench portion in the Y-axis direction is shown. The same structure may be provided near the other end of the trench portion. For example, the other end of the gate trench portion 40 in the Y-axis direction may extend into the well region 11 and be connected to the gate wiring.

[0074] Figure 3 It shows Figure 2 FIG2 shows an example of an X1-X1' cross section in FIG2 . The X1-X1' cross section is an XZ plane passing through emitter region 12 and well region 11 near edge 231-1. In this example, edge 231-1 may be the first edge. In another example, edge 231-1 may be an edge 231 other than the first edge. Figure 3 The well region 11 is arranged opposite to the edge 231 - 1 and extends along the Y-axis direction. Figure 3 The X1-X1' cross section includes the outside of the well region 11. An edge terminal structure such as a P-type guard ring can be provided outside the well region 11, but Figure 3 Omitted in.

[0075] In each cross-sectional view of this specification, the direction in which one of the edge sides 231 of the semiconductor substrate 10 is arranged is sometimes indicated by an arrow. Figure 3The semiconductor device 100 of this example includes the semiconductor substrate 10 , the interlayer insulating film 38 , the first gate wiring 50 , the second gate wiring 51 , the upper surface electrode 52 , the plated layer 210 , the protective film 251 , and the collector electrode 24 in this cross section.

[0076] Semiconductor substrate 10 has an upper surface 21 and a lower surface 23. An interlayer insulating film 38 is provided between the upper surface of semiconductor substrate 10 and upper surface electrode 52. Interlayer insulating film 38 is a film comprising at least one of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermally oxidized film, and other insulating films. A first contact hole 54 and a second contact hole 55 are provided in interlayer insulating film 38 at this cross section.

[0077] The upper surface electrode 52 is provided above the interlayer insulating film 38 . The upper surface electrode 52 is connected to the upper surface 21 of the semiconductor substrate 10 through a first contact hole 54 in the interlayer insulating film 38 .

[0078] The first gate wiring 50 is provided above the interlayer insulating film 38, and the second gate wiring 51 is provided between the first gate wiring 50 and the semiconductor substrate 10. The interlayer insulating film 38 or another insulating film is provided between the second gate wiring 51 and the semiconductor substrate 10. The interlayer insulating film 38 is provided between the first gate wiring 50 and the second gate wiring 51. The first gate wiring 50 and the second gate wiring 51 are electrically connected through a second contact hole 55. The first gate wiring 50 is, for example, a metal wiring formed of aluminum or the like. The second gate wiring 51 is, for example, a wiring formed of polysilicon or the like. The first gate wiring 50, the second gate wiring 51, and the second contact hole 55 can be provided so as to surround the active portion 160 when viewed from above. The second gate wiring 51 is connected to the gate conductive portion 44, which will be described later, near the front end of the gate trench portion 40.

[0079] The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The upper surface electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction connecting the upper surface electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0080] Semiconductor substrate 10 includes an N-type drift region 18. Drift region 18 can be provided throughout semiconductor substrate 10 when viewed from above. Well region 11 surrounds upper surface electrode 52 when viewed from above. Well region 11 is a P+ type region exposed on upper surface 21 of semiconductor substrate 10. Well region 11 can be formed deeper than both gate trench 40 and dummy trench 30.

[0081] The end of the upper surface electrode 52 may overlap the well region 11 in a plan view. The first gate wiring 50 and the second gate wiring 51 may overlap the well region 11 in a plan view. The entire first gate wiring 50 and the entire second gate wiring 51 may overlap the well region 11 in a plan view.

[0082] A protective film 251 is provided on the interlayer insulating film 38. At least a portion of the protective film 251 is provided to cover the upper surface 53 of the upper surface electrode 52. In this example, the protective film 251 also covers the entire first gate wiring 50. The protective film 251 can be provided continuously from the upper surface electrode 52 to the edge of the semiconductor substrate 10 (edge 231 - 1 in this example). A portion of the protective film 251 can be in contact with the interlayer insulating film 38.

[0083] The plating layer 210 is provided on the upper surface 53 of the upper surface electrode 52. The plating layer 210 is provided in the area of the upper surface 53 of the upper surface electrode 52 that is not covered by the protective film 251. The plating layer 210 can include at least one of nickel and copper. The plating layer 210 can be nickel-plated or copper-plated. The plating layer 210 can be in contact with the protective film 251 or separated from the protective film 251.

[0084] Wiring such as a linear lead or a plate-shaped lead frame that connects an external circuit to the semiconductor device 100 may be connected to the plating layer 210. The wiring may be soldered to the plating layer 210 or may be crimped to the plating layer 210.

[0085] A plurality of grooves are provided on the upper surface 21 of the semiconductor substrate 10. The details of each groove will be described later. Each groove is formed from the upper surface 21 of the semiconductor substrate 10 to a predetermined depth. Figure 3 In the cross section, the plurality of grooves are arranged at predetermined intervals in the X-axis direction. At least a portion of the grooves is provided below the upper surface electrode 52. A portion of the grooves may be provided outside the upper surface electrode 52. A portion of the grooves may also be provided within the well region 11.

[0086] Each mesa portion sandwiched between two trench portions in the X-axis direction is provided with a P-type base region 14. Base region 14 may be in contact with the trench portions on either side of the mesa portion. In this specification, the region sandwiched between two trench portions not included in well region 11 is referred to as the mesa portion. A drift region 18 is provided below base region 14.

[0087] An N+ type emitter region 12 is provided in at least a portion of the mesa portion. Alternatively, a P+ type contact region 15 may be provided in place of the emitter region 12 in a portion of the mesa portion. Figure 2 and Figure 3In the example, the emitter region 12 is not provided in one or more mesa portions closest to the well region 11, but a contact region 15-e is provided. By arranging the contact region 15-e in the mesa portion, holes are extracted to the upper surface electrode 52 through the mesa portion.

[0088] The emitter region 12 and the contact region 15 are exposed on the upper surface 21 of the semiconductor substrate 10. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. The doping concentration of the contact region 15 is higher than the doping concentration of the base region 14.

[0089] The emitter region 12 and the contact region 15 are disposed between the base region 14 and the upper surface 21 of the semiconductor substrate 10 . At least a portion of the emitter region 12 is disposed in contact with the gate trench portion 40 .

[0090] When a predetermined on-voltage is applied to the gate conductive portion 44 of the gate trench 40, the surface layer of the base region 14 in contact with the gate trench 40 inverts to an N-type to form a channel layer. This connects the emitter region 12 to the drift region 18, turning the transistor on.

[0091] An N-type accumulation region 16 may be provided in at least a portion of the mesa portion. The accumulation region 16 is disposed between the base region 14 and the drift region 18. The accumulation region 16 is an N-type region with a higher doping concentration than the drift region 18. Providing a high-concentration accumulation region 16 between the drift region 18 and the base region 14 enhances the carrier injection enhancement effect (IE effect) and reduces the on-state voltage. The accumulation region 16 may be provided to cover the entire lower surface of the base region 14 in each mesa portion.

[0092] An N+-type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The buffer region 20 may function as a field stop layer to prevent the depletion layer extending from the lower end of the base region 14 from reaching the P+-type collector region 22. If a MOSFET is provided on the semiconductor substrate 10, the buffer region 20 may not be provided.

[0093] In the semiconductor substrate 10, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 is connected to a collector electrode 24. The collector electrode 24 is formed of a metal material such as aluminum. When a MOSFET is provided in the semiconductor substrate 10, an N+ type drain region is provided in place of the collector region 22. When a diode is provided in the semiconductor substrate 10, a P-type anode region is provided in place of the emitter region 12, and an N+ type cathode region is provided in place of the collector region 22.

[0094] One or more gate groove portions 40 and one or more dummy groove portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10. In the respective figures, the gate groove portion 40 is sometimes labeled with the symbol G, and the dummy groove portion 30 is sometimes labeled with the symbol E. Each groove portion extends from the upper surface 21 of the semiconductor substrate 10 through the base region 14 and is provided below the base region 14. In the region where at least any one of the emitter region 12, the contact region 15, and the storage region 16 is provided, each groove portion also extends through these doped regions. The manufacturing order in which the groove portion extends through the doped region is not limited to the order in which the groove portion is formed after the doped region is formed. The order in which the doped region is formed between the groove portions after the groove portion is formed is also included in the manufacturing order in which the groove portion extends through the doped region.

[0095] The gate trench portion 40 includes a gate insulating film 42 and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the trench, which extends from the upper surface 21 of the semiconductor substrate 10 to the interior of the semiconductor substrate 10. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor substrate 10 exposed at the inner wall of the trench. The gate conductive portion 44 is provided within the trench, further inward than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0096] The gate conductive portion 44 can be provided longer in the depth direction than the base region 14. The gate trench portion 40 at this cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the second gate wiring 51. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed in the surface layer of the interface between the base region 14 and the gate trench portion 40.

[0097] The dummy groove portion 30 may have the same structure as the gate groove portion 40 in this cross section. The dummy groove portion 30 includes a dummy insulating film 32 and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the upper surface electrode 52. The dummy insulating film 32 is provided so as to cover the inner wall of the groove. The dummy conductive portion 34 is provided inside the groove and at a position further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0098] In this example, the first contact hole 54 is a contact hole provided in the interlayer insulating film 38, which connects the upper surface electrode 52 to the well region 11 or the active portion 160 of the upper surface electrode 52. Figure 3As shown in FIG. 1 , a plurality of first contact holes 54 may be provided in the interlayer insulating film 38. The first contact hole 54 may also be a contact hole connecting the upper surface electrode 52 to the upper surface 21 of the semiconductor substrate 10 at a position further inside than the first gate wiring 50 or the second gate wiring 51. The first contact hole 54 may also be a contact hole in the direction toward the end side 231 closest to the end portion of the active portion 160 (at Figure 3 The first contact holes 54 are formed by connecting the upper surface electrode 52 at a position further inward than the center 111 of the well region 11 in the X-axis direction. Of the contact holes provided in the interlayer insulating film 38, those that are in contact with the upper surface 21 of the semiconductor substrate 10 at a position further outward than the well region 11 can be excluded from the first contact holes 54.

[0099] Figure 3 The first contact hole 54 of the example has at least one of a well hole end portion 201 and an active hole end portion 211. The well hole end portion 201 electrically connects the upper surface electrode 52 to the well region 11. The well hole end portion 201 is the portion of the first contact hole 54 that is arranged to overlap with the well region 11 and is closest to the end side 231-1 in the X-axis direction.

[0100] The active hole end portion 211 electrically connects the upper surface electrode 52 and the active portion 160. The active hole end portion 211 is a portion of the first contact hole 54 arranged to overlap with the active portion 160 and closest to the end side 231-1 in the X-axis direction.

[0101] The well hole end portion 201 and the active hole end portion 211 may be portions of the first contact hole 54 that are in contact with the upper surface 21 of the semiconductor substrate 10. Figure 3 In the example of FIG. 1 , the well hole end portion 201 is the portion where the side surface of the interlayer insulating film 38 contacts the well region 11. Figure 3 In the example, the active hole end portion 211 is a boundary portion between the well region 11 and the active portion 160 that is exposed through the first contact hole 54 .

[0102] The first contact hole 54 has a first outer hole end portion closest to the first end side of the semiconductor substrate 10. When the end side 231-1 is the first end side, the portion of the first contact hole 54 closest to the end side 231-1 in the X-axis direction is defined as the first outer hole end portion. When the end side 231-1 is the first end side, Figure 3The well hole end 201 shown is an example of a first outer hole end. If well hole end 201 is not provided, active hole end 211 functions as the first outer hole end. The first outer hole end is provided relative to the two end edges 231-1 and 231-3 of semiconductor substrate 10, respectively. Furthermore, if end edge 231-1 is the second end edge, the portion of first contact hole 54 closest to end edge 231-1 in the X-axis direction is defined as the second outer hole end. Similarly, if end edge 231-1 is the third end edge, the portion of first contact hole 54 closest to end edge 231-1 in the X-axis direction is defined as the third outer hole end.

[0103] A plating layer 210 is formed on the upper surface 53 of the upper surface electrode 52 that overlaps with the first outer hole end in a plan view. A plating layer 210 may also be formed on the upper surface 53 of the upper surface electrode 52 that overlaps with the second outer hole end, and on the upper surface 53 of the upper surface electrode 52 that overlaps with the third outer hole end. Furthermore, at each end side 231 of the semiconductor substrate 10, the portion of the first contact hole 54 closest to the end side 231 is defined as the outer hole end. At all outer hole end portions, a plating layer 210 may be formed on the upper surface 53 of the upper surface electrode 52 that overlaps with the outer hole end. In this example, a plating layer 210 is formed on the upper surface 53 of the upper surface electrode 52 that overlaps with the outer hole end for each of the end sides 231-1, 231-2, 231-3, and 231-4.

[0104] In this example, a plating layer 210 is formed on the upper surface 53 of the upper surface electrode 52 that overlaps with the well hole end 201. Alternatively, a plating layer 210 may be formed on the upper surface 53 of the upper surface electrode 52 that overlaps with the active hole end 211. The plating layer 210 may be formed continuously from above the well hole end 201 to above the active hole end 211.

[0105] By forming a plating layer 210 on the upper surface electrode 52 that overlaps with the end of the first outer hole, the generation of stress on the upper surface electrode 52 can be suppressed. During actual use, there are cases where the temperature of the upper surface electrode 52 changes repeatedly and stress is generated. In this case, stress migration sometimes occurs in the upper surface electrode 52. In particular, when the upper surface electrode 52 contains aluminum, stress migration is likely to occur. If stress migration occurs, the movement of holes in the XY plane of the upper surface electrode 52 is suppressed. It should be noted that when the semiconductor substrate 10 is a silicon carbide substrate, it is often used in an environment with large temperature fluctuations, and the stress generated in the upper surface electrode 52 becomes larger. In addition, when the semiconductor device 100 is installed in a semiconductor module equipped with a water cooling device, it is also often used in an environment with large temperature fluctuations.

[0106] In contrast, by providing the plating layer 210 above the first outer hole end, deformation of the upper surface electrode 52 near the first outer hole end can be suppressed, thereby suppressing the generation of stress, compared to the case where the protective film 251 is provided to overlap the first outer hole end. The plating layer 210 can be provided continuously from the first outer hole end to the center of the semiconductor substrate 10 when viewed from above. The protective film may not be provided on the upper surface 53 of the upper surface electrode 52 at a position further inward than the first outer hole end. In another example, a protective film may be provided on the upper surface 53 of the upper surface electrode 52 at a position further inward than the first outer hole end.

[0107] In this example, holes that reach the first outer hole end from the semiconductor substrate 10 can move from the upper surface electrode 52 along the Z-axis direction toward the plated layer 210. Holes that reach the upper surface electrode 52 from the first outer hole end hardly move along the X-axis direction within the upper surface electrode 52. Therefore, even if stress migration or the like occurs in the upper surface electrode 52, the movement of holes from the upper surface electrode 52 to the plated layer 210 is hardly suppressed.

[0108] The protective film 251 of this embodiment is disposed between the first outer hole end and the first end edge (at Figure 3 In the example, it is between the end side 231-1). Protective film 251 is an example of an outer protective portion. Protective film 251 has an inner protective end portion 261. Inner protective end portion 261 is the portion of protective film 251 closest to first contact hole 54. Inner protective end portion 261 may be the portion of the side surface of protective film 251 that contacts upper surface 53 of upper surface electrode 52. Inner protective end portion 261 is provided between well hole end portion 201 and end side 231-1 when viewed from above.

[0109] The X-axis position of the well hole end 201 is denoted as Px1, and the X-axis position of the inner protection end 261 is denoted as Px2. If the well hole end 201 is not provided, the X-axis position of the active hole end 211 is denoted as Px1. The X-axis position of the portion of the reservoir region 16 closest to the edge 231-1 is denoted as Px3. The X-axis position of the portion of the well region 11 closest to the innermost portion in the X-axis direction is denoted as Px4. The X-axis position of the portion of the emitter region 12 closest to the edge 231-1 is denoted as Px5.

[0110] Position Px1 is located further inboard (i.e., closer to the center of active portion 160) than position Px2. Both position Px1 and position Px2 can be located further inboard than center 111 of well region 11. Both position Px1 and position Px2 can be located so as to overlap well region 11. That is, position Px1 and position Px2 can be located between center 111 and position Px4. In another example, position Px2 can overlap well region 11, and position Px1 can be located further inboard than position Px4. Alternatively, both position Px1 and position Px2 can be located further inboard than position Px4.

[0111] In another example, position Px2 may be located outside the center 111 of the well region 11, and position Px1 may be located inside the center 111. In this case, position Px2 may overlap with the well region 11. Position Px1 may be located outside or inside the position Px4.

[0112] Positions Px1 and Px2 can both be positioned outward from position Px3. That is, in the X-axis direction, the outer hole end and inner protective end 261 can be positioned between the reservoir 16 and the edge 231-1. Furthermore, positions Px1 and Px2 can both be positioned outward from position Px5.

[0113] The distance between positions Px1 and Px2 in the X-axis direction can be smaller than the width of well region 11 in the X-axis direction. By reducing the distance between positions Px1 and Px2, a larger area can be protected by protective film 251. The distance between positions Px1 and Px2 can be less than half the width of well region 11, and can be less than 10 μm or less than 5 μm. This distance can be 0 μm or greater than 0 μm.

[0114] The position Px2 may be arranged at a position further outward than the groove portion closest to the edge 231-1 among the plurality of groove portions. Figure 3 As shown, the position Px2 may overlap with the groove portion closest to the edge 231 - 1 . The position Px2 may be arranged further inside the groove portion closest to the edge 231 - 1 .

[0115] The first contact hole 54 has an active hole end portion 211 that is closest to the first end side (end side 231-1 in this example) in the portion connecting the active portion 160 to the upper surface electrode 52. In this example, the position of the active hole end portion 211 in the X-axis direction coincides with position Px4 of the end of the well region 11. In another example, the active hole end portion 211 may be located further inward than position Px4.

[0116] In the X-axis direction, the inner protection end portion 261 may be disposed between the contact area 15 and the end edge 231 - 1 . Figure 3 In the example of FIG, the position Px4 is the outer end of the contact area 15. The inner protection end portion 261 may be disposed between the position Px4 and the end side 231-1.

[0117] In a plan view, a plating layer 210 is provided on the upper surface 53 of the upper surface electrode 52 that overlaps with the active hole end portion 211. Since a relatively large number of holes exist in the active portion 160, a relatively large number of holes reach the active hole end portion 211. Providing the plating layer 210 above the active hole end portion 211 can suppress stress in the portion of the upper surface electrode 52 where a relatively large number of holes flow.

[0118] like Figure 3 As shown, the active hole end portion 211 may be disposed further inward than the well hole end portion 201. In another example, the first contact hole 54 and the well hole end portion 201 may not be disposed at a position overlapping the well region 11.

[0119] The plating layer 210 may be continuously provided in the X-axis direction from the active hole end 211 to a position further inward than the position Px3. The plating layer 210 may be continuously provided in the X-axis direction from the active hole end 211 to a position further inward than the position Px5. The plating layer 210 may be continuously provided in the X-axis direction from the active hole end 211 to the center of the active portion 160.

[0120] Figure 4 It shows Figure 2 The Y1-Y1' cross section is a YZ plane passing through the first contact hole 54 and the well region 11 near the end 231-2. In this example, the end 231-2 can be the first end. In this case, the end 231-1 is the second end or the third end. In the case where the end 231-1 is the second end or the third end, Figure 3 As shown, a plating layer 210 is provided above the well hole end 201, and a protective film 251 may also be provided. In addition, a plating layer 210 or a protective film 251 may also be provided above the active hole end 211.

[0121] Figure 4 The well region 11 is arranged opposite to the edge 231 - 2 and extends along the X-axis direction. Figure 4 The Y1-Y1' cross section includes the outside of the well region 11. An edge terminal structure such as a guard ring can be provided outside the well region 11, but Figure 4 Omitted in.

[0122] exist Figure 4The direction of the edge 231-2 is indicated by an arrow in FIG. The semiconductor device 100 of this example includes the semiconductor substrate 10, the interlayer insulating film 38, the first gate wiring 50, the second gate wiring 51, the upper surface electrode 52, the pad electrode 280, the pad 57-5, the plating layer 210, the protective film 251, the protective film 252, and the collector electrode 24 in this cross section. Figure 4 The structure shown is marked with Figure 3 The same symbol structure has Figure 3 The structure and function described in.

[0123] The end of the upper surface electrode 52 in the Y-axis direction in this example can overlap with the well region 11 when viewed from above. In this example, a pad 57-5 is provided at a position further outward than the first gate wiring 50 and the second gate wiring 51. The pad 57-5 can be connected to a diode for temperature detection, etc. The pad 57-5 is provided above the interlayer insulating film 38. The pad 57-5 in this example has a pad electrode 280 and a plating layer 210. The pad electrode 280 can be formed of the same material as the upper surface electrode 52. The pad electrode 280 is provided separately from the upper surface electrode 52. The plating layer 210 is formed on the upper surface of the pad electrode 280. Wiring such as a wire can be connected to the upper surface of the plating layer 210.

[0124] Protective film 251 and protective film 252 are provided on interlayer insulating film 38. Protective film 251 is provided to cover a portion of the upper surface of pad electrode 280. Protective film 251 may be provided continuously from pad electrode 280 to an edge of semiconductor substrate 10 (edge 231 - 2 in this example). A portion of protective film 251 may be in contact with interlayer insulating film 38.

[0125] The protective film 252 is provided so as to cover a portion of the upper surface of the pad electrode 280. The plating layer 210 is provided in the area of the upper surface of the pad electrode 280 that is not covered by the protective film 251 and the protective film 252. In another example, the plating layer 210 may not be provided on the pad 57-5. The protective film 252 is provided so as to cover a portion of the upper surface of the upper surface electrode 52. In addition, the protective film 252 also covers the entire first gate wiring 50. The protective film 252 may be in contact with the interlayer insulating film 38 between the pad electrode 280 and the first gate wiring 50, and between the first gate wiring 50 and the upper surface electrode 52.

[0126] The first contact hole 54 provided in the active portion 160 extends in the Y-axis direction. The emitter regions 12 and the contact regions 15 are alternately arranged in the Y-axis direction. In this example, the first contact hole 54 exposes the emitter regions 12 and the contact regions 15.

[0127] The first contact hole 54 may be provided at a position overlapping with the well region 11. An interlayer insulating film 38 may be provided between the first contact hole 54 of the active portion 160 and the first contact hole 54 of the well region 11.

[0128] Figure 4 In the example shown, the first contact hole 54 has at least one of a well hole end portion 202 and an active hole end portion 222. The well hole end portion 202 electrically connects the upper surface electrode 52 to the well region 11. The well hole end portion 202 is the portion of the first contact hole 54 that is arranged to overlap with the well region 11 and is closest to the end side 231-2 in the Y-axis direction.

[0129] The active hole end portion 222 electrically connects the upper surface electrode 52 and the active portion 160. The active hole end portion 222 is a portion of the first contact hole 54 arranged to overlap with the active portion 160 and closest to the end side 231-2 in the Y-axis direction.

[0130] The well hole end portion 202 and the active hole end portion 222 may be portions of the first contact hole 54 that are in contact with the upper surface 21 of the semiconductor substrate 10. Figure 4 In the example of FIG. 1 , the well hole end portion 202 is the portion where the side surface of the interlayer insulating film 38 contacts the well region 11. Figure 4 In the example shown in FIG. 2 , the active hole end portion 222 is a portion where the side surface of the interlayer insulating film 38 contacts the contact region 15 or the emitter region 12 .

[0131] The first contact hole 54 has a first outer hole end portion closest to the first end side of the semiconductor substrate 10. When the end side 231-2 is the first end side, the portion of the first contact hole 54 closest to the end side 231-2 in the Y-axis direction is defined as the first outer hole end portion. When the end side 231-2 is the first end side, Figure 4 The well hole end 202 shown is an example of a first outer hole end. If well hole end 202 is not provided, active hole end 222 functions as the first outer hole end. If edge 231-2 is the second edge, the portion of first contact hole 54 closest to edge 231-2 in the Y-axis direction is the second outer hole end. Similarly, if edge 231-2 is the third edge, the portion of first contact hole 54 closest to edge 231-2 in the Y-axis direction is the third outer hole end.

[0132] In this example, a plating layer 210 is formed on the upper surface 53 of the upper surface electrode 52 that overlaps with the well hole end 202. A plating layer 210 may also be formed on the upper surface 53 of the upper surface electrode 52 that overlaps with the active hole end 222. The plating layer 210 may be formed continuously from above the well hole end 202 to above the active hole end 222.

[0133] In this example, deformation of the upper surface electrode 52 near the first outer hole end can be suppressed, thereby suppressing stress generation. In addition, even if stress migration occurs in the upper surface electrode 52, the movement of holes in the upper surface electrode 52 is hardly suppressed.

[0134] The protective film 251 and the protective film 252 of this embodiment are arranged as a whole between the end of the first outer hole and the first end edge (at Figure 4 In the example, it is between the end edge 231-2). Protective film 251 and protective film 252 are examples of outer protective portions. Protective film 252 has an inner protective end portion 262. Inner protective end portion 262 is the portion of protective film 252 closest to first contact hole 54. Inner protective end portion 262 may be the portion where the side surface of protective film 252 contacts the upper surface 53 of the upper surface electrode 52. Inner protective end portion 262 is provided between well end portion 202 and end edge 231-2 when viewed from above.

[0135] The Y-axis position of the well hole end 202 is denoted as Py1, and the Y-axis position of the inner protection end 262 is denoted as Py2. If the well hole end 202 is not provided, the Y-axis position of the active hole end 222 is denoted as Py1. The Y-axis position of the portion of the reservoir region 16 closest to the edge 231-2 is denoted as Py3. The Y-axis position of the innermost portion of the well region 11 is denoted as Py4. The Y-axis position of the portion of the emitter region 12 closest to the edge 231-2 is denoted as Py5.

[0136] Position Py1 is located further inboard (i.e., closer to the center of active portion 160) than position Py2. Both position Py1 and position Py2 can be located further inboard than center 111 of well region 11. Both position Py1 and position Py2 can be located so as to overlap well region 11. That is, both position Py1 and position Py2 can be located between center 111 and position Py4. In another example, position Py2 can overlap well region 11, and position Py1 can be located further inboard than position Py4. Alternatively, both position Py1 and position Py2 can be located further inboard than position Py4.

[0137] In another example, position Py2 may be located outside center 111 of well region 11, and position Py1 may be located inside center 111. In this case, position Py2 may overlap well region 11. Position Py1 may be located outside or inside position Py4.

[0138] Positions Py1 and Py2 can both be positioned outside of position Py3. That is, in the Y-axis direction, inner protective end portion 262 can be positioned between reservoir 16 and edge 231-2. Furthermore, positions Py1 and Py2 can both be positioned outside of position Py5.

[0139] The distance between positions Py1 and Py2 in the X-axis direction can be smaller than the width of well region 11 in the X-axis direction. By shortening the distance between positions Py1 and Py2, a wider area can be protected by protective film 252. The distance between positions Py1 and Py2 can be less than half the width of well region 11, and can be less than 10 μm or less than 5 μm. This distance can be 0 μm or greater than 0 μm.

[0140] The position of the active hole end portion 222 in the Y-axis direction in this example is arranged inside the position Py4 of the end portion of the well region 11. In another example, the active hole end portion 222 may coincide with the position Py4.

[0141] In a plan view, a plating layer 210 is provided on the upper surface 53 of the upper surface electrode 52 that overlaps with the active hole end portion 222. Since a relatively large number of holes exist in the active portion 160, a relatively large number of holes reach the active hole end portion 222. By providing the plating layer 210 above the active hole end portion 222, stress in the portion of the upper surface electrode 52 where a relatively large number of holes flow can be suppressed.

[0142] The plating layer 210 may be continuously provided from the active hole end 222 to a position further inward than the position Py3 in the Y-axis direction. The plating layer 210 may be continuously provided from the active hole end 222 to a position further inward than the position Py5 in the Y-axis direction. The plating layer 210 may be continuously provided from the active hole end 222 to the center of the active portion 160 along the Y-axis direction.

[0143] Figure 5 : is a diagram showing an example of a Y2-Y2' cross section. Figure 1 As shown, the Y2-Y2' cross section is the YZ plane passing through the pad 57-1 near the edge 231-2. Unless otherwise specified, the structure of the Y2-Y2' cross section can be the same as that of the Y1-Y1' cross section. In this example, the Y2-Y2' cross section does not include the first gate wiring 50 and the second gate wiring 51. The first gate wiring 50 and the second gate wiring 51 can be located closer to the edge 231-2 than the pad 57-1.

[0144] The pad 57-1 has the same potential as the upper surface electrode 52. The pad 57-1 is also called a Kelvin emitter pad. By detecting the potential at the pad 57-1, the potential of the upper surface electrode 52 can be detected. A wiring such as a wire can be connected to the pad 57-1.

[0145] Under the pad 57-1, a well region 11 is provided. The width of the well region 11 in the Y-axis direction as shown in the Y2-Y2' cross section may be larger than or equal to the width of the well region 11 in the Y-axis direction as shown in the Y1-Y1' cross section.

[0146] In this example, the upper surface electrode 52 is provided to extend to the region of the pad 57-1. The pad 57-1 of this example includes the upper surface electrode 52 and the plating layer 210. The plating layer 210 in the active portion 160 and the plating layer 210 of the pad 57-1 may be separated by a protective film 252. In another example, the protective film 252 may not be provided, and the plating layer 210 of the active portion 160 and the plating layer 210 of the pad 57-1 may be provided continuously.

[0147] The upper surface electrode 52 of this example extends to a position further outside the well region 11 along the Y-axis direction when viewed from above. In another example, the upper surface electrode 52 may also end above the well region 11 in the Y-axis direction. Figure 3 As shown, the upper surface electrode 52 may include an outer connection portion 204 that contacts the semiconductor substrate 10 outside the well region 11. As described above, the portion contacting the semiconductor substrate 10 outside the well region 11 is excluded from the first contact hole 54.

[0148] The protective film 251 is provided to cover a portion of the upper surface 53 of the upper surface electrode 52. The protective film 251 may be provided continuously from the upper surface electrode 52 to the edge of the semiconductor substrate 10 (edge 231-2 in this example). An insulating film 270 such as an oxide film may be provided between the protective film 251 and the semiconductor substrate 10, further outward from the upper surface electrode 52, or an interlayer insulating film 38 may be provided.

[0149] The protective film 252 is provided on the upper surface 53 of the upper surface electrode 52. The protective film 252 may be in contact with the upper surface 53 of the upper surface electrode 52 over its entire length in the Y-axis direction. The provision of the protective film 252 allows the plated layer 210 of the active portion 160 to be separated from the plated layer 210 in the pad 57-1. Using the protective film 252 as a reference position facilitates control of the connection position of wiring such as a wire relative to the pad 57-1. At least a portion of the protective film 252 may be disposed above the well region 11. At least a portion of the protective film 252 may be provided on the active portion 160.

[0150] The first contact hole 54 of this example is not provided at a position overlapping the well region 11. The first contact hole 54 of this example has an active hole end portion 222 and does not have a well hole end portion 202. However, in this example, the first contact hole 54 may also have a well hole end portion 202.

[0151] In this example, the active hole end portion 222 functions as a first outer hole end portion. In this example, a plating layer 210 is also formed on the upper surface 53 of the upper surface electrode 52 that overlaps with the active hole end portion 222. The plating layer 210 can be continuously provided from the active hole end portion 222 to a position further inward from position Py5 in the Y-axis direction. The plating layer 210 can be continuously provided from the active hole end portion 222 to the center of the active portion 160 along the Y-axis direction.

[0152] The position Py1 of the active hole end 222 is arranged inwardly of the position Py2 of the inner protection end 262. The position Py1 can be arranged inwardly of the position Py3 of the outer end of the storage area 16 or inwardly of the position Py3 of the outer end of the storage area 16. Figure 5 In the example of , position Py1 is arranged between position Py3 and position Py5. In another example, position Py1 may be arranged at a position further inside than position Py5.

[0153] Position Py2 is located outside of position Py1. Position Py2 may be located inside of position Py4. Position Py2 may be located between position Py3 and position Py4. In another example, position Py2 may be located outside of position Py4. Position Py2 may be located inside of center 111 of well region 11.

[0154] In this example, deformation of the upper surface electrode 52 near the first outer hole end can be suppressed, thereby suppressing stress generation. In addition, even if stress migration occurs in the upper surface electrode 52, the movement of the holes at the upper surface electrode 52 is hardly suppressed.

[0155] Figure 6 This figure shows another example of a cross section taken along line Y2-Y2'. Semiconductor device 100 in this example further includes a protective film 255, as compared to the various embodiments described in this specification. Protective film 255 is positioned farther from edge 231-2 than the outer protective portion (protective films 251 and 252 in this example) when viewed from above, and is arranged to overlap first contact hole 54. Protective film 255 is an example of an inner protective portion.

[0156] A plating layer 210 is provided between the protective film 255 and the protective film 252. The protective film 255 may be provided on Figure 1The protective film 253 is shown between the protective film 251 and the protective film 255. The protective film 255 can extend in the X-axis direction and be connected to the protective film 251, or it can be separated from the protective film 251 in the X-axis direction. The width of the protective film 255 in the Y-axis direction can be smaller than the width of the protective film 252 in the Y-axis direction, or it can be smaller than the width of the protective film 251 in the Y-axis direction.

[0157] For the plated layer 210 of the active portion 160, a wire or other wiring can be soldered at a position further inside than the protective film 255. By providing the protective film 255, it is possible to prevent the solder from flowing to the outside of the protective film 255. This can prevent the solder of the active portion 160 from scattering to other pads 57. The protective film 255 can also be provided at Figure 4 The protective film 255 can be Figure 1 The protective film 252 and the protective film 253 are shown extending in the X-axis direction so as to connect the protective film 251 and the protective film 254 .

[0158] Figure 7 This figure illustrates the path of hole current from the outer hole end 281 in a comparative example. The outer hole end 281 is either the well hole end 202 or the active hole end 222 described above. In the comparative example, a protective film 251 is provided on the upper surface 53 of the upper surface electrode 52 at position Py1 of the outer hole end 281. The protective film 251 extends inwardly of the outer hole end 281 along the Y-axis direction.

[0159] In this example, the hole current from the outer hole end 281 flows in the Y-axis direction inside the upper surface electrode 52 and reaches the plated layer 210. If cracks or the like occur in the upper surface electrode 52, the resistance value with respect to the hole current flowing in the Y-axis direction increases, making it difficult for the hole current from the outer hole end 281 to flow.

[0160] Figure 8 2 is a diagram illustrating the path of the hole current from the outer hole end 281 of the embodiment. Figures 1 to 6 As described in , the plated layer 210 is provided on the upper surface 53 of the upper surface electrode 52 at the position Py1 of the outer hole end 281 . The protective film 251 is provided at a position further outward than the outer hole end 281 .

[0161] In this example, a plating layer 210 is also provided above the outer hole end 281. Figure 7Compared to the example shown in FIG. , the area covered by the plating layer 210 is increased. Therefore, the generation of stress in the upper surface electrode 52 can be suppressed, and the generation of cracks in the upper surface electrode 52 can be suppressed. In addition, in this example, the hole current from the outer hole end 281 flows to the plating layer 210 directly above. Therefore, even if cracks or the like occur in the upper surface electrode 52, the hole current from the outer hole end 281 will not be hindered from flowing to the plating layer 210.

[0162] While the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various modifications or improvements can be made to the above embodiments. As can be seen from the claims, embodiments incorporating such modifications or improvements are also encompassed within the technical scope of the present invention.

[0163] It should be noted that the order of execution of actions, sequences, steps, and stages, etc., in the apparatus, system, program, and method described in the claims, specifications, and drawings may be implemented in any order unless otherwise expressly stated, such as "before," "prior to," or "before," and unless the results of a previous process are used in a subsequent process. Even if, for convenience, the process flow in the claims, specifications, and drawings is described using the phrases "first," "next," etc., this does not necessarily mean that the process must be performed in that order.

Claims

1. A semiconductor device, characterized in that: have: a semiconductor substrate having an upper surface and a lower surface; a top surface electrode comprising aluminum; an interlayer insulating film provided between the upper surface of the semiconductor substrate and the upper surface electrode, and having a first contact hole connecting the semiconductor substrate and the upper surface electrode; a protective film disposed on the upper surface of the upper surface electrode; as well as a plating layer provided on a region of the upper surface of the upper surface electrode that is not covered by the protective film, When viewed from above, the semiconductor substrate has a first end edge. The first contact hole has a first outer hole end portion closest to the first end edge, The plating layer is formed on a portion of the upper surface electrode overlapping with the first outer hole end portion.

2. The semiconductor device according to claim 1, wherein The protection film has an outer protection portion provided between the first outer hole end and the first end side in a plan view.

3. The semiconductor device according to claim 2, wherein An inner protection end portion of the outer protection portion, which is closest to the first contact hole, is disposed between the first outer hole end portion and the first end side.

4. The semiconductor device according to claim 3, wherein The protective film further includes an inner protective portion. The inner protective portion is disposed at a position farther from the first end side than the outer protective portion in a plan view and is disposed so as to overlap with the first contact hole.

5. The semiconductor device according to claim 1, wherein The semiconductor substrate has an active portion on which a semiconductor element is formed. The first contact hole has an active hole end portion closest to the first end side in a portion connecting the active portion and the upper surface electrode. The plating layer is formed on a portion of the upper surface electrode overlapping with an end portion of the active hole.

6. The semiconductor device according to claim 5, wherein The semiconductor substrate has: a drift region of a first conductivity type, disposed in the active portion; and a well region of the second conductivity type, which is provided to surround the active portion in a plan view, The first contact hole has a well hole end portion closest to the first end side in a portion connecting the well region and the upper surface electrode. The plating layer is formed on a portion of the upper surface electrode that overlaps with an end portion of the well hole.

7. The semiconductor device according to any one of claims 1 to 5, wherein: The semiconductor substrate has a groove portion, the groove portion is provided from the upper surface to the inside of the semiconductor substrate and has a length along a first direction on the upper surface, The first outer hole end portion is an end portion of the first contact hole in the first direction.

8. The semiconductor device according to claim 2, wherein The semiconductor substrate has a groove portion, the groove portion is provided from the upper surface to the inside of the semiconductor substrate and has a length along a first direction on the upper surface, The outer protection portion is provided between the first outer hole end and the first end edge in the first direction.

9. The semiconductor device according to claim 3, wherein The semiconductor substrate has: an active portion having a semiconductor element formed therein; a groove portion provided from the upper surface to the inside of the semiconductor substrate and having a length along a first direction on the upper surface; a drift region of a first conductivity type, disposed in the active portion; a base region of a second conductivity type, disposed between the drift region and the upper surface and in contact with the trench portion; and an accumulation region of the first conductivity type, which is provided between the drift region and the base region and has a concentration higher than that of the drift region; In the first direction, the inner protection end portion is disposed between the storage area and the first end edge.

10. The semiconductor device according to any one of claims 1 to 5, wherein: The semiconductor substrate has a plurality of grooves arranged in a second direction on the upper surface. The plurality of grooves are respectively provided from the upper surface to the interior of the semiconductor substrate and have a length along a first direction on the upper surface. The first outer hole end portion is an end portion of the first contact hole in the second direction.

11. The semiconductor device according to claim 3, wherein The semiconductor substrate has: an active portion having a semiconductor element formed therein; a plurality of groove portions arranged along a second direction on the upper surface; a drift region of a first conductivity type, disposed in the active portion; a base region of a second conductivity type, disposed between the drift region and the upper surface; as well as an accumulation region of the first conductivity type, which is provided between the drift region and the base region and has a concentration higher than that of the drift region; The plurality of grooves are respectively provided from the upper surface to the interior of the semiconductor substrate and have a length along a first direction on the upper surface. In the second direction, the inner protection end portion is disposed between the storage area and the first end edge.

12. The semiconductor device according to claim 3, wherein The semiconductor substrate has: an active portion having a semiconductor element formed therein; a plurality of groove portions arranged along a second direction on the upper surface; a drift region of a first conductivity type, disposed in the active portion; a base region of a second conductivity type, disposed between the drift region and the upper surface and in contact with the trench portion; as well as a contact region of the second conductive type, which is provided between the upper surface and the base region, connected to the upper surface electrode, and has a concentration higher than that of the base region; The plurality of grooves are respectively provided from the upper surface to the interior of the semiconductor substrate and have a length along a first direction on the upper surface. In the second direction, the inner protection end portion is disposed between the contact area and the first end edge.

13. The semiconductor device according to any one of claims 1 to 5, wherein: The semiconductor substrate further has a second end side and a third end side when viewed from above. The first contact hole has a second outer hole end closest to the second end side, and a third outer hole end closest to the third end side, The plating layer is formed on a portion of the upper surface electrode overlapping with the second outer hole end portion and a portion of the upper surface electrode overlapping with the third outer hole end portion.

14. The semiconductor device according to any one of claims 1 to 5, wherein: The plating layer includes at least one of nickel and copper.

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