Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package capable of maximizing heat dissipation characteristics and achieving a small form factor and a method of manufacturing the semiconductor package are provided. The semiconductor package includes: a first redistribution substrate; a first semiconductor chip disposed on the first redistribution substrate at a right side in the first direction, and including a through electrode; a first through pillar disposed on the first redistribution substrate on a left side in the first direction on one side of the first semiconductor chip; a second redistribution substrate disposed on the first semiconductor chip and the first through pillar; a semiconductor device disposed on the second redistribution substrate at a left side in the first direction; and a second semiconductor chip disposed on the second redistribution substrate on a right side in the first direction on one side of the semiconductor device.

Description

[0001] This application is based upon and claims the benefit of priority from Korean Patent Application No. 10-2024-0019178 filed on February 7, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including a redistribution substrate on and under a semiconductor chip and a manufacturing method of the semiconductor package. Background Art

[0003] With the rapid development of the electronics industry and user demands, electronic devices are becoming smaller and lighter. As electronic devices become smaller and lighter, the semiconductor packages used in them are also becoming smaller and lighter, and semiconductor packages are required to have high reliability, high performance, and high capacity. As the performance and capacity of semiconductor packages improve, their power consumption is increasing. Consequently, reducing the size of semiconductor packages while improving their performance and heat dissipation characteristics is becoming increasingly important. Summary of the Invention

[0004] The inventive concept relates to a semiconductor package capable of maximizing heat dissipation characteristics and achieving a small form factor and a method of manufacturing the semiconductor package.

[0005] In addition, problems to be solved by the technical idea of the inventive concept are not limited to the above-mentioned problems, and other problems not mentioned may be clearly understood by those skilled in the art from the following description.

[0006] According to one aspect of the inventive concept, a semiconductor package is provided, comprising: a first redistribution substrate; a first semiconductor chip, arranged on the first redistribution substrate on the right side in a first direction, and comprising a through-electrode; a first through-pillar, arranged on the first redistribution substrate on the left side in the first direction on one side of the first semiconductor chip; a second redistribution substrate, arranged on the first semiconductor chip and the first through-pillar; a semiconductor device, arranged on the second redistribution substrate on the left side in the first direction; and a second semiconductor chip, arranged on the second redistribution substrate on the right side in the first direction on one side of the semiconductor device.

[0007] According to another aspect of the inventive concept, a semiconductor package is provided, comprising: a first redistribution substrate; a first semiconductor chip, arranged on the first redistribution substrate on the right side in a first direction and comprising a through-electrode; a first sealant, arranged on the first redistribution substrate and sealing the first semiconductor chip; a first through-pillar, arranged on the first redistribution substrate on the left side in the first direction to be side by side with the first semiconductor chip, and extending through the first sealant; a second redistribution substrate, arranged on the first semiconductor chip and the first through-pillar; a semiconductor device, arranged on the second redistribution substrate on the left side in the first direction; a second semiconductor chip, arranged on the second redistribution substrate on the right side in the first direction to be side by side with the semiconductor device; and a second sealant, arranged on the second redistribution substrate and sealing the semiconductor device and the second semiconductor chip, and the top surfaces of the semiconductor device and the second semiconductor chip are exposed from the second sealant.

[0008] According to another aspect of the inventive concept, a semiconductor package is provided, comprising: a first redistribution substrate; a first semiconductor chip arranged on the first redistribution substrate and comprising a through electrode; a second redistribution substrate arranged on the first semiconductor chip; a semiconductor device arranged on the second redistribution substrate on the left side in a first direction; and a second semiconductor chip arranged on the second redistribution substrate on the right side in the first direction to be side by side with the semiconductor device.

[0009] According to another aspect of the inventive concept, a method for manufacturing a semiconductor package is provided, comprising: forming an upper redistribution substrate on a first carrier substrate; attaching a semiconductor device and a top semiconductor chip to a first surface of the upper redistribution substrate; attaching a bottom semiconductor chip to a second surface of the upper redistribution substrate opposite to the first surface; forming a lower redistribution substrate on the bottom semiconductor chip; and attaching passive elements and external connection terminals to the lower redistribution substrate, wherein the bottom semiconductor chip includes through-electrodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1A and Figure 1B 1 and 2 are respectively a plan view and a cross-sectional view of a semiconductor package according to an embodiment.

[0012] Figures 2A to 2C is shown in more detail Figure 1B A cross-sectional view of the structure of a memory device in a semiconductor package.

[0013] Figure 3A and Figure 3B is a plan view of a semiconductor package according to some embodiments.

[0014] Figure 4 is a cross-sectional view of a semiconductor package according to an embodiment.

[0015] Figures 5A to 5J are cross-sectional views schematically illustrating processes of a method of manufacturing a semiconductor package according to an embodiment.

[0016] Figures 6A to 6F is shown in more detail Figure 5E Cross-sectional view of the process.

[0017] 7A to 7C are cross-sectional views schematically illustrating processes of a method of manufacturing a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0018] Throughout the specification, when a component is described as "comprising" a particular element or group of elements, it will be understood that, unless the context clearly and / or explicitly states otherwise, the component is formed solely of that element or group of elements, or that the element or group of elements may be combined with additional elements to form the component. On the other hand, the term "consisting of" indicates that the component is formed solely of the listed elements.

[0019] It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or directly on the other element or intervening elements may be present.

[0020] It will be understood that when an element is referred to as being “connected” or “coupled” to another element or being “on” another element, the element can be directly connected or coupled to or directly on the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as being “contacting” or “in contact with” another element (or any form of the word “contacting” is used), there are no intervening elements at the point of contact.

[0021] As used herein, terms such as "same," "equal," "planar," "coplanar," "parallel," and "perpendicular" encompass identity or near identity, including variations that may occur (e.g., due to manufacturing processes). Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning.

[0022] Ordinal numbers such as "first," "second," and "third" may simply be used as labels for specific elements, steps, and the like to distinguish them from one another. Terms not described using "first," "second," and the like in the specification may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced with a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0023] For ease of description, spatially relative terms (such as "under," "beneath," "lower," "above," "upper," "top," "bottom," "front," "back," etc.) may be used herein to describe positional relationships, for example, as shown in the figures. It will be understood that the spatially relative terms also encompass different orientations of the device in addition to the orientation depicted in the figures.

[0024] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Like reference numerals denote like elements, and their repeated descriptions are omitted.

[0025] Figure 1A and Figure 1B 1 and 2 are respectively a plan view and a cross-sectional view of a semiconductor package 1000 according to an embodiment.

[0026] Reference Figure 1A and Figure 1B The semiconductor package 1000 of the current embodiment may include a first redistribution substrate 100, a first semiconductor chip 200, a through-pillar 300, a second redistribution substrate 400, a semiconductor device 500, a second semiconductor chip 600, external connection terminals 700, a passive element 800, and an encapsulant 900.

[0027] The first redistribution substrate 100 may be disposed under the first semiconductor chip 200, the through pillars 300, and the first sealant 910. The first redistribution substrate 100 may redistribute the chip pads of the first semiconductor chip 200 to an outer region of the first semiconductor chip 200. The first redistribution substrate 100 may include a first body insulating layer 101 and first redistribution lines 110.

[0028] The first body insulating layer 101 may include an insulating material (e.g., a photoimageable dielectric (PID) or a photoimageable polyimide (PIP) resin) and may further include an inorganic filler. However, the material of the first body insulating layer 101 is not limited thereto. For example, the first body insulating layer 101 may include polyimide isoindolequinazolinedione (PIQ), polyimide (PI), or polybenzoxazole (PBO).

[0029] The first body insulating layer 101 may have a multi-layer structure according to the multi-layer structure of the first redistribution line 110. However, in Figure 1B , for convenience, the first body insulating layer 101 is shown as having a single-layer structure. When the first body insulating layer 101 has a multi-layer structure, all layers of the first body insulating layer 101 may include the same material, or at least one layer may include different materials.

[0030] The first redistribution lines 110 may be arranged in multiple layers in the first body insulating layer 101. The first redistribution lines 110 arranged in multiple layers may be connected to each other through vertical vias. For reference, Figure 1B The vertical vias are not shown in FIG. The first redistribution line 110 and the vertical vias may include, for example, copper (Cu). However, the materials of the first redistribution line 110 and the vertical vias are not limited to Cu.

[0031] The external connection terminals 700 may be disposed on the bottom surface of the first body insulating layer 101. The external connection terminals 700 may be respectively disposed on external connection pads disposed on the bottom surface of the first body insulating layer 101. The external connection pads may be included as part of the first redistribution line 110. However, in some embodiments, the external connection pads may be considered as a component separate from the first redistribution line 110.

[0032] The first semiconductor chip 200 can be mounted on the first redistribution substrate 100 via the first connection terminals 250. Each of the first connection terminals 250 may include a metal pillar or solder. In some embodiments, the first connection terminals 250 may include a metal pillar and / or solder (e.g., a solder ball or solder bump). Here, the metal pillar may include, for example, Cu. However, the material of the metal pillar is not limited to Cu.

[0033] The first semiconductor chip 200 may be arranged on the first redistribution substrate 100 to be offset to one side in the x-direction (e.g., placed on one side). For example, in a plan view, the center of the first semiconductor chip 200 may not be disposed at the center of the first redistribution substrate 100, but may be spaced apart from the center of the first redistribution substrate 100 in the x-direction in the plan view. For example, Figure 1B As shown in FIG, the first semiconductor chip 200 can be arranged on the first redistribution substrate 100 so as to be offset to the right in the x-direction (e.g., placed on one side). Since the first semiconductor chip 200 is offset to the right in the x-direction, the second semiconductor chip 600 above the first semiconductor chip 200 can also be offset to the right. This arrangement can effectively dissipate heat generated by the first semiconductor chip 200 and the second semiconductor chip 600.

[0034] The first semiconductor chip 200 may be an analog chip. For example, the first semiconductor chip 200 may be a modem chip that supports communication with the second semiconductor chip 600. However, the type of the first semiconductor chip 200 is not limited to a modem chip. For example, the first semiconductor chip 200 may include other types of integrated devices that support the operation of the second semiconductor chip 600. The first semiconductor chip 200 may include a multi-channel I / O interface for exchanging memory signals with the semiconductor device 500. The first semiconductor chip 200 may include static random access memory (SRAM) for temporary data storage.

[0035] like Figure 1B As shown in , the first semiconductor chip 200 may include a substrate 201, an active layer 210, and a through-electrode 220. The substrate 201 may constitute the main body of the first semiconductor chip 200 and may be based on a silicon wafer. The active layer 210 may be arranged below the substrate 201. For example, the active layer 210 may include an integrated circuit layer on which active elements (such as transistors) are arranged, and a multilayer wiring structure arranged on the integrated circuit layer. The multilayer wiring structure may occupy most of the active layer 210, and the integrated circuit layer may occupy only a portion of the active layer 210. For example, the multilayer wiring structure may include multiple layers of wiring lines, and the wiring lines in different layers may be connected to each other through vias. Chip pads electrically connected to the multilayer wiring lines may be arranged on the bottom surface of the active layer 210, and the first connection terminals 250 may be arranged on the chip pads, respectively.

[0036] The through-electrode 220 may extend through the substrate 201 in the vertical direction (i.e., the z-direction). The bottom surface of the through-electrode 220 may be electrically connected to (e.g., in contact with) the multilayer wiring lines of the active layer 210, and the top surface of the through-electrode 220 may be electrically connected to (e.g., in contact with) the second connection terminal 270. For example, an upper pad may be arranged on the top surface of the through-electrode 220, and the second connection terminal 270 may be electrically connected to the through-electrode 220 via the upper pad. Thus, the first semiconductor chip 200 may be electrically connected to the second redistribution substrate 400 via the through-electrode 220 and the second connection terminal 270. Furthermore, the first semiconductor chip 200 may be electrically connected to the second semiconductor chip 600 via the second redistribution line 410 and the fourth connection terminal 650 of the second redistribution substrate 400.

[0037] Because the through-electrodes 220 penetrate the silicon constituting the substrate 201, each through-electrode 220 may be referred to as a through-silicon via (TSV, or through-silicon via). For reference, the through-electrodes 220 may include a via-initial structure formed before forming the integrated circuit layer of the active layer 210, a via-intermediate structure formed after forming the integrated circuit layer and before forming the multi-layer wiring structure of the active layer 210, and / or a via-final structure formed after forming the multi-layer wiring structure. Figure 1B In the embodiment shown in , the through-electrode 220 may correspond to or may have, for example, a via-middle structure. However, the inventive concept is not limited thereto. In the semiconductor package 1000 of the current embodiment, the through-electrode 220 may have a via-first structure or a via-last structure.

[0038] In the first semiconductor chip 200, the bottom surface may be the front side, which is the active surface, and the top surface may be the back side, which is the inactive surface. For example, the bottom surface of the active layer 210 may correspond to or may be the front side of the first semiconductor chip 200, while the top surface of the substrate 201 may correspond to or may be the back side of the first semiconductor chip 200. A die pad may be formed on the front side, which is the active surface, and the first semiconductor chip 200 may be mounted on the first redistribution substrate 100 via the first connection terminals 250 arranged on the die pad.

[0039] The through-pillars 300 may be disposed between the first redistribution substrate 100 and the second redistribution substrate 400. Since the first encapsulant 910 is disposed between the first redistribution substrate 100 and the second redistribution substrate 400, the through-pillars 300 may extend in the z-direction through the first encapsulant 910. The through-pillars 300 may electrically connect the first redistribution substrate 100 to the second redistribution substrate 400. For example, the through-pillars 300 may be electrically connected to (e.g., in contact with) the first redistribution lines 110 of the first redistribution substrate 100, and may also be electrically connected to (e.g., in contact with) the second redistribution lines 410 of the second redistribution substrate 400.

[0040] In the semiconductor package 1000 of the current embodiment, the through-pillar 300 may include a first through-pillar 310 and a second through-pillar 320. Figure 1A and Figure 1B Note that the first through-pillars 310 may be arranged on the first redistribution substrate 100 on the left side of the first semiconductor chip 200 in the x-direction. For example, the first through-pillars 310 may be arranged in a two-dimensional array on the first redistribution substrate 100 on the left side of the first semiconductor chip 200 in the x-direction. The first through-pillars 310 may be electrically connected to the semiconductor device 500 through the second redistribution substrate 400.

[0041] The second through-pillars 320 may be arranged on the first redistribution line substrate 100 to the right of the first semiconductor chip 200 in the x-direction. For example, the second through-pillars 320 may be arranged in a row in a horizontal direction (e.g., the y-direction) on the first redistribution substrate 100 to the right of the first semiconductor chip 200 in the x-direction. However, in some embodiments, the second through-pillars 320 may be arranged in multiple rows (e.g., in the y-direction). The second through-pillars 320 may be electrically connected to the second semiconductor chip 600 via the second redistribution substrate 400.

[0042] The left and right sides in the x-direction can be relative concepts. Therefore, the positions of the first semiconductor chip 200, the first through-pillar 310, and the second through-pillar 320 can be varied. For example, the first semiconductor chip 200 can be offset to the left in the x-direction, the first through-pillar 310 can be arranged on the right side of the first semiconductor chip 200 in the x-direction, and the second through-pillar 320 can be arranged on the left side of the first semiconductor chip 200 in the x-direction. For example, the first through-pillar 310 and the second through-pillar 320 can be arranged on opposite sides of the first semiconductor chip 200 in the horizontal direction (e.g., the x-direction). Furthermore, the second semiconductor chip 600 can be arranged on the left side in the x-direction to correspond to the first semiconductor chip 200 (e.g., vertically stacked), and the semiconductor device 500 can be arranged on the right side in the x-direction.

[0043] The through-pillar 300 may include, for example, Cu. Therefore, each of the through-pillars 300 may be referred to as a copper pillar. However, the material of the through-pillar 300 is not limited to Cu. The through-pillar 300 may be formed by electroplating using a seed metal. The seed metal may include one of various metal materials such as Cu, titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN). In the semiconductor package 1000 of the current embodiment, the seed metal may be included as part of the through-pillar 300. For example, both the seed metal and the through-pillar 300 may include Cu. Therefore, in Figure 1B , the seed metal is not shown separately.

[0044] The second redistribution substrate 400 may be arranged on the first semiconductor chip 200, the through-pillars 300, and the first encapsulant 910. The second redistribution substrate 400 has a structure similar to that of the first redistribution substrate 100, but may differ in thickness. For example, the second redistribution substrate 400 may include a second body insulating layer 401 and second redistribution lines 410. For example, the second redistribution substrate 400 may include a plurality of second redistribution lines 410 spaced apart from each other in the vertical direction. However, the number of layers of the second redistribution lines 410 of the second redistribution substrate 400 may be less than the number of layers of the first redistribution lines 110 of the first redistribution substrate 100. However, in some embodiments, the number of layers of the second redistribution lines 410 of the second redistribution substrate 400 may be the same or substantially the same as the number of layers of the first redistribution lines 110 of the first redistribution substrate 100. The second redistribution lines 410 of the second redistribution substrate 400 may be electrically connected to the external connection terminals 700 through the through-pillars 300 and the first redistribution lines 110 of the first redistribution substrate 100.

[0045] The semiconductor device 500 can be mounted on the second redistribution substrate 400 through the third connection terminal 550. The semiconductor device 500 can be arranged on the left side of the second redistribution substrate 400 in the x-direction to correspond to the first through-pillar 310 (e.g., vertically stacked). The semiconductor device 500 can be a single chip or a package including a plurality of chips. For example, when the semiconductor device 500 is a single chip, the semiconductor device 500 may include or may be a memory chip. When the semiconductor device 500 is a package, the semiconductor device 500 may include, for example, a plurality of memory chips. Each memory chip of the semiconductor device 500 may include or may be, for example, a volatile memory device (such as a dynamic random access memory (DRAM) or SRAM) or a non-volatile memory device (such as a flash memory). In the semiconductor package 1000 of the current embodiment, each memory chip of the semiconductor device 500 may be, for example, a DRAM chip. The type of memory chip of the semiconductor device 500 is not limited to a DRAM chip. In the case of Figures 2A to 2C The single chip structure or package structure of the semiconductor device 500 is described in more detail in the description of FIG.

[0046] When the semiconductor device 500 is a package, the semiconductor package 1000 of the present embodiment may correspond to or have a package-on-package (POP) structure. For example, in the semiconductor package 1000 of the present embodiment, the first redistribution substrate 100, the first semiconductor chip 200, the through-pillars 300, and the second redistribution substrate 400 may constitute a lower package, and the semiconductor device 500 having the package structure may constitute an upper package. Therefore, the semiconductor package 1000 of the present embodiment may have a POP structure in which an upper package is stacked on a lower package.

[0047] The second semiconductor chip 600 can be mounted on the second redistribution substrate 400 via the fourth connection terminals 650. The second semiconductor chip 600 can be arranged on the right side of the second redistribution substrate 400 in the x-direction to correspond to (e.g., vertically stacked with) the first semiconductor chip 200. As described above, since the second semiconductor chip 600 is arranged on the first semiconductor chip 200, the signal path between the first semiconductor chip 200 and the second semiconductor chip 600 can be minimized and heat dissipation characteristics can be maximized.

[0048] In some embodiments, the second semiconductor chip 600 can be mounted on the second redistribution substrate 400 via pad-to-pad bonding, hybrid bonding (HB), or bonding using an anisotropic conductive film (ACF). For reference, because the pads typically include Cu, pad-to-pad bonding is also referred to as Cu-to-Cu bonding in certain embodiments. HB can mean a combination of pad-to-pad bonding and insulator-to-insulator bonding. ACF, which conducts electricity in only one direction, can refer to a conductive film made by mixing fine conductive particles with an adhesive resin to form a film.

[0049] The second semiconductor chip 600 may be a logic chip. Therefore, the second semiconductor chip 600 may include multiple logic elements. Here, the logic elements that perform various signal processing may include, for example, AND, OR, NOT, or flip-flops. In the semiconductor package 1000 of the current embodiment, the second semiconductor chip 600 may be, for example, an application processor (AP) chip. Depending on the function of the second semiconductor chip 600, the second semiconductor chip 600 may be a control chip, a processing chip, or a central processing unit (CPU) chip. In terms of integrated functionality, the second semiconductor chip 600 may be a system-on-chip (SoC) together with the first semiconductor chip 200 or independently of the first semiconductor chip 200.

[0050] The second semiconductor chip 600 may include a substrate and an active layer. However, unlike the first semiconductor chip 200, the second semiconductor chip 600 may not include a through-electrode. The active layer may include an integrated circuit layer and a multilayer wiring structure. The integrated circuit layer may include a plurality of integrated devices. The multilayer wiring structure may be arranged below the integrated circuit layer and may include multilayer wiring lines. The bottom surface of the second semiconductor chip 600 may be a front side serving as an active surface, and the top surface of the second semiconductor chip 600 may be a back side serving as an inactive surface. For example, the bottom surface of the active layer may correspond to the front side of the second semiconductor chip 600, and the top surface of the substrate may correspond to the back side of the second semiconductor chip 600.

[0051] The external connection terminals 700 can be electrically connected to the first redistribution lines 110 via external connection pads arranged on the bottom surface of the first redistribution substrate 100. Thus, the external connection terminals 700 can be electrically connected to the first semiconductor chip 200 via the first redistribution lines 110 and the first connection terminals 250 of the first redistribution substrate 100. Furthermore, the external connection terminals 700 can electrically connect the semiconductor package 1000 to a package substrate of an external system or a mainboard of an electronic device (such as a mobile device). The external connection terminals 700 may include at least one of a conductive material (e.g., solder, tin (Sn), silver (Ag), Cu, and aluminum (Al)). However, the material of the external connection terminals 700 is not limited to the above materials.

[0052] The external connection terminals 700 may be arranged on a first bottom surface of the first redistribution substrate 100 that corresponds to (e.g., vertically overlaps) the bottom surface of the first semiconductor chip 200, and on a second bottom surface of the first redistribution substrate 100 that extends outward from the first bottom surface in the x and y directions (e.g., a portion of the bottom surface of the first redistribution substrate 100 that does not vertically overlap the bottom surface of the first semiconductor chip 200). In this manner, a package structure in which the external connection terminals 700 are arranged in an area wider than the bottom surface of the first semiconductor chip 200 is referred to as a fan-out (FO) package structure. A package structure in which the external connection terminals 700 are arranged only on the first bottom surface that corresponds to (e.g., vertically overlaps) the bottom surface of the first semiconductor chip 200 is referred to as a fan-in (FI) package structure.

[0053] The passive component 800 may be arranged on the bottom surface of the first redistribution substrate 100. Depending on the embodiment, the passive component 800 may be arranged on the top surface of the first redistribution substrate 100 or within the first redistribution substrate 100. In certain embodiments, the passive component 800 may be arranged on the bottom or top surface of the second redistribution substrate 400 or within the second redistribution substrate 400. The passive component 800 may include a two-terminal component such as a resistor, inductor, or capacitor. In the semiconductor package 1000 of the current embodiment, the passive component 800 may include a multilayer ceramic capacitor (MLCC) 810 and a Si capacitor 820.

[0054] The encapsulant 900 may include a first encapsulant 910 and a second encapsulant 920. The first encapsulant 910 may be disposed between the first redistribution line substrate 100 and the second redistribution line substrate 400. The first encapsulant 910 may cover (e.g., contact) and seal the side surfaces of the through-pillars 300 and the side and top surfaces of the first semiconductor chip 200. In some embodiments, the first semiconductor chip 200 may be connected to the second redistribution substrate 400 via pad-to-pad bonding, HB bonding, or bonding using an ACF, and the first encapsulant 910 may not be disposed between the first semiconductor chip 200 and the second redistribution substrate 400.

[0055] The second encapsulant 920 may be disposed on the second redistribution substrate 400 and may cover (e.g., contact) and seal the side surfaces of the semiconductor device 500 and the side surfaces of the second semiconductor chip 600. The second encapsulant 920 may fill the space between the second redistribution substrate 400 and the semiconductor device 500 and the space between / among the third connection terminals 550. In addition, the second encapsulant 920 may fill the space between the second redistribution substrate 400 and the second semiconductor chip 600 and the space between / among the fourth connection terminals 650.

[0056] However, in some embodiments, an underfill may be filled between the semiconductor device 500 and the second redistribution substrate 400 and in / between the third connection terminals 550, and a side surface of the underfill may be covered with (e.g., in contact with) the second sealant 920. In some embodiments, an underfill may be filled between the second semiconductor chip 600 and the second redistribution substrate 400 and in / between the fourth connection terminals 650, and a side surface of the underfill may be covered with (e.g., in contact with) the second sealant 920.

[0057] The second sealant 920 may seal the semiconductor device 500 and the second semiconductor chip 600 to expose the top surface of the semiconductor device 500 and the top surface of the second semiconductor chip 600. Figure 1B As shown in , the top surface of the semiconductor device 500, the top surface of the second semiconductor chip 600, and the top surface of the second encapsulant 920 can be substantially coplanar. Because the top surface of the second semiconductor chip 600 is exposed from the second encapsulant 920, the heat dissipation characteristics of the second semiconductor chip 600 can be maximized. Because the second encapsulant 920 exposes the top surface of the semiconductor device 500 and the top surface of the second semiconductor chip 600, the thickness of the second encapsulant 920 can be minimized and the overall thickness of the semiconductor package 1000 can be reduced.

[0058] In the semiconductor package 1000 of the current embodiment, for example, the first semiconductor chip 200 may have a thickness of 0.2 mm or less, the second semiconductor chip 600 may have a thickness of 0.5 mm or less, and the total thickness of the semiconductor package 1000 may be 1.0 mm or less. In terms of the area of the semiconductor package 1000 of the current embodiment, for example, in a plan view, the first semiconductor chip 200 may have a thickness of 13.0*11.0 mm. 2 or smaller, the second semiconductor chip 600 may have a size of 12*10mm 2 or smaller, the semiconductor device 500 may have a size of 7.0*12.5mm 2 or smaller size, and the total area of the package can be 17.0*14.0mm 2 However, the thickness and area of the components of the semiconductor package 1000 of the current embodiment are not limited to the above values.

[0059] The sealant 900 may include an insulating material (e.g., a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin including a reinforcing material such as an inorganic filler). For example, the sealant 900 may include ABF (Ajinomoto Build-up Film), FR-4, or BT (Bismaleimide Triazine) resin. In some embodiments, the sealant 900 may include a molding material such as epoxy molding compound (EMC) or a photosensitive material such as photoimageable encapsulant (PIE). However, the material of the sealant 900 is not limited to the above materials.

[0060] Reference Figure 1A Briefly observing the relationship between the planar sizes and positions of the first redistribution substrate 100, the second redistribution substrate 400, the first semiconductor chip 200, the second semiconductor chip 600, and the semiconductor device 500, the first redistribution substrate 100 and the second redistribution substrate 400 may have substantially the same size in plan view as the encapsulant 900. Therefore, the first semiconductor chip 200 and the through-pillars 300 may be located in the first redistribution substrate 100 in plan view. In addition, the semiconductor device 500 and the second semiconductor chip 600 arranged on the through-pillars 300 and the first semiconductor chip 200 may also be located in the second redistribution substrate 400 in plan view.

[0061] Most of the first semiconductor chip 200 may vertically overlap with the second semiconductor chip 600, and only a portion of the first semiconductor chip 200 may vertically overlap with the semiconductor device 500. For example, the semiconductor device 500 may vertically overlap with the first through-pillar 310 and the left portion of the first semiconductor chip 200 in the x-direction. The second semiconductor chip 600 may vertically overlap with the second through-pillar 320 and the center and right portions of the first semiconductor chip 200 in the x-direction.

[0062] The semiconductor package 1000 of the present embodiment utilizes a fan-out wafer-level packaging (FOWLP) structure to simultaneously maximize heat dissipation characteristics and achieve a small form factor. For example, the first semiconductor chip 200 can be electrically connected to the second redistribution substrate 400 via through-electrodes 220 and second connection terminals 270, and can have a thickness corresponding to the first encapsulant 910. Therefore, heat generated by the first semiconductor chip 200 can be efficiently transferred to the second redistribution substrate 400. Furthermore, the second semiconductor chip 600 can be arranged on the second redistribution substrate 400 with its top surface exposed and can have a thickness corresponding to the second encapsulant 920. Therefore, heat generated by the second semiconductor chip 600 can be effectively dissipated, and heat generated by the first semiconductor chip 200 can also be dissipated upward from the semiconductor package 1000 together with the second redistribution substrate 400. For example, heat generated by the first semiconductor chip 200 can be dissipated upward through the second redistribution substrate 400 and the second semiconductor chip 600. As a result, the heat dissipation characteristics of the semiconductor package 1000 can be significantly improved.

[0063] In addition, in the semiconductor package 1000 of the present embodiment, as shown in FIG. Figure 1A and Figure 1B As shown in FIG, the first semiconductor chip 200 and the second semiconductor chip 600 can be vertically stacked via the second redistribution substrate 400. Therefore, the semiconductor package 1000 of the present embodiment can achieve a small form factor. Furthermore, because the second through-pillars 320 are arranged below the second semiconductor chip 600, power can be efficiently transmitted to the second semiconductor chip 600 via the second through-pillars 320. For example, by using the second through-pillars 320 and the second redistribution substrate 400, the power path to the second semiconductor chip 600 can have the shortest distance. In the semiconductor package 1000 of the present embodiment, the first semiconductor chip 200 and the second semiconductor chip 600 do not need to be separately manufactured in a 3D-IC structure. Therefore, the semiconductor package 1000 of the present embodiment can benefit from improved turnaround time (TAT) and can be highly advantageous in terms of production yield and investment / manufacturing cost efficiency. For example, compared to the comparative example, the semiconductor package 1000 of the present embodiment can increase data transmission rate and reduce manufacturing costs of the semiconductor package 1000.

[0064] For reference, consider a structure in which a first semiconductor chip 200 and a second semiconductor chip 600 having a 3D-IC structure are applied to a semiconductor package. Here, the 3D-IC structure may be a structure in which the second semiconductor chip 600 is directly stacked on the first semiconductor chip 200 via connection terminals and integrated with the first semiconductor chip 200. In the case of a semiconductor package structure in which the 3D-IC structure is arranged between a lower redistribution substrate and an upper redistribution substrate, a small form factor can be achieved, but there are limitations in terms of heat dissipation characteristics. Furthermore, to improve heat dissipation characteristics, a heat path block (HPB) (such as a heat sink) may be added to the upper redistribution substrate, which may increase the overall thickness of the semiconductor package. In the case of a semiconductor package structure in which the upper redistribution substrate is omitted and a semiconductor device including a memory chip and a 3D-IC are arranged together on a single redistribution substrate, heat dissipation characteristics can be maximized, but since the 3D-IC is arranged side by side next to the semiconductor device, achieving a small form factor may be limited.

[0065] As described above, the semiconductor package 1000 of the present embodiment may have a FOWLP structure and may simultaneously maximize heat dissipation characteristics and achieve a small form factor. In addition, compared to a package structure including a 3D-IC structure, the semiconductor package 1000 of the present embodiment may be advantageous in terms of power supply to the second semiconductor chip 600, TAT gain, data yield, and investment / manufacturing cost.

[0066] Figures 2A to 2C is shown in more detail Figure 1B FIG. 1 is a cross-sectional view of the structure of a memory device in a semiconductor package 1000 .

[0067] Reference Figure 2A The semiconductor device 500 may include or may be a memory chip. The memory chip may include, for example, a volatile memory device (such as DRAM or SRAM) or a non-volatile memory device (such as flash memory). In the semiconductor package 1000 of the current embodiment, the memory chip of the semiconductor device 500 may include or may be, for example, a DRAM chip. The semiconductor device 500 may be mounted on the second redistribution substrate 400 using the third connection terminals 550 in a flip-chip bonding structure. Each of the third connection terminals 550 may include a connection column and solder, or may include only solder.

[0068] Reference Figure 2B, the semiconductor device 500a may include or may be a semiconductor package with a wire bonding structure. For example, the semiconductor device 500a may include a package substrate 510 and a plurality of memory chips 520 stacked on the package substrate 510. The plurality of memory chips 520 may be mounted on the package substrate 510 in a wire bonding structure using an adhesive layer 525 and wires 530. For example, each of the memory chips 520 may be connected to another memory chip 520 and / or the package substrate 510 via one or more wires. Each memory chip 520 of the semiconductor device 500a may include or may be, for example, a volatile memory device (such as DRAM or SRAM) or a non-volatile memory device (such as flash memory). In the semiconductor package 1000 of the current embodiment, the memory chip 520 of the semiconductor device 500a may include, for example, a DRAM chip. The semiconductor device 500a may include an internal sealant that seals the plurality of memory chips 520 and the wires 530 on the package substrate 510. However, in Figure 2B For convenience, the internal sealant is omitted.

[0069] exist Figure 2B , although four memory chips 520 are stacked on the package substrate 510, the number of memory chips 520 is not limited to four. For example, three or less or five or more memory chips 520 may be stacked on the package substrate 510. In addition, the stacking or arrangement of the memory chips 520 is not limited to the step structure, and may be stacked on the package substrate 510 in a zigzag structure or a combination of a step structure and a zigzag structure. For example, the zigzag structure may be a stacking structure in which the memory chips 520 are stacked vertically and alternately shifted a predetermined distance in two opposite horizontal directions from the corresponding immediately below memory chips 520. The semiconductor device 500a having a package structure may also be mounted on the second redistribution substrate 400 via the third connection terminal 550.

[0070] Reference Figure 2C The semiconductor device 500b may include or may be a high-bandwidth memory (HBM) package. For example, the semiconductor device 500b may include a base chip 510a, multiple core chips 520a stacked on the base chip 510a, and an internal encapsulant 540. Furthermore, the base chip 510a and the multiple core chips 520a may include through-electrodes 530a therein. The uppermost core chip 520a among the multiple core chips 520a may not include the through-electrode 530a.

[0071] The base chip 510a may include logic elements. Therefore, the base chip 510a may be a logic chip. The base chip 510a may be arranged below the core chip 520a, may integrate signals received from the core chip 520a and send the integrated signals to the outside, and may send signals and power from the outside to the core chip 520a. Therefore, the base chip 510a may be a buffer chip or a control chip. Each of the multiple core chips 520a may be a memory chip. For example, each of the multiple core chips 520a may be a DRAM chip. Each of the core chips 520a may be stacked on the base chip 510a or the lower core chip 520a by pad-to-pad bonding, HB, bonding using connection terminals, or bonding using ACF. In Figure 2C In FIG. 5 , although four core chips 520 a are stacked on the base chip 510 a , the number of core chips 520 a is not limited to four. For example, three or less or five or more core chips 520 a may be stacked on the base chip 510 a.

[0072] The third connection terminals 550 may be arranged on the bottom surface of the base chip 510a. Thus, the semiconductor device 500b of the HBM package can also be mounted on the second redistribution substrate 400 via the third connection terminals 550. The plurality of core chips 520a on the base chip 510a may be sealed by the internal sealant 540. However, the top surface of the uppermost core chip 520a among the plurality of core chips 520a may not be covered by the internal sealant 540. However, in other embodiments, the top surface of the uppermost core chip 520a may be covered by (e.g., in contact with) the internal sealant 540.

[0073] Figure 3A and Figure 3B is a plan view of semiconductor packages 1000a and 1000b according to an embodiment, and each may be Figure 1A The previous reference Figures 1A to 2C The given description is applicable to the present embodiment and will be briefly given or omitted in the following description for the sake of simplicity of description.

[0074] Reference Figure 3A , the semiconductor package 1000a of the current embodiment may be different from the semiconductor package 1000a in terms of the arrangement of the through pillars 300a. Figure 1AFor example, the semiconductor package 1000a of the current embodiment may include a first redistribution substrate 100, a first semiconductor chip 200, a through-pillar 300a, a second redistribution substrate 400, a semiconductor device 500, a second semiconductor chip 600, an external connection terminal 700, a passive component 800, and a sealant 900. The description of the first redistribution substrate 100, the first semiconductor chip 200, the second redistribution substrate 400, the semiconductor device 500, the second semiconductor chip 600, the external connection terminal 700, the passive component 800, and the sealant 900 is the same as that of the first redistribution substrate 100. Figure 1A and Figure 1B The first redistribution substrate 100 , the first semiconductor chip 200 , the second redistribution substrate 400 , the semiconductor device 500 , the second semiconductor chip 600 , the external connection terminals 700 , the passive elements 800 , and the sealant 900 of the semiconductor package 1000 are the same as described above.

[0075] In the semiconductor package 1000a of the current embodiment, the through-pillars 300a may be arranged on the first redistribution substrate 100 only on the left side of the first semiconductor chip 200 in the x-direction. For example, the through-pillars 300a may not be arranged on the first redistribution substrate 100 on the right side of the first semiconductor chip 200 in the x-direction. Therefore, the first semiconductor chip 200 may be arranged on the first redistribution substrate 100 so as to be offset / shifted further to the right in the x-direction. As a result, the area in which the first semiconductor chip 200 and the second semiconductor chip 600 vertically overlap can be increased, and the heat dissipation efficiency of the first semiconductor chip 200 can be improved.

[0076] Reference Figure 3B , the semiconductor package 1000b of the current embodiment may be different from the arrangement of the through pillars 300b. Figure 1A For example, the semiconductor package 1000b of the current embodiment may include a first redistribution substrate 100, a first semiconductor chip 200, a through-pillar 300b, a second redistribution substrate 400, a semiconductor device 500, a second semiconductor chip 600, an external connection terminal 700, a passive component 800, and a sealant 900. The description of the first redistribution substrate 100, the first semiconductor chip 200, the second redistribution substrate 400, the semiconductor device 500, the second semiconductor chip 600, the external connection terminal 700, the passive component 800, and the sealant 900 is the same as that of the first redistribution substrate 100. Figure 1A and Figure 1B The description of the first redistribution substrate 100 , the first semiconductor chip 200 , the second redistribution substrate 400 , the semiconductor device 500 , the second semiconductor chip 600 , the external connection terminals 700 , the passive elements 800 , and the sealant 900 of the semiconductor package 1000 are the same.

[0077] In the semiconductor package 1000b of the current embodiment, the through-pillars 300b may include a first through-pillar 310 and a second through-pillar 320a. The first through-pillar 310 may be arranged on the first redistribution substrate 100 on the left side of the first semiconductor chip 200 in the x-direction. The second through-pillar 320a may be arranged on the first redistribution substrate 100 on the right side of the first semiconductor chip 200 in the x-direction and on both sides of the first semiconductor chip 200 in the y-direction. For example, the second through-pillar 320a may be arranged on the right side of the first semiconductor chip 200 in the x-direction and on both sides of the first semiconductor chip 200 in the y-direction to surround the first semiconductor chip 200. For example, the second through-pillars 320a may be arranged in a row to surround three side surfaces of the first semiconductor chip 200. However, in some embodiments, the second through-pillars 320a may be arranged in multiple rows on each of the three side surfaces to surround the three side surfaces of the first semiconductor chip 200.

[0078] In the semiconductor package 1000b of the current embodiment, more second through-pillars 320a may be arranged under the second redistribution substrate 400 corresponding to the second semiconductor chip 600. Therefore, since the power supply path to the second semiconductor chip 600 increases, the effect of power transmission to the second semiconductor chip 600 may be further improved.

[0079] Figure 4 is a cross-sectional view of a semiconductor package according to an embodiment, and may be compared with Figure 1B The sectional view of the previous reference Figures 1A to 3B The given description is also applicable to the present embodiment and will be briefly given or omitted in the following description for the sake of simplicity of description.

[0080] Reference Figure 4 , the semiconductor package 1000c of the current embodiment may be different from the semiconductor package 1000c in terms of the structure of the second semiconductor chip 600a and the sealant 900a. Figure 1B For example, the semiconductor package 1000c of the current embodiment may include a first redistribution substrate 100, a first semiconductor chip 200, a through-pillar 300, a second redistribution substrate 400, a semiconductor device 500, a second semiconductor chip 600a, an external connection terminal 700, a passive element 800, and a sealant 900a. The description of the first redistribution substrate 100, the first semiconductor chip 200, the second redistribution substrate 400, the semiconductor device 500, the external connection terminal 700, and the passive element 800 is the same as that of the embodiment. Figure 1A The description of the first redistribution substrate 100 , the first semiconductor chip 200 , the second redistribution substrate 400 , the semiconductor device 500 , the external connection terminals 700 , and the passive elements 800 of the semiconductor package 1000 are the same.

[0081] In the semiconductor package 1000c of the current embodiment, the thickness of the second semiconductor chip 600a may be less than Figure 1B The thickness of the second semiconductor chip 600 of the semiconductor package 1000 is determined by the second height H2. Therefore, the second height H2, which is the height of the top surface of the second semiconductor chip 600a mounted on the second redistribution substrate 400, may be less than the first height H1, which is the height of the top surface of the semiconductor device 500 mounted on the second redistribution substrate 400. Because the top surface of the second semiconductor chip 600a is lower than the top surface of the semiconductor device 500, the encapsulant 900a may cover (e.g., contact) the top surface of the second semiconductor chip 600a. For example, the second encapsulant 920a may expose the top surface of the semiconductor device 500 but may not expose the top surface of the second semiconductor chip 600a. For reference, exposing the top surface of the second semiconductor chip 600a from the encapsulant 900a may be advantageous in terms of heat dissipation. However, when the semiconductor device 500 has a package structure, the second semiconductor chip 600a, as a chip, may be thinner than the semiconductor device 500 (e.g., as a package). Therefore, the semiconductor package 1000c of the present embodiment may be implemented in a manufacturing process in certain embodiments to accommodate a chip and a package. 7A to 7C A method of manufacturing the semiconductor package 1000 c according to the current embodiment is described in more detail.

[0082] While the structures of several semiconductor packages 1000 and 1000a to 1000c have been described so far, the inventive concept is not limited to the aforementioned semiconductor package structures. For example, the inventive concept is applicable to all semiconductor package structures having a 3D stacked structure with FOWLP, and is also applicable to all semiconductor package structures requiring a redistribution layer (RDL) process.

[0083] Figures 5A to 5J is a cross-sectional view schematically showing a process of a method for manufacturing a semiconductor package according to an embodiment. Figure 1A and Figure 1B Give Figures 5A to 5J The description of the method shown in and previously referred to Figures 1A to 4 The given description is also applicable to the present embodiment and will be briefly given or omitted in the following description for the sake of simplicity of description.

[0084] Reference Figure 5AIn the semiconductor package manufacturing method of the current embodiment, first, an upper redistribution substrate 400s is formed. The upper redistribution substrate 400s may include a second body insulating layer 401 and second redistribution lines 410. The upper redistribution substrate 400s may be formed on a first carrier substrate 2000a. The first carrier substrate 2000a may be a large-sized substrate (such as a wafer). Alternatively, the upper redistribution substrate 400s formed on the first carrier substrate 2000a may be a large-sized redistribution substrate including a plurality of second redistribution substrates 400. Although not shown, an adhesive layer may be disposed between the upper redistribution substrate 400s and the first carrier substrate 2000a. The adhesive layer may adhere and secure the upper redistribution substrate 400s to the first carrier substrate 2000a.

[0085] For reference, a semiconductor package that is individualized by a sawing process or a singulation process after subsequent components are formed on a large-scale redistribution substrate is called a wafer-level package (WLP). For example, the packaging process can be performed at the wafer level and then the package can be singulated by a sawing process. However, for convenience, Figure 5A Only components corresponding to one second redistribution substrate 400 are shown in the drawings and the subsequent drawings.

[0086] Reference Figure 5B After forming the upper redistribution substrate 400s, the semiconductor device 500 and the second semiconductor chip 600 are mounted (or attached) on the first surface of the upper redistribution substrate 400s. Here, the first surface may be Figure 1B The top surface of the second redistribution substrate 400 in the semiconductor package 1000 corresponds to the top surface of the second redistribution substrate 400 in the semiconductor package 1000. For example, the semiconductor device 500 can be mounted on the first surface of the upper redistribution substrate 400s through the third connection terminals 550, and the second semiconductor chip 600 can be mounted on the first surface of the upper redistribution substrate 400s through the fourth connection terminals 650 to be adjacent to (e.g., side by side with) the semiconductor device 500 in the x-direction. Various bonding processes (such as reflow, thermocompression bonding (TCB), and laser assisted bonding (LAB)) can be used to mount the semiconductor device 500 by using the third connection terminals 550 and to mount the second semiconductor chip 600 by using the fourth connection terminals 650. The semiconductor device 500 and the second semiconductor chip 600 are connected to the reference Figures 1A to 2C The described semiconductor device is the same as the second semiconductor chip.

[0087] like Figure 5BAs shown in FIG, the top surfaces of the semiconductor device 500 and the second semiconductor chip 600 mounted on the first surface of the upper redistribution substrate 400s are substantially the same height, and each of the top surface of the semiconductor device 500 and the top surface of the second semiconductor chip 600 may have a first height H1. However, the thicknesses of the semiconductor device 500 and the second semiconductor chip 600 may be the same or different. Therefore, in order to make the height of the top surface of the semiconductor device 500 and the height of the top surface of the second semiconductor chip 600 substantially the same, the heights of the third connection terminal 550 and the fourth connection terminal 650 may be adjusted, for example, to be the same or different from each other. In certain embodiments, in a subsequent grinding process for the upper encapsulant 920s1, the upper portion of the semiconductor device 500 or the second semiconductor chip 600 may be removed.

[0088] Reference Figure 5C , after the semiconductor device 500 and the second semiconductor chip 600 are mounted on the first surface of the upper redistribution substrate 400s, the semiconductor device 500 and the second semiconductor chip 600 are sealed with an upper sealant 920s1. The upper sealant 920s1 may cover / contact the side surfaces and top surfaces of the semiconductor device 500 and the second semiconductor chip 600. In addition, the upper sealant 920s1 may fill the space between the upper redistribution substrate 400s and the semiconductor device 500, the space between the upper redistribution substrate 400s and the second semiconductor chip 600, the space in / between the third connection terminals 550, and the space in / between the fourth connection terminals 650. However, in some embodiments, an underfill is filled between the upper redistribution substrate 400s and the semiconductor device 500, in / between the third connection terminals 550, between the upper redistribution substrate 400s and the second semiconductor chip 600, and in / between the fourth connection terminals 650, and the upper sealant 920s1 may cover / contact the side surfaces of the underfill. The material of the upper sealant 920s1 is the same as that in Figure 1B The material of the second sealant 920 is the same as that described in the description of the semiconductor package 1000 .

[0089] Reference Figure 5D , thereafter, the upper portion of the upper encapsulant 920s1 is removed by a die grinding MG process to form an upper encapsulant 920s. After the MG process, the top surfaces of the semiconductor device 500 and the second semiconductor chip 600 may be exposed from the upper encapsulant 920s. As the top surfaces of the semiconductor device 500 and the second semiconductor chip 600 are exposed by the MG process, the top surfaces of the semiconductor device 500, the second semiconductor chip 600, and the upper encapsulant 920s may be substantially coplanar. In some embodiments, the material of the upper encapsulant 920s may be the same as that in the Figure 1B The material of the second sealant 920 is the same as that described in the description of the semiconductor package 1000 .

[0090] Reference Figure 5E After the MG process, the upper redistribution substrate 400s and the structures thereon are separated from the first carrier substrate 2000a, inverted, and attached to the second carrier substrate 2000b. Figure 5E As shown in FIG, the semiconductor device 500, the second semiconductor chip 600, and the upper encapsulant 920s may be located at a lower portion on the second carrier substrate 2000b, and the upper redistribution substrate 400s may be located at an upper portion on the second carrier substrate 2000b. For example, the exposed top surfaces of the semiconductor device 500, the second semiconductor chip 600, and the upper encapsulant 920s may face downward and may be attached to the top surface of the second carrier substrate 2000b. Although not shown, an adhesive layer may be disposed between the exposed top surfaces of the semiconductor device 500, the second semiconductor chip 600, and the upper encapsulant 920s and the second carrier substrate 2000b.

[0091] Thereafter, the through-pillars 300 are formed on the second surface of the upper redistribution substrate 400s. Here, the second surface of the upper redistribution substrate 400s refers to an opposite surface of the first surface of the upper redistribution substrate 400s and may be Figure 1B The through-pillars 300 may include a first through-pillar 310 and a second through-pillar 320. The first through-pillar 310 may be arranged on the left side of the second surface of the upper redistribution substrate 400s in the x-direction to correspond to the semiconductor device 500 (e.g., vertically stacked). The second through-pillar 320 may be arranged on the right side of the second surface of the upper redistribution substrate 400s in the x-direction to correspond to the second semiconductor chip 600 (e.g., vertically stacked). Figures 6A to 6F The method of forming the through-pillar 300 is described in more detail.

[0092] Reference Figure 5F After forming the through pillars 300, the first semiconductor chip 200 is mounted in a portion of the second surface of the upper redistribution substrate 400s where the through pillars 300 are not arranged. For example, the first semiconductor chip 200 may be mounted on the second surface of the upper redistribution substrate 400s via the second connection terminals 270. The first connection terminals 250 may be arranged on the top surface of the first semiconductor chip 200. The first semiconductor chip 200 of this embodiment is connected to the first semiconductor chip 200 on the upper redistribution substrate 400s. Figure 1B The first semiconductor chip 200 is the same as described in the description of the semiconductor package 1000 .

[0093] Reference Figure 5GAfter the first semiconductor chip 200 is mounted, a lower encapsulant 910s is formed on the second surface of the upper redistribution substrate 400s, covering the through-pillars 300 and the first semiconductor chip 200. The lower encapsulant 910s may cover / contact the side surfaces and top surfaces of the through-pillars 300 and the first semiconductor chip 200. In addition, the lower encapsulant 910s may fill the space between the first semiconductor chip 200 and the upper redistribution substrate 400s, the space between / among the second connection terminals 270, and the space between / among the first connection terminals 250.

[0094] Thereafter, the upper portion of the lower sealant 910s is removed by the MG process. The top surface of the through-pillar 300 may be exposed from the lower sealant 910s by the MG process for the lower sealant 910s. Figure 1B The material of the first sealant 910 is the same as that described in the description of the semiconductor package 1000 .

[0095] Reference Figure 5H Subsequently, a lower redistribution substrate 100s is formed on the first semiconductor chip 200, the through-pillars 300, and the lower sealant 910s. The lower redistribution substrate 100s may include a first body insulating layer 101 and first redistribution lines 110. The lower redistribution substrate 100s may include a plurality of first redistribution lines 110.

[0096] Reference Figure 5I After forming the lower redistribution substrate 100s, the external connection terminals 700 and the passive components 800 are attached to the first surface of the lower redistribution substrate 100s. The first surface of the lower redistribution substrate 100s may be connected to the Figure 1B The external connection terminals 700 and the passive elements 800 are connected to the bottom surface of the first redistribution substrate 100 in the semiconductor package 1000. Figure 1B The external connection terminals 700 and the passive elements 800 described in the description of the semiconductor package 1000 are the same.

[0097] Reference Figure 5J After the external connection terminals 700 and the passive elements 800 are attached to the first surface of the lower redistribution substrate 100s, the semiconductor packages included in the entire structure may be individualized by a sawing S process for the entire structure. Figure 1B The semiconductor package 1000 is shown in FIG. 1 . In addition, after the sawing S process, a sorting process may be performed through electrical testing to sort good products from defective products.

[0098] Figures 6A to 6F is shown in more detail Figure 5E Cross-sectional view of the process.

[0099] Reference Figure 6A In the method for manufacturing a semiconductor package of the current embodiment, the through-pillars 300 can be formed on the second surface of the upper redistribution substrate 400s by the following process. First, a seed metal 301 is formed on the second surface of the upper redistribution substrate 400s. The seed metal 301 can be used in an electroplating process for later forming the through-pillars 300. The seed metal 301 can include one of various metal materials (e.g., Cu, Ti, Ta, TiN, and TaN). In the method for manufacturing a semiconductor package of the current embodiment, the seed metal 301 can include Cu, for example.

[0100] Reference Figure 6B Subsequently, a photoresist (PR) 1500 is applied on the seed metal 301 of the upper redistribution substrate 400s. The PR 1500 may be applied by, for example, a spin coating method using a spin coater. The PR 1500 may be formed to have a thickness corresponding to (e.g., the same as) the length of the through-pillar 300 in the vertical direction.

[0101] Reference Figure 6C , an exposure process is performed after applying the PR 1500. The exposure process may be performed by using a mask including a specific pattern. For example, light may be transmitted through a transparent portion of a transmissive mask to irradiate a predetermined portion of the PR 1500 with light. The chemical properties of the portion of the PR 1500 irradiated with light may be changed. For example, after the exposure process, the PR 1500 may be divided into an unexposed portion 1510 and an exposed portion 1520. As shown in FIG. Figure 6C Note that the exposure portion 1520 may be located on the left and right sides of the upper redistribution substrate 400s in the x-direction. The exposure portion 1520 on the left may correspond to the first through-pillar 310, and the exposure portion 1520 on the right may correspond to the second through-pillar 320. Figure 3A and Figure 3B When the semiconductor packages 1000a and 1000b are shown in FIG. 1 , the position of the exposure portion 1520 may vary according to the arrangement of the through-pillars 300a and 300b.

[0102] Reference Figure 6D After the exposure process, a development process is performed for the PR 1500. In the development process, for example, the exposed portion 1520 may be removed. For example, the PR 1500 may be a positive PR. According to one embodiment, a negative PR may be used. When a negative PR is used, the unexposed portion may be removed in the development process.

[0103] The exposed portion 1520 is removed by a development process to form a PR pattern 1500b. The PR pattern 1500b may include a plurality of through-holes H. The seed metal 301 may be exposed at the bottom surface of the plurality of through-holes H. After the development process, byproducts (such as PR scum) may remain within the plurality of through-holes H. Therefore, a cleaning process is performed to remove the byproducts. For reference, the process of removing PR scum is referred to as a PR descum process. The PR descum process may be included in the cleaning process.

[0104] Reference Figure 6E After a cleaning process, through-pillars 300 are formed in each of the plurality of through-holes H by electroplating. The through-pillars 300 may include a first through-pillar 310 on the left side of the upper redistribution substrate 400s in the x-direction and a second through-pillar 320 on the right side of the upper redistribution substrate 400s. The through-pillars 300 may include, for example, Cu. Although not shown, the through-pillars 300 may be formed on a portion of the top surface of the PR pattern 1500b adjacent to the plurality of through-holes H that extends beyond the plurality of through-holes H.

[0105] Reference Figure 6F , after forming the through-pillar 300, the PR pattern 1500b is removed. The PR pattern 1500b may be removed by an ashing / stripping process. After removing the PR pattern 1500b, the seed metal 301 may be exposed in / between the through-pillars 300. Subsequently, the seed metal 301 exposed in / between the through-pillars 300 is removed by an etching process. By removing the seed metal 301, the second surface of the upper redistribution substrate 400s may be exposed in / between the through-pillars 300. The seed metal 301 may remain on the bottom surface of the through-pillar 300. Because both the seed metal 301 and the through-pillar 300 include Cu, Figures 5E to 5J , the seed metal 301 and the through-pillar 300 are shown as being integrated into the through-pillar 300 .

[0106] 7A to 7C is a cross-sectional view schematically showing a process of a method for manufacturing a semiconductor package according to an embodiment. Figure 4 Give together 7A to 7C The description of the method shown in and previously referred to Figures 5A to 6F The given description is also applicable to the present embodiment and will be briefly given or omitted.

[0107] Reference Figure 7A In the semiconductor package manufacturing method of the current embodiment, first, Figure 5AAn upper redistribution substrate 400s is formed on a first carrier substrate 2000a using a process. Subsequently, a semiconductor device 500 and a second semiconductor chip 600a are mounted on the first surface of the upper redistribution substrate 400s. For example, the semiconductor device 500 may be mounted on the first surface of the upper redistribution substrate 400s via the third connection terminals 550, and the second semiconductor chip 600a may be mounted on the first surface of the upper redistribution substrate 400s via the fourth connection terminals 650, adjacent to (e.g., side by side with) the semiconductor device 500.

[0108] The top surface of the semiconductor device 500 mounted on the first surface of the upper redistribution substrate 400s may have a first height H1, and the top surface of the second semiconductor chip 600a mounted on the first surface of the upper redistribution substrate 400s may have a second height H2. Figure 7A As shown in , the second height H2 may be less than the first height H1. For example, the semiconductor device 500, the third connection terminal 550, and the fourth connection terminal 650 are the same or substantially the same as the semiconductor device 500, the third connection terminal 550, and the fourth connection terminal 650 of the first semiconductor package 1000, and may have the same thickness or height accordingly. The second semiconductor chip 600a may have a thickness less than that of the second semiconductor chip 600 of the first semiconductor package 1000. Therefore, the second height H2 of the top surface of the second semiconductor chip 600a may be less than the first height H1 of the top surface of the semiconductor device 500.

[0109] Reference Figure 7B After the semiconductor device 500 and the second semiconductor chip 600a are mounted on the first surface of the upper redistribution substrate 400s, the semiconductor device 500 and the second semiconductor chip 600a are sealed with an upper encapsulant 920s2. The upper encapsulant 920s2 may cover or contact the side surfaces and top surfaces of the semiconductor device 500 and the second semiconductor chip 600a. Furthermore, the upper encapsulant 920s2 may fill the space between the upper redistribution substrate 400s and the semiconductor device 500, the space between the upper redistribution substrate 400s and the second semiconductor chip 600a, the space between the third connection terminals 550, and the space between the fourth connection terminals 650. However, in some embodiments, an underfill fills the space between the upper redistribution substrate 400s and the semiconductor device 500, the space between the third connection terminals 550, the space between the upper redistribution substrate 400s and the second semiconductor chip 600a, and the space between the fourth connection terminals 650, and the upper encapsulant 920s2 may cover or contact the side surfaces of the underfill.

[0110] Reference Figure 7C, the upper portion of the upper sealant 920s2 is removed by the MG process to form an upper sealant 920sa. After the MG process, the top surface of the semiconductor device 500 may be exposed from the upper sealant 920sa. However, the top surface of the second semiconductor chip 600a may not be exposed and may be covered with (eg, in contact with) the upper sealant 920sa. Thereafter, Figures 5E to 5J Process manufacturing Figure 4 Semiconductor package 1000c.

[0111] Even though different figures illustrate variations of exemplary embodiments and different embodiments disclose different features from one another, these figures and embodiments are not necessarily intended to be mutually exclusive. Rather, when the figures and the associated description of the embodiments are considered as a whole, features depicted in different figures and / or described above in different embodiments may be combined with other features from other figures / embodiments to produce additional variations of the embodiments. For example, unless the context clearly indicates otherwise, components and / or features of the different embodiments described above may be combined interchangeably or additionally with components and / or features of other embodiments to form additional embodiments, and the present disclosure includes such additional embodiments.

[0112] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: a first redistribution substrate; a first semiconductor chip arranged on the first redistribution substrate on the right side in the first direction and including a through electrode; a first through-pillar arranged on the first redistribution substrate on the left side of the first semiconductor chip in the first direction; a second redistribution substrate disposed on the first semiconductor chip and the first through-pillar; a semiconductor device disposed on the second redistribution substrate on the left side in the first direction; as well as The second semiconductor chip is arranged on the second redistribution substrate on the right side of the semiconductor device in the first direction.

2. The semiconductor package according to claim 1, wherein The first semiconductor chip is electrically connected to the first redistribution substrate through first connection terminals arranged on a bottom surface of the first semiconductor chip and is electrically connected to the second redistribution substrate through second connection terminals arranged on a top surface of the first semiconductor chip.

3. The semiconductor package according to claim 2, wherein The first semiconductor chip is electrically connected to the second semiconductor chip through the second redistribution substrate and the second connection terminals.

4. The semiconductor package according to claim 1, wherein The semiconductor device vertically overlaps the first through-pillar and the left side portion of the first semiconductor chip in the first direction, and The second semiconductor chip is vertically overlapped with a center portion and a right portion of the first semiconductor chip in a first direction.

5. The semiconductor package according to claim 4, further comprising: second through-pillars arranged on the first redistribution substrate on at least one of both sides of the first semiconductor chip in a second direction perpendicular to the first direction and a right side of the first semiconductor chip in the first direction, The first through-pillar and the second through-pillar electrically connect the first redistribution substrate and the second redistribution substrate to each other.

6. The semiconductor package according to claim 1, further comprising: a first sealant disposed between the first redistribution substrate and the second redistribution substrate and sealing the first semiconductor chip; as well as The second encapsulant is disposed on the second redistribution substrate and seals the semiconductor device and the second semiconductor chip.

7. The semiconductor package according to claim 6, wherein A top surface of the second semiconductor chip is exposed from the second encapsulant.

8. The semiconductor package according to claim 1, wherein The semiconductor device is a memory chip or a memory package, and The first semiconductor chip and the second semiconductor chip are logic chips.

9. A semiconductor package comprising: a first redistribution substrate; a first semiconductor chip arranged on the first redistribution substrate on the right side in the first direction and including a through electrode; a first encapsulant disposed on the first redistribution substrate and encapsulating the first semiconductor chip; a first through-pillar arranged on the first redistribution substrate on the left side in the first direction to be side by side with the first semiconductor chip and extending through the first encapsulant; a second redistribution substrate disposed on the first semiconductor chip and the first through-pillar; a semiconductor device disposed on the second redistribution substrate on the left side in the first direction; a second semiconductor chip arranged on the second redistribution substrate on the right side in the first direction so as to be side by side with the semiconductor device; as well as a second encapsulant disposed on the second redistribution substrate and encapsulating the semiconductor device and the second semiconductor chip, The top surface of the semiconductor device and the top surface of the second semiconductor chip are exposed from the second sealant.

10. The semiconductor package according to claim 9, wherein The first semiconductor chip is electrically connected to the first redistribution substrate through first connection terminals arranged on a bottom surface of the first semiconductor chip and is electrically connected to the second redistribution substrate through second connection terminals arranged on a top surface of the first semiconductor chip, and The first semiconductor chip is electrically connected to the second semiconductor chip through the second redistribution substrate and the second connection terminal.

11. The semiconductor package according to claim 9, further comprising: second through-pillars arranged on the first redistribution substrate on at least one of both sides of the first semiconductor chip in a second direction perpendicular to the first direction and a right side of the first semiconductor chip in the first direction, and extending through the first sealant, The first through-pillar and the second through-pillar electrically connect the first redistribution substrate and the second redistribution substrate to each other.

12. A semiconductor package, comprising: a first redistribution substrate; a first semiconductor chip disposed on the first redistribution substrate and including a through electrode; a second redistribution substrate disposed on the first semiconductor chip; a semiconductor device disposed on the second redistribution substrate on the left side in the first direction; as well as The second semiconductor chip is arranged on the second redistribution substrate on the right side in the first direction to be side by side with the semiconductor device.

13. The semiconductor package according to claim 12, further comprising: a first through-pillar arranged on the first redistribution substrate on the left side of the first semiconductor chip in the first direction; as well as second through-pillars arranged on the first redistribution substrate on at least one of two sides of the first semiconductor chip in a second direction perpendicular to the first direction and a right side of the first semiconductor chip in the first direction, The first semiconductor chip is arranged on the first redistribution substrate on the right side in the first direction.

14. The semiconductor package according to claim 13, wherein The first semiconductor chip is electrically connected to the first redistribution substrate through first connection terminals arranged on a bottom surface of the first semiconductor chip and is electrically connected to the second redistribution substrate through second connection terminals arranged on a top surface of the first semiconductor chip, and The first semiconductor chip is electrically connected to the second semiconductor chip through the second redistribution substrate and the second connection terminal.

15. The semiconductor package according to claim 13, further comprising: a first sealant disposed between the first redistribution substrate and the second redistribution substrate and sealing the first semiconductor chip; as well as a second encapsulant disposed on the second redistribution substrate and encapsulating the semiconductor device and the second semiconductor chip, The top surface of the semiconductor device and the top surface of the second semiconductor chip are exposed from the second sealant.

16. The semiconductor package according to claim 13, wherein The semiconductor device is a high bandwidth memory package, and The first semiconductor chip and the second semiconductor chip are logic chips.

17. A method for manufacturing a semiconductor package, the method comprising: forming an upper redistribution substrate on the first carrier substrate; attaching a semiconductor device and a top semiconductor chip to the first surface of the upper redistribution substrate; attaching a bottom semiconductor chip to a second surface of the upper redistribution substrate opposite the first surface; forming a lower redistribution substrate on the bottom semiconductor chip; as well as Attach the passive components and external connection terminals to the lower redistribution substrate, The bottom semiconductor chip includes a through electrode.

18. The method of claim 17, before attaching the bottom semiconductor chip to a second surface of the upper redistribution substrate opposite to the first surface, further comprising: sealing the semiconductor device and the top semiconductor chip with an upper encapsulant; as well as grinding the upper encapsulant to expose the top surface of the semiconductor device and the top surface of the top semiconductor chip, The upper redistribution substrate, the semiconductor device, and the top semiconductor chip are flipped to attach the top surface of the semiconductor device and the top surface of the top semiconductor chip to the second carrier substrate such that the second surface of the upper redistribution substrate faces upward.

19. The method according to claim 17, in the step of attaching the bottom semiconductor chip to the second surface of the upper redistribution substrate opposite to the first surface, after forming through pillars on the second surface of the upper redistribution substrate except for the first portion where the bottom semiconductor chip is to be arranged, the bottom semiconductor chip is attached to the first portion.

20. The method according to claim 17, wherein The bottom semiconductor chip is attached to the second surface of the upper redistribution substrate through the second connection terminals, wherein the bottom semiconductor chip is electrically connected to the upper redistribution substrate via the second connection terminal, and The bottom semiconductor chip is electrically connected to the top semiconductor chip through the upper redistribution substrate and the second connection terminals.

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