Monolithic integrated device and preparation method thereof

Abstract

The invention provides a monolithic integrated device. The monolithic integrated device comprises a substrate layer; a high electron mobility transistor stack disposed on the substrate layer; and the laser diode lamination layer is arranged on one side of the high electron mobility transistor lamination layer. Wherein the laser diode lamination layer is multiplexed as a drain electrode of the high-electron-mobility transistor lamination layer, and the high-electron-mobility transistor lamination layer is multiplexed as a cathode of the laser diode lamination layer. The on-off control capability of the laser diode in a high-frequency, large-current and high-power application scene can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more specifically, to a monolithic integrated device and a method for manufacturing the same. Background Art

[0002] In optical communications, optoelectronic integrated systems, and high-power applications, laser diodes serve as light sources, and their performance directly impacts the efficiency and stability of the entire system. However, traditional laser diode driver circuits often utilize discrete components, resulting in large system size, low integration, and high power consumption, making it difficult to meet the demands of modern electronic devices for miniaturization, integration, and low power consumption. Furthermore, in high-frequency, high-current, and high-power applications, the switching control capability of the laser diode becomes a key factor limiting system performance. Summary of the Invention

[0003] In view of this, the present disclosure provides a monolithic integrated device and a method for preparing the same.

[0004] One aspect of the present disclosure provides a monolithic integrated device, comprising:

[0005] substrate layer;

[0006] A high electron mobility transistor stack is disposed on the substrate layer;

[0007] The laser diode stack is arranged on one side of the high electron mobility transistor stack.

[0008] The laser diode stack is multiplexed as the drain of the high electron mobility transistor stack, and the high electron mobility transistor stack is multiplexed as the cathode of the laser diode stack.

[0009] According to an embodiment of the present disclosure, the high electron mobility transistor stack includes a buffer layer, a channel layer, and a barrier layer sequentially stacked on the substrate layer, and a two-dimensional electron gas layer is formed between the channel layer and the barrier layer.

[0010] According to an embodiment of the present disclosure, the laser diode stack includes a lower contact layer, a lower confinement layer, a lower waveguide layer, a pre-well layer, an active layer, an upper waveguide layer, an electron blocking layer, an upper confinement layer, and an upper contact layer stacked in sequence on the high electron mobility transistor stack; or,

[0011] The laser diode stack includes a lower contact layer, a lower confinement layer, a lower waveguide layer, a pre-well layer, an active layer, an upper waveguide layer, an electron blocking layer, an upper confinement layer and an upper contact layer stacked in sequence from a portion of the channel layer.

[0012] According to an embodiment of the present disclosure, the semiconductor laser further includes:

[0013] a back electrode layer, disposed under the substrate layer;

[0014] A front electrode layer is provided on the laser diode stack and a portion of the high electron mobility transistor stack.

[0015] According to an embodiment of the present disclosure, the front electrode layer includes:

[0016] an anode, disposed on a portion of the laser diode stack and a portion of the high electron mobility transistor stack;

[0017] a gate, disposed on the other side of a portion of the high electron mobility transistor stack;

[0018] A source electrode is arranged on the laser diode stack and a portion of the high electron mobility transistor stack.

[0019] According to an embodiment of the present disclosure, the semiconductor laser further includes:

[0020] A current spreading layer is provided between the laser diode stack and the drain.

[0021] According to an embodiment of the present disclosure, the semiconductor laser further includes:

[0022] a passivation layer, disposed at a connection between the other side of a portion of the high electron mobility transistor stack and a portion of the laser diode stack;

[0023] The current spreading layer is disposed between the laser diode stack and a passivation layer located on the laser diode stack.

[0024] According to an embodiment of the present disclosure, the semiconductor laser further includes:

[0025] a high reflective layer, located on one side of the laser diode stack and the high electron mobility transistor stack; and / or,

[0026] an anti-reflection layer, arranged opposite to the high-reflection layer and located on the other side of the laser diode stack and the high electron mobility transistor stack;

[0027] Wherein, a resonant cavity is formed between the high reflection layer and the anti-reflection layer.

[0028] Another aspect of the present disclosure provides a method for preparing a monolithic integrated device, characterized by comprising:

[0029] preparing a high electron mobility transistor stack on the substrate layer;

[0030] A laser diode stack is prepared on one side of the high electron mobility transistor stack, so that the laser diode stack is reused as the drain of the high electron mobility transistor stack, and the high electron mobility transistor stack is reused as the cathode of the laser diode stack.

[0031] According to an embodiment of the present disclosure, the step of preparing a high electron mobility transistor stack on a substrate layer includes:

[0032] A buffer layer, a channel layer, and a barrier layer are sequentially formed on the substrate layer, wherein a two-dimensional electron gas layer is formed between the channel layer and the barrier layer;

[0033] The step of preparing a laser diode stack on one side of the high electron mobility transistor stack comprises:

[0034] A stacked lower contact layer, a lower confinement layer, a lower waveguide layer, a pre-well layer, an active layer, an upper waveguide layer, an electron blocking layer, an upper confinement layer and an upper contact layer are sequentially prepared on one side of the high electron mobility transistor stack.

[0035] According to the embodiments of the present disclosure, a monolithic integrated voltage-controlled LD device can be realized, and the laser power output by the LD can be controlled by the gate voltage, thereby effectively improving the LD switch control capability in high-frequency, high-current, and high-power application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0037] Figure 1 Schematically shows a structural diagram of a monolithic integrated device according to an embodiment of the present disclosure;

[0038] Figure 2 Schematically shows a structural diagram of a monolithic integrated device according to another embodiment of the present disclosure;

[0039] Figure 3 Schematically shows a schematic structural diagram of an LD stack according to an embodiment of the present disclosure;

[0040] Figure 4 Schematically shows an equivalent circuit diagram of a monolithic integrated device provided according to an embodiment of the present disclosure;

[0041] Figure 5 Schematically shows the position diagram of cavity surface coating according to an embodiment of the present disclosure;

[0042] Figure 6 A flow chart schematically illustrates a method for preparing a monolithic integrated device according to an embodiment of the present disclosure;

[0043] Figure 7A A flow chart schematically illustrates a method for preparing a monolithic integrated device according to another embodiment of the present disclosure;

[0044] Figure 7B A schematic diagram schematically illustrates a method for preparing a monolithic integrated device according to another embodiment of the present disclosure;

[0045] Figure 8A A flow chart schematically illustrates a method for preparing a monolithic integrated device according to another embodiment of the present disclosure;

[0046] Figure 8B A schematic diagram schematically illustrates a method for preparing a monolithic integrated device according to yet another embodiment of the present disclosure;

[0047] Figure 9A A flow chart schematically illustrates a method for preparing a monolithic integrated device according to another embodiment of the present disclosure;

[0048] Figure 9B A schematic diagram schematically illustrates a method for preparing a monolithic integrated device according to yet another embodiment of the present disclosure;

[0049] Description of reference numerals:

[0050] 1- substrate layer;

[0051] 2-Layered structure;

[0052] 21-HEMT stack; 211-buffer layer, 212-channel layer, 213-two-dimensional electron gas layer, 214-barrier layer;

[0053] 22-LD stack; 221-lower contact layer, 222-lower confinement layer, 223-lower waveguide layer, 224-prewell layer, 225-active layer, 226-upper waveguide layer, 227-electron blocking layer, 228-upper confinement layer, 229-upper contact layer;

[0054] 3-current spreading layer and metal electrode;

[0055] 31-current spreading layer;

[0056] 32-metal electrode; 321-anode, 322-gate, 323-source;

[0057] 4-passivation layer;

[0058] 51-antireflection layer;

[0059] 52-High reflective layer. DETAILED DESCRIPTION

[0060] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0061] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0062] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0063] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0064] Lasers are widely used in a wide range of fields, including laser displays, laser televisions, laser projectors, communications, medical treatment, weaponry, guidance, rangefinders, spectral analysis, cutting, precision welding, and high-density optical storage. Depending on the working medium, lasers can be categorized as solid, gas, liquid, dye, and semiconductor. Compared to other types of lasers, all-solid-state semiconductor lasers offer advantages such as small size, high efficiency, light weight, excellent stability, long life, and compact structure.

[0065] Group III nitrides, represented by gallium nitride, are direct-transition wide-bandgap semiconductors, ideal for laser devices operating in wavelengths from the ultraviolet to green and even red. The output power of a single nitride laser can reach several watts, but high-frequency switching control requires complex and fragile external circuitry. This not only increases control system costs and reduces overall system lifespan, but also makes higher-frequency control difficult. This significantly limits the application of nitride lasers in high-frequency, high-current, and high-power scenarios.

[0066] Figure 1The structure of a monolithic integrated device according to an embodiment of the present disclosure is schematically shown. Figure 2 The figure schematically shows a structural diagram of a monolithic integrated device according to another embodiment of the present disclosure.

[0067] like Figure 1 and Figure 2 As shown, the monolithic integrated device includes: a substrate layer 1 and a stacked structure 2. The stacked structure 2 includes a high electron mobility transistor (HEMT) stacked layer 21 and a laser diode (LD) stacked layer 22.

[0068] The HEMT stack 21 is provided on the substrate layer 1. The LD stack 22 is provided on one side of the HEMT stack 21. The LD stack 22 is multiplexed as the drain of the HEMT stack 21, and the HEMT stack 21 is multiplexed as the cathode of the LD stack 22.

[0069] The substrate 1 may be one of a sapphire substrate, a silicon substrate, a gallium nitride substrate, a silicon carbide substrate, a diamond substrate, a patterned substrate formed based on the above substrates, and an AlN composite substrate, but is not limited thereto.

[0070] HEMT stacked structure 21 includes a buffer layer 211, a channel layer 212, and a barrier layer 214 stacked sequentially on the surface of substrate 1. A two-dimensional electron gas layer 213 is formed between channel layer 212 and barrier layer 214. Two-dimensional electron gas layer 213 is a thin layer of highly concentrated electrons that forms at a high speed at the heterojunction between different Group III nitrides. The region where two-dimensional electron gas layer 213 is located has low resistivity and good electron transport.

[0071] The buffer layer 211 may be made of, but is not limited to, one or a combination of GaN, AlN, AlGaN, InGaN, and AlInGaN. The buffer layer 211 is used to adjust material properties such as dislocations and stress in the epitaxial layer. The channel layer 212 may be made of, but is not limited to, GaN. The barrier layer 214 may be made of, but is not limited to, one or a combination of AlN, AlGaN, InGaN, and AlInN.

[0072] The thickness of the buffer layer 211 may be in the range of 50-5000 nm, the thickness of the channel layer 212 may be in the range of 20-2000 nm, and the thickness of the barrier layer 214 may be in the range of 5-50 nm, but are not limited thereto.

[0073] Figure 3 Schematically shows the embodiment of the present disclosure Figure 1 and Figure 2 Schematic diagram of the structure of the LD stack.

[0074] like Figure 3 As shown, the LD stack 22 includes a lower contact layer 221 , a lower confinement layer 222 , a lower waveguide layer 223 , a prewell layer 224 , an active layer 225 , an upper waveguide layer 226 , an electron blocking layer 227 , an upper confinement layer 228 and an upper contact layer 229 .

[0075] In one embodiment, reference Figure 1 The LD stack 22 is disposed on the barrier layer 214. The barrier layer 214 is in direct contact with the lower contact layer 221. The two-dimensional electron gas layer 213 forms a current path through the barrier layer 214 and the lower contact layer 221, forming the cathode of the LD stack 22. The lower contact layer 221 forms the drain of the HEMT stack 21.

[0076] In yet another embodiment, referring to Figure 2 The LD stack 22 is disposed on the channel layer 212 , and the two-dimensional electron gas layer 213 contacts the lower contact layer 221 on the side of the LD stack, forming a current path and constituting the cathode of the LD stack 22 . The lower contact layer 221 constitutes the drain of the HEMT stack 21 .

[0077] The lower contact layer 221 may be made of one or a combination of two or more of GaN and InGaN, but not limited thereto, and has n-type doping. The dopant may be Si, but not limited thereto, and the doping concentration may be between 1×10 18 cm -3 ~1×10 20 cm -3 The lower contact layer 221 is used to form a good electrical contact with the HEMT stack 21 .

[0078] The lower confinement layer 222 may be made of one or a combination of two or more of GaN and AlGaN, but not limited thereto, and has n-type doping. The dopant may be Si, but not limited thereto, and the doping concentration may be between 1×10 17 cm -3 ~1×10 19 cm -3 scope, but not limited to this.

[0079] The lower waveguide layer 223 can be made of one or more of GaN and InGaN, but is not limited thereto. The lower waveguide layer 223 can be undoped or n-type doped, and the dopant can be Si, but is not limited thereto. The doping concentration can be between 1×10 16 cm -3 ~1×10 18 cm -3The refractive index of the lower limiting layer 222 is lower than that of the lower waveguide layer 223. The lower limiting layer 222 cooperates with the lower waveguide layer 223 to form a total reflection interface for the signal light, thereby limiting the propagation of the optical signal in the waveguide layer and achieving an optical gain effect.

[0080] The pre-well layer 224 may be a combination of GaN and InGaN, but is not limited thereto. The pre-well layer 224 may be undoped or n-type doped, and the dopant may be Si, but is not limited thereto. The doping concentration may be between 1×10 16 cm -3 ~1×10 18 cm -3 The pre-well layer 224 may have a single quantum well structure or a multi-quantum well structure. Compared to a single quantum well structure, a multi-quantum well structure can more easily regulate dislocations and stresses in the epitaxial layer, providing a better growth environment for the active layer 225, improving the material quality of the active layer 225, and thereby improving the optoelectronic and structural performance of the laser. The active layer 225 may be a combination of GaN and InGaN, but is not limited thereto.

[0081] The active layer 225 has a single quantum well structure or a multi-quantum well structure. Compared with the single quantum well structure, the multi-quantum well structure is more likely to obtain sufficient gain.

[0082] The upper waveguide layer 226 can be made of one or more of GaN and InGaN, but is not limited thereto. The upper waveguide layer 226 can be undoped or p-type doped, and the dopant can be Mg, but is not limited thereto. The doping concentration can be between 1×10 17 cm -3 ~1×10 19 cm -3 scope, but not limited to this.

[0083] The electron blocking layer 227 may be made of one or a combination of two or more of GaN and AlGaN, but is not limited thereto, and has p-type doping. The dopant may be Mg, but is not limited thereto, and the doping concentration may be between 1×10 18 cm -3 ~1×10 20 cm -3 The electron blocking layer 227 is used to block electrons from the cathode of the laser through the active layer 225 and the upper waveguide layer 226, thereby preventing excessive consumption of holes injected into the anode 321 through the current spreading layer 31 and the upper confinement layer 228. Furthermore, the electron blocking layer 227 is disposed between the upper waveguide layer 226 and the upper confinement layer 228 to prevent excessive light absorption and loss caused by the electron blocking layer 227 being disposed between the active layer 225 and the upper waveguide layer 226.

[0084] The upper confinement layer 228 may be made of one or a combination of two or more of GaN and AlGaN, but is not limited thereto, and has p-type doping. The dopant may be Mg, but is not limited thereto, and the doping concentration may be between 1×10 18 cm -3 ~1×10 20 cm -3 The upper confinement layer 228 has a lower refractive index than the upper waveguide layer 226. The upper waveguide layer 226, the electron blocking layer 227 and the upper confinement layer 228 cooperate to form a total reflection interface for the signal light, thereby limiting the propagation of the optical signal within the waveguide layer and achieving an optical gain effect.

[0085] The upper contact layer 229 may be made of one or a combination of two or more of GaN and InGaN, but is not limited thereto, and has p-type doping. The dopant may be Mg, but is not limited thereto, and the doping concentration may be between 1×10 19 cm -3 ~4×10 20 cm -3 The upper contact layer 229 is used to form a good electrical contact with the current spreading layer 31 .

[0086] Optionally, the thickness of the lower contact layer 221 may be in the range of 10~500nm, the thickness of the lower confinement layer 222 may be in the range of 100~2000nm, the thickness of the lower waveguide layer 223 may be in the range of 30~300nm, the thickness of the pre-well layer 224 may be in the range of 5~50nm, the thickness of the active layer 225 may be in the range of 5~50nm, the thickness of the upper waveguide layer 226 may be in the range of 30~300nm, the thickness of the electron blocking layer 227 may be in the range of 5~50nm, the thickness of the upper confinement layer 228 may be in the range of 100~1000nm, and the thickness of the upper contact layer 229 may be in the range of 5~50nm, but is not limited thereto.

[0087] like Figure 1 and Figure 2As shown, a current spreading layer and metal electrode 3 are provided on the other side of the LD stack 22 and HEMT stack 21. The current spreading layer and metal electrode 3 comprise a current spreading layer 31 and a metal electrode 32; the metal electrode 32 comprises an anode 321, a gate 322, and a source 323. The current spreading layer 31 forms a good ohmic contact with the upper contact layer 229 located in the upper middle portion of the LD stack 22. The low resistivity of the current spreading layer 31 facilitates better diffusion of holes injected from the drain electrode 321, thereby improving current uniformity within the LD stack 22 and enhancing the performance of the monolithic integrated device. The current spreading layer 31 can be composed of, but is not limited to, transparent conductive materials such as ITO, IZO, or ZnO, and metals such as Ni, Pt, Pd, Ti, Al, Cr, Ag, and Au. Its thickness can range from 20 to 500 nm, but is not limited to this.

[0088] like Figure 1 and Figure 2 As shown, a passivation layer 4 can be provided on the HEMT stack 21 and the LD stack 22. The passivation layer 4 is provided at the junction between a portion of the HEMT stack 21 and a portion of the LD stack 22. In other words, the passivation layer 4 covers the sidewalls of the LD stack 22 and a portion of the HEMT stack 21 and the LD stack 22. The passivation layer 4 is used to passivate the sidewalls of the LD stack 22, reducing the impact of surface states on the luminescence of the active layer 225 and the propagation of optical signals in the lower waveguide layer 223 and the upper waveguide layer 226. The passivation layer 4 can be composed of a single layer or a multilayer of a material such as an oxide or nitride of Si, Al, Zr, Ti, Nb, or Ta, but is not limited thereto. The thickness can be between 50 and 500 nm, but is not limited thereto.

[0089] like Figure 1 and Figure 2As shown, an anode 321 can be disposed above the current spreading layer 31 and the passivation layer 4, and a gate 322 and a source 323 can be disposed above the HEMT stack 21. The anode 321 can be composed of, but not limited to, one or more of Ni, Pt, Pd, Ti, Al, Cr, Ag, and Au, and has a thickness of 50 to 5000 nm. The anode 321 forms a good ohmic contact with the current spreading layer 31, thereby providing holes for the LD stack 22. The gate 322 can be composed of, but not limited to, one or more of a metal Schottky gate, a metal / insulator gate, and a metal / p-type semiconductor gate. Different gates 322 can provide different electrical properties for the HEMT stack 21. Using a metal Schottky gate or a metal / insulator gate can form a normally-on or depletion-mode HEMT. When the voltage applied to the gate 322 is zero, the two-dimensional electron gas layer 213 beneath the gate 322 remains, and the HEMT stack 21 can continue to conduct normally. Using a metal / p-type semiconductor gate, a normally-off or enhanced-mode HEMT can be formed. When the voltage applied to the gate 322 is 0, the two-dimensional electron gas layer 213 under the gate 322 is depleted, and the HEMT stack 21 cannot conduct and is in the cut-off state. The metal in the gate 322 can be composed of one or more of Ni, Pt, Pd, Ti, Al, Cr, Ag, Au, but not limited thereto, with a thickness of 50~5000nm. The insulating layer in the gate 322 can be a single layer or multilayer film of oxides or nitrides of materials such as Si, Al, Zr, Ti, Nb, Ta, etc., but not limited thereto, with a thickness of 1~100nm, but not limited thereto. The p-type semiconductor in the gate 322 can be GaN, but not limited thereto, and has p-type doping. The dopant can be Mg, but not limited thereto, and the doping concentration can be between 1×10 19 cm -3 ~4×10 20 cm -3 The thickness of the source electrode 323 may be within the range of, but not limited to, 1 to 100 nm. The source electrode 323 may be composed of, but not limited to, one or more of Ni, Pt, Pd, Ti, Al, Cr, Ag, and Au, with a thickness of 50 to 5000 nm. The source electrode 323 is used to form a good ohmic contact with the HEMT stack structure 21.

[0090] Figure 4 The equivalent circuit diagram of the monolithic integrated device provided by the embodiment of the present disclosure is schematically shown.

[0091] like Figure 4As shown, HEMT stack 21 can be understood as a HEMT device within a monolithic integrated device, and LD stack 22 can be understood as an LD device within a monolithic integrated device. HEMT stack 21 drives LD stack 22 to emit light. Using HEMT stack 21 to drive LD stack 22 eliminates the need for an additional drive unit, effectively reducing the size of the integrated device, reducing parasitic capacitance of external circuits, and improving device performance and reliability.

[0092] Figure 5 The side structural diagram of the monolithic integrated device provided by the embodiment of the present disclosure is schematically shown.

[0093] like Figure 5 As shown, Figure 5 The side surface is parallel to Figure 1 and Figure 2 The structural diagram is shown below. The left and right sides of the substrate layer 1 and the stacked structure 2 can be coated with an anti-reflection layer 51 and a high-reflection layer 52, respectively, to enhance the performance of the laser. The cavity surface coated with the anti-reflection layer 51 is the laser emission end face, and the cavity surface coated with the high-reflection layer 52 is the far end of the laser emission direction. The anti-reflection layer 51 can be composed of a single layer or a multilayer film of materials such as oxides or nitrides of Si, Al, Zr, Ti, Nb, Ta, etc., but is not limited thereto, and the thickness can be 5~5000nm, but is not limited thereto. The high-reflection layer 52 can be composed of a single layer or a multilayer film of materials such as oxides or nitrides of Si, Al, Zr, Ti, Nb, Ta, etc., but is not limited thereto, and the thickness can be 5~5000nm, but is not limited thereto.

[0094] The monolithic integrated device provided by the present disclosure may also include any structure known to those skilled in the art, and the embodiments of the present disclosure are not limited thereto.

[0095] This disclosure does not limit the specific fabrication processes for HEMT stack 21 and LD stack 22; those skilled in the art may configure these processes based on practical needs. By way of example, several possible monolithic device fabrication processes and methods are described below. This disclosure does not limit the specific fabrication processes and corresponding process parameters used in each process; those skilled in the art may configure these processes based on practical needs.

[0096] Figure 6 The flowchart of the method for preparing a monolithic integrated device according to an embodiment of the present disclosure is schematically shown.

[0097] like Figure 6 As shown, the method includes operations S610 to S620.

[0098] In operation S610 , a high electron mobility transistor stack is prepared on a substrate layer.

[0099] In operation S620 , a laser diode stack is prepared on one side of the high electron mobility transistor stack.

[0100] According to an embodiment of the present disclosure, the laser diode stack is multiplexed as the drain of the high electron mobility transistor stack, and the high electron mobility transistor stack is multiplexed as the cathode of the laser diode stack.

[0101] In some embodiments, preparing a high electron mobility transistor stack on the substrate layer includes:

[0102] A buffer layer, a channel layer, and a barrier layer are sequentially formed on the substrate layer, wherein a two-dimensional electron gas layer is formed between the channel layer and the barrier layer;

[0103] In some embodiments, preparing a laser diode stack on one side of the high electron mobility transistor stack comprises:

[0104] A stacked lower contact layer, a lower confinement layer, a lower waveguide layer, a pre-well layer, an active layer, an upper waveguide layer, an electron blocking layer, an upper confinement layer and an upper contact layer are sequentially prepared on one side of the high electron mobility transistor stack.

[0105] In some embodiments, the method further includes: preparing a back electrode layer under the substrate layer; and preparing a front electrode layer on the laser diode stack and a portion of the high electron mobility transistor stack.

[0106] In some embodiments, preparing a front electrode layer on the laser diode stack and a portion of the high electron mobility transistor stack includes: preparing an anode on a portion of the laser diode stack and a portion of the high electron mobility transistor stack; preparing a gate on the other side of a portion of the high electron mobility transistor stack; and preparing a source on the laser diode stack, the passivation layer, and a portion of the high electron mobility transistor stack.

[0107] It can be understood that when the semiconductor laser also includes a passivation layer, preparing a front electrode layer on the laser diode stack and part of the high electron mobility transistor stack includes: preparing an anode on part of the laser diode stack and part of the passivation layer; preparing a gate on the other side of part of the high electron mobility transistor stack; and preparing a source on part of the high electron mobility transistor stack.

[0108] In some embodiments, the method further comprises: preparing a current spreading layer between the laser diode stack and the anode.

[0109] In some embodiments, the method further includes: providing a passivation layer at a connection from the other side of a portion of the high electron mobility transistor stack to a portion of the laser diode stack, and a current spreading layer is provided between the laser diode stack and the passivation layer located on the laser diode stack.

[0110] In some embodiments, the method further includes: preparing a high-reflection layer on one side of the laser diode stack and the high electron mobility transistor stack; and / or preparing an anti-reflection layer on the other side of the laser diode stack and the high electron mobility transistor stack, which is arranged opposite to the high-reflection layer; wherein a resonant cavity is formed between the high-reflection layer and the anti-reflection layer.

[0111] Figure 7A The flowchart of the method for preparing a monolithic integrated device according to an embodiment of the present disclosure is schematically shown. Figure 7B A schematic diagram schematically illustrates a method for preparing a monolithic integrated device according to an embodiment of the present disclosure.

[0112] like Figure 7A As shown, the method includes operations S11 to S18.

[0113] In operation S11, a substrate is obtained. Referring to FIG. 7B (a), the arrangement of the substrate 1 can refer to the above embodiment and will not be repeated here.

[0114] In operation S12, a buffer layer, a channel layer, a barrier layer, and a laser structure layer are sequentially grown on the upper surface of the substrate from bottom to top. Referring to FIG. 7B (b), the buffer layer 211, the channel layer 212, and the barrier layer 214 constitute the HEMT stack structure 21, with a two-dimensional electron gas layer 213 existing at the interface between the channel layer 212 and the barrier layer 214. The laser structure layer is the LD stack structure 22, comprising a lower contact layer 221, a lower confinement layer 222, a lower waveguide layer 223, a pre-well layer 224, an active layer 225, an upper waveguide layer 226, an electron blocking layer 227, an upper confinement layer 228, and an upper contact layer 229. The lower contact layer 221 is in direct contact with the barrier layer 214, so that the LD stack structure 22 constitutes the source of the HEMT stack structure 21, and the HEMT stack structure 21, in turn, constitutes the cathode of the LD stack structure 22. Optionally, the HEMT stacked structure 21 and the LD stacked structure 22 may be fabricated by metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), but are not limited thereto.

[0115] In operation S13, a current spreading layer is grown on the upper surface of the laser structure layer. See (c) in FIG. 7B . Alternatively, the current spreading layer 31 may be formed by MOCVD, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or magnetron sputtering, but is not limited thereto.

[0116] In operation S14, the current expansion layer and the laser structure layer in a partial area are etched to form a laser strip structure. Refer to (d) in Figure 7 B. The etching process may include a photolithography process and an etching process. Furthermore, the photolithography process may include processes such as coating, baking, exposure, development, and degumming; the etching process may be a dry etching process, such as inductively coupled plasma dry etching ICP and reactive ion beam etching RIE, but is not limited thereto. The laser strip structure is perpendicular to Figure 1 and Figure 2 The present disclosure does not limit the specific dimensions of the side shown, and those skilled in the art can set them according to actual needs.

[0117] In operation S15, a passivation layer is grown on the etched laser stripe structure mesa and a portion of the barrier layer surface near it. Figure 7B Optionally, the passivation layer 4 can be prepared by PVD, CVD, PECVD, or atomic layer deposition ALD, but is not limited thereto.

[0118] In operation S16, metal electrodes are prepared on partial areas of the surface of the laser structure and the barrier layer to form a laser anode, gate and source. Refer to (f) in Figure 7 B. Optionally, the anode 321, the gate 322 and the source 323 can be prepared by magnetron sputtering, thermal evaporation, or electron beam evaporation, but are not limited thereto. Furthermore, after each metal electrode is prepared, it can also be annealed. After annealing, the metal electrode can form a good ohmic contact with the adjacent semiconductor material layer.

[0119] In operation S17, the wafer is cleaved or etched at both ends of the laser structure to form resonant cavity surfaces. Wafer cleavage utilizes the property of a crystalline substrate, under the action of external forces, to split into smooth planes along a specific crystallographic direction due to its crystal structure. The smooth planes formed are cleavage planes, which serve as the resonant cavity surfaces of the laser in this disclosure. Etching can be dry etching, and the sidewalls formed by etching should be smooth and straight, otherwise it will increase laser optical loss and reduce output laser power.

[0120] In operation S18, a high-reflection film and an anti-reflection film are coated on the resonant cavity surface to form a cavity surface coating. Optionally, the anti-reflection layer 51 and the high-reflection layer 52 can be prepared by PVD, CVD, PECVD, or atomic layer deposition ALD, but are not limited thereto.

[0121] Figure 8A The flowchart of a method for preparing a monolithic integrated device according to another embodiment of the present disclosure is schematically shown. Figure 8B The figure schematically shows a method for preparing a monolithic integrated device according to another embodiment of the present disclosure.

[0122] like Figure 8A As shown, the preparation method includes operations S21-S27.

[0123] In operation S21, a substrate is obtained, on the upper surface of which a HEMT structure is prepared, that is, including a buffer layer, a channel layer and a barrier layer. Figure 8B In (a), the substrate comprises substrate 1 and HEMT stack structure 21. HEMT stack structure 21 comprises a buffer layer 211, a channel layer 212, a barrier layer 214, and a two-dimensional electron gas layer 213 formed between the channel layer 212 and the barrier layer 214. This substrate configuration allows for the growth of HEMT stack structure 21 and LD stack structure 22 in two stages, leveraging the growth advantages of different growth platforms, such as MOCVD, while also taking into account the availability of commercial substrates to improve production efficiency.

[0124] In operation S22, a laser structure layer is grown on a portion of the upper surface of the barrier layer to form a laser stripe structure. Figure 8B (b) in the figure, wherein the laser structure layer is the above-mentioned LD stack structure 22, including a lower contact layer 221, a lower confinement layer 222, a lower waveguide layer 223, a pre-well layer 224, an active layer 225, an upper waveguide layer 226, an electron blocking layer 227, an upper confinement layer 228 and an upper contact layer 229. Optionally, the growth of the LD stack structure 22 in the above-mentioned partial area can be carried out by selective epitaxy. The above-mentioned LD stack structure 22 can be prepared by MOCVD or MBE, but is not limited thereto. Specifically, the selective epitaxy can be achieved by covering the side of the barrier layer 214 that is not the LD stack structure 22 with a mask. The mask can be a single layer or a multilayer film of a material such as an oxide or nitride of Si, Al, Zr, Ti, Nb, Ta, etc., but is not limited thereto. The corresponding thickness can be set by those skilled in the art according to actual needs.

[0125] In operation S23, a current spreading layer is grown on the upper surface of the laser structure layer. Figure 8B(c) in the figure. Optionally, the current spreading layer 31 on the surface of the LD stack structure 22 can be grown by selective growth. The current spreading layer 31 can be prepared by MOCVD, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or magnetron sputtering, but is not limited thereto. Specifically, selective growth can be achieved by covering the side of the barrier layer 214 that is not the LD stack structure 22 with a mask. The mask can be a single layer or a multilayer film of a material such as an oxide or nitride of Si, Al, Zr, Ti, Nb, or Ta, but is not limited thereto. The corresponding thickness can be set by those skilled in the art according to actual needs.

[0126] In operation S24, a passivation layer is grown on the laser stripe structure mesa and a portion of the barrier layer surface near the laser stripe structure mesa. Figure 8B Optionally, the passivation layer 4 can be prepared by PVD, CVD, PECVD, or atomic layer deposition ALD, but is not limited thereto.

[0127] In operation S25, metal electrodes are prepared on the surface of the laser structure and the barrier layer to form the laser anode, gate and source. Figure 8B (e) in the figure. Optionally, the anode 321, the gate 322, and the source 323 can be prepared by magnetron sputtering, thermal evaporation, or electron beam evaporation, but are not limited thereto. Furthermore, after each metal electrode is prepared, it can be annealed. After annealing, the metal electrode can form a good ohmic contact with the adjacent semiconductor material layer.

[0128] In operation S26, the wafer is cleaved or etched at both ends of the laser structure to form resonant cavity surfaces. Wafer cleavage utilizes the property of a crystalline substrate, under the action of external forces, to split into smooth planes along a specific crystallographic direction due to its crystal structure. The resulting smooth planes are cleaved planes, which serve as the resonant cavity surfaces of the laser in this disclosure. Etching can be dry etching, and the resulting sidewalls must be smooth and straight; otherwise, this will increase laser optical loss and reduce output laser power.

[0129] In operation S27 , the wafer is cleaved or etched at both ends of the laser structure to form resonant cavity surfaces. Optionally, the anti-reflection layer 51 and the high-reflection layer 52 can be prepared by PVD, CVD, PECVD, or atomic layer deposition (ALD), but are not limited thereto.

[0130] Figure 9A The flowchart of a method for preparing a monolithic integrated device according to another embodiment of the present disclosure is schematically shown. Figure 9B The figure schematically shows a method for preparing a monolithic integrated device according to another embodiment of the present disclosure.

[0131] like Figure 9A As shown, the preparation method includes operations S31-S38.

[0132] In operation S31, a substrate is obtained, on the upper surface of which a HEMT structure is prepared, that is, including a buffer layer, a channel layer and a barrier layer. Figure 9B In (a), the arrangement of the substrate 1 and the HEMT stacked structure can refer to the above embodiment and will not be repeated here.

[0133] In operation S32, a portion of the upper surface of the barrier layer is etched to form a groove in the corresponding area of the channel layer. Figure 9B (b) in FIG. Optionally, the etching may be a dry etching process, such as inductively coupled plasma dry etching (ICP) and reactive ion beam etching (RIE), but is not limited thereto. The etching process may remove a portion of the thickness of the barrier layer 214 in a partial region, or the entire thickness of the barrier layer 214 in a partial region, or the entire thickness of the barrier layer 214 and a portion of the thickness of the channel layer 212 in a partial region. If a portion of the thickness of the barrier layer 214 in a partial region is removed, a certain concentration of the two-dimensional electron gas layer 213 still exists between the channel layer 212 and the remaining thickness of the barrier layer 214. The contact between the lower contact layer 221 of the LD stack structure 22 and the two-dimensional electron gas layer 213 becomes better due to the reduced thickness of the barrier layer 214.

[0134] By adjusting the depth of removal of the barrier layer 214 and the channel layer 212, different electrical contacts can be achieved between the LD stack structure 22 and the HEMT stack structure 21 obtained by secondary epitaxy within this region, thereby achieving different performance characteristics of the monolithic integrated device. This disclosure does not specifically limit the depth of this etching process; those skilled in the art may adjust it based on actual needs.

[0135] In operation S33, a laser structure layer is grown on the upper surface of the groove area to form a laser stripe structure. Figure 9B (c) in the figure. The laser structure layer is the aforementioned LD stack structure 22, comprising a lower contact layer 221, a lower confinement layer 222, a lower waveguide layer 223, a pre-well layer 224, an active layer 225, an upper waveguide layer 226, an electron blocking layer 227, an upper confinement layer 228, and an upper contact layer 229. Lower contact layer 221 is in direct contact with barrier layer 214 or channel layer 212, so that LD stack structure 22 constitutes the source of HEMT stack structure 21, which in turn constitutes the cathode of LD stack structure 22. Alternatively, LD stack structure 22 may be fabricated by metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), but is not limited thereto.

[0136] In operation S34, a current spreading layer is grown on the upper surface of the laser structure layer. Figure 9BThe configuration of the current spreading layer 31 can refer to the above embodiment and will not be described in detail here.

[0137] In operation S35, a passivation layer is grown on the laser stripe structure mesa and a portion of the barrier layer surface near the laser stripe structure mesa. Figure 9B Optionally, the passivation layer 4 can be prepared by PVD, CVD, PECVD, or atomic layer deposition ALD, but is not limited thereto.

[0138] In operation S36, metal electrodes are formed on the laser structure and the surface of the barrier layer to form the laser anode, gate and source. The arrangement of the anode 321, gate 322 and source 323 can refer to the above embodiment and will not be repeated here.

[0139] In operation S37, the wafer is cleaved or etched at both ends of the laser structure to form resonant cavity faces. The configuration of the wafer cleavage or etching can refer to the above embodiment and will not be repeated here.

[0140] In operation S38, a high-reflection film and an anti-reflection film are coated on the resonant cavity surface to form a cavity surface coating. The arrangement of the anti-reflection layer 51 and the high-reflection layer 52 can refer to the above embodiment and will not be repeated here.

[0141] In the monolithic integrated device fabricated using the above-described fabrication method, the drain of the HEMT stack 22 and the cathode of the LD stack 21 are reused, thereby realizing a monolithic integrated voltage-controlled LD device. A relatively low gate voltage can be used to control the current intensity between the source and drain of the HEMT stack 22, thereby controlling the laser power output by the LD. This effectively improves the LD switching control capability in high-frequency, high-current, and high-power application scenarios.

[0142] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A monolithic integrated device, characterized in that: include: substrate layer; A high electron mobility transistor stack is disposed on the substrate layer; a laser diode stack, disposed on one side of the high electron mobility transistor stack; The laser diode stack is multiplexed as the drain of the high electron mobility transistor stack, and the high electron mobility transistor stack is multiplexed as the cathode of the laser diode stack.

2. The monolithic integrated device according to claim 1, wherein: The high electron mobility transistor stack includes a buffer layer, a channel layer, and a barrier layer stacked in sequence on the substrate layer, and a two-dimensional electron gas layer is formed between the channel layer and the barrier layer.

3. The monolithic integrated device according to claim 2, wherein: The laser diode stack includes a lower contact layer, a lower confinement layer, a lower waveguide layer, a pre-well layer, an active layer, an upper waveguide layer, an electron blocking layer, an upper confinement layer and an upper contact layer stacked in sequence on the high electron mobility transistor stack; or, The laser diode stack includes a lower contact layer, a lower confinement layer, a lower waveguide layer, a pre-well layer, an active layer, an upper waveguide layer, an electron blocking layer, an upper confinement layer and an upper contact layer stacked in sequence from a portion of the channel layer.

4. The monolithic integrated device according to claim 1, wherein: The semiconductor laser further comprises: a back electrode layer, disposed under the substrate layer; A front electrode layer is provided on the laser diode stack and a portion of the high electron mobility transistor stack.

5. The monolithic integrated device according to claim 4, wherein: The front electrode layer comprises: an anode, disposed on a portion of the laser diode stack and a portion of the high electron mobility transistor stack; a gate, disposed on the other side of a portion of the high electron mobility transistor stack; A source electrode is arranged on the laser diode stack and a portion of the high electron mobility transistor stack.

6. The monolithic integrated device according to claim 5, characterized in that: The semiconductor laser further comprises: A current spreading layer is provided between the laser diode stack and the anode.

7. The monolithic integrated device according to claim 6, wherein: The semiconductor laser further comprises: a passivation layer, disposed at a connection between the other side of a portion of the high electron mobility transistor stack and a portion of the laser diode stack; The current spreading layer is disposed between the laser diode stack and a passivation layer located on the laser diode stack.

8. The monolithic integrated device according to claim 1, wherein: The semiconductor laser further comprises: a high reflective layer, located on one side of the laser diode stack and the high electron mobility transistor stack; and / or, an anti-reflection layer, arranged opposite to the high-reflection layer and located on the other side of the laser diode stack and the high electron mobility transistor stack; Wherein, a resonant cavity is formed between the high reflection layer and the anti-reflection layer.

9. A method for preparing a monolithic integrated device, characterized in that: include: preparing a high electron mobility transistor stack on the substrate layer; A laser diode stack is prepared on one side of the high electron mobility transistor stack, so that the laser diode stack is reused as the drain of the high electron mobility transistor stack, and the high electron mobility transistor stack is reused as the cathode of the laser diode stack.

10. The method for preparing a monolithic integrated device according to claim 9, wherein: The step of preparing a high electron mobility transistor stack on a substrate layer comprises: A buffer layer, a channel layer, and a barrier layer are sequentially formed on the substrate layer, wherein a two-dimensional electron gas layer is formed between the channel layer and the barrier layer; The step of preparing a laser diode stack on one side of the high electron mobility transistor stack comprises: A stacked lower contact layer, a lower confinement layer, a lower waveguide layer, a pre-well layer, an active layer, an upper waveguide layer, an electron blocking layer, an upper confinement layer and an upper contact layer are sequentially prepared on one side of the high electron mobility transistor stack.

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