Gate drive circuit and method for switching semiconductor switches

Abstract

The invention relates to a gate drive circuit for switching a semiconductor switch and a switching method. A gate drive circuit (10) for switching a semiconductor switch (3) of an inverter (20) is provided, comprising an operating device (12) designed to alternate an electrical gate quantity (UGE, IG) between a maximum gate quantity value (UGE, max, IG, max) and a minimum gate quantity value (UGE, min, IG, min) in order to switch the semiconductor switch (3), the operating device (12) is further designed to adjust the maximum gate quantity value (UGE, max, IG, max) to an adjusted maximum gate quantity value (Umax, A, Imax, A) at an adjustment point in time during an operating interval (Top) in order to further alternate the electrical gate quantity (UGE, IG) between the adjusted maximum gate quantity value (UGE, max, A, IG, max, A) and the minimum gate quantity value (UGE, min, IG, min).

Description

Technical Field

[0001] The present invention relates to a gate drive circuit for driving an electric gate quantity present at a gate electrode of a semiconductor switch of an inverter, the gate drive circuit comprising an operating device designed to alternate the electric gate quantity between a maximum gate quantity value and a minimum gate quantity value during predefined operating intervals to switch the semiconductor switch to connect or disconnect a power supply voltage to an inverter output. The present invention also relates to an assembly of an inverter, a cable, and an electric load, the inverter being electrically connected to the electric load via the cable to supply the electric load. Furthermore, the present invention relates to a method for operating a gate drive circuit for driving an electric gate quantity present at a gate electrode of a semiconductor switch of an inverter. Background Art

[0002] In the design of modern power converters, people pay great attention to power conversion efficiency, power density and system cost. Recently, the reliability of power electronic systems has also received increasing attention, especially for systems that operate for long periods of time in harsh environments.

[0003] Another area of increasing concern in today's power electronics sector is the steadily increasing switching frequency. Significant progress has recently been made in this area, leading to new technologies such as so-called wide-bandgap switches ("WBG") that allow for fast switching capabilities of up to 10V / ns and higher, especially when compared to classical switching materials and / or classical switching technologies. Unfortunately, high switching speeds are still associated with adverse effects in the case of WBG, but even more so in the case of "conventional" semiconductors, such as conventional insulated-gate bipolar transistors (IGBTs), conventional metal-oxide-semiconductor field-effect transistors (MOSFETs), and the like. These adverse effects range from voltage overshoots and / or voltage ringing between the drain / emitter and source / collector of the switch to degraded electromagnetic interference (EMC) characteristics.

[0004] These problems are known in the prior art, see US 2019 / 0074827 A1, US 11,316,513 B2 or GB 2589296 A. Problems associated with high-speed switching of semiconductor switches, in particular IGBT switches, are also described in detail in the scientific literature.

[0005] “A four-step control for IGBT switching improvement using an active voltage gate driver,” Chen Li et al., Wiley, IET Power Electronics, 2021, for example, discloses a drive circuit and a corresponding method for switching an IGBT switch, which provides a step-by-step modification of the gate-source voltage in the process of changing the gate-source voltage from a minimum value to a maximum value to switch the IGBT, with the goal of reducing the overshoot of the gate-source voltage.

[0006] “A Voltage Controlled Current Source Gate Drive Method for IGBTDevices”, Lu Shu et al., IEEE, 2014, discloses a similar concept, in which different modification methods of the gate-source voltage are suggested depending on whether the gate-source voltage changes from minimum to maximum or from maximum to minimum.

[0007] Although the above-mentioned prior art discloses highly complex concepts aimed at improving the performance of semiconductor switches at high switching frequencies, it has been shown that these concepts do not maintain their performance over the entire operating range. Summary of the Invention

[0008] Against this background, the object of the present invention is to provide an improved gate drive circuit with reduced losses, allowing high consistency over the entire operating range of the switch or inverter driven by the gate drive circuit. Within the scope of the present invention, the term "gate drive circuit" should be interpreted broadly and generally refers to a circuit capable of switching a semiconductor switch, such as a BJT, IGBT or FET, as is known for example with different pins (BCE, GCE, GDS, respectively).

[0009] According to independent claim 1, for the gate drive circuit mentioned at the beginning, this object is achieved in the following way: the operating device is also designed to adjust the maximum gate magnitude to an adjusted maximum gate magnitude at an adjustment time point during the operating interval, so as to further cause the electric gate magnitude to alternate between the adjusted maximum gate magnitude and the minimum gate magnitude to switch the semiconductor switch.

[0010] By adjusting (i.e. reducing or increasing) the maximum gate magnitude, i.e. continuously switching the electrical gate magnitude to switch (i.e. open and close) the semiconductor switches, the switching behavior of the power semiconductors is modified. According to the considerations presented previously, the maximum gate magnitude can be increased in order to speed up the switching process, or the maximum gate magnitude can be reduced in order to slow down the switching process. As a result, a substantially constant EMC emission spectrum can be achieved over the entire operating range of the inverter. In addition, the switching losses are also reduced relative to a specific operating point. For example, at idling or low output currents, high capacitive motor cable currents can generally be reduced by slowly opening and closing the semiconductors. On the other hand, fast switching edges lead to reduced switching losses at high operating currents. Therefore, by adjusting the switching edges during operation, the present invention allows continuous operation at an optimal setting of the switching speed for switching the individual semiconductor switches.

[0011] Furthermore, for the assembly mentioned at the outset, the above object is achieved in that the inverter present in the assembly comprises at least one semiconductor switch and a gate drive circuit according to the invention.

[0012] In addition, for the method mentioned at the beginning, the above-mentioned purpose is achieved in the following manner: the method also includes the following steps: in a predefined operating interval during the operation of the inverter, the electric gate amount is alternating between a maximum gate amount value and a minimum gate amount value so as to switch the semiconductor switch, and at an adjustment time point during the operating interval, the maximum gate amount value is adjusted to an adjusted maximum gate amount value.

[0013] Furthermore, preferred embodiments of the gate driver circuit, the assembly and the method are subject matter of the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Refer to the following Figures 1 to 6 Describing the present invention in more detail, Figures 1 to 6 The exemplary and non-limiting advantageous embodiments of the present invention are shown by way of example. The specific examples described herein are intended only to illustrate the present invention and are not intended to limit the present embodiments. As shown below:

[0015] Figure 1 is the arrangement of gate driver circuits, inverters, cables and electrical loads,

[0016] Figure 2a 、 2b is a possible curve of the turn-on behavior of the IGBT collector-emitter voltage

[0017] Figure 3 are possible signals occurring in the gate driver circuit according to the present invention,

[0018] Figure 4 is an implementation of a switched resistor based gate driver circuit according to the present invention,

[0019] Figure 5 is an implementation of a gate driver circuit based on a push-pull converter according to the present invention,

[0020] Figure 6 is an advantageous implementation of a gate driver circuit employing feedback control according to the present invention. DETAILED DESCRIPTION

[0021] Figure 1 The diagram shows a gate driver circuit 10, an inverter 20 including two semiconductor (power) switches 3, a cable 30, an electrical load 40, a supply voltage U0, and input capacitors C1, C2. Each semiconductor switch 3 has a gate electrode G, a collector C, and an emitter E. Such circuits and possible ways of operating such circuits are known in the prior art, for example, see US Pat. No. 944,448 B2.

[0022] The purpose of the gate drive circuit 10 is to drive the gate charge U present at the gate electrode G of the semiconductor switch 3 of the inverter 20 GE , I G , so as to switch the semiconductor switch 3, and finally drive the electrical output current I of the inverter 20 through the cable 30 20 and / or electrical output voltage U 20 , supplying power to the load 40. To this end, the gate drive circuit 10 includes an operating device 12, which is designed to make the gate amount U GE , I G At the maximum gate value U GE,max , I G,max With the minimum gate value U GE,min , I G,min to switch the semiconductor switch 3.

[0023] The operating device 12 is also well known from the prior art and can itself comprise a semiconductor switch and, for example, a control unit to provide one or more control signals to switch the semiconductor switch 3, such as Figure 1 The possible implementation of the gate drive circuit 10, the operating device 12, etc. will be discussed in detail later. Figure 4 and Figure 5 As shown. Therefore, details about this aspect of the present invention are omitted for now. This will also be explained in detail later within the scope of the present invention. The semiconductor switch 3 is by no means limited to a specific type of semiconductor switch and can be implemented in the form of an insulated gate bipolar transistor IGBT, a bipolar junction transistor BJT or a field effect transistor FET.

[0024] Preferably, the electric gate quantity U GE , I GIt is the voltage dropped from the gate electrode G to the emitter electrode E, or the current flowing to or from the gate electrode G. GE , I G At the maximum gate value U GE,max , I G,max and minimum gate value U GE,min , I G,min The switch 3 is switched on by alternating between the gate-emitter region and the gate-emitter region (usually a positive gate-emitter voltage is applied to turn on the switch 3, and a negative gate-emitter region voltage is applied to turn off the switch 3). Several well-known operation methods can be used, such as pulse width modulation (PWM), pulse frequency modulation (PFM), etc., with the purpose of generating a pulsed electrical output current I with a predefined current-time region within a predefined time interval. 20 and / or a pulsed electrical output voltage U with a predefined voltage-time region 20 .like Figure 1 As shown, the basic principles of the operating circuit, in particular the implementation methods such as PWM, PFM, etc., are well known in the prior art, for example from US2019 / 0074827 A1, US 11,316,513 B2 or GB 2589296 A, and further details in this regard are omitted here.

[0025] In the course of the present invention, it was found that certain physical quantities, the most important of which is the above-mentioned electric gate quantity, namely the gate-emitter voltage U GE and / or gate current I G , in particular the maximum value for switching the corresponding semiconductor switch 3, has a crucial influence on the performance indicators of the gate drive circuit 10, such as (power) loss, EMC, output (such as U 20 and / or I 20 ) will be discussed below based on the dynamic and transient behavior of Figure 2a and Figure 2b Explain

[0026] to this end, Figure 2a First, the possible switching time t of the semiconductor switch 3 is given S The switching time (in the case shown for an IGBT) is the collector current I C It can be found that the time t required to switch the semiconductor switch 3, that is, to complete the transition from fully closed to fully open, is S As the collector current I drawn from the semiconductor switch 3 C However, due to various reasons, changing the switching time t SThis is problematic. On the one hand, for obvious reasons, large switching times and the resulting slow switching increase switching losses, as the switching process takes longer, resulting in longer periods of time in which the current flowing through the switch and the voltage drop across the switch are not equal to zero. On the other hand, small switching times and the resulting high switching speeds lead to rapid changes in the quantities involved, which in turn lead to increased electromechanical emissions and, in turn, worsen EMC performance. Therefore, the optimal switching time t is selected for a given application, taking into account the pros and cons of increasing or decreasing the switching time. S , and it is very important to maintain this switching time throughout the operation.

[0027] on the contrary, Figure 2b Shown as Figure 1 The inverter 20 shown has a gate-emitter voltage U GE The output voltage U generated at different maximum values 20 At a higher voltage, the gate charge required to switch the semiconductor switch 3 (in this case an IGBT) is applied more quickly, thus shortening the switching time t S Therefore, for the switching process, it can be said that when a larger gate-emitter voltage U GE When the switching time t S .

[0028] Combine Figure 2a and Figure 2b From the findings, it can be concluded that due to the collector current I C The switching speed change caused by the change can be adjusted by adjusting the gate power supply and thus adjusting the gate-emitter voltage U GE Therefore, by adjusting U GE To compensate for the higher operating current I C The switching time is increased to maintain the optimized switching time t S .

[0029] However, in the prior art, a permanent gate-emitter voltage with a constant maximum amplitude is typically employed, particularly when switching IGBT switches. Due to the fixed gate-emitter voltage, the switching behavior of the IGBT module is defined for a single, specific operating point. This leads to the aforementioned disadvantages under dynamic load profiles, such as voltage ringing between the drain and source of the power semiconductor switch, increased losses, and deteriorated electromagnetic interference (EMI) performance.

[0030] According to the present invention, in order to overcome these drawbacks and provide a gate drive circuit 10 that allows for greater consistency within the operating range of the inverter 20 driven thereby, the operating device 12 is further designed to operate the inverter 20 at a predefined operating interval T during operation. opAdjustment time point t A The maximum gate value U GE,max , I G,max Adjusted to the adjusted maximum gate value U max,A , I max,A , to further make the electric gate amount U GE , I G At the adjusted minimum gate magnitude U max,A , I max,A and the minimum gate magnitude U GE,min , I G,min To switch the semiconductor switch 3, the operation interval T op For example, it can be a user-selected interval or an interval selected in another way, where the maximum gate magnitude U max,A , I max,A Modification of the maximum gate magnitude U may be permitted according to the present invention. If modification of the maximum gate magnitude U is permitted at any time during operation max,A , I max,A , then the predefined operation interval T op Of course, it can also simply correspond to the on-time of the inverter 20. In addition, a plurality of operating intervals T can be provided during operation. op , in order to allow modification in certain selected time periods, such as only in low load conditions or only in high load conditions, etc. In addition, the operation interval T op The length of may of course vary, from just a few sampling intervals, such as 10, 50 or 100 sampling intervals, thus less than a second in length, to longer time periods, such as several minutes or hours in length, etc.

[0031] By setting the maximum gate value U max,A , I max,A Adjust (i.e. reduce or increase) to the continuous switching gate quantity U GE , I G , to switch (ie open and close) the semiconductor switch 3, the switching behavior of the power semiconductor 3 is modified. According to the considerations presented above, the maximum gate magnitude U max,A , I max,A It can be increased to speed up the switching process or decreased to slow it down. Thus, a constant EMC emission spectrum can be achieved across the entire operating range of inverter 20. Furthermore, switching losses are reduced relative to a specific operating point. For example, at idle or low output currents, high capacitive motor cable currents can often be reduced by slowly opening and closing the semiconductors. On the other hand, fast switching edges result in reduced switching losses at high operating currents. Therefore, by adjusting the switching edges during operation, the present invention allows for consistent operation at optimal settings for the switching speeds used to switch the individual semiconductor switches 3.

[0032] As mentioned above, the adjusted maximum gate magnitude U max,A , I max,A May be greater than the maximum gate value U GE,max , I G,max Small, for example, 10% smaller, or 20% smaller, or 50% smaller, or the adjusted maximum gate value U max,A , I max,A It can also be compared with the maximum gate value U GE,max , I G,max Larger, for example, 10% larger, or 20% larger, or 50% larger, or 100% larger, depending on whether it is necessary to increase or decrease the maximum gate value U GE,max , I G,max , to save the optimized switching time t S .

[0033] In a particularly advantageous embodiment of the present invention, the gate drive circuit 10 may comprise a detection device 11 for detecting the gate drive circuit 10 during the operation interval T op At least one detection time point t during D At this time, the detection indicates that the inverter 20 is in the operation interval T op At least one measured value x of a physical inverter quantity x during an assumed operating state meas,D Depending on the physical characteristics, such a detection device 11 can be implemented, for example, in the form of a current sensor, a voltage sensor, a temperature sensor or a Hall sensor, preferably connected to an appropriate signal processing device. Preferably, such a signal processing device can be implemented in the form of microprocessor-based hardware, such as a microcontroller and / or an integrated circuit (ASIC, FPGA).

[0034] In case the detection device 11 is provided, the time point t can be adjusted A As the detection time point t D The subsequent operation interval T op Adjustment time point t during the period A . Use at least one measurement x meas,D , the operating device can be designed to adjust the time point t A At least one measured value x of the physical inverter quantity x meas,D , the maximum gate value U GE,max , I G,max Adjusted to the adjusted maximum gate value U max,A , I max,A .

[0035] Considering the measured value x meas,D , so the value x can be measured, for example, by measuring the collector current meas,DTo monitor the collector current, define the rated current, such as 5A, or 10A, or 15A, or 50A, or 100A, and reduce the maximum gate value U if the collector current is insufficient max,A , I max,A , for example 5%, 10%, 20%, 35%, or 50% of the rated current. meas,D It can also correspond to the temperature of the inverter, wherein a temperature threshold can be defined and in case of falling below or exceeding this threshold the maximum gate magnitude value U can be modified max,A , I max,A , or, as mentioned above, a percentage value below or above such a temperature threshold. In addition, the load condition can be measured by the value x meas,D The parameter to be monitored can be a parameter describing the losses occurring in the inverter 20, which can also be a temperature, for example the temperature of the semiconductor switch 3 or the temperature of the housing of the semiconductor switch 3. Due to this flexibility, the invention allows a dynamic adaptation of the switching behavior of the semiconductor switch 3, in particular taking into account those quantities that are important in a given application.

[0036] Specifically, in this embodiment of the present invention, the physical inverter quantity x can be selected from the gate current or the collector current I G , gate current or collector current time difference dI G / dt, the gate-emitter or collector-emitter voltage U in the semiconductor switch 3 GE , gate-emitter or collector-emitter voltage time difference dU GE / dt, the component temperatures of the components of the inverter 20, and the inverter 20 during the operation interval T op The electrical power processed during the

[0037] exist Figure 1 In the case of the assembly 1 shown, it includes an inverter 20, a power cable 30 and an electric load 40. The inverter 20 is electrically connected to the electric load 40 via the power cable 30 to supply power to the electric load 40. The inverter 20 includes at least one semiconductor switch 3 and a gate drive circuit 100 according to the present invention. The detection device can be further designed in a particularly advantageous manner to detect the cable quantity U of the power cable 30. cab , I cab As at least one measurement value x meas Therefore, the detection device can also be designed to obtain the value x from at least one measurement value x. meas At least one cable parameter is identified in the ??, which cable parameter represents the inverter 20 in the operation interval T op The operating state assumed during the operation, and the operating device can be designed to adjust the maximum gate value U according to at least one cable parameter GE,max , I G,maxThe at least one cable parameter may be selected from the group consisting of cable length, cable resistance, cable inductance, cable material, cable cross-section, cable diameter, and cable capacity.

[0038] In order to identify the at least one cable parameter, the gate drive circuit 10 can advantageously be designed to convert the gate quantity U GE , I G Set to identify the gate value U GE,I , I G,I , at the excitation time point t E At the output terminal 50 of the inverter 20, a marked output voltage to be fed to the cable 30 is generated. At the marked time point t I At least one detection time point t D Measure at least one cable quantity x cable At least one measurement x meas , and at the detection time point t D The next identification time point t I From at least one measurement x meas and identify the gate value U GE,I , I G,I Identify at least one cable parameter Z cab .

[0039] In the preferred embodiment, at least one cable parameter Z cab can be selected from the group consisting of cable length, cable resistance, cable inductance, cable material, cable cross section, cable diameter, cable capacity, and wherein at least one cable quantity x cable Can be selected from the cable current I cable , cable voltage U cable , cable temperature T cable , Cable magnetic field B cable The group composed of.

[0040] With this cable marking method, it is possible to use the electrical grid quantities exclusively for marking, which has never been done before. In this respect, it is also possible to excite the cable at multiple (preferably consecutive) times t E,1 , t E,2 , ... is provided, the electric grid quantity U GE , I G Set at each excitation time point t E,1 , t E,2 , the corresponding identification gate value U at... GE,I,1 , U GE,I,2 ..., to measure the E,1 , t E,2 , ...corresponding to multiple detection time points t D,1 , t D,2At least one cable quantity x at ... cable Multiple measurements x meas , and from multiple measurements x meas and multiple identification gate values U GE,I , I G,I Identify at least one cable parameter Z of the cable 30 cab .

[0041] However, it should be noted that during the operation interval T op It is not mandatory to measure and take into account the physical quantities representing the assumed operating state of the inverter 20 during the period. Instead, the time point t A and the adjusted maximum gate magnitude U max,A , I max,A It can also be pre-set before the inverter 20 starts operating. For example, it can be known in advance that the inverter 20 starts operating and adjusts the time point t A After a predetermined time between the two, a low load state will be assumed so that the maximum gate magnitude U max,A , I max,A of the reduction.

[0042] Of course, according to the measured value x meas Adjust the maximum gate value U GE,max , I G,max In the case of the maximum gate value U GE,max , I G,max It can be preferably pre-set before the inverter 20 starts to operate, and the inverter 20 is set at the adjustment time point t A During operation, the maximum gate magnitude U max,A , I max,A .

[0043] Figure 3 Further shown are signals that may appear during operation of the gate driver circuit 10 according to the present invention. Figure 3 In the case shown, the operation starts at time t0, after which the quantity x is measured. meas Increases sharply, for which the first high maximum gate magnitude U is used GE,max , I G,max Alternating grid quantity U GE , I G To switch the semiconductor switch 3. However, at the detection time point t D Detect fixed value x of physical inverter quantity x meas,D , which can be current, temperature or voltage, etc., indicating that the inverter 20 is in the operation interval T op The operating state assumed during the period. The measured value x can be found meas,D Below the preset threshold x th, resulting in a maximum gate magnitude U GE,max , I G,max At the adjustment time t A Reduce to a smaller adjusted maximum gate magnitude value U max,A , I max,A From digital signal processing, we know that the measured value x meas,D Of course, it is also possible to detect at more than one time point t D but preferably at multiple detection time points t D,k These detection time points can be obtained from a time discretization, preferably an equidistant time discretization, where the detection time point t D,k There is a pre-determined sampling time t between D The value of may be continuously compared with pre-described threshold values in order to react immediately to potential changes in the operating state of the inverter 20 .

[0044] As mentioned above, the gate drive circuit according to the present invention is specifically implemented as follows: Figure 4 and Figure 5 shown.

[0045] Specifically, Figure 4 The switch resistor R G,switch The gate driver is realized according to Figure 4 In an embodiment, a device for supplying a power supply U to the gate electrode G is provided. S , I S To generate the electric gate quantity U GE , I G The power supply unit S, the main gate resistor R G,main , at least one switchable gate resistor R G,switch and bypass switch S by The power supply unit S is connected to the power supply unit output terminal T S and the first main gate resistor terminal T 1,main The electrical connection between the main gate resistor R G,main , at least one switchable gate resistor R G,switch Through the first switchable gate resistor terminal T 1,switch and the second main gate resistor terminal T 2,main The electrical connection in series is connected to the main gate resistor R G,main , bypass switch S by connected in parallel to at least one switchable gate resistor R G,switch , and at least one switchable gate resistor R G,switch Through the second switchable gate resistor terminal T 2,switch Electrically connected to the gate electrode G.

[0046] In this arrangement, the operating device 12 is designed to switch the bypass switch S by , thereby bypassing at least one switchable gate resistor R G,switch , so that the maximum gate value U GE,max , I G,max Adjusted to the adjusted maximum gate magnitude U max,A , I max,A

[0047] The advantage of this implementation is that the switching speed can be changed rapidly, i.e. high dynamics are possible, without having to give up precise control of the gate supply voltage.

[0048] on the contrary, Figure 5 The implementation of a gate driver based on a push-pull converter PPC according to the present invention is presented. Figure 5 In the embodiment of the present invention, the power supply unit S supplies power to the gate electrode G. The gate driving circuit 10 is provided with a circuit for supplying a power supply U to the gate electrode G. S , I S To generate the electric gate quantity U GE , I G In this case, the push-pull converter PPC outputs the power supply unit S through the power supply unit output terminal T S and the first push-pull converter terminal T 1,PPC The electrical connection between the power supply unit S and the at least one push-pull converter PPC is electrically connected to the power supply unit S via the second push-pull converter terminal T 2,PPC is electrically connected to the gate electrode G. Figure 5 In the case where the operating device is designed to switch at least one switch S 1,PPC ,exist Figure 5 When closed, the two switches S of the push-pull converter PPC are switched 1,PPC and S 2,PPC , to set the maximum gate value U GE,max , I G,max Adjusted to the adjusted maximum gate magnitude U max,A , I max,A

[0049] Two switches S 1,PPC and S 2,PPC The symmetrical control of the primary DC voltage U S Converted into AC voltage and transmitted to the secondary side. Rectification on the secondary side also allows the generation of two gate voltages U with different signs G1 and U G2 , whereby the amplitude is determined by the transformer turns ratio. The potential-free gate voltage U on the secondary side of the transformer G1 and UG2 With the primary input voltage U IN Proportional to:

[0050]

[0051] By changing the primary input voltage U S , the final gate voltage for controlling the semiconductor switch 3 (IGBT or FET) can be adjusted without any further hardware work. The advantage of this implementation is that no hardware adjustment is required to adapt to the maximum gate magnitude U GE,max , I G,max This is particularly beneficial in use cases with high operating voltages. It also means that there are no additional costs, for example, for further isolating the signal transmission to accommodate the switching behavior in the hardware design.

[0052] Figure 6 Another advantageous implementation of the gate driver circuit according to the present invention is shown in FIG. Figure 6 In the gate drive circuit 10, a control unit 101 is further provided, which is designed to receive the measured value x of the physical inverter quantity x. meas,D As the control feedback signal y, the measured value x meas Calculate the control signal u and feed the control signal u to the operating device so that the operating device adjusts the maximum gate value U according to the control signal u GE,max , I G,max .

[0053] As a signal processing device, the control unit 101 can also be implemented in the form of microprocessor-based hardware, such as a microcontroller and / or an integrated circuit (ASIC, FPGA). Figure 6 In a particularly advantageous embodiment of the embodiment with the control unit 101, the control unit 101 can be designed to continuously receive the operation interval T op Preferably, at the above-mentioned equidistant detection time point t D,k The measured value x detected at meas,D , as the control feedback signal y, and continuously calculating the control signal u from the control feedback signal y according to a predefined control law R implemented in the control unit 101.

[0054] Specifically, the control law R can be configured to calculate a control error e by comparing the feedback signal y with a predefined set point value r, which corresponds to a desired operating state of the inverter 20, and calculate the control signal u from the control error e according to the control law R, which is preferably selected from the group consisting of a PID controller, an MPC controller, a flatness-based controller, a sliding mode controller or even a neural network-based controller.

Claims

1. A gate drive circuit (10) for driving an electric gate quantity (U) present at a gate electrode (G) of a semiconductor switch (3) of an inverter (20) GE , I G ), the gate drive circuit (10) comprises an operating device (12) designed to operate at a predefined operating interval (T op ), the electric gate amount (U GE , I G ) at the maximum gate value (U GE,max , I G,max ) and the minimum gate value (U GE,min , I G,min ) to switch the semiconductor switch (3) alternately between the two so as to connect the power supply voltage (U0) to the output (50) of the inverter (20) or disconnect it from the output (50) of the inverter (20), characterized in that The operating device (12) is also designed to op ) during the adjustment period (t A ), the maximum gate value (U GE,max , I G,max ) is adjusted to the adjusted maximum gate value (U max,A , I max,A ) to further increase the gate capacity (U GE , I G ) at the adjusted maximum gate magnitude (U max,A , I max,A ) and the minimum gate value (U GE,min , I G,min ) alternately to switch the semiconductor switch (3).

2. The gate drive circuit (10) according to claim 1, characterized in that: The gate drive circuit (10) further comprises a detection device for detecting the gate drive circuit during the operation interval (T op ) at least one detection time point (t D ) at the time of detection, the detection indicates that the operation interval (T op ) of at least one measured value (x) of a physical inverter quantity (x) of an operating state assumed by the inverter (20) during meas,D ), characterized in that the adjustment time point (t A ) is provided as the detection time point (t D ) after the operation interval (T op ) during the adjustment period (t A ), and is characterized in that the operating device is designed to at the adjustment time point (t A ), according to the at least one measured value (x) of the physical inverter quantity (x) meas,D ), the maximum gate value (U GE,max , I G,max ) is adjusted to the adjusted maximum gate magnitude (U max,A , I max,A ).

3. The gate drive circuit (10) according to any one of claims 1 to 2, characterized in that: The maximum gate magnitude (U GE,max , I G,max ) is preset before the operation of the inverter (20) starts, and at the adjustment time point (t A ) is adjusted to the adjusted maximum gate magnitude (U max,A , I max,A ).

4. The gate drive circuit (10) according to any one of claims 1 to 3, characterized in that: The adjusted maximum gate magnitude (U max,A , I max,A ) is less than the maximum gate value (U GE,max , I G,max ), or characterized in that the adjusted maximum gate value (U max,A , I max,A ) is greater than the maximum gate value (U GE,max , I G,max ).

5. The gate drive circuit (10) according to any one of claims 1 to 4, characterized in that: The gate drive circuit (10) is provided with a circuit for supplying a power supply (U) to the gate electrode (G). S , I S ) to generate the electric gate quantity (U GE , I G ) power supply unit (S), main gate resistor (R G,main ), at least one switchable gate resistor (R G,switch ) and bypass switch (S by ), the power supply unit (S) outputs the power supply unit through the output terminal (T S ) and the first main gate resistor terminal (T 1,main ) is electrically connected to the main gate resistor (R G,main ), the at least one switchable gate resistor (R G,switch ) through the first switchable gate resistor terminal (T 1,switch ) and the second main gate resistor terminal (T 2,main ) is electrically connected in series to the main gate resistor (R G,main ), the bypass switch (S by ) is connected in parallel to the at least one switchable gate resistor (R G,switch ), the at least one switchable gate resistor (R G,switch ) through the second switchable gate resistor terminal (T 2,switch ) is electrically connected to the gate electrode (G), and is characterized in that the operating device is designed to switch the bypass switch (S by ), thereby bypassing the at least one switchable gate resistor (R G,switch ) in order to set the maximum gate value (U GE,max , I G,max ) is adjusted to the adjusted maximum gate magnitude (U max,A , I max,A ).

6. The gate drive circuit (10) according to any one of claims 1 to 4, characterized in that: The gate drive circuit (10) is provided with a circuit for supplying a power supply (U) to the gate electrode (G). S , I S ) to generate the electric gate quantity (U GE , I G ) of the power supply unit (S) and the push-pull converter (PPC), wherein the push-pull converter (PPC) outputs the power supply unit through the output terminal (T S ) and the first push-pull converter terminal (T 1,PPC ) is electrically connected to the power supply unit (S), the at least one push-pull converter (PPC) is electrically connected to the power supply unit (S) via the second push-pull converter terminal (T 2,PPC ) is electrically connected to the gate electrode (G), and is characterized in that the operating device is designed to switch at least one switch (S) of the push-pull converter (PPC) 1,PPC ) to set the maximum gate value (U GE,max , I G,max ) is adjusted to the adjusted maximum gate magnitude (U max,A , I max,A ).

7. The gate drive circuit (10) according to any one of the preceding claims 2 to 6, characterized in that A control unit (101) is provided in the gate drive circuit (10), and the control unit (101) is designed to receive the measured value (x) of the physical inverter quantity (x) meas,D ) as the control feedback signal (y), from the measured value (x meas ) calculates a control signal (u), and feeds the control signal (u) to the operating device so that the operating device adjusts the maximum gate value (U) according to the control signal (u) GE,max , I G,max ).

8. The gate drive circuit (10) according to claim 7, characterized in that: The control unit (101) is designed to continuously receive the op ), preferably at equidistant detection time points (t D,k ) detected at the measured value (x meas,D ) as a control feedback signal (y), and continuously calculating the control signal (u) from the control feedback signal (y) according to a predefined control law (R) implemented in the control unit (101).

9. The gate drive circuit (10) according to claim 8, characterized in that: The control law (R) is configured to calculate a control error (e) by comparing the feedback signal (y) with a predefined set point value (r), the predefined set point value (r) corresponding to a desired operating state of the inverter (20), and to calculate the control signal (u) from the control error (e) according to the control law (R), the control law (R) preferably being selected from the group consisting of a PID controller, an MPC controller, a flatness-based controller, a sliding mode controller or a neural network-based controller.

10. The gate drive circuit (10) according to any one of the preceding claims 2 to 9, characterized in that The physical inverter quantity (x) is selected from the gate or collector current (I G ), gate or collector current time difference (dI G / dt), gate-emitter or collector-emitter voltage (U GE ), gate-emitter or collector-emitter voltage time difference (dU GE / dt), component temperatures of components of the inverter (20), and during the operating interval (T op ) during which the electric power is processed by the inverter (20).

11. The gate drive circuit (10) according to any one of the preceding claims, characterized in that In order to adjust the maximum gate value (U GE,max , I G,max ), the operating device is designed to modify the gate resistance (R G ), at least one value from the group consisting of gate supply voltage, gate current, gate-emitter capacitance, and gate-emitter capacitance.

12. The gate drive circuit (10) according to claim 1, characterized in that The adjustment time point (t A ) and the adjusted maximum gate magnitude (U max,A , I max,A ) is preset before the operation of the inverter (20) begins.

13. An assembly (1) comprising an inverter (20), a power cable (30) and an electric load (40), wherein an output (50) of the inverter (20) is electrically connected to the electric load (40) via the power cable (30) so as to supply power to the electric load (40), and the inverter (20) comprises at least one semiconductor switch (3) and a gate drive circuit (10) according to any one of the preceding claims.

14. Assembly (1) according to claim 13, characterized in that The detection device is designed to detect the cable electrical quantity (U cab , I cab ) as the at least one measured value (x meas ), characterized in that the detection device is further designed to obtain the value of the at least one measurement value (x meas ) identifies at least one cable parameter, said cable parameter representing the operation interval (T op ) during the operation state assumed by the inverter (20), and characterized in that the operating device is designed to adjust the maximum gate magnitude value (U GE,max , I G,max ).

15. A method for operating a gate drive circuit (10) for driving an electric gate quantity (U) present at a gate electrode (G) of a semiconductor switch (3) of an inverter (20). GE , I G ), the method comprising the following steps: During the operation of the inverter (20) a predefined operating interval (T op ), the electric gate amount (U GE , I G ) at the maximum gate value (U GE,max , I G,max ) and the minimum gate value (U GE,min , I G,min ) alternately so as to switch the semiconductor switch (3) During the operation interval (T op ) during the adjustment time point (t A ), the maximum gate value (U GE,max , I G,max ) is adjusted to the adjusted maximum gate value (U max,A , I max,A ).

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