A voltage stabilizing circuit and a voltage stabilizer

Abstract

The present disclosure provides a voltage stabilizing circuit and a voltage stabilizer, comprising a sampling control circuit, a voltage follower circuit and a discharge circuit; the voltage follower circuit is used to respond to the change of a load current signal at the load end of the voltage stabilizing circuit, and to change the output voltage of the voltage stabilizing circuit according to the load current signal; the sampling control circuit is used to sample the output voltage of the voltage stabilizing circuit, and to adjust the output voltage of the voltage stabilizing circuit by adjusting the voltage follower circuit based on the comparison with a predetermined reference voltage; and the discharge circuit is used to recover the overshoot generated by the voltage stabilizing circuit in response to the change of the load current signal according to the transient current of the sampling control circuit. The present disclosure can obtain the transient current in the sampling control circuit through the discharge circuit, and improve the ground current of the load capacitance based on the transient current, so as to accelerate the release speed of the electric energy in the load capacitance, thereby recovering the overshoot quickly.

Description

Technical Field

[0001] The present disclosure relates to the field of analog integrated circuits, and in particular to a voltage stabilizing circuit and a voltage stabilizer. Background Art

[0002] Traditional flipped voltage follower low-dropout regulators (FVFLDO) employ a nested loop structure. The main loop provides high gain and low bandwidth to ensure high output voltage accuracy. Simultaneously, the embedded flipped voltage follower (FVF) loop leverages its inherent wide bandwidth to quickly respond to transient changes in the output voltage, effectively improving load transient response and achieving a high power supply rejection ratio (PSRR) across a wide bandwidth.

[0003] However, when the load current changes from high to low, the output voltage suddenly rises (i.e., overshoots). Although the FVF loop can quickly respond to voltage changes and suppress the peak amplitude of the overshoot, causing it to reach its peak as early as possible, the output node lacks a sufficiently large discharge current path to ground. After the overshoot reaches its peak, the output voltage cannot quickly fall back to its static set value, resulting in a significantly longer overshoot recovery time. Therefore, a voltage regulator circuit is urgently needed that can quickly recover from overshoot while maintaining output voltage accuracy and transient response speed. Summary of the Invention

[0004] The embodiments of the present disclosure provide a voltage stabilization circuit and a voltage stabilizer, so as to solve the problem of long output voltage overshoot recovery time of the existing voltage stabilizer.

[0005] Based on the above problems, in a first aspect, an embodiment of the present disclosure provides a voltage stabilizing circuit, comprising: a sampling control circuit, a voltage follower circuit, and a discharge circuit;

[0006] The voltage follower circuit is used to respond to changes in the load electrical signal at the load end of the voltage stabilizing circuit and change the output voltage of the voltage stabilizing circuit according to the load electrical signal;

[0007] The sampling control circuit is used to sample the output voltage of the voltage stabilizing circuit and adjust the output voltage of the voltage stabilizing circuit by adjusting the voltage follower circuit based on a comparison with a predetermined reference voltage;

[0008] The discharge circuit is used to recover the overshoot generated by the voltage stabilization circuit in response to the change of the load electrical signal according to the transient current of the sampling control circuit.

[0009] In combination with the first aspect, in a possible implementation manner, the sampling control circuit includes: an error sampling circuit and a control voltage output circuit;

[0010] The error sampling circuit is used to detect the error between the output voltage of the voltage stabilizing circuit and the reference voltage, and generate a corresponding control voltage;

[0011] The control voltage output circuit is used to output the control voltage to the voltage follower circuit, so that the output voltage of the voltage stabilizing circuit is stabilized at the reference voltage.

[0012] In combination with the first aspect, in a possible implementation, the error sampling circuit includes: a fully differential amplifier, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor;

[0013] The fully differential amplifier has an inverting input terminal that obtains the output voltage of the voltage stabilization circuit, a forward input terminal that obtains a predetermined reference voltage, a forward output terminal that is connected to the gate of the first PMOS transistor, and a reverse output terminal that is connected to the gate of the second PMOS transistor;

[0014] The source electrodes of the first PMOS transistor and the second PMOS transistor are connected to each other and are also connected to a power supply;

[0015] The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor;

[0016] The drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and is connected to the control voltage output circuit;

[0017] The drain of the first NMOS transistor is also connected to its own gate, the gate is also connected to the gate of the second NMOS transistor, and the source is connected to the source of the second NMOS transistor and is grounded.

[0018] In combination with the first aspect, in a possible implementation, the control voltage output circuit includes: a first capacitor, a third PMOS transistor, and a first current source;

[0019] The source of the third PMOS transistor is respectively connected to one end of the first capacitor and the error sampling circuit, the drain is respectively connected to its own gate and one end of the first current source, and the gate is also connected to the voltage follower circuit;

[0020] The other end of the first capacitor is connected to the other end of the first current source and the error sampling circuit and is grounded.

[0021] In combination with the first aspect, in a possible implementation, the voltage follower circuit includes: a source follower, a fourth PMOS transistor, a fifth PMOS transistor, and a second current source;

[0022] The source of the fourth PMOS transistor is connected to a power supply, the drain is connected to the source of the fifth PMOS transistor and a load respectively, and the gate is connected to the output end of the source follower;

[0023] The drain of the fifth PMOS transistor is grounded through the second current source and connected to the input end of the source follower, and the gate is connected to the sampling control circuit.

[0024] In combination with the first aspect, in a possible implementation manner, the discharge circuit includes: a third NMOS transistor;

[0025] The third NMOS transistor is used to obtain the transient current of the error sampling circuit, and change the capacitor discharge speed of the load end of the voltage stabilizing circuit according to the transient current to restore the overshoot generated by the voltage stabilizing circuit;

[0026] The drain of the third NMOS tube is connected to the load, the source is grounded, and the gate is connected to the sampling control circuit.

[0027] In combination with the first aspect, in one possible implementation, the fully differential amplifier is configured to perform a differential operation on the output voltage of the voltage stabilization circuit and a reference voltage to obtain two differential output voltages;

[0028] The first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are used to convert two differential output voltages into a single-ended control voltage and output it to the control voltage output circuit.

[0029] In combination with the first aspect, in a possible implementation manner, the first NMOS transistor and the second NMOS transistor form a current mirror circuit, which is used to copy the transient current of the first NMOS transistor to the second NMOS transistor;

[0030] The second NMOS transistor is used to change the discharge speed of the control voltage output circuit to the ground according to the transient current of the first NMOS transistor.

[0031] With reference to the first aspect, in one possible implementation, the gate of the third NMOS transistor is connected to the gate of the first NMOS transistor;

[0032] The third NMOS transistor and the second NMOS transistor form a current mirror circuit for copying the transient current of the first NMOS transistor to the third NMOS transistor;

[0033] The third NMOS transistor is used to change the discharge speed of the capacitor at the load end of the voltage stabilizing circuit according to the transient current of the first NMOS transistor.

[0034] In a second aspect, the present disclosure provides a voltage stabilizer, comprising the voltage stabilizing circuit described in any one of the first aspects.

[0035] The beneficial effects of the embodiments of the present disclosure include:

[0036] The present disclosure provides a voltage stabilizing circuit, comprising: a sampling control circuit, a voltage follower circuit, and a discharge circuit; the voltage follower circuit is used to respond to changes in a load electrical signal at a load end of the voltage stabilizing circuit and change the output voltage of the voltage stabilizing circuit according to the load electrical signal; the sampling control circuit is used to sample the output voltage of the voltage stabilizing circuit and adjust the output voltage of the voltage stabilizing circuit by adjusting the voltage follower circuit based on a comparison with a predetermined reference voltage; the discharge circuit is used to recover overshoot caused by the voltage stabilizing circuit responding to changes in the load electrical signal according to the transient current of the sampling control circuit. The present disclosure can obtain the transient current from the sampling control circuit through the discharge circuit, and based on this transient current, increase the current to ground of the load capacitor, accelerate the release rate of the electrical energy in the load capacitor, and thus quickly recover the overshoot. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of the voltage stabilization circuit structure provided in an embodiment of the present disclosure;

[0038] Figure 2 A schematic diagram of the structure of an existing voltage stabilizing circuit provided in an embodiment of the present disclosure;

[0039] Figure 3 A comparison chart of overshoot recovery time provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] The present disclosure provides a voltage stabilizing circuit and a voltage stabilizer. Preferred embodiments of the present disclosure are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are intended only to illustrate and explain the present disclosure and are not intended to limit the present disclosure. Furthermore, the embodiments and features of the embodiments may be combined with one another unless there is a conflict.

[0041] The embodiment of the present disclosure provides a voltage stabilizing circuit, such as Figure 1 As shown, it includes: a sampling control circuit 1, a voltage follower circuit 2 and a discharge circuit 3;

[0042] The voltage follower circuit 2 is used to respond to changes in the load electrical signal at the load end of the voltage stabilizing circuit and change the output voltage of the voltage stabilizing circuit according to the load electrical signal;

[0043] The sampling control circuit 1 is used to sample the output voltage of the voltage stabilizing circuit and adjust the output voltage of the voltage stabilizing circuit by adjusting the voltage follower circuit 2 based on a comparison with a predetermined reference voltage;

[0044] The discharge circuit 3 is used to recover the overshoot caused by the voltage stabilization circuit responding to the change of the load electrical signal according to the transient current of the sampling control circuit 1.

[0045] In the embodiment of the present disclosure, the voltage stabilizing circuit may be an electronic circuit that can provide a stable DC output voltage for a load, and the voltage output by the circuit may be controlled by a reference voltage source. Figure 1 middle ), the components in the voltage stabilizing circuit can be dynamically adjusted so that the voltage value output by the voltage stabilizing circuit is stabilized at the reference voltage value.

[0046] The voltage follower circuit 2 provided by the present disclosure can be a circuit based on the negative feedback principle, wherein one end of the voltage follower circuit 2 inputs a voltage provided by a power supply (i.e. Figure 1 middle ), and the other end is connected to the load. The voltage follower circuit 2 may include multiple transistors, through which the voltage input from the power supply to the voltage stabilizing circuit can be received, and the output voltage output to the load end can be controlled; further, the conduction state of the transistor can be adjusted according to the change of the load electrical signal to suppress the influence of the change of the load electrical signal on the output voltage of the voltage stabilizing circuit, so as to ensure the stability of the output voltage of the voltage stabilizing circuit. The output end of the voltage follower circuit 2 can be the output end of the voltage stabilizing circuit, and the output voltage of the voltage follower circuit 2 can be the output voltage of the voltage stabilizing circuit (i.e. Figure 1 middle ).

[0047] Sampling control circuit 1 can be a circuit based on an error amplifier. By obtaining the output voltage of the voltage regulator circuit and comparing it with a reference voltage, it generates a corresponding control voltage, adjusts the conduction state of the transistors in voltage follower circuit 2, and thus further adjusts the output voltage of the voltage regulator circuit, precisely controlling the output voltage. It should be noted that the bandwidth of voltage follower circuit 2 can be greater than the bandwidth of sampling control circuit 1. Voltage follower circuit 2 can quickly respond to the impact of load changes on the output voltage, suppress changes in the output voltage, and maintain the stability of the output voltage. Sampling control circuit 1 can further precisely control the output voltage based on the output voltage control already performed by voltage follower circuit 2.

[0048] In practical applications, when the load current (i.e. Figure 1 middle If the load current suddenly increases, the output voltage will decrease due to the sudden increase in current demand. If the load current suddenly decreases, the output voltage will increase due to the decrease in current demand. Voltage follower circuit 2 can adjust the conduction state of its internal transistors based on these changes to stabilize the output voltage. However, this transistor adjustment has a certain response delay, which can cause some fluctuation in the output voltage (i.e., overshoot and undershoot).

[0049] Furthermore, the peak values ​​of overshoot and undershoot can be controlled by setting a load capacitor for the load end. When the load current suddenly increases, the load capacitor can be discharged to compensate for the current gap during the transistor response delay in the voltage follower circuit 2.

[0050] When the load current suddenly drops, the load capacitor can absorb the excess electrical energy, and combined with the feedback control of the voltage follower circuit 2, the overshoot peak is reduced and reaches the peak quickly. However, at this time, the load current is low, resulting in a low current in the load capacitor relative to the ground terminal, which leads to a slow release rate of the electrical energy absorbed in the load capacitor, and a slow recovery rate of the voltage fluctuation caused by the overshoot. In response to this situation, the present disclosure can obtain the transient current from the sampling control circuit 1 through the discharge circuit 3, and based on this transient current, increase the load capacitor's current to ground, speed up the release rate of the electrical energy in the load capacitor, and thus quickly recover from the overshoot.

[0051] In another embodiment provided by the present disclosure, Figure 1 As shown, the sampling control circuit 1 includes: an error sampling circuit 11 and a control voltage output circuit 12;

[0052] The error sampling circuit 11 is used to detect the error between the output voltage of the voltage stabilization circuit and the reference voltage, and generate a corresponding control voltage;

[0053] The control voltage output circuit 12 is used to output the control voltage to the voltage follower circuit 2 so that the output voltage of the voltage stabilization circuit is stabilized at the reference voltage.

[0054] In the disclosed embodiment, the error sampling circuit 11 can convert the two received signals (i.e., the output voltage of the voltage regulator circuit and the reference voltage) into a single-ended control voltage after calculation. The control voltage output circuit 12 can receive the control voltage and apply it to the corresponding transistor in the voltage follower circuit 2, controlling the conduction state of the corresponding transistor, thereby adjusting the output voltage of the voltage regulator circuit to stabilize it at the reference voltage, thereby achieving precise voltage regulation control.

[0055] In another embodiment provided by the present disclosure, Figure 1As shown, the error sampling circuit 11 includes: a fully differential amplifier 111, a first P-channel metal oxide semiconductor (PMOS) transistor 112, a second PMOS transistor 113, a first N-channel metal oxide semiconductor (NMOS) transistor 114, and a second NMOS transistor 115;

[0056] The fully differential amplifier 111 has an inverting input terminal that obtains the output voltage of the voltage stabilization circuit, a forward input terminal that obtains a predetermined reference voltage, a forward output terminal that is connected to the gate of the first PMOS transistor 112, and an inverting output terminal that is connected to the gate of the second PMOS transistor 113;

[0057] The sources of the first PMOS transistor 112 and the second PMOS transistor 113 are connected to each other and are also connected to a power supply;

[0058] The drain of the first PMOS transistor 112 is connected to the drain of the first NMOS transistor 114;

[0059] The drain of the second PMOS transistor 113 is connected to the drain of the second NMOS transistor 115 and is also connected to the control voltage output circuit 12;

[0060] The drain of the first NMOS transistor 114 is also connected to its own gate, the gate is also connected to the gate of the second NMOS transistor 115 , and the source is connected to the source of the second NMOS transistor 115 and grounded.

[0061] In the disclosed embodiment, the positive input terminal of the fully differential amplifier 111 can obtain a reference voltage, where the reference voltage can be a voltage that the voltage stabilization circuit needs to output stably. The reference voltage can be provided by a reference voltage source (e.g., a Zener diode or a bandgap reference source).

[0062] The inverting input terminal of the fully differential amplifier 111 can sample and obtain the output voltage of the voltage stabilizing circuit. By utilizing the electrical characteristics of the fully differential amplifier 111 , the common-mode interference of the input signal can be better suppressed, thereby improving the accuracy of error sampling.

[0063] The output voltage of the non-inverting output terminal of the fully differential amplifier 111 is , the output voltage of the inverting output terminal of the fully differential amplifier 111 .in, is the differential voltage gain, which indicates the amplifier's ability to amplify the signal; is the input voltage of the same-direction input terminal, which can be the reference voltage in this disclosure ; is the input voltage of the reverse input terminal, which can be the output voltage of the voltage stabilizing circuit in this disclosure .

[0064] The output end of the error sampling circuit 11 may be between the drain of the second PMOS transistor 113 and the drain of the second NMOS transistor 115 , through which a control voltage determined based on the error between the reference voltage and the output voltage may be output to the control voltage output circuit 12 .

[0065] In another embodiment provided by the present disclosure, Figure 1 As shown, the control voltage output circuit 12 includes: a first capacitor 121, a third PMOS transistor 122 and a first current source 123;

[0066] The source of the third PMOS transistor 122 is connected to one end of the first capacitor 121 and the error sampling circuit 11, the drain is connected to its own gate and one end of the first current source 123, and the gate is also connected to the voltage follower circuit 2;

[0067] The other end of the first capacitor 121 is connected to the other end of the first current source 123 and is grounded.

[0068] In the disclosed embodiment, the control voltage output circuit 12 can output the control voltage output by the error sampling circuit 11 to the voltage follower circuit 2. The third PMOS transistor 122 is connected in a diode manner with its drain and gate short-circuited, and can form a current mirror circuit with corresponding components in the voltage follower circuit 2, so that the voltage follower circuit 2 generates a corresponding control voltage.

[0069] The first voltage is used to optimize the output characteristics of the circuit and maintain circuit stability. The first current source 123 is used to provide a DC bias for the third PMOS transistor 122. By providing a small current, a suitable operating point is set for the third PMOS transistor 122, allowing the MOS transistor to operate in a predetermined conduction state to ensure normal operation of the circuit.

[0070] In another embodiment provided by the present disclosure, Figure 1 As shown, the voltage follower circuit 2 includes: a source follower 21, a fourth PMOS transistor 22, a fifth PMOS transistor 23 and a second current source 24;

[0071] The source of the fourth PMOS transistor 22 is connected to the power supply, the drain is connected to the source of the fifth PMOS transistor 23 and the load respectively, and the gate is connected to the output end of the source follower 21;

[0072] The drain of the fifth PMOS transistor 23 is grounded through the second current source 24 and connected to the input end of the source follower 21 , and the gate is connected to the sampling control circuit 1 .

[0073] In the embodiment of the present disclosure, the output end of the voltage follower circuit 2 is between the source of the fifth PMOS transistor 23 and the drain of the fourth PMOS transistor 22 , and is connected to the load end through this, and can also serve as the output end of the voltage stabilizing circuit.

[0074] The second current source 24 can provide a small current to provide a DC bias for the fifth PMOS transistor 23 to adjust the operating point of the fifth PMOS transistor 23 to ensure normal operation of the MOS transistor.

[0075] The source follower 21 can be an amplifier circuit composed of transistors, whose output signal has the same phase and similar amplitude as the input signal, and can adjust the output impedance, improve the circuit driving capability, and provide buffer isolation.

[0076] When the voltage stabilizing circuit is operating, if the load changes, causing the output voltage of the voltage stabilizing circuit to change, the drain voltage of the fifth PMOS transistor 23 will change. This change will be output to the gate of the fourth PMOS transistor 22 through the source follower 21, changing the voltage between the gate and source of the fourth PMOS transistor 22.

[0077] When the output voltage decreases, the gate potential of the fourth PMOS transistor 22 becomes lower than the source potential, and the voltage between the gate and source of the fourth PMOS transistor 22 increases. To stabilize the output current, the voltage between the gate and drain of the fourth PMOS transistor 22 decreases. Since the input power supply voltage is constant, the output voltage of the drain of the fourth PMOS transistor 22 (i.e., the output voltage of the voltage stabilization circuit) increases to offset the downward trend of the output voltage, thereby achieving a voltage stabilization effect.

[0078] On the contrary, when the output voltage increases, the voltage between the gate and source of the fourth PMOS transistor 22 decreases, the voltage between the gate and drain of the fourth PMOS transistor 22 increases, and the output voltage of the drain of the fourth PMOS transistor 22 decreases to offset the rising trend of the output voltage.

[0079] The fifth PMOS transistor 23 can receive the control voltage sent by the control voltage output circuit 12 and adjust its own conduction state according to the control voltage, thereby further adjusting the output voltage.

[0080] In another embodiment provided by the present disclosure, Figure 1 As shown, the discharge circuit 3 includes: a third NMOS transistor 31;

[0081] The third NMOS transistor 31 is used to obtain the transient current of the error sampling circuit 11 and change the capacitor discharge speed of the load end of the voltage stabilizing circuit according to the transient current to restore the overshoot generated by the voltage stabilizing circuit;

[0082] The drain of the third NMOS transistor 31 is connected to the load, the source is grounded, and the gate is connected to the sampling control circuit 1 .

[0083] In the embodiment of the present disclosure, the third NMOS transistor 31 can mirror the transient current of the first NMOS transistor 114 by forming a current mirror with the first NMOS transistor 114 .

[0084] When the voltage stabilization circuit generates an overshoot, a large current is also generated in the first NMOS transistor 114 in the error sampling circuit 11. The third NMOS transistor 31 can mirror this current, thereby increasing the ground current of the third NMOS transistor 31, thereby increasing the current of the load capacitor connected to the third NMOS transistor 31, thereby increasing the discharge speed of the load capacitor and accelerating the recovery of the overshoot.

[0085] In another embodiment provided by the present disclosure, the fully differential amplifier 111 is used to perform differential operation on the output voltage of the voltage stabilization circuit and the reference voltage, and obtain two differential output voltages;

[0086] The first PMOS transistor 112 , the second PMOS transistor 113 , the first NMOS transistor 114 and the second NMOS transistor 115 are used to convert two differential output voltages into a single-ended control voltage and output it to the control voltage output circuit 12 .

[0087] In the disclosed embodiment, the error sampling circuit 11 is essentially a push-pull two-stage voltage regulation circuit consisting of a fully differential amplifier 111 and MOS transistors. The fully differential amplifier 111 in the first stage applies voltages to the gates of the first PMOS transistor 112 and the second PMOS transistor 113, respectively, based on the input voltage. This voltage is then applied to the gates of the second stage circuit, which consists of four MOS transistors (the first PMOS transistor 112, the second PMOS transistor 113, the first NMOS transistor 114, and the second NMOS transistor 115). The first PMOS transistor 112 is controlled by the voltage output from the positive output terminal of the fully differential amplifier 111. A current is generated between the first PMOS transistor 112 and the first NMOS transistor 114. Based on the current in the on-state of the first PMOS transistor 112, the current mirror structure formed by the first NMOS transistor 114 and the second NMOS transistor 115 can mirror this current to the second PMOS transistor 113 and the second NMOS transistor 115. This results in the control voltage output by the error sampling circuit 11 being clamped by the output voltage of the voltage regulator circuit and the reference voltage.

[0088] In another embodiment provided by the present disclosure, Figure 1 As shown, the first NMOS transistor 114 and the second NMOS transistor 115 form a current mirror circuit, which is used to copy the transient current of the first NMOS transistor 114 to the second NMOS transistor 115;

[0089] The second NMOS transistor 115 is used to change the discharge speed of the control voltage output circuit 12 to the ground according to the transient current of the first NMOS transistor 114 .

[0090] In the embodiment of the present disclosure, when the voltage stabilization circuit generates an overshoot, a large current will be generated at the first NMOS transistor 114 in the error sampling circuit 11. The second NMOS transistor 115 can mirror this current, so that the current of the second NMOS transistor 115 increases, thereby increasing the current of the capacitor (i.e., the first capacitor 121) in the control voltage output circuit 12, thereby accelerating the discharge speed of the first capacitor 121, so that the control voltage can also quickly get rid of the influence of the overshoot.

[0091] In another embodiment provided by the present disclosure, Figure 1 As shown, the gate of the third NMOS transistor 31 is connected to the gate of the first NMOS transistor 114;

[0092] The third NMOS transistor 31 and the second NMOS transistor 115 form a current mirror circuit for copying the transient current of the first NMOS transistor 114 to the third NMOS transistor 31;

[0093] The third NMOS transistor 31 is used to change the discharge speed of the capacitor at the load end of the voltage stabilizing circuit according to the transient current of the first NMOS transistor 114 .

[0094] In the embodiment of the present disclosure, the third NMOS transistor 31 and the first NMOS transistor 114 may form a current mirror circuit to accelerate the discharge speed of the load capacitor, thereby allowing the overshoot to recover quickly.

[0095] Here is a Figure 2 The conventional voltage stabilizing circuit shown in the figure is used as a comparison. The main difference between the voltage stabilizing circuit and the voltage stabilizing circuit provided by the present disclosure is that the reference voltage and the output voltage of the voltage stabilizing circuit are input, and the amplifier circuit composed of four MOS tubes amplifies and compares the reference voltage and the output voltage, and then passes through a PMOS tube (i.e. Figure 2 middle ) will move the comparison result to As a control voltage output. And the conventional voltage stabilizing circuit does not have the discharge circuit 3 provided by the present disclosure. Figure 3 The recovery time after overshoot of the embodiment provided by the present disclosure is compared with the recovery time of the traditional voltage stabilizing circuit. It should be noted that the overshoot recovery time of the circuits using different processes is also different. The two circuits used for comparison here are both Take the process as an example. Figure 3 In the figure, the vertical axis is the voltage value, and the unit can be volts ( ); The horizontal axis is the recovery time, the unit can be nanoseconds ( ). It can be seen that the overshoot recovery time of the circuit provided by this embodiment can be controlled within The overshoot recovery time of the traditional voltage stabilization circuit is hundreds of This shows that the overshoot recovery time of the embodiment is significantly shorter than that of the traditional voltage stabilizing circuit, and the present disclosure solves the problem of slow overshoot recovery speed in the related art.

[0096] In summary, the voltage stabilizing circuit provided in this embodiment accelerates the discharge speed of the capacitor and reduces the overshoot recovery time by collecting transient current.

[0097] The present disclosure also provides a voltage stabilizer, comprising the voltage stabilization circuit provided by any one of the embodiments of the present disclosure.

[0098] Through the above description of the embodiments, those skilled in the art will clearly understand that the embodiments of the present disclosure can be implemented through hardware or through software plus the necessary general hardware platform. Based on this understanding, the technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, or mobile hard drive) and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in the various embodiments of the present disclosure.

[0099] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of a preferred embodiment, and the modules or processes in the accompanying drawings are not necessarily required for implementing the present disclosure.

[0100] Those skilled in the art will appreciate that the modules in the devices of the embodiments may be distributed in the devices of the embodiments as described in the embodiments, or may be located in one or more devices different from the embodiments with corresponding changes. The modules of the above embodiments may be combined into one module or further divided into multiple submodules.

[0101] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0102] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A voltage stabilizing circuit, characterized in that: include: Sampling control circuit, voltage follower circuit and discharge circuit; The voltage follower circuit is used to respond to changes in the load electrical signal at the load end of the voltage stabilizing circuit and change the output voltage of the voltage stabilizing circuit according to the load electrical signal; The sampling control circuit is used to sample the output voltage of the voltage stabilizing circuit and adjust the output voltage of the voltage stabilizing circuit by adjusting the voltage follower circuit based on a comparison with a predetermined reference voltage; The discharge circuit is used to recover the overshoot caused by the voltage stabilization circuit responding to the change of the load electrical signal according to the transient current of the sampling control circuit; The sampling control circuit includes: an error sampling circuit and a control voltage output circuit; The error sampling circuit includes: a fully differential amplifier, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor; The fully differential amplifier has an inverting input terminal that obtains the output voltage of the voltage stabilization circuit, a forward input terminal that obtains a predetermined reference voltage, a forward output terminal that is connected to the gate of the first PMOS transistor, and a reverse output terminal that is connected to the gate of the second PMOS transistor; The source electrodes of the first PMOS transistor and the second PMOS transistor are connected to each other and are also connected to a power supply; The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor; The drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and is connected to the control voltage output circuit; The drain of the first NMOS transistor is also connected to its own gate, the gate is also connected to the gate of the second NMOS transistor, and the source is connected to the source of the second NMOS transistor and grounded; The discharge circuit includes: a third NMOS transistor; The third NMOS transistor is used to obtain the transient current of the error sampling circuit, and change the capacitor discharge speed of the load end of the voltage stabilizing circuit according to the transient current to restore the overshoot generated by the voltage stabilizing circuit; The drain of the third NMOS tube is connected to the load, the source is grounded, and the gate is connected to the sampling control circuit; The gate of the third NMOS transistor is connected to the gate of the first NMOS transistor; The third NMOS transistor and the second NMOS transistor form a current mirror circuit for copying the transient current of the first NMOS transistor to the third NMOS transistor; The third NMOS transistor is used to change the discharge speed of the capacitor at the load end of the voltage stabilizing circuit according to the transient current of the first NMOS transistor.

2. The voltage stabilizing circuit according to claim 1, wherein: The error sampling circuit is used to detect the error between the output voltage of the voltage stabilizing circuit and the reference voltage, and generate a corresponding control voltage; The control voltage output circuit is used to output the control voltage to the voltage follower circuit, so that the output voltage of the voltage stabilizing circuit is stabilized at the reference voltage.

3. The voltage stabilizing circuit according to claim 2, wherein: The control voltage output circuit includes: a first capacitor, a third PMOS transistor and a first current source; The source of the third PMOS transistor is respectively connected to one end of the first capacitor and the error sampling circuit, the drain is respectively connected to its own gate and one end of the first current source, and the gate is also connected to the voltage follower circuit; The other end of the first capacitor is connected to the other end of the first current source and the error sampling circuit and is grounded.

4. The voltage stabilizing circuit according to claim 1, wherein: The voltage follower circuit includes: a source follower, a fourth PMOS transistor, a fifth PMOS transistor and a second current source; The source of the fourth PMOS transistor is connected to a power supply, the drain is connected to the source of the fifth PMOS transistor and a load respectively, and the gate is connected to the output end of the source follower; The drain of the fifth PMOS transistor is grounded through the second current source and connected to the input end of the source follower, and the gate is connected to the sampling control circuit.

5. The voltage stabilizing circuit according to claim 2, wherein: The fully differential amplifier is used to perform differential operation on the output voltage of the voltage stabilization circuit and the reference voltage to obtain two differential output voltages; The first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are used to convert two differential output voltages into a single-ended control voltage and output it to the control voltage output circuit.

6. The voltage stabilizing circuit according to claim 2, wherein: The first NMOS transistor and the second NMOS transistor form a current mirror circuit, which is used to copy the transient current of the first NMOS transistor to the second NMOS transistor; The second NMOS transistor is used to change the discharge speed of the control voltage output circuit to the ground according to the transient current of the first NMOS transistor.

7. A voltage stabilizer, characterized in that: The invention comprises the voltage stabilizing circuit according to any one of claims 1 to 6.

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