Voltage-type adaptive bias circuit, power amplification circuit, chip and electronic equipment

Abstract

The invention provides a voltage type adaptive bias circuit, a power amplification circuit, a chip and electronic equipment. The voltage-type adaptive bias circuit comprises a degree-of-freedom adaptation module and a linearization bias module, a first end of the degree-of-freedom adaptation module and a first end of the linearization bias module are used for receiving power supply voltage, and a control end of the degree-of-freedom adaptation module and a second end of the linearization bias module are coupled to a first node. The second end of the degree-of-freedom adaptation module and the control end of the linearization bias module are coupled to a second node, and the third end of the degree-of-freedom adaptation module serves as a bias node and is used for being coupled to a grid electrode of a power amplification tube of the power amplification circuit. The degree-of-freedom adaptation module and the linearization bias module form a negative feedback circuit structure, and the feedback circuit structure can stabilize the voltage of a bias node. While the design freedom degree is improved, the stability of the grid static bias voltage of the power amplifier tube can be ensured, and the overall performance of the power amplifier circuit can be remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency power amplifiers, and in particular to a voltage-type adaptive bias circuit, a power amplifier circuit, a chip, and an electronic device. Background Art

[0002] A radio frequency power amplifier (RFPA) is an electronic amplifier. As a key component in wireless communication links, RFPAs amplify low-power RF signals carrying useful information to a certain power level and radiate them through antennas. They are increasingly used in mobile devices and IoT consumer products. However, with the rapid development of wireless communication technology, performance requirements for RFPAs are becoming increasingly stringent. Linearity is a key performance metric for RFPAs. Linearity generally refers to the ability of a component or system to provide an output signal that is proportional to the input signal. Research has found that the bias circuit significantly affects the linearity of RFPAs.

[0003] For RF power amplifiers based on CMOS technology, when the input power of the RF power amplifier increases, the gate-source voltage of the power amplifier tube (such as MOS tube) increases. Due to the presence of the gate-source PN junction diode of the MOS tube, a clamping effect will occur when the input signal is very large. After being shaped by the gate-source PN junction diode, the DC value of the gate-source voltage VGS (that is, the DC voltage value applied between the gate and source of the MOS tube) will be lowered, causing the gain compression linearity to deteriorate. The gain compression phenomenon is the main source of nonlinearity in power amplifiers.

[0004] In order to improve the gain compression phenomenon, diode linearization compensation technology is often used in existing technologies. Figure 1 , Figure 1 FIG. 1 is a topological diagram of a diode linearization bias circuit in the prior art. Figure 1 As shown, the diode linearization bias circuit is based on the traditional current mirror bias circuit with an additional diode-connected transistor M02 ( Figure 1 The working principle is as follows: When the input power is small, the drain voltage V D Subtracting the source voltage Vs is always less than the turn-on voltage of transistor M02. At this time, transistor M02 is in the reverse cut-off state. As the input power continues to increase, the voltage swing increases, which will cause the drain voltage V of transistor M02 to decrease during the voltage swing period. DThe minus source voltage Vs is greater than its turn-on voltage and lasts for a period of time. During this period, transistor M02 is forward-conducted, which will clip the lower swing of the gate voltage waveform of the power amplifier tube M03, thereby raising the DC voltage component of the gate terminal, thereby achieving the effect of compensating the gain of the power amplifier tube. In order to optimize the performance of the RF power amplifier, it is necessary to ensure that the bias circuit has appropriate bias adjustment capabilities within a certain power range. For example, the bias adjustment capability of the diode linearization bias circuit can be adjusted by adjusting the size of the diode-connected transistor M02. However, the values of transistor M01 and resistor R02 will affect the gate and source voltages of transistor M02. At the same time, the static operating point is jointly determined by resistors R01 and R02 and transistors M01 and M02. Therefore, in practical applications, it is difficult to ensure that the static operating point of the power amplifier tube and the bias adjustment capability of the linearization bias circuit are both in the optimal state. This solution lacks sufficient parameter adjustment freedom.

[0005] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0006] The present invention aims to address the problem in the prior art that diode linearization bias circuits have difficulty ensuring that both the static operating point of a power amplifier tube and the bias adjustment capability of the linearization bias circuit are in an optimal state, and lack sufficient freedom in parameter adjustment. The present invention provides a voltage-type adaptive bias circuit, a power amplifier circuit, a chip, and an electronic device. While improving the degree of design freedom, the present invention can ensure the stability of the static bias voltage of the gate of the power amplifier tube of the power amplifier circuit, effectively ensure that both the static operating point of the power amplifier tube and the bias adjustment capability of the voltage-type adaptive bias circuit are in an optimal state, and can significantly improve the overall performance of the power amplifier circuit.

[0007] To achieve the above objectives, the present invention is implemented through the following technical solutions: a voltage-type adaptive bias circuit for adjusting the bias state of a power amplifier circuit, the power amplifier circuit including a power amplifier tube, the gate of the power amplifier tube being coupled to a bias node; the voltage-type adaptive bias circuit including a degree of freedom adaptation module and a linearization bias module, the first end of the degree of freedom adaptation module and the first end of the linearization bias module being configured to receive a supply voltage, the control end of the degree of freedom adaptation module and the second end of the linearization bias module being coupled to a first node, the second end of the degree of freedom adaptation module and the control end of the linearization bias module being coupled to a second node, and the third end of the degree of freedom adaptation module being coupled to the bias node;

[0008] The degree of freedom adaptation module and the linearization bias module constitute a negative feedback circuit structure, which is configured to stabilize the voltage of the bias node when the state change of the power amplifier tube causes the voltage of the bias node to change, and adjust the negative feedback depth by adjusting the linearization bias module.

[0009] Optionally, the degree of freedom adaptation module includes a first transistor and a first mirror signal branch and a second mirror signal branch, wherein one end of the first transistor is used to receive a supply voltage, a gate of the first transistor is coupled to the first node, the other end of the first transistor, a first end of the first mirror signal branch, and a first end of the second mirror signal branch are coupled to a third node, a second end of the first mirror signal branch is coupled to the second node, a second end of the second mirror signal branch is coupled to the bias node, and a third end of the first mirror signal branch and a third end of the second mirror signal branch are coupled to a reference ground;

[0010] The first mirror signal branch and the second mirror signal branch are configured to feed back the voltage change of the bias node to the linearization bias module, so as to adjust the working state of the first transistor through the linearization bias module, thereby stabilizing the voltage of the bias node.

[0011] Optionally, the first mirror signal branch includes a second transistor and a first resistor, the second mirror signal branch includes a third transistor and a second resistor, the gate of the second transistor, one end of the second transistor, the gate of the third transistor and one end of the third transistor are coupled to the third node, the other end of the second transistor and the first end of the first resistor are coupled to the second node, the other end of the third transistor and the first end of the second resistor are coupled to the bias node, and the second end of the first resistor and the second end of the second resistor are coupled to the reference ground.

[0012] Optionally, a size ratio of the second transistor to the third transistor is equal to a resistance ratio of the second resistor to the first resistor.

[0013] Optionally, the first transistor, the second transistor and / or the third transistor include MOS transistors.

[0014] Optionally, the linearization bias module includes a third resistor and a fourth transistor, the first end of the third resistor is used to receive the supply voltage, the second end of the third resistor and one end of the fourth transistor are coupled to the first node, the gate of the fourth transistor is coupled to the second node, and the other end of the fourth transistor is coupled to the reference ground.

[0015] Optionally, the linearization bias module further includes a capacitor coupled between the second node and the reference ground.

[0016] In order to achieve the above object, the present invention further provides a power amplifier circuit, which includes a power amplifier tube and any of the above-mentioned voltage-type adaptive bias circuits.

[0017] In order to achieve the above object, the present invention further provides a chip on which any of the above-mentioned voltage-type adaptive bias circuits or the above-mentioned power amplifier circuits are integrated.

[0018] In order to achieve the above object, the present invention further provides an electronic device, comprising any one of the above-mentioned voltage-type adaptive bias circuits, or the above-mentioned power amplifier circuit, or the above-mentioned chip.

[0019] Compared with the prior art, the voltage-type adaptive bias circuit, power amplifier circuit, chip, and electronic device provided by the present invention have the following advantages:

[0020] The voltage-type adaptive bias circuit provided by the present invention includes a degrees of freedom adaptation module and the linearized bias module, and has a simple structure and is easy to implement. Furthermore, the degrees of freedom adaptation module and the linearized bias module form a negative feedback circuit structure. When the state of the power amplifier tube changes, causing the voltage of the bias node to change, the negative feedback circuit structure can stabilize the voltage of the bias node. By adjusting the linearized bias module, the depth of negative feedback can be adjusted. Thus, the voltage-type adaptive bias circuit provided by the present invention can improve design freedom while ensuring the stability of the static bias voltage of the gate of the power amplifier tube of the power amplifier circuit. It effectively ensures that the static operating point of the power amplifier tube and the bias adjustment capability of the voltage-type adaptive bias circuit are both in an optimal state, and can significantly improve the overall performance of the power amplifier circuit.

[0021] Furthermore, since the power amplifier circuit, chip, and electronic device provided by the present invention are based on the same inventive concept as the voltage-type adaptive bias circuit provided by the present invention, the power amplifier circuit, chip, and electronic device provided by the present invention have at least all the advantages of the voltage-type adaptive bias circuit provided by the present invention. For details on the beneficial effects of the power amplifier circuit, chip, and electronic device provided by the present invention, please refer to the above description of the beneficial effects of the voltage-type adaptive bias circuit provided by the present invention, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of the topological structure of a diode linearization bias circuit in the prior art;

[0023] Figure 2A schematic diagram of the topology of a power amplifier circuit provided in one embodiment of the present invention;

[0024] Figure 3 A structural block diagram of a voltage-type adaptive bias circuit provided in one embodiment of the present invention;

[0025] Figure 4 A schematic diagram of the topological structure of a specific example of the voltage-type adaptive bias circuit provided by the present invention;

[0026] The accompanying drawings are numerals as follows:

[0027] Transistors - M01, M02; Resistors - R01, R02;

[0028] Voltage type adaptive bias circuit-100;

[0029] Degree of freedom adaptation module 110, first transistor M1, first mirror signal branch 111, second transistor M2, first resistor R1, second mirror signal branch 112, third transistor M3, second resistor R2, linearization bias module 120, third resistor R3, fourth transistor M4, capacitor C;

[0030] Supply voltage - VDD1, VDD2, bias voltage - V bias , reference ground - GND;

[0031] First node - N1, second node - N2, third node - N3;

[0032] Power amplifier tubes-M03, M5, input matching network-200, output matching network-300. DETAILED DESCRIPTION

[0033] The following, in conjunction with the accompanying drawings, further details the voltage-type adaptive bias circuit, power amplifier circuit, chip, and electronic device proposed by the present invention. The following description will further clarify the advantages and features of the present invention. It should be noted that the drawings are simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the purpose of the embodiments of the present invention. To make the purposes, features, and advantages of the present invention more readily apparent, please refer to the drawings. It should be noted that the structures, proportions, and sizes illustrated in the drawings of this specification are intended solely to facilitate understanding and reading by those skilled in the art, and are not intended to limit the implementation of the present invention. Any structural modifications, changes in proportions, or adjustments in size, provided they produce the same or similar effects and achieve the same objectives as the present invention, are intended to fall within the scope of the technical content disclosed herein. The specific design features of the present invention disclosed herein, including, for example, specific dimensions, directions, positions, and shapes, will be determined in part by the specific application and environment in which they are intended. Furthermore, in the embodiments described below, the same reference numerals may be used across different drawings to denote the same parts or parts having the same functions, and their repeated descriptions may be omitted. In this specification, like reference numerals and letters are used to refer to like items, and thus, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0034] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element. The singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features.

[0035] It should be understood that when an element is referred to as being "connected," "connected to," or "coupled to" another element, it can be directly connected to the other element or there can be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly connected to" another element, there are no intervening elements.

[0036] The core concept of the present invention is to provide a voltage-type adaptive bias circuit, a power amplifier circuit, a chip, and an electronic device. While improving design freedom, the present invention can ensure the stability of the static bias voltage of the gate of the power amplifier tube of the power amplifier circuit, effectively ensure that the static operating point of the power amplifier tube and the bias adjustment capability of the voltage-type adaptive bias circuit are both in a relatively good state, and can significantly improve the overall performance of the power amplifier circuit.

[0037] It should be noted that the voltage-type adaptive bias circuit provided by the present invention can be used in the power amplifier circuit and electronic device provided by the present invention, and the power amplifier circuit and chip provided by the present invention can be used in the electronic device provided by the present invention. For example, the electronic devices include, but are not limited to, video products such as televisions, video recorders, and digital cameras, communication products such as mobile phones, communication switching equipment, and communication transmission equipment, and learning assistance products such as translators, learning machines, and electronic dictionaries, to name a few. Those skilled in the art will appreciate that the present invention does not impose any limitations on the electronic devices described.

[0038] Furthermore, to facilitate understanding of the present invention, this document uses the voltage-type adaptive bias circuit provided by the present invention as an example for application to a power amplifier circuit. However, this is not intended to limit the present invention. The voltage-type adaptive bias circuit provided by the present invention can be applied to any scenario where a voltage waveform changes. For example, the voltage-type adaptive bias circuit provided by the present invention can be used in power amplifiers, oscillators, and modulators, including but not limited to power amplifier circuits.

[0039] In order to realize the above idea, one embodiment of the present invention provides a voltage-type adaptive bias circuit for adjusting the bias state of a power amplifier circuit. For example, see Figure 2 and Figure 3 ,in, Figure 2 A schematic diagram of the topology of a power amplifier circuit provided in one embodiment of the present invention is shown. Figure 3 This is a structural block diagram of a voltage-type adaptive bias circuit provided by one embodiment of the present invention. Figure 2 It can be seen that the power amplifier circuit includes the voltage-type adaptive bias circuit 100 provided by the present invention, and the power amplifier circuit includes a power amplifier tube M5, the gate of the power amplifier tube M5 is coupled to the bias node ( Figure 2 and Figure 3Not marked in the figure, the bias voltage V at the bias node is used. bias Further, from Figure 3 As can be seen, the voltage-type adaptive bias circuit 100 includes a degrees-of-freedom adaptation module 110 and a linearized bias module 120. A first terminal of the degrees-of-freedom adaptation module 110 and a first terminal of the linearized bias module 120 are configured to receive a supply voltage VDD1. A control terminal of the degrees-of-freedom adaptation module 110 and a second terminal of the linearized bias module 120 are coupled to a first node N1. A second terminal of the degrees-of-freedom adaptation module 110 and a control terminal of the linearized bias module 120 are coupled to a second node N2. A third terminal of the degrees-of-freedom adaptation module 110 is coupled to the bias node. Furthermore, the degrees-of-freedom adaptation module 110 and the linearized bias module 120 form a negative feedback circuit structure. This negative feedback circuit structure is configured to stabilize the voltage of the bias node when a change in the state of the power amplifier transistor M5 causes a change in the voltage of the bias node, and to adjust the depth of the negative feedback by adjusting the linearized bias module 120.

[0040] The voltage-type adaptive bias circuit 100 provided by the present invention includes a degree of freedom adaptation module 110 and the linearization bias module 120, and has a simple structure and is easy to implement. Furthermore, the degree of freedom adaptation module 110 and the linearization bias module 120 form a negative feedback circuit structure. When the state change of the power amplifier tube M5 causes the voltage of the bias node to change, the negative feedback circuit structure can stabilize the voltage of the bias node. By adjusting the linearization bias module 120, the depth of negative feedback can be adjusted. Therefore, the voltage-type adaptive bias circuit 100 provided by the present invention can ensure the static bias voltage V of the gate of the power amplifier tube M5 of the power amplifier circuit while improving the degree of design freedom. bias The stability of the power amplifier circuit can be improved, and the static operating point of the power amplifier tube M5 and the bias adjustment capability of the voltage-type adaptive bias circuit can be effectively guaranteed to be in a better state, which can significantly improve the overall performance of the power amplifier circuit.

[0041] For example, when the working state of the power amplifier tube M5 changes and causes the voltage of the bias node to decrease, the voltage at the second node N2 is reduced by the freedom adaptation module 110, so that the voltage at the first node N1 is increased by the linearization bias module 120, and then the voltage of the bias node is raised by the freedom adaptation module 110. Thus, the voltage at the bias node can be stabilized through the negative feedback closed loop, thereby effectively ensuring the gate static bias voltage V bias stability.

[0042] For example, in some of the exemplary embodiments, see Figure 4 , Figure 4 This is a schematic diagram of the topology of a specific example of the voltage-type adaptive bias circuit provided by the present invention. Figure 4 As can be seen, the degree-of-freedom adaptation module 110 includes a first transistor M1, a first mirror signal branch 111, and a second mirror signal branch 112. One terminal of the first transistor M1 is configured to receive a supply voltage VDD1. The gate of the first transistor M1 is coupled to the first node N1. The other terminal of the first transistor M1, the first terminal of the first mirror signal branch 111, and the first terminal of the second mirror signal branch 112 are coupled to a third node N3. A second terminal of the first mirror signal branch 111 is coupled to the second node N2. A second terminal of the second mirror signal branch 112 is coupled to the bias node. A third terminal of the first mirror signal branch 111 and a third terminal of the second mirror signal branch 112 are coupled to a reference ground GND. Furthermore, the first mirror signal branch 111 and the second mirror signal branch 112 are configured to feed back voltage changes at the bias node to the linearization bias module 120, so that the linearization bias module 120 can adjust the operating state of the first transistor M1, thereby stabilizing the voltage at the bias node through the second mirror signal branch 112.

[0043] Thus, the voltage-type adaptive bias circuit 100 provided by the present invention can mirror the voltage change at the bias node to the second node N2 via the second mirror signal branch 112 and the first mirror signal branch 111. Furthermore, the linearized bias module 120 increases the voltage at the first node N1. This increases the gate voltage of the first transistor M1 operating in the linear region, reduces the on-resistance, and thereby raises the voltage at the bias node, achieving the effect of stabilizing the voltage at the bias node. Furthermore, the design of the degree-of-freedom adaptive module 110, which utilizes the first transistor M1, the first mirror signal branch 111, and the second mirror signal branch 112, is simple in structure and easy to implement.

[0044] It should be noted that those skilled in the art should understand that the design of the degree of freedom adaptation module 110 implemented using the first transistor M1, the first mirror signal branch 111, and the second mirror signal branch 112 is merely an exemplary description of a preferred embodiment, and is not intended to be limiting of the present invention. For example, in other embodiments, the degree of freedom adaptation module 110 may be implemented using other circuit structures other than the first transistor M1, the first mirror signal branch 111, and the second mirror signal branch 112. Such circuit structures are sufficient as long as they can achieve a reduction in the voltage at the second node N2 when the voltage at the bias node decreases, and increase the voltage at the first node N1 through the linearized bias module 120, thereby increasing the voltage at the bias node.

[0045] For example, in some exemplary embodiments, please continue to refer to Figure 4 ,like Figure 4 As shown, the first mirror signal branch 111 includes a second transistor M2 and a first resistor R1, and the second mirror signal branch 112 includes a third transistor M3 and a second resistor R2. The gate of the second transistor M2, one end of the second transistor M2, the gate of the third transistor M3, and one end of the third transistor M3 are coupled to the third node N3, the other end of the second transistor M2 and the first end of the first resistor R1 are coupled to the second node N2, the other end of the third transistor M3 and the first end of the second resistor R2 are coupled to the bias node, and the second end of the first resistor R1 and the second end of the second resistor R2 are coupled to the reference ground GND.

[0046] Therefore, in the voltage-type adaptive bias circuit 100 provided by the present invention, the second transistor M2 of the first mirror signal branch 111 and the third transistor M3 of the second mirror signal branch 112 are both connected in a diode manner, so that the first mirror signal branch 111 and the second mirror signal branch 112 play the role of diode linearization, which can significantly increase the gate static bias voltage V of the power amplifier tube M5. bias and can compensate for the gain compression phenomenon caused by the presence of the gate-source PN junction diodes of the second transistor M2 and the third transistor M3, so that the overall performance of the power amplifier tube M5 is significantly improved.

[0047] Preferably, in some preferred embodiments, the size ratio of the second transistor M2 to the third transistor M3 is equal to the resistance ratio of the second resistor R2 to the first resistor R1. Thus, by adopting a design in which the size ratio of the second transistor M2 to the third transistor M3 is equal to the resistance ratio of the second resistor R2 to the first resistor R1, the voltage at the other end (e.g., the drain) of the second transistor M2 and the other end (e.g., the drain) of the third transistor M3 are equal in static state, i.e., the voltage at the second node N2 and the bias node are equal in static state, thereby further improving the negative feedback accuracy of the degree of freedom adaptation module 110.

[0048] For example, in some exemplary embodiments, please continue to refer to Figure 4 ,like Figure 4 As shown, the first transistor M1, the second transistor M2, and / or the third transistor M3 include MOS transistors. It should be understood that the present invention does not impose excessive limitations on the first transistor M1, the second transistor M2, and the third transistor M3. For example, the first transistor M1, the second transistor M2, and the third transistor M3 may be, but are not limited to, NMOS transistors and PMOS transistors.

[0049] For example, in some exemplary embodiments, Figure 4 As shown, taking the first transistor M1, the second transistor M2, and the third transistor M3 as NMOS transistors as an example, one end (i.e., the drain) of the first transistor M1 is used to receive the supply voltage VDD1, the other end (i.e., the source) of the first transistor M1, the gate and one end (i.e., the drain) of the second transistor M2, and the gate and one end (i.e., the drain) of the third transistor M3 are coupled to a third node N3, the other end (i.e., the source) of the second transistor M2 is coupled to the second node N2, and the other end (i.e., the source) of the third transistor M3 is coupled to the bias node. Correspondingly, in some other exemplary embodiments, taking the first transistor M1, the second transistor M2, and the third transistor M3 as an example where all are PMOS transistors, one end (i.e., the source) of the first transistor M1 is used to receive the supply voltage VDD1, the other end (i.e., the drain) of the first transistor M1, the gate and one end (i.e., the source) of the second transistor M2, and the gate and one end (i.e., the source) of the third transistor M3 are coupled to a third node N3, the other end (i.e., the drain) of the second transistor M2 is coupled to the second node N2, and the other end (i.e., the drain) of the third transistor M3 is coupled to the bias node.

[0050] For example, in some exemplary embodiments, please continue to refer to Figure 4 ,like Figure 4 As shown, the linearization bias module 120 includes a third resistor R3 and a fourth transistor M4. A first end of the third resistor R3 is used to receive the supply voltage VDD1. A second end of the third resistor R3 and one end of the fourth transistor M4 are coupled to the first node N1. A gate of the fourth transistor M4 is coupled to the second node N2. The other end of the fourth transistor M4 is coupled to the reference ground GND.

[0051] The voltage-type adaptive bias circuit 100 provided by the present invention uses the third resistor R3 and the fourth transistor M4 to implement the design of the linear configuration module. This not only allows the negative feedback depth to be adjusted by adjusting the third resistor R3, thereby improving design freedom, but also has a simple structure and is easy to implement.

[0052] It should be noted that those skilled in the art should be able to understand that the present invention does not impose too many restrictions on the specific implementation of the fourth transistor M4. For example, the fourth transistor M4 can be, but is not limited to, a PMOS transistor or an NMOS transistor.

[0053] For example, in some exemplary embodiments, taking the fourth transistor as an NMOS transistor as an example, Figure 4 As shown, one end (i.e., the drain) of the fourth transistor M4 is coupled to the second end of the third resistor R3, and the other end (i.e., the source) of the fourth transistor M4 is coupled to the second node N2. In some other embodiments, taking the fourth transistor M4 as a PMOS transistor as an example, one end (i.e., the source) of the fourth transistor M4 is coupled to the second end of the third resistor R3, and the other end (i.e., the drain) of the fourth transistor M4 is coupled to the second node N2.

[0054] The following combination Figure 4 The working principle of the voltage-type adaptive bias circuit 100 provided by the present invention is described as follows:

[0055] When the input RF signal (Radio Frequency Signal) is small, the source voltage of the third transistor M3 (using a PMOS transistor as an example) is small. The third transistor M3 is turned on during the entire cycle of the RF signal, and the voltage-type adaptive bias circuit 100 outputs a voltage V at the bias node. biasStable and unchanged; when the input RF signal continues to increase, the source voltage of the third transistor M3 will be very large in part of the signal cycle, causing the third transistor M3 to be reverse biased, causing the DC (direct current) voltage at the source of the third transistor M3 to decrease, thereby increasing the gate-source voltage VGS of the third transistor M3, resulting in an increase in the current on the third transistor M3, which is converted into a voltage V at the bias node through the second resistor R2. bias Increase, thereby achieving the effect of compensating the amplifier tube gain when a large signal is input.

[0056] Furthermore, the degree of freedom adaptation module 110 and the linearization bias module 120 form a negative feedback circuit structure to realize the working principle of negative feedback as follows: the fourth transistor M4 works in the saturation region, the first transistor M1 works in the linear region, and when the working state of the power amplifier tube M5 changes, the voltage V bias When the voltage decreases, the currents of the second transistor M2 and the third transistor M3 decrease, the gate voltage of the fourth transistor M4 decreases, and the current flowing through the third resistor R3 decreases, causing the gate voltage of the first transistor M1 to increase and the on-resistance of the first transistor M1 to decrease, thereby causing the voltage V bias Thus, the voltage-type adaptive bias circuit 100 provided by the present invention can stabilize the voltage of the bias node, and can adjust the feedback depth by adjusting the resistance value of the third resistor R3. This configuration can effectively ensure that the static operating point of the power amplifier tube M5 and the bias adjustment capability of the linearized bias circuit are both in an optimal state, and significantly improve the overall performance of the power amplifier circuit.

[0057] For example, in some exemplary embodiments, please continue to refer to Figure 4 ,like Figure 4 As shown, the linearization bias module 120 further includes a capacitor C coupled between the second node N2 and the reference ground GND. Thus, the capacitor C can filter out high-frequency interference signals, reduce regulation sensitivity, and stabilize node voltage.

[0058] Another embodiment of the present invention provides a power amplifier circuit. For example, see Figure 2 ,like Figure 2 As shown, the power amplifier circuit provided by the present invention includes a power amplifier tube M5 and the voltage-type adaptive bias circuit 100 described in any of the above embodiments. Figure 2 As shown, the power amplifier circuit also includes an input matching network 200 for receiving radio frequency signals and an output matching network 300 for sending radio frequency signals. For more detailed information about the power amplifier circuit, please refer to the relevant technical adaptability understanding known to those skilled in the art. Due to space limitations, this article will not elaborate on this.

[0059] Yet another embodiment of the present invention provides a chip on which the voltage-type adaptive bias circuit described in any one of the above embodiments or the power amplifier circuit described in any one of the above embodiments is integrated.

[0060] Another embodiment of the present invention provides an electronic device, which includes the voltage-type adaptive bias circuit V described in any of the above embodiments. bias Or the power amplifier circuit described in any of the above embodiments, or the above chip.

[0061] Since the chip provided by the present invention and the voltage-type adaptive bias circuit or power amplifier circuit provided by the present invention are based on the same inventive concept, the electronic device provided by the present invention and the voltage-type adaptive bias circuit, power amplifier circuit, or chip provided by the present invention are based on the same inventive concept, and the power amplifier circuit provided by the present invention and the voltage-type adaptive bias circuit provided by the present invention are based on the same inventive concept, the chip and electronic device provided by the present invention have at least all the advantages of the voltage-type adaptive bias circuit provided by the present invention. For details on the beneficial effects of the chip and electronic device provided by the present invention, please refer to the above description of the beneficial effects of the voltage-type adaptive bias circuit provided by the present invention, and will not be repeated here.

[0062] It is particularly important to note that, as those skilled in the art will appreciate, the present invention does not impose any limitation on the specific value of the supply voltage; the two may be the same or different, and should be reasonably set according to actual needs when implementing the present invention.

[0063] It should be noted that the functional modules in the various embodiments of this document may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0064] Compared with the prior art, the voltage-type adaptive bias circuit, power amplifier circuit, chip, and electronic device provided by the present invention have the following advantages:

[0065] The voltage-type adaptive bias circuit provided by the present invention includes a degrees of freedom adaptation module and the linearized bias module, and has a simple structure and is easy to implement. Furthermore, the degrees of freedom adaptation module and the linearized bias module form a negative feedback circuit structure. When the state of the power amplifier tube changes, causing the voltage of the bias node to change, the negative feedback circuit structure can stabilize the voltage of the bias node. By adjusting the linearized bias module, the depth of negative feedback can be adjusted. Thus, the voltage-type adaptive bias circuit provided by the present invention can improve design freedom while ensuring the stability of the static bias voltage of the gate of the power amplifier tube of the power amplifier circuit. It effectively ensures that the static operating point of the power amplifier tube and the bias adjustment capability of the voltage-type adaptive bias circuit are both in an optimal state, and can significantly improve the overall performance of the power amplifier circuit.

[0066] The foregoing description merely describes preferred embodiments of the voltage-type adaptive bias circuit, power amplifier circuit, chip, and electronic device provided by the present invention and does not limit the scope of the present invention. Any changes or modifications made by persons skilled in the art based on the foregoing disclosure are considered within the scope of protection of the present invention. Obviously, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the present invention. Thus, if such modifications and variations fall within the scope of the present invention and its equivalents, the present invention is intended to encompass such modifications and variations.

Claims

1. A voltage-type adaptive bias circuit for adjusting the bias state of a power amplifier circuit, characterized in that: The power amplifier circuit includes a power amplifier tube, the gate of which is coupled to a bias node; the voltage-type adaptive bias circuit includes a degree of freedom adaptation module and a linearization bias module, a first end of the degree of freedom adaptation module and a first end of the linearization bias module are used to receive a supply voltage, a control end of the degree of freedom adaptation module and a second end of the linearization bias module are coupled to a first node, a second end of the degree of freedom adaptation module and a control end of the linearization bias module are coupled to a second node, and a third end of the degree of freedom adaptation module is coupled to the bias node; The degree of freedom adaptation module and the linearization bias module constitute a negative feedback circuit structure, which is configured to stabilize the voltage of the bias node when the state change of the power amplifier tube causes the voltage of the bias node to change, and adjust the negative feedback depth by adjusting the linearization bias module.

2. The voltage-type adaptive bias circuit according to claim 1, wherein: The degree of freedom adaptation module includes a first transistor and a first mirror signal branch and a second mirror signal branch, wherein one end of the first transistor is used to receive a supply voltage, a gate of the first transistor is coupled to the first node, the other end of the first transistor, a first end of the first mirror signal branch, and a first end of the second mirror signal branch are coupled to a third node, a second end of the first mirror signal branch is coupled to the second node, a second end of the second mirror signal branch is coupled to the bias node, and a third end of the first mirror signal branch and a third end of the second mirror signal branch are coupled to a reference ground; The first mirror signal branch and the second mirror signal branch are configured to feed back the voltage change of the bias node to the linearization bias module, so as to adjust the working state of the first transistor through the linearization bias module, thereby stabilizing the voltage of the bias node.

3. The voltage-type adaptive bias circuit according to claim 2, wherein: The first mirror signal branch includes a second transistor and a first resistor, and the second mirror signal branch includes a third transistor and a second resistor. The gate of the second transistor, one end of the second transistor, the gate of the third transistor, and one end of the third transistor are coupled to the third node, the other end of the second transistor and the first end of the first resistor are coupled to the second node, the other end of the third transistor and the first end of the second resistor are coupled to the bias node, and the second end of the first resistor and the second end of the second resistor are coupled to the reference ground.

4. The voltage-type adaptive bias circuit according to claim 3, wherein: A ratio of the sizes of the second transistor to the third transistor is equal to a ratio of the resistance values of the second resistor to the first resistor.

5. The voltage-type adaptive bias circuit according to claim 3, wherein: The first transistor, the second transistor and / or the third transistor include MOS transistors.

6. The voltage-type adaptive bias circuit according to claim 1, wherein: The linearization bias module includes a third resistor and a fourth transistor. A first end of the third resistor is used to receive the supply voltage. A second end of the third resistor and one end of the fourth transistor are coupled to the first node. A gate of the fourth transistor is coupled to the second node. The other end of the fourth transistor is coupled to a reference ground.

7. The voltage-type adaptive bias circuit according to claim 6, wherein: The linearization bias module further includes a capacitor coupled between the second node and the reference ground.

8. A power amplifier circuit, characterized in that: The invention comprises a power amplifier tube and a voltage-type adaptive bias circuit as claimed in any one of claims 1 to 7.

9. A chip, characterized in that: The voltage-type adaptive bias circuit according to any one of claims 1 to 7 or the power amplifier circuit according to claim 8 is integrated thereon.

10. An electronic device, characterized in that: The device comprises the voltage-type adaptive bias circuit according to any one of claims 1 to 7, or the power amplifier circuit according to claim 8, or the chip according to claim 9.

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