Three-node upset-tolerant latch circuit and chip based on polarity reinforcement technology

Abstract

The present invention discloses a three-node flip-tolerant latch circuit and chip based on polarity reinforcement technology, and relates to the technical field of integrated circuit design. The present invention provides a three-node flip-tolerant latch circuit based on polarity reinforcement technology, comprising: a pull-up tube portion, a pull-down tube portion, a signal inverting portion, a C unit portion, a transmission tube portion, and a transmission gate portion. The present invention adopts a combination of polarity reinforcement and C units to reduce the number of sensitive nodes in the circuit, and cooperates with the signal inverting portion, the transmission tube portion, and the transmission gate portion to enable the circuit to have complete SNU self-recovery capability and complete DNU and TNU tolerance capability; the circuit of the present invention has improved indicators such as power consumption, delay power consumption product, and comprehensive radiation resistance compared to existing circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and more specifically, to: 1. a three-node upset (TNU)-tolerant latch circuit based on polarity reinforcement technology (which may be referred to as an LSTNUT circuit); 2. a latch chip packaged based on the three-node upset-tolerant latch circuit based on polarity reinforcement technology. Background Art

[0002] In recent years, with the continuous shrinking of semiconductor manufacturing process nodes, the probability of soft errors within nanoscale memory circuit chips when bombarded by cosmic ray particles has continued to increase. Furthermore, because the electron-hole pair cloud generated by heavy ion bombardment is larger than the transistor size, nanoscale memory circuit chips are also more susceptible to node upsets (including single-node upsets (SNU), double-node upsets (DNU), and triple-node upsets (TNU). In radiation environments, latch circuits bombarded by heavy ions can affect the reliability of memory chips. Therefore, radiation protection for memory circuits is necessary and urgently needs to be addressed.

[0003] In the prior art, there are several typical solutions for latch anti-TNU design:

[0004] 1) In 2021, Huang et al. proposed a memory circuit (abbreviated as IHTRL circuit), whose structure is as follows Figure 1 As shown in Figure 1. The IHTRL circuit uses C-cells to construct a multi-level feedback loop and add redundant nodes to design a latch circuit. When DNU and TNU occur in the circuit, if two inputs of the same C-cell experience SEU, the output of that C-cell flips. However, since the subsequent C-cells are in a high-impedance state or remain normal, their outputs maintain the correct logic value. The erroneous signal is then restored through the feedback loop to achieve multi-node flip self-recovery of the latch circuit. However, this circuit uses multiple levels of C-cells to increase redundant nodes, resulting in an increase in the number of transistors. Furthermore, the circuit has a large amount of gate capacitance and leakage current that generates power consumption, resulting in high power consumption overhead.

[0005] 2) In 2021, Yan et al. proposed a memory structure (abbreviated as LCTNUT circuit), which is as follows Figure 2As shown in Figure 2, the LCTNUT circuit uses multiple stages of dual-input inverters in series to design the circuit and increase redundant nodes. In transparent mode, the input signal is directly written out of the storage node and output node through a transmission gate, reducing propagation delay. In hold mode, the internal node transmits the stored signal to the output signal Q through two stages of C cells. When an SNU occurs, the error is directly blocked by the dual-input inverter, and the erroneous signal is restored to a correct state through subsequent storage nodes. When a DNU or TNU occurs, the multiple stages of dual-input inverters in series ensure that a storage node exists after the node where the error flipped, which can restore the erroneous node. Therefore, this circuit can effectively suppress DNU and TNU, achieving dual-node and triple-node self-recovery. However, the use of multiple stages of dual-input inverters in the circuit design results in a large number of transistors, resulting in high circuit power consumption and area overhead, and thus poor radiation resistance compared to similar radiation-hardened storage circuits.

[0006] 3) In 2023, HUANG et al. proposed a memory structure (referred to as FATNU circuit), which is as follows Figure 3 The FATNU circuit uses an approximate C-cell structure to design the circuit. Feedback loops are coupled to add internal storage nodes, and transmission tubes and gates are used to write input signals to polarity-hardened nodes and other nodes. When the circuit is bombarded by radiation particles, some of the polarity-hardened nodes act as insensitive nodes, reducing the possibility of multiple node flips. Furthermore, if other nodes flip simultaneously, the approximate C-cells block the erroneous signal, allowing it to be recovered through the correct signal at the next stage. However, this design approach uses a large number of approximate C-cells to construct the storage nodes, resulting in a large circuit area overhead.

[0007] 4) In 2024, Xu et al. proposed a memory structure (referred to as DOCTRL circuit) with the following structure: Figure 4 As shown in Figure 2, the DOCTRL circuit uses dual-output C-cells to construct a multi-stage feedback loop and add redundant nodes to design a latch circuit. When a DNU or TNU condition occurs in one of the dual-output C-cells in the circuit, the output of the subsequent C-cells remains in a high-impedance state or a normal state, maintaining the correct logic value. The erroneous signal is then restored through the feedback loop, achieving multi-node flip self-recovery in the latch circuit. However, the output node Q of this circuit controls internal nodes, resulting in a large delay. Furthermore, the circuit uses a large number of transistors to increase the redundant nodes, resulting in a large circuit area overhead. Summary of the Invention

[0008] Based on this, it is necessary to provide a three-node flip-tolerant latch circuit and chip based on polarity reinforcement technology to address the problems of large delay and high power consumption in existing anti-TNU circuits.

[0009] The present invention is achieved by adopting the following technical solutions:

[0010] In a first aspect, the present invention provides a three-node flip-tolerant latch circuit based on polarity reinforcement technology, comprising: a pull-up tube portion, a pull-down tube portion, a signal inversion portion, a C unit portion, a transmission tube portion, and a transmission gate portion.

[0011] The pull-up transistor is used to pull up storage nodes X1 to X8 in conjunction with power supply VDD. The pull-down transistor is used to pull down storage nodes X1 to X8 in conjunction with ground GND. X1 to X8 are N-polarity reinforcement nodes.

[0012] The signal inversion unit includes two inverters INV1 and INV2. INV1 is used to convert the input signal D into an inverted input signal DN; INV2 is used to convert the clock signal CLK into an inverted clock signal NCK.

[0013] The C unit section includes: C unit 1, C unit 2, and C unit 3. C unit 1 includes two PMOS transistors P1 and P2 and two NMOS transistors N25 and N26, which generate intermediate signal X9 based on X1 and X5. C unit 2 includes two PMOS transistors P3 and P4 and two NMOS transistors N27 and N28, which generate intermediate signal X10 based on X3 and X7. C unit 3 includes three PMOS transistors P5 and P7 and three NMOS transistors N29 and N31, which generate output signal Q based on X9, X10, CLK, and NCK.

[0014] The transmission tube part includes: 8 NMOS tubes N17~N24, which are used to connect D to X1, X3, X5, and X7 through N17, N18, N19, and N20 respectively when CLK=1, and connect DN to X4, X6, and X8 respectively through N22, N23, and N24.

[0015] The transmission gate section includes: 1 transmission gate G1, which is used to connect D to Q through G1 when CLK=1.

[0016] The implementation of the three-node upset-tolerant latch circuit based on polarity reinforcement technology is a method or process according to an embodiment of the present disclosure.

[0017] In a second aspect, the present invention discloses a three-node flip-tolerant latch chip based on polarity reinforcement technology, which is packaged using the three-node flip-tolerant latch circuit based on polarity reinforcement technology disclosed in the first aspect.

[0018] The implementation of the three-node upset tolerant latch based on polarity reinforcement technology is a method or process according to an embodiment of the present disclosure.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] 1. The present invention provides a three-node flip-tolerant latch circuit based on polarity reinforcement technology. By combining polarity reinforcement with C units, the number of sensitive nodes in the circuit is reduced. Combined with a signal inversion unit, a transmission tube unit, and a transmission gate unit, the circuit is equipped with complete SNU self-recovery capability and complete DNU and TNU tolerance. Compared with existing circuits, the circuit of the present invention has improved power consumption, delay-power product, and comprehensive radiation resistance.

[0021] 2. The circuit of the present invention uses a relatively small number of transistors, requiring only 44 transistors at the minimum to complete the circuit, which can effectively reduce the circuit area occupied. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 1 is a circuit structure diagram of the IHTRL circuit mentioned in the background technology of the present invention;

[0024] Figure 2 1 is a circuit structure diagram of the LCTNUT circuit mentioned in the background technology of the present invention;

[0025] Figure 3 1 is a circuit structure diagram of the FATNU circuit mentioned in the background technology of the present invention;

[0026] Figure 4 1 is a circuit structure diagram of the DOCTRL circuit mentioned in the background technology of the present invention;

[0027] Figure 5 A circuit structure diagram of the LSTNUT circuit provided in Example 1 of the present invention;

[0028] Figure 6 for Figure 5 Circuit structure diagram of inverters INV1~INV2;

[0029] Figure 7 for Figure 5 Circuit structure diagram of transmission gate G1;

[0030] Figure 8 for Figure 5 The timing waveform of the LSTNUT circuit with single node bombardment;

[0031] Figure 9 for Figure 5The timing waveform of the LSTNUT circuit with double node bombardment;

[0032] Figure 10 for Figure 5 The timing waveform diagram of the LSTNUT circuit achieving self-recovery when three nodes are bombarded;

[0033] Figure 11 for Figure 5 The timing waveform diagram of achieving fault tolerance when three nodes are bombarded in the LSTNUT circuit;

[0034] Figure 12 This is a performance comparison chart of five circuits provided in Example 2 of the present invention;

[0035] Figure 13 This is a pinout diagram of a three-node upset-tolerant latch chip based on polarity reinforcement technology provided in Example 3 of the present invention. DETAILED DESCRIPTION

[0036] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0037] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component. When a component is considered to be "fixed to" another component, it may be directly fixed to the other component or there may be a central component.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0039] Example 1

[0040] See Figure 5 , which is a circuit structure diagram of the LSTNUT circuit provided in this embodiment 1.

[0041] like Figure 5As shown, from a functional perspective, the LSTNUT includes: a pull-up tube part, a pull-down tube part, a signal inversion part, a C unit part, a transmission tube part, and a transmission gate part.

[0042] The following are the details:

[0043] 1. The pull-up tube portion is used to pull up the storage nodes X1 to X8 in conjunction with the power supply VDD; the pull-down tube portion is used to pull down the storage nodes X1 to X8 in conjunction with the ground GND.

[0044] It should be emphasized that X1~X8 are N-polarity reinforcement points.

[0045] In this embodiment 1, the upper pull tube portion and the lower pull tube portion can be designed as follows:

[0046] The pull-up tube section includes: 8 PMOS tubes N1~N4, N9~N12; the pull-down tube section includes: 8 NMOS tubes N5~N8, N13~N16.

[0047] like Figure 5 As shown, the sources of N1~N4 and N9~N12 are connected to VDD;

[0048] The drains of N5~N8 and N13~N16 are connected to GND;

[0049] The drain of N1, the source of N5, the gate of N3, and the gate of N6 are connected to X1;

[0050] The drain of N2, the source of N6, the gate of N4, and the gate of N7 are connected to X2;

[0051] The drain of N3, the source of N7, the gate of N1, and the gate of N8 are connected to X3;

[0052] The drain of N4, the source of N8, the gate of N2, and the gate of N5 are connected to X4;

[0053] The drain of N9, the source of N13, the gate of N11, and the gate of N14 are connected to X5;

[0054] The drain of N10, the source of N14, the gate of N12, and the gate of N15 are connected to X6;

[0055] The drain of N11, the source of N15, the gate of N9, and the gate of N16 are connected to X7;

[0056] The drain of N12, the source of N16, the gate of N10, and the gate of N13 are connected to X8.

[0057] Specifically, X1 is the connection node between N1 and N5; X2 is the connection node between N2 and N6; X3 is the connection node between N3 and N7; X4 is the connection node between N4 and N8; X5 is the connection node between N9 and N13; X6 is the connection node between N10 and N14; X7 is the connection node between N11 and N15; and X8 is the connection node between N12 and N16. Based on the principle of N-polarity hardening, when an SEU occurs at these eight nodes, only "1→0" and "0→0" voltage pulses are generated, meaning only negative-going pulses are generated. Therefore, if the data stored at these eight nodes is 0, the voltage state remains unchanged when an SEU occurs, and they are not sensitive nodes.

[0058] Furthermore, in this first embodiment, the recommended MOS transistor parameter configuration is: all MOS transistors have a gate length of 30 nm and a gate width of 100 nm. Furthermore, to reduce power consumption and mitigate threshold loss, low-threshold devices are recommended for N1-N4 and N9-N12, and standard-threshold devices are recommended for the remaining MOS transistors.

[0059] 2. The signal inversion unit includes two inverters INV1 and INV2. INV1 is used to convert the input signal D into an inverted input signal DN; INV2 is used to convert the clock signal CLK into an inverted clock signal NCK.

[0060] Specifically, the input end of INV1 is connected to D, and the output end is connected to DN. The input end of INV2 is connected to CLK, and the output end is connected to NCK.

[0061] Considering the circuit area occupied, INV1 and INV2 are recommended to adopt a simple design of one NMOS tube and one PMOS tube. Figure 6 INV1 includes one PMOS transistor P8 and one NMOS transistor N32. P8's gate is connected to N32's gate and serves as INV1's input. P8's drain is connected to N32's drain and serves as INV1's output. P8's source is connected to VDD, and N32's drain is connected to GND. INV2 includes one PMOS transistor P9 and one NMOS transistor N33. P9's gate is connected to N33's gate and serves as INV2's input. P9's drain is connected to N33's drain and serves as INV2's output. P9's source is connected to VDD, and N33's drain is connected to GND.

[0062] 3. The C unit section includes: C unit 1, C unit 2, and C unit 3.

[0063] 301. Unit C 1 includes two PMOS transistors P1 and P2 and two NMOS transistors N25 and N26, which are used to generate an intermediate signal X9 based on X1 and X5. Specifically, P1's gate is connected to X1, and its source is connected to VDD; P2's gate is connected to X5, its source is connected to P1's drain, and its drain is connected to X9; N25's gate is connected to X5, its source is connected to X9; N26's gate is connected to X1, its source is connected to N25's drain, and its drain is connected to ground GND.

[0064] 302. Unit C 2 includes two PMOS transistors P3 and P4 and two NMOS transistors N27 and N28, which are used to generate intermediate signal X10 based on X3 and X7. Specifically, P3's gate is connected to X3, and its source is connected to VDD; P4's gate is connected to X7, its source is connected to P3's drain, and its drain is connected to X10; N27's gate is connected to X7, its source is connected to X10; N28's gate is connected to X3, its source is connected to N27's drain, and its drain is connected to ground GND.

[0065] 303. Unit C 3 includes: three PMOS transistors P5-P7 and three NMOS transistors N29-N31, which are used to generate output signal Q based on X9, X10, CLK, and NCK. Specifically, P5's gate is connected to X9, and its source is connected to VDD; P6's gate is connected to X10, and its source is connected to P5's drain; P7's gate is connected to CLK, its source is connected to P6's drain, and its drain is connected to Q; N29's gate is connected to NCK, and its source is connected to Q; N30's gate is connected to X10, and its source is connected to N29's drain; N31's gate is connected to X9, its source is connected to N30's drain, and its drain is connected to ground GND.

[0066] For the aforementioned C cell, when its input values ​​are the same, it acts as an inverter: that is, when all input values ​​are the same, its output value is the inverse of the input value. However, when the input value of the C cell changes, its output can temporarily maintain the previous value (entering a high-impedance state). This means that if the change in the input value of the C cell is caused by an error, the C cell can intercept the error. Therefore, the only sensitive nodes in the C cell are X9, X10, and Q.

[0067] 4. The transmission tube part includes: 8 NMOS tubes N17~N24.

[0068] The transmission pipe part is used to connect D to X1, X3, X5, and X7 through N17, N18, N19, and N20 respectively, and to connect DN to X4, X6, and X8 through N22, N23, and N24 respectively when CLK=1;

[0069] In addition, it should be noted that when CLK=0, the transmission pipe keeps D disconnected from X1, X3, X5, and X7, and keeps DN disconnected from X4, X6, and X8.

[0070] In this embodiment 1, the transmission pipe portion can be designed as follows:

[0071] The gates of N17 to N24 are connected to CLK; the sources of N17 to N24 are connected to D;

[0072] The drain of N17 is connected to X1; the drain of N18 is connected to X2; the drain of N19 is connected to X3; the drain of N20 is connected to X4; the drain of N21 is connected to X5; the drain of N22 is connected to X6; the drain of N23 is connected to X7; and the drain of N24 is connected to X8.

[0073] 5. The transmission gate portion includes: 1 transmission gate G1.

[0074] The transmission gate is used to connect D to Q through G1 when CLK=1.

[0075] Also note that when CLK=0, the transmission gate keeps D and Q disconnected.

[0076] In this embodiment 1, see Figure 7 , the transmission gate part can be designed as:

[0077] The input end of G1 is connected to D, the output end is connected to Q, the control end of C is connected to CLK, and the control end of C' is connected to NCK.

[0078] Considering circuit area usage, G1 is recommended to adopt a simple design consisting of one NMOS transistor and one PMOS transistor. Specifically, G1 consists of one PMOS transistor, P10, and one NMOS transistor, N34. The source of N34 is connected to the source of P10 and serves as the input of G1. The drain of N34 is connected to the drain of P10 and serves as the output of G1. The gate of N34 serves as the C control terminal of TG1, and the gate of P10 serves as the C' control terminal of G1.

[0079] In general, to construct the LSTNUT circuit of the above structure, at least 34 NMOS tubes and 10 PMOS tubes are required - a total of 44 MOS tubes.

[0080] Based on the above LSTNUT circuit:

[0081] When CLK=1, NCK=0, the transmission gate and transmission tube are open, and the LSTNUT circuit is in transparent mode; D is directly output to Q through G1; D is written to X1, X3, X5, and X7 respectively through N17, N18, N19, and N20; DN is written to X2, X4, X6, and X8 respectively through N21, N22, N23, and N24; X1 and X5 are written to X9 through C unit 1; X3 and X7 are written to X10 through C unit 2; the data is latched.

[0082] When CLK=0, NCK=1, the transmission gate and transmission tube are cut off (no data is written anymore), and the LSTNUT circuit is in hold mode; the P7 and N29 channels of C unit three make X9 and X10 output to Q through C unit three, keeping data Q stable.

[0083] It's important to note that the bombardment occurred in hold mode. When a storage node is bombarded, the LSTNUT circuit achieves: 1. Complete SNU self-recovery; 2. Complete DNU and TNU tolerance (supporting partial node self-recovery while ensuring Q stability). Therefore, it can be said that the LSTNUT circuit fully tolerates SNU, DNU, and TNU.

[0084] The SNU, DNU, and TNU tolerance mechanisms of this LSTNUT circuit are introduced as follows: Taking the storage data as 1 as an example, that is, X1=X3=X5=X7=Q=1, X2=X4=X6=X8=X9=X10=0.

[0085] Referring to the above description, due to the use of polarity reinforcement and C unit, there are 7 sensitive nodes - X1, X3, X5, X7, X9, X10, and Q.

[0086] (1) SNU self-recovery mechanism:

[0087] SNU contains 7 situations in total.

[0088] 101: SNU X1, X3, X5, or X7 occurs - Since this part has a symmetrical structure, it is only necessary to analyze the case where one of the nodes flips.

[0089] For example, if an SNU occurs at X1, X1 flips from 1 to 0, turning off N6 and N3. X2 is unaffected by the SNU, so its state remains unchanged. N7 turns off, X3 remains in a high-impedance state, and N8 turns on. X4 remains unchanged. N1's gate is controlled by X3, and N5's gate by X4. Therefore, X3 and X4 restore X1, and Q remains unaffected.

[0090] 102: SNU occurs at X9 or X10 - Since this part has a symmetrical structure, only the flipping of one of the nodes needs to be analyzed.

[0091] For example, if an SNU occurs at X9, the state of X9 flips from 0 to 1, the state of X10 remains unchanged, and C unit 3 is in a high-impedance state, preventing the error signal from being transmitted to Q. Other nodes are unaffected by the SNU, and X9 is restored to its normal state through C unit 1.

[0092] 103: When SNU occurs in Q, the internal storage nodes are not affected by the SNU and therefore all remain in the correct state. Q is restored to the correct state through C unit three.

[0093] In addition, for ease of understanding, this embodiment 1 also performs simulation verification on the SNU. The simulation status is shown in Table 1, and the corresponding timing waveform is shown in Table 1. Figure 8 shown.

[0094] Table 1 SNU simulation verification table

[0095]

[0096] (2) DNU tolerance mechanism:

[0097] DNU contains 21 situations in total.

[0098] 201: DNU occurs in<X1,X3> or<X5,X7> .

[0099] by<X1,X3> For example, consider a DNU error: X1 and X3 flip from 1 to 0, turning off N1, N3, N6, and N8, while X2 and X4 remain at 0. N2, N4, N5, and N7 also remain off. Consequently, X1, X2, X3, and X4 enter a high-impedance state, preventing them from recovering from the error signal. At this point, the input signals to C units 1 and 2 are X1 = X3 = 0 and X5 = X7 = 1, resulting in a high-impedance state for C units 1 and 2. This prevents the error signal from being transmitted to X9 and X10, and thus to Q. This achieves DNU error tolerance. Note that X1 and X3 cannot self-recover.

[0100] <X5,X7> and<X1,X3> The principle is similar and will not be described in detail.

[0101] 202: DNU occurs in<X1,X5> or<X1,X7> or<X3,X5> or<X3,X7> .

[0102] by<X1,X5> For example, if a DNU occurs, X1 and X5 flip from 1 to 0. For the SNU case, refer to the above description. Therefore, both X1 and X5 can recover, and Q will not be affected.

[0103] <X1,X7> 、<X3,X5> 、<X3,X7> and<X1,X5> The principle is similar and will not be described in detail.

[0104] 203: DNU occurs in<X1,X9> 、<X3,X9> 、<X5,X9> 、<X7,X9> 、<X1,X10> 、<X3,X10> 、<X5,X10> 、<X7,X10> 、<X1,Q> 、<X3,Q> 、<X5,Q> 、<X7,Q> Any of the scenarios.

[0105] by<X1,X9> For example, consider a DNU event: X1 flips from 1 to 0, and X9 flips from 0 to 1. For the SNU event on X1, see the description above. While X9 changes, X10 remains unaffected by the DNU event. Therefore, C unit 3 remains in a high-impedance state, and Q does not flip. After X1 recovers, X1 and X5 restore X9 through C unit 1.

[0106] <X1,X9> 、<X3,X9> 、<X5,X9> 、<X7,X9> 、<X1,X10> 、<X3,X10> 、<X5,X10> 、<X7,X10> 、<X1,Q> 、<X3,Q> 、<X5,Q> 、<X7,Q> and<X1,X9> The principle is similar and will not be repeated here.

[0107] 204: DNU occurs in<X9,X10> or<X9,Q> or<X10,Q> .

[0108] by<X9,X10> Take DNU as an example: X9 and X10 flip from 0 to 1, and both inputs of C unit 3 flip, so Q flips. Other nodes are not affected by DNU. X1, X3, X5, and X7 restore X9 and X10 through C unit 1 and C unit 2, and X9 and X10 restore Q through C unit 3.

[0109] <X9,Q> 、<X10,Q> and<X9,X10> The principle is similar and will not be repeated here.

[0110] In addition, for ease of understanding, this embodiment 1 also performs simulation verification on DNU. The simulation status is shown in Table 2, and the corresponding timing waveform is shown in Table 2. Figure 9 shown.

[0111] Table 2 DNU simulation verification table

[0112]

[0113] (3) TNU tolerance mechanism:

[0114] TNU contains a total of 35 situations.

[0115] 301: TNU occurs in<X1,X9,X10> 、<X1,X9,Q> 、<X1,X10,Q> 、<X3,X9,X10> 、<X3,X9,Q> 、<X3,X10,Q> 、<X5,X9,X10> 、<X5,X9,Q> 、<X5,X10,Q> 、<X7,X9,X10> 、<X7,X9,Q> 、<X7,X10,Q> 、<X1,X5,X9> 、<X1,X5,X10> 、<X1,X5,Q> 、<X3,X5,X9> 、<X3,X5,X10> 、<X3,X5,Q> 、<X1,X7,X9> 、<X1,X7,X10> 、<X1,X7,Q> 、<X3,X7,X9> 、<X3,X7,X10> 、<X3,X7,Q> 、<X9,X10,Q> Any of the scenarios.

[0116] by<X1,X9,X10> Take TNU as an example: X1 has SNU,<X9,X10> For the situation where DNU occurs, please refer to the above record; therefore, the status of X1, X3, X5, and X7 are all correct, and X9 and X10 are restored through C unit 1 and C unit 2, and X9 and X10 are then restored to Q through C unit 3.

[0117] <X1,X9,Q> 、<X1,X10,Q> 、<X3,X9,X10> 、<X3,X9,Q> 、<X3,X10,Q> 、<X5,X9,X10> 、<X5,X9,Q> 、<X5,X10,Q> 、<X7,X9,X10> 、<X7,X9,Q> 、<X7,X10,Q> 、<X1,X5,X9> 、<X1,X5,X10> 、<X1,X5,Q> 、<X3,X5,X9> 、<X3,X5,X10> 、<X3,X5,Q> 、<X1,X7,X9> 、<X1,X7,X10> 、<X1,X7,Q> 、<X3,X7,X9> 、<X3,X7,X10> 、<X3,X7,Q> 、<X9,X10,Q> The principle is similar and will not be repeated here.

[0118] 302: TNU occurs in<X1,X3,X5> 、<X1,X3,X7> 、<X1,X5,X7> 、<X3,X5,X7> 、<X1,X3,X9> 、<X1,X3,X10> 、<X1,X3,Q> 、<X5,X7,X9> 、<X5,X7,X10> 、<X5,X7,Q> Any of the scenarios.

[0119] by<X1,X3,X5> Take TNU as an example:<X1,X3> For DNU and SNU at X5, refer to the above description. Therefore, X1 = X3 = 0, X5 = X7 = 1, causing C1 and C2 to enter a high-impedance state. The states of X9 and X10 remain unchanged, so Q does not change. It should be noted that X1 and X3 cannot achieve self-recovery.

[0120] <X1,X3,X7> 、<X1,X5,X7> 、<X3,X5,X7> 、<X1,X3,X9> 、<X1,X3,X10> 、<X1,X3,Q> 、<X5,X7,X9> 、<X5,X7,X10> 、<X5,X7,Q> The principle is similar and will not be repeated here.

[0121] In addition, for ease of understanding, this embodiment 1 also performs simulation verification on TNU. The simulation states are shown in Table 3 and Table 4, and the corresponding timing waveforms are shown in Table 3 and Table 4. Figure 10 、 Figure 11 As shown in Table 3. Figure 10 Table 4 shows the situation of node self-recovery when TNU occurs. Figure 11 Demonstrates how to achieve fault tolerance when TNU occurs.

[0122] Table 3 TNU simulation verification table 1

[0123]

[0124] Table 4 TNU simulation verification Table 2

[0125]

[0126] Example 2

[0127] This embodiment 2 simulates and compares the LSTNUT circuit proposed in embodiment 1 (using a 44-transistor design) with the other four latch circuits proposed in the background art, and compares the relevant performance: the delay time from D to Q (Tdq), the delay time from CLK to Q (Tcq), the average power consumption of the circuit, the delay power product (PDP) of the latch, and the comprehensive radiation resistance performance.

[0128] 1. The results of Tdq, Tcq, average power consumption of the circuit, and PDP are shown in Figure 12 .

[0129] Depend on Figure 12It can be seen that the LSTNUT circuit has a Tdq of only 2.33 ps, which is very close to the lowest Tdq (2.21 ps for the LCTNUT circuit); the LSTNUT circuit has a Tcq of only 4.57 ps, which is significantly lower than the other circuits; the LSTNUT circuit has a power consumption of only 0.792 μW, the lowest among the five circuits; and the LSTNUT circuit has the smallest PDP of only 8.43.

[0130] 2. Comprehensive radiation resistance performance SER (Soft Error Rate, soft error rate) to measure:

[0131] The five latch circuits under different VDD values ​​were investigated. SER , see Table 5 for the results.

[0132] Table 5 Five types of latches SER Value comparison

[0133]

[0134] From Table 5, we can see that LSTNUT can achieve the minimum under different VDD values. SER , indicating that its comprehensive radiation resistance is optimal.

[0135] Example 3

[0136] This embodiment 3 discloses a three-node upset-tolerant latch chip based on polarity hardening technology, which is packaged using the three-node upset-tolerant latch storage circuit based on polarity hardening technology described in embodiment 1. The chip packaging model facilitates the promotion and application of the three-node upset self-recovery latch circuit.

[0137] See Figure 13 The pins of the three-node flip-tolerant latch chip based on polarity reinforcement technology include 5 pins: a first pin, a second pin, a third pin, a fourth pin, and a fifth pin.

[0138] The first pin is connected to VDD, the second pin is connected to GND, the third pin is connected to CLK, the fourth pin is connected to D, and the fifth pin is connected to Q.

[0139] Of course, the LSTNUT circuit can also be designed as a module. If it is designed as a module, the corresponding pins can be designed as terminals. After all, the cost of designing it as a chip is very high. If it is designed in a modular form, it will also be convenient for technicians in this field to quickly use the LSTNUT circuit. They only need to refer to the product manual and connect the wiring terminals of the module, without having to solder various components to connect the LSTNUT circuit itself.

[0140] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0141] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A three-node upset-tolerant latch circuit based on polarity reinforcement technology, characterized in that: include: A pull-up tube portion, which is used to pull up the storage nodes X1 to X8 in conjunction with the power supply VDD; A pull-down tube portion, which is used to pull down the storage nodes X1 to X8 in conjunction with the ground GND; wherein X1 to X8 are N-polarity reinforcement points; The pull-up tube section includes: 8 PMOS tubes N1~N4, N9~N12; the pull-down tube section includes: 8 NMOS tubes N5~N8, N13~N16; the source of N1~N4, N9~N12 is connected to VDD; the drain of N5~N8, N13~N16 is connected to GND; the drain of N1, the source of N5, the gate of N3, and the gate of N6 are connected to X1; the drain of N2, the source of N6, the gate of N4, and the gate of N7 are connected to X2; the drain of N3, the source of N7, and the gate of N1 are connected to X1; The gate of N10 and the gate of N15 are connected to X6; the drain of N11, the source of N15, the gate of N9, and the gate of N16 are connected to X7; the drain of N12, the source of N16, the gate of N10, and the gate of N13 are connected to X8; The signal inversion unit includes two inverters INV1 and INV2. INV1 is used to convert the input signal D into an inverted input signal DN. INV2 is used to convert the clock signal CLK into an inverted clock signal NCK. The C unit section includes: C unit 1, C unit 2, and C unit 3. C unit 1 includes: two PMOS transistors P1-P2, two NMOS transistors N25-N26, for generating an intermediate signal X9 based on X1 and X5; C unit 2 includes: two PMOS transistors P3-P4, two NMOS transistors N27-N28, for generating an intermediate signal X10 based on X3 and X7; C unit 3 includes: three PMOS transistors P5-P7, three NMOS transistors N29-N31, for generating an output signal Q based on X9, X10, CLK, and NCK; The transmission tube part includes: 8 NMOS tubes N17 to N24, which are used to connect D to X1, X3, X5, and X7 through N17, N18, N19, and N20 respectively, and connect DN to X2, X4, X6, and X8 respectively through N21, N22, N23, and N24 when CLK=1; The transmission gate portion includes: a transmission gate G1, which is used to connect D to Q through G1 when CLK=1.

2. The three-node upset tolerant latch circuit based on polarity hardening technology according to claim 1, characterized in that: The input end of INV1 is connected to D, and the output end is connected to DN; The input end of INV2 is connected to CLK, and the output end is connected to NCK.

3. The three-node upset-tolerant latch circuit based on polarity hardening technology according to claim 2, characterized in that: INV1 includes: 1 PMOS tube P8, 1 NMOS tube N32; The gate of P8 is connected to the gate of N32 and serves as the input terminal of INV1; the drain of P8 is connected to the drain of N32 and serves as the output terminal of INV1; The source of P8 is connected to VDD; The drain of N32 is connected to GND; INV2 includes: 1 PMOS tube P9, 1 NMOS tube N33; The gate of P9 is connected to the gate of N33 and serves as the input end of INV2; the drain of P9 is connected to the drain of N33 and serves as the output end of INV2; the source of P9 is connected to VDD; and the drain of N33 is connected to GND.

4. The three-node upset tolerant latch circuit based on polarity reinforcement technology according to claim 1, characterized in that: The gate of P1 is connected to X1 and the source is connected to VDD; The gate of P2 is connected to X5, the source is connected to the drain of P1, and the drain is connected to X9; The gate of N25 is connected to X5 and the source is connected to X9; The gate of N26 is connected to X1, the source is connected to the drain of N25, and the drain is grounded GND; The gate of P3 is connected to X3, and the source is connected to VDD; The gate of P4 is connected to X7, the source is connected to the drain of P3, and the drain is connected to X10; The gate of N27 is connected to X7 and the source is connected to X10; The gate of N28 is connected to X3, the source is connected to the drain of N27, and the drain is grounded to GND; The gate of P5 is connected to X9 and the source is connected to VDD; The gate of P6 is connected to X10, and the source is connected to the drain of P5; The gate of P7 is connected to CLK, the source is connected to the drain of P6, and the drain is connected to Q; The gate of N29 is connected to NCK and the source is connected to Q; The gate of N30 is connected to X10, and the source is connected to the drain of N29; The gate of N31 is connected to X9, the source is connected to the drain of N30, and the drain is grounded GND.

5. The three-node upset tolerant latch circuit based on polarity reinforcement technology according to claim 1, characterized in that: The gates of N17 to N24 are connected to CLK; the sources of N17 to N24 are connected to D; The drain of N17 is connected to X1; the drain of N18 is connected to X2; the drain of N19 is connected to X3; the drain of N20 is connected to X4; the drain of N21 is connected to X5; the drain of N22 is connected to X6; the drain of N23 is connected to X7; and the drain of N24 is connected to X8.

6. The three-node upset tolerant latch circuit based on polarity hardening technology according to claim 1, characterized in that: The input end of G1 is connected to D, the output end is connected to Q, the control end of C is connected to CLK, and the control end of C' is connected to NCK.

7. The three-node upset tolerant latch circuit based on polarity reinforcement technology according to claim 6, characterized in that: G1 includes: 1 PMOS tube P10, 1 NMOS tube N34; The source of N34 is connected to the source of P10 and serves as the input of G1; the drain of N34 is connected to the drain of P10 and serves as the output of G1; the gate of N34 serves as the C control terminal of TG1; the gate of P10 serves as the C' control terminal of G1.

8. A three-node upset-tolerant latch chip based on polarity reinforcement technology, characterized in that: The invention is encapsulated by a three-node upset tolerant latch circuit based on polarity reinforcement technology as described in any one of claims 1 to 7.

9. The three-node upset tolerant latch chip based on polarity reinforcement technology according to claim 8, characterized in that: The pins of the three-node upset-tolerant latch chip based on polarity reinforcement technology include: a first pin, which is used to connect to VDD; The second pin is used to connect to GND; The third pin is used to connect CLK; A fourth pin is used to connect to D; and The fifth pin is used to connect Q.

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