Fault current limiting solid state switching device

Abstract

The invention relates to a fault current limiting solid state switching device. Systems and apparatus for providing fault current limit protection in a power circuit may include a solid state switching device (SSSD) including: at least one switching device including a semiconductor device; a voltage clamp circuit connected in parallel with the at least one switching device; and one or more circuit breakers connected in series with the SSSD. The at least one switching device may include a second semiconductor device. The at least one switching device may include a first switching device and a second switching device. The fault current limit protection includes, in order to be able to clear the fault, turning off one of the switching devices to maintain the current at a threshold for a defined period of time, and in response to failing to clear the fault, turning off the other switching device to interrupt the current between the power source and the electrical load (s) connected to the power circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of circuits, and more particularly to fault current limiting solid-state switching devices in power circuits. Background Art

[0002] Electrical fault protection devices, such as circuit breakers, are designed to interrupt electrical current to provide protection in power distribution systems. These circuit breakers prevent electrical fault events, such as electrical short circuits and / or overcurrents, to protect connected equipment and personnel. Such systems may include electromechanical circuit breakers (EMCBs), solid-state circuit breakers (SSCBs), or both.

[0003] EMCBs are commonly used as fault protection devices in power systems due to their relatively low cost compared to SSCBs. EMCBs typically operate on a timescale of 10 milliseconds. This speed of operation may be suitable for some AC systems or for slowly rising fault currents in DC systems. However, the rate of rise of fault current in DC systems can be significantly higher than in AC systems. The rate of rise of fault current (di / dt) can range from a few amperes per microsecond to hundreds of amperes per microsecond (A / μs). Therefore, in a short-circuit event, the fault current can swell to unmanageable levels due to the time it takes for the EMCB to open and interrupt the fault.

[0004] Alternatively, SSCBs typically operate within a few microseconds, allowing them to interrupt fast-rising DC faults. In this regard, SSCBs are often used in power systems, compared to EMCBs, because they can quickly disconnect in response to electrical faults to interrupt current flow. However, SSCBs are generally more expensive than EMCBs. Consequently, many systems typically utilize a single upstream SSCB and multiple downstream EMCBs to protect individual feeders. In systems with this or similar configurations, the downstream CB is disconnected to interrupt the electrical fault to protect the electrical loads connected to the corresponding feeder. Alternatively, if it is determined that the downstream CB cannot disconnect in a timely manner, the upstream SSCB is disconnected to interrupt the electrical fault current to protect the power system. Summary of the Invention

[0005] In some embodiments, a device for providing fault current protection in a power circuit includes a solid-state switching device (SSSD), the SSSD including: at least one switching device including a first semiconductor device; a voltage clamping circuit connected in parallel with the at least one switching device; and one or more circuit breakers connected in series with the SSSD. In some embodiments, in response to determining a fault at a circuit breaker of the one or more circuit breakers, operation of the at least one switching device is selectively controlled to maintain a current at a threshold value for a defined period of time to enable clearing of the fault at the circuit breaker.

[0006] In some embodiments, selectively controlling the operation of at least one switching device to maintain the current at a threshold within a defined time period includes: in response to the current reaching the threshold, opening the at least one switching device to commutate the current to a voltage clamping circuit and causing the voltage across the at least one switching device to increase, wherein a fault at the circuit breaker is determined based on a measured current at the circuit breaker exceeding a second threshold.

[0007] In some embodiments, the voltage clamp circuit includes a fault current limit level configured to maintain a voltage across the at least one switching device consistent with a voltage in the power circuit while commutating current during a defined time period.

[0008] In some embodiments, the at least one switching device further includes a second semiconductor device, and the voltage clamping circuit includes a varistor connected in parallel across the first semiconductor device and the second semiconductor device.

[0009] In some embodiments, the first semiconductor device and the second semiconductor device include a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), an integrated gate commutated thyristor (IGCT), a bipolar transistor, a Darlington transistor, a field effect transistor (FET), a silicon controlled rectifier (SCR), a thyristor, a triac, a unijunction transistor, a diode, or any combination thereof.

[0010] In some embodiments, the first semiconductor device is connected in anti-series with the second semiconductor device; and the first semiconductor device and the second semiconductor device include MOSFETs.

[0011] In some embodiments, the first semiconductor device is connected in anti-parallel with the second semiconductor device, and the first semiconductor device and the second semiconductor device include IGCTs.

[0012] In some embodiments, the at least one switching device includes a first switching device and a second switching device. In some embodiments, controlling the at least one switching device to maintain the current at a threshold value during a defined time period further comprises: in response to the current reaching the threshold value, opening one of the first switching device or the second switching device to commutate the current to a corresponding voltage clamping circuit and increasing a voltage across one of the first switching device or the second switching device; and in response to a failure to clear the fault at the circuit breaker within the defined time period, opening the other of the first switching device and the second switching device to commutate the current to a corresponding voltage clamping circuit and interrupting the current flow at the SSSD. In some embodiments, the fault at the circuit breaker is determined based on a measured current at the circuit breaker exceeding a second threshold value.

[0013] In some embodiments, the apparatus further comprises a controller. In some embodiments, the controller is configured to send a gate command signal to the at least one switching device to selectively turn on and off the at least one switching device using a single turn-off trigger.

[0014] In some embodiments, the controller does not utilize pulse width modulation to control operation of the at least one switching device.

[0015] In some embodiments, a system for providing current fault protection in a power circuit includes a solid-state switching device (SSSD), the SSSD including: at least one switching device including a first semiconductor device; and a varistor connected in parallel with the at least one switching device; and one or more circuit breakers, and in response to determining a fault at a circuit breaker in the one or more circuit breakers, selectively controlling operation of the at least one switching device to maintain current at a fault current trip threshold for a defined time period to enable clearing of the fault at the circuit breaker. In some embodiments, the varistor includes a fault current limit level configured to maintain a voltage across the at least one switching device consistent with a voltage in the power circuit when commutating current during the defined time period.

[0016] In some embodiments, selectively controlling operation of the at least one switching device to maintain the current at a threshold value during a defined time period includes, in response to the current reaching a fault current trip threshold, opening the at least one switching device to commutate the current to a varistor and causing a voltage across the at least one switching device to increase. In some embodiments, a fault at the circuit breaker is determined based on a measured current at the circuit breaker exceeding a second threshold value.

[0017] In some embodiments, the at least one switching device further comprises a second semiconductor device, the first semiconductor device and the second semiconductor device being connected in anti-series. In some embodiments, the first semiconductor device and the second semiconductor device comprise MOSFETs.

[0018] In some embodiments, the at least one switching device further includes a second semiconductor device, the first semiconductor device and the second semiconductor device are connected in anti-parallel, and the first semiconductor device and the second semiconductor device include IGCTs.

[0019] In some embodiments, the at least one switching device includes a first switching device and a second switching device, and the varistor includes a first varistor connected in parallel with the first switching device and a second varistor connected in parallel with the second switching device.

[0020] In some embodiments, controlling the operation of at least one switching device to maintain the current at a threshold during a defined period further includes: in response to the current reaching a fault current trip threshold, opening one of the first switching device or the second switching device to commutate the current to a corresponding one of the first varistor or the second varistor, and increasing the voltage across one of the first switching device or the second switching device; opening the circuit breaker in one or more circuit breakers to clear the fault within a defined period; and in response to opening the circuit breaker in one or more circuit breakers, closing one of the first switching device or the second switching device. The fault current trip threshold includes a level Ith such that Ith > Ithi and Ith < Ith1, where Ithi is the fault current trip threshold of the circuit breaker and Ith1 is the fault current trip threshold of the SSSD.

[0021] In some embodiments, controlling the operation of at least one switching device to maintain the current at a fault current trip threshold during a defined period further includes: in response to failure to clear the fault within the defined period, opening the other switching device in the first switching device and the second switching device to commutate the current to the corresponding first varistor or second varistor to interrupt the current at the SSSD.

[0022] In some embodiments, the system further includes a controller, and the controller is configured to send a gate command signal to at least one switching device to selectively turn on and off at least one switching device using a single turn-off trigger, and the controller does not utilize pulse width modulation to control the operation of at least one switching device.

[0023] In some embodiments, a method for providing fault protection in a power circuit, the power circuit including a solid-state switching device (SSSD), the SSSD including at least one switching device and a varistor connected in parallel across the at least one switching device, the SSSD being connected upstream of one or more circuit breakers, the method includes: by a controller, in response to determining a fault at the circuit breaker in one or more circuit breakers, based on the current reaching a threshold, opening at least one switching device within a defined period to commutate the current to the varistor and increasing the voltage across the at least one switching device; by the controller, opening the circuit breaker in one or more circuit breakers to clear the fault within the defined period; and by the controller, in response to opening the circuit breaker in one or more circuit breakers and clearing the fault within the defined period, closing at least one switching device. In some embodiments, the controller is configured to send a gate command signal to at least one switching device to selectively turn on and off at least one switching device using a single turn-off trigger, and the controller does not utilize pulse width modulation to control the operation of at least one switching device.

[0024] In some embodiments, the at least one switching device includes a first switching device located on a first pole and a second switching device located on a second pole, and opening the at least one switching device within a defined time period includes opening one of the first switching device or the second switching device within a defined time period, and the method further includes: in response to a failure to clear the fault within the defined time period, the controller opening the other of the first switching device and the second switching device to commutate current to a varistor connected in parallel with the other of the first switching device and the second switching device to interrupt current at the SSSD. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Some embodiments of the present disclosure are described herein by way of example only with reference to the accompanying drawings. With specific reference now to the drawings in detail, it is emphasized that the embodiments shown are by way of example and for purposes of illustrative discussion of the embodiments of the present disclosure. In this regard, the description taken in conjunction with the drawings will make apparent to those skilled in the art how the embodiments of the present disclosure may be practiced.

[0026] Figure 1 is a schematic diagram illustrating a system according to some embodiments.

[0027] Figure 2 is a diagram illustrating a non-limiting example of an SSSD in accordance with some embodiments.

[0028] Figure 3 is a schematic diagram illustrating another non-limiting example of an SSSD in accordance with some embodiments.

[0029] Figure 4 is a schematic diagram illustrating another non-limiting example of an SSSD in accordance with some embodiments.

[0030] Figure 5 is a schematic diagram illustrating another non-limiting example of an SSSD in accordance with some embodiments.

[0031] Figure 6 is a schematic diagram illustrating a non-limiting example of a system according to some embodiments.

[0032] Figure 7 is a schematic diagram illustrating a non-limiting example of a system according to some embodiments.

[0033] Figure 8 is a flowchart illustrating a method according to some embodiments.

[0034] Figure 9 is a graphical diagram illustrating implementation of fault current limiting protection according to some embodiments.

[0035] Figure 10is a flowchart illustrating a method according to some embodiments.

[0036] Figure 11 is a graphical diagram illustrating implementation of fault current limiting protection according to some embodiments.

[0037] Figure 12 is a flow chart illustrating a method of performing fault current limiting protection according to some embodiments.

[0038] Figure 13 is a flow chart illustrating implementation of fault current limiting protection in a system according to some embodiments. DETAILED DESCRIPTION

[0039] Various embodiments of the present disclosure relate to systems, devices, assemblies, and methods for providing fault current limiting protection in a power distribution system (such as, for example, a DC power circuit, a DC microgrid, etc.) and maintaining circuit breaker coordination between upstream and downstream circuit breakers (CBs) without the need for additional fault current limiting circuits. According to some embodiments, a system for providing fault current limiting protection in a DC power circuit may include an upstream CB electrically connected to one or more other downstream CBs. The system described herein is used for a DC power circuit, but may also be suitable for other power circuits, such as, for example, an AC power circuit. According to some embodiments, the upstream CB may be referred to herein as a solid-state switching device (SSSD) or a solid-state circuit breaker (SSCB). In addition, each downstream CB in the downstream CB may be referred to as an electromechanical circuit breaker (EMCB). In some embodiments, the downstream CB may also be an SSSD having one or more semiconductor devices therein and capable of fast switching operations to interrupt current in the power line. In some embodiments, the downstream CB may be a device similar to the upstream CB.

[0040] Typically, the upstream CB is configured to switch between open and closed states to direct current through the upstream CB and between the electrical load and the downstream circuit breaker. According to some embodiments, the upstream CB may include one or more switching devices, and the upstream CB may be configured to selectively operate the switching device(s) upon detecting an electrical fault at one of the downstream CBs to provide current limiting protection to the DC power circuit. That is, the upstream CB may be configured to selectively operate the one or more switching devices in the upstream CB to limit the electrical fault current to a certain level within a predefined time period, thereby enabling the downstream CB (e.g., an EMCB or SSSD) to disconnect and protect the electrical load equipment connected to the corresponding feeder from the fault. In addition, each switching device may include one or more turn-off power semiconductor devices for interrupting current flow, as further described herein. The upstream CB and the switching devices therein may be configured to provide unidirectional or bidirectional control of current flow in the system, as further described herein.

[0041] According to some embodiments, the upstream CB may include one or more switching devices therein that are configured to selectively switch on and off to provide improved current limiting capabilities over known prior art technologies, as further described herein. In response to determining that an electrical fault condition exists at one of the downstream CBs, at least one switching device in the upstream CB may be selectively controlled to provide a predefined time period to the downstream CB to disconnect and interrupt the electrical fault current at the downstream CB without necessarily interrupting the current flow at the upstream CB, thereby limiting the loss of protection coordination in the system between the upstream and downstream CBs and causing all downstream feeders to lose power, even though the fault may have occurred in only one of the downstream feeders.

[0042] By selectively operating one or more switching devices in the upstream CB to commutate current to the corresponding voltage-limiting circuit within a predefined time period, the upstream CB can provide current limiting functionality in response to rapidly rising downstream fault currents. This is an improvement over conventional systems known in the prior art, in which both upstream and downstream CBs would trip due to a loss of circuit breaker coordination. In this regard, the maximum fault di / dt at which the system can successfully maintain coordination is also improved.

[0043] According to some embodiments, the DC power circuit may include a positive pole, a negative pole, and a ground pole, and one or more switching devices of the upstream CB may be located on one or more poles of the DC power circuit. The upstream CB may include one or more switching devices on each pole of the DC power circuit. In some embodiments, the upstream CB may include one or more switching devices on one pole of the DC power circuit. In other embodiments, the upstream CB may include one or more switching devices on each of the first and second poles of the DC power circuit. For example, the positive pole and the negative pole may respectively include one or more switching devices on the corresponding poles, and the switching device on the positive pole may provide fault current limiting protection in an instance where there is a positive-to-ground electrical fault. In other embodiments, the upstream CB may include one or more switching devices on all three poles (e.g., positive, negative, and ground). According to some embodiments, each switching device may be a two-quadrant switching device. In other embodiments, the switching device may be a four-quadrant switch (FQS).

[0044] For a given pole, the upstream CB may include one or more switching devices. Each switching device is capable of switching between an open and closed state to control the current directed across the switching device. According to some embodiments, the upstream CB may include one switching device on a given pole of a DC power circuit. As will be further described herein, one switching device may be turned on to direct current through the switching device and turned off to limit the current to a fault current threshold by commutating the current to a voltage limiting circuit.

[0045] According to some embodiments, an upstream CB at a given pole of a DC power circuit may include at least two switching devices. The at least two switching devices may be connected in series, i.e., the switching devices may be electrically connected in series with each other and with a downstream CB at the given pole. In some embodiments, the at least two switching devices include a first switching device and a second switching device. During normal operation, the at least two switching devices may be in a closed state to direct current through the upstream CB. In response to detecting a fault downstream of the CB, one of the first and second switching devices may switch from a closed state to an open state to limit the current directed through the upstream CB. By opening the corresponding switching device, the voltage is commutated to a voltage-limiting circuit. After a predefined period of time, and in response to the downstream CB failing to clear the fault, the other of the first and second switching devices may switch from a closed state to an open state to reduce the current at the upstream CB to zero by commutating the voltage to the voltage-limiting circuit. In some embodiments, the upstream CB may include at least two switching devices, including, for example, a first switching device and a second switching device located at a pole, to provide bidirectional current control.

[0046] Each switching device may include one or more semiconductor devices. The operation of the semiconductor devices may be selectively controlled so that the semiconductor devices are opened and closed to conduct or guide the current directed through the semiconductor devices, respectively, and to guide the current through the switching devices. The configuration or arrangement of the semiconductor devices included in each switching device may be determined based on the type of semiconductor device. In addition, the configuration and arrangement of the semiconductor devices included in each switching device may be based on whether the upstream CB is configured for unidirectional or bidirectional current control. In some embodiments, the switching device may include a first semiconductor switching device connected in anti-series with a second semiconductor switching device. In other embodiments, the switching device may include a first semiconductor switching device connected in anti-parallel with the second semiconductor switching device. According to some embodiments, the upstream CB may be a true FQS device connected in series between the electrical load and the downstream CB, which is configured to conduct current in both directions and block voltages of both polarities.

[0047] According to some embodiments, the upstream CB may include a voltage limiting circuit connected in parallel across each switching device. In some embodiments, the voltage limiting circuit may include a varistor selected to include a fault current limiting level appropriate for the DC voltage level of the system. For example, the varistor may be a metal oxide varistor (MOV). In this regard, the varistor is configured to commutate current in response to the switching device switching to an off state. By commutating the current to the varistor, the voltage across the varistor during commutation is maintained at a level substantially similar to the voltage in the rest of the power circuit, thereby enabling fault current limiting protection in the upstream CB.

[0048] According to some embodiments, the upstream CB may be an SSSD configured to provide fault current limiting protection by triggering the switching device(s) and the corresponding semiconductor devices therein using a single off trigger. In this regard, those skilled in the art will appreciate that the upstream CB does not provide fault current limiting protection by triggering the switching device(s) or the corresponding semiconductor devices therein using pulse control (e.g., pulse width modulation) on the semiconductor devices. Thus, this system provides improved current limiting protection compared to known prior art systems that utilize separate fault current trip circuits to implement pulse control to rapidly switch the semiconductor devices in the upstream CB open and closed, thereby maintaining the electrical fault current within a certain level until the downstream CB can be disconnected. In this regard, these conventional systems include an upstream CB having a semiconductor device topology that is configured to continuously switch on and off within the limits set by the trip circuit to maintain the current at a constant peak fault current level. These conventional di / dt compensators operate by artificially lowering the trip threshold so that the SSCB will still trip at the peak fault current within the operating range of the di / dt compensator.

[0049] According to some embodiments, the system may include a controller. The controller may be configured to control the operation of the upstream CB based on current measurements obtained by one or more sensor devices. In some embodiments, the controller may be connected to the upstream CB and each downstream CB in the downstream CB to control the operation of the upstream CB and the downstream CB respectively. In other embodiments, each upstream CB in the upstream CB and each downstream CB in the downstream CB may have a local controller associated therewith for controlling the operation of the corresponding device. Therefore, in some embodiments, the system may include a host controller that controls the local controller of each device in the device. The local controller may be configured to monitor parameters at each corresponding device on the power line, such as, for example, the current measured at the local sensor device, and each controller may also be in electronic communication with one or more other local controllers to be able to perform fault current limiting protection in accordance with the present disclosure.

[0050] The controller can be electrically connected to the semiconductor devices in the SSCB to control the operation of the corresponding semiconductor devices by sending corresponding gate signals to the corresponding semiconductor devices, thereby switching between a closed state and an open state. In some embodiments, each CB can include a controller associated therewith, or a group of CBs in the system can include corresponding controllers associated therewith, and the controller associated with the upstream CB can coordinate the operation of the other CBs to provide fault current limiting protection in the system. In other embodiments, the system can include a controller that electrically communicates with (multiple) local controllers associated with the CBs to perform fault current limiting protection according to the present disclosure.

[0051] According to some embodiments, in order to provide fault current limiting protection in a system, the current (ie, the fault current) may be limited to a specific threshold level I th , so that I th >I thi , and I th th1 , where I thi is the fault current tripping threshold of the i-th CB (i.e., downstream CB), and I th1 is the fault current tripping threshold of the upstream CB. The upstream CB can keep the fault current at I th A preset time (defined period) is used to give the downstream CB enough time to trip and clear the fault current. In this regard, proper circuit breaker coordination is maintained between the upstream and downstream CBs, thereby improving the reliability of the DC power system.

[0052] ​The upstream CB can be configured to primarily provide fault current limiting protection in the system. That is, the upstream CB can be designed to handle fault current limiting within a defined time period, which is designed to allow the corresponding downstream CB sufficient time to trip and disconnect in response to the current at the corresponding downstream CB exceeding a fault current trip threshold. In some embodiments, fault current limiting protection can be initiated by the controller at the upstream CB based on the electrical fault current reaching a specific threshold current level. In other embodiments, fault current limiting protection can be initiated by the controller at the upstream CB based on the rate of rise di / dt of the electrical fault current reaching a specific rate of rise limit threshold.

[0053] According to some embodiments, upon detecting an electrical fault at any one of the downstream CBs, the controller may perform operations including, in response to a current at one of the downstream CBs exceeding a fault current threshold, opening a switching device to commutate current to an associated varistor and increasing a voltage across the switching device (and varistor). The varistor is configured to maintain a voltage at a level substantially similar to a voltage (e.g., an operating voltage) in the remainder of the DC power circuit. Additionally, in response to the downstream CB failing to interrupt the electrical fault current within a defined time period, the controller may open another switching device in the upstream CB, causing the current to commutate to the associated varistor, effectively reducing the current to zero amperes (A), and blocking current directed through the upstream CB. According to some embodiments, the controller may further control the operation of the downstream CB, including opening the downstream CB to interrupt current at the downstream feeder in response to detecting the electrical fault, and closing the downstream CB to direct current to the downstream feeder in response to determining that the electrical fault has cleared.

[0054] Those skilled in the art will appreciate that the upstream CB topologies described herein and illustrated in the accompanying figures are exemplary and not intended to be limiting. That is, the upstream CB may include the topologies described herein, or may be implemented using one or more other topologies, including one or more different types of semiconductor devices, to enable the upstream SSCB to perform fault current limiting protection according to the present disclosure, as further described herein.

[0055] Among the benefits and improvements already disclosed, other objects and advantages of the present disclosure will become apparent from the following description taken in conjunction with the accompanying drawings. Detailed embodiments of the present disclosure are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the present disclosure that can be implemented in various forms. In addition, each of the examples given with respect to the various embodiments of the present disclosure is intended to be illustrative rather than restrictive.

[0056] Figure 1 is a schematic diagram illustrating a system 100 according to some embodiments.

[0057] System 100 is configured to provide fault current protection in a DC power circuit 102, such as, for example, a DC microgrid. In this regard, system 100 includes a high-speed, high-bandwidth control circuit that processes current and voltage information, detects short-circuit events, and provides digital commands to corresponding gate drive units at regular intervals to perform fault current limiting functions in accordance with the present disclosure.

[0058] System 100 includes a solid-state switching device (SSSD) 104. SSSD 104 is an upstream CB electrically connected to one or more circuit breakers 106 downstream of SSSD 104. SSSD 104 can be connected in series with one or more circuit breakers 106. In some embodiments, SSSD 104 can be connected in series between circuit breakers 106 and power source 108.

[0059] According to some embodiments, system 100 may include a plurality of circuit breakers 106 electrically connected to SSSD 104. SSSD 104 may be connected in series with the plurality of circuit breakers 106, and circuit breaker 106 may be connected in parallel with other circuit breakers 106 in DC power circuit 102. Furthermore, although not shown, circuit breaker 106 may be electrically connected to one or more electrical devices on a corresponding feeder, and circuit breaker 106 may be configured to provide electrical fault current protection to the one or more connected electrical devices. In this regard, in response to detecting an electrical fault at one of the one or more circuit breakers 106, the corresponding circuit breaker 106 is configured to trip and interrupt current flow to protect the connected electrical devices from the fault. According to some embodiments, circuit breaker 106 may be an electromechanical circuit breaker (EMCB). In other embodiments, circuit breaker 106 may be an SSSD, such as SSSD 104, and include one or more semiconductor devices capable of fast switching operations therein to provide electrical fault protection to electrical load devices connected to DC power circuit 102 and the feeders of system 100. Those skilled in the art will appreciate that, in light of the present disclosure, the types of downstream circuit breakers described herein are exemplary and not intended to be limiting and may include any of a variety of different types of fault current protection devices capable of performing switching operations to electrically interrupt a fault current.

[0060] According to some embodiments, the SSSD 104 is a solid-state switching device capable of rapid switching operations to interrupt current flow in the DC power circuit 102, i.e., the SSSD 104 may be capable of interrupting current flow between a power source 108 and one or more circuit breakers 106. The SSSD 104 may also be referred to as a solid-state circuit breaker (SSCB) 104. The SSSD 104 may be configured to provide unidirectional or bidirectional fault current limiting, as will be further described herein.

[0061] The SSSD 104 provides fault current limiting protection for the DC power circuit 104 by operating to maintain the current at a specific fault current threshold for a preset or predefined time period in response to detecting a fault in the DC power circuit 102, so that the corresponding downstream circuit breaker 106 has sufficient time to trip and open and protect downstream electrical equipment electrically connected to the feeder from the fault. In this regard, by not tripping and opening the SSSD 104 within the defined time period, allowing the downstream circuit breaker(s) 106 affected by the electrical fault an opportunity to open, the current limiting function of the SSSD 104 maintains circuit breaker coordination between the SSSD 104 and the downstream circuit breakers 106, so that when the electrical fault current reaches a certain threshold, the SSSD 104 does not have to interrupt power delivery to other circuit breakers 106 in the DC power circuit 102 and other electrical systems or equipment electrically connected to the DC power circuit 102 at the corresponding feeder.

[0062] It is to be understood that, although not shown in the figures, the system 100 may also include one or more sensor devices for detecting voltage, current, other electrical characteristics, or any combination thereof across the DC power circuit 102 and enabling one or more components of the system 100 to perform operations in accordance with the present disclosure. For example, the system 100 may include current sensors on respective feeders adjacent to the circuit breaker 106, between the SSSD 104 and the circuit breaker 106, between the SSSD 104 and the power source 108, within the SSSD 104, within any of the circuit breakers 106, and at any of a number of other locations within the DC power circuit 102 to enable the system 100 to detect current in the DC power circuit 102, determine that a fault has occurred in the DC power circuit 102, determine that the circuit breaker 106 has opened to interrupt the fault, and perform any other operations in accordance with the present disclosure.

[0063] Figure 2 is a diagram illustrating a method according to some embodiments Figure 1 FIG. 1 is a schematic diagram of a non-limiting example of an SSSD 104 in FIG. SSSD 104 can be located on a pole and include at least one switching device 110. Switching device 110 can be capable of conducting current in both directions and can also be capable of blocking voltages of both polarities. In this regard, switching device 110 functions as a four-quadrant switching (FQS) device. SSSD 104 and switching device 110 can be connected in series with a downstream circuit breaker 106. Furthermore, in some embodiments, SSSD 104 and switching device 110 can be connected in series between circuit breaker 106 and power source 108.

[0064] The switching device 110 includes one or more semiconductor devices 116 therein. A gate control signal may be used to selectively control the opening and closing of the semiconductor devices 116 to control the current and voltage directed through the switching device 110. Figure 2 The switching device 110 includes a semiconductor device 116a connected in anti-series with a semiconductor device 116b at a given pole. In addition, the SSSD 104 includes a voltage clamp circuit 112 connected in parallel with the switching device 110 across the semiconductor devices 116a and 116b.

[0065] To open switching device 110, such as when an electrical fault is detected at any downstream circuit breaker 106, gate control signals can be sent to semiconductor devices 116a and 116b to open switching device 110. When switching device 110 opens, current is commutated into voltage clamping circuit 112, which is connected in parallel with switching device 110, causing the voltage across the terminals of switching device 110 to rise according to the IV characteristics of voltage clamping circuit 112. The components of voltage clamping circuit 112 can be selected so that the voltage rise across the terminals is substantially equal to the voltage of DC power circuit 102. By doing so, SSSD 104 can remain in this state as long as the energy dissipated by voltage clamping circuit 112 remains below the thermal limits of the components selected in the design (e.g., varistor 114), which can at least partially define the period of time that SSSD 104 remains open to allow downstream circuit breaker 106 to open during an electrical fault event.

[0066] The DC power circuit 102 may include one or more poles. Additionally, the SSSD 104 may include at least one switching device 110 located on one or more poles of the DC power circuit 102. For example, the DC power circuit 102 may include a first pole (positive), a second pole (negative), and a third pole (ground), and the SSSD 104 may include at least one switching device 110 located on each of the first and second poles. In some embodiments, the SSSD 104 includes at least one switching device 110 on one pole. For example, the positive pole may include a first switching device 110 and a second switching device 110. In other embodiments, the SSSD 104 includes at least one switching device 110 on both poles. For example, the positive pole and the negative pole may include a first switching device 110 and a second switching device 110, respectively. In this regard, having at least one switching device 110 on both poles enables the system 100 to provide current limiting protection when a fault occurs between the third pole and one of the two poles that includes at least one switching device 110. For example, if both the positive pole and the negative pole include at least one switching device 110, current limiting protection can still be provided for electrical faults between the positive pole and the ground pole.

[0067] Figure 3 is a diagram illustrating a method according to some embodiments Figure 1 FIG2 is a schematic diagram of another non-limiting example of an SSSD 104 in FIG2 . According to some embodiments, the SSSD 104 can be a two-pole CB and include at least one switching device 110 on each pole capable of providing bidirectional current limiting. Furthermore, according to the present disclosure, a switching device 110 on a respective pole can be operated in series with another switching device 110 on another pole to provide fault current limiting protection.

[0068] Reference Figure 3 SSSD 104 includes a switching device 110a at the positive electrode and a switching device 110b at the negative electrode. Switching device 110a includes semiconductor devices 116a and 116b connected in an anti-parallel arrangement, and a varistor 114a connected in parallel with semiconductor devices 116a and 116b. Switching device 110b also includes semiconductor devices 116a and 116b connected in an anti-parallel arrangement, and a varistor 114b connected in parallel with semiconductor devices 116a and 116b. In some embodiments, SSSD 104 may further include a switching device 110 at the ground electrode, which may be similar to switching devices 110a and 110b.

[0069] Switching device 110 a or switching device 110 b may be selectively opened and closed to open and close SSSD 104 to control the current directed through SSSD 104. In the event a fault is detected at one of downstream circuit breakers 106, switching device 110 a or switching device 110 b may be selectively operated to commutate current to varistor 114 a or varistor 114 b, thereby maintaining the voltage across SSSD 104 at a level substantially equal to the voltage in DC power circuit 102.

[0070] According to some embodiments, the system 100 may include, for example Figure 3 The SSSD 104 shown is configured to provide current limiting capability in the DC power circuit 102 within a predefined time period, as described herein, thereby providing sufficient shutdown time for the downstream CB. Additionally, according to some embodiments, the system 100 may include, for example, Figure 3Another SSSD 104 is shown, connected in series with the first SSSD 104 in the DC power circuit 102, to provide current interruption capability to the DC power circuit 102. That is, in response to a downstream CB failing to disconnect within a predefined time period, the second SSSD 104 connected in series with the first SSSD 104 can also be turned off (e.g., disconnected) to commutate current to the corresponding varistor 114 without interrupting power delivered from the power source 108 to the downstream electrical load device. In some embodiments, the first SSSD 104 and the second SSSD 104 can be combined into a single device and include at least two switching devices 110 on each pole connected in series.

[0071] Figure 4 is a diagram illustrating a method according to some embodiments Figure 1 FIG. 1 is a schematic diagram of another non-limiting example of an SSSD 104 in FIG. According to some embodiments, the SSSD 104 may be a two-pole CB, each pole including one or more switching devices thereon capable of providing unidirectional current limiting. That is, each of the switching devices 110 a and 110 b may conduct current in one direction and block voltages of both polarities. For example, Figure 4 The illustrated SSSD 104 may be used in the power circuit of an electric vehicle charging system, as the system is configured for a unidirectional flow of electrical current directed from a grid power source to an electric vehicle.

[0072] Reference Figure 4 According to some embodiments, the SSSD 104 may be a two-pole CB, each pole including at least one switching device 110. According to the present disclosure, a switching device 110 on one pole may be operated in series with another switching device 110 on another pole to provide fault current limiting protection.

[0073] like Figure 4As shown, the SSSD 104 includes a switching device 110a located on the positive pole and a switching device 110b located on the negative pole. In some embodiments, the SSSD 104 may also include a switching device 110 on the ground pole. The switching device 110a includes a semiconductor device 116a and a varistor 114a connected in parallel with the semiconductor device 116a. The switching device 110b includes a semiconductor device 116b and a varistor 114b connected in parallel with the semiconductor device 116b. In order to open and close the SSSD 104 to control the current directed through the SSSD 104, the switching device 110a and the switching device 110b can be turned off and on simultaneously, respectively. In the event that a fault is detected at one of the downstream circuit breakers 106, the switching device 110a can be selectively operated in series with the switching device 110b to interrupt the current and maintain the voltage across the SSSD 104 at a level substantially equal to the voltage in the DC power circuit 102. For example, referring to Figure 4 When an electrical fault occurs between the positive and negative poles, both the switching device 110 a and the switching device 110 b may be opened to commutate the current to the corresponding varistor 114 a and the varistor 114 b, thereby providing current limiting capability within a predefined time period based on the IV characteristics of the selected varistor 114 .

[0074] According to some embodiments, the system 100 may include, for example Figure 4 The first SSSD 104 is shown to provide current limiting protection capability to the DC power circuit 102. In addition, in some embodiments, the system 100 may include, for example Figure 4 The second SSSD 104 is shown to provide a current interruption capability to the DC power circuit 102 to interrupt the current between the power source 108 and the downstream electrical load device in response to the downstream CB failing to disconnect during a predefined time period of a current fault event occurring at the downstream CB. In some embodiments, the first SSSD 104 and the second SSSD 104 can be combined into a single device and include at least two switching devices 110 on each pole connected in series.

[0075] Figure 5 is a schematic diagram illustrating another non-limiting example of an SSSD 104 according to some embodiments. According to some embodiments, the SSSD 104 may include at least two switching devices 110 located on a pole of the DC power circuit 102. That is, referring to Figure 5 SSSD 104 may include a switching device 110a and a switching device 110b connected in series on a single pole. In some embodiments, SSSD 104 may be a two-pole CB, each pole including Figure 5At least two switching devices 110 are shown, and can be operated in series to provide electrical fault current limiting capability to the DC power circuit 102, so as to provide time for the downstream CB to switch off within a predefined time period if the fault current reaches a certain threshold, and to provide current interruption capability if the downstream CB does not switch off or open within the predefined time period.

[0076] Each switching device 110 may include one or more semiconductor devices 116, which may be selectively controlled using corresponding gate control signals to open and close each switching device 110. According to some embodiments, each switching device 110 includes a semiconductor device 116a and a semiconductor device 116b, which may be collectively referred to as semiconductor devices 116 hereinafter.

[0077] According to some embodiments, the switching device 110 in the SSSD 104 may include one or more different types of semiconductor devices 116 therein. The topology of the switching device 110 and the configuration and arrangement of the semiconductor devices 116 therein may depend on the type of semiconductor devices 116 used in the switching device 110. According to some embodiments, the semiconductor devices 116 may include metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), integrated gate commutated thyristors (IGCTs), bipolar transistors, Darlington transistors, field effect transistors (FETs), silicon controlled rectifiers (SCRs), thyristors, triacs, unijunction transistors, diodes, other semiconductor devices, or any combination thereof. For example, the switching device 110 may include a first RB-IGCT and a second RB-IGCT arranged in anti-parallel.

[0078] According to some embodiments, the semiconductor device 116 in the switch device 110 may be, for example, a MOSFET, an IGBT, or other similar type of semiconductor device, and may be connected in anti-series with other semiconductor device(s) in the switch device 110. In other embodiments, the semiconductor device 116 may be, for example, an RB-IGCT, a GTO, or other similar type of semiconductor device, and may be connected in anti-parallel with other semiconductor device(s) in the switch device 110.

[0079] exist Figure 5 In the exemplary embodiment of the SSSD 104 shown, the SSSD 104 includes a switching device 110a and a switching device 110b connected in series with each other. Each switching device 110 includes a semiconductor device 116a and a semiconductor device 116b. The semiconductor devices 116 are MOSFETs connected in anti-series with each other in the corresponding switching device 110. Although Figure 5The semiconductor devices 116 in the switching device 110 are shown as being connected in anti-series, but one of ordinary skill in the art will appreciate that this configuration of the switching device 110 is exemplary and not intended to be limiting, and that the configuration of the semiconductor devices 116 in the switching device 110 may vary depending on the type of semiconductor devices used in the switching device 110, as will be further described herein. In this regard, the switching devices 110 in the system 100 may include a variety of different topologies and include a variety of different types of semiconductor devices therein, as long as the switching devices 110 can be operated to open and close, thereby interrupting the current across the corresponding switching device 110, to perform current limiting protection according to the present disclosure.

[0080] System 100 and SSSD 104 also include a voltage clamping circuit 112. In some embodiments, SSSD 104 can include a voltage clamping circuit 112 connected in parallel with each switching device 110. In some embodiments, voltage clamping circuit 112 can include a varistor 114 connected in parallel with switching device 110 to commutate current at the corresponding switching device 110. Voltage clamping circuit 112 can include one or more components for commutating current to voltage clamping circuit 112 to provide current limiting protection. The one or more components in voltage clamping circuit 112 can include, but are not limited to, a varistor, a transient voltage suppressor diode, a resistor, a capacitor, other electrical components, or any combination thereof. In some embodiments, varistor 114 can be a metal oxide varistor (MOV).

[0081] Figure 5 The illustrated SSSD 104 includes a voltage clamping circuit 112. The voltage clamping circuit 112 includes a varistor 114a connected in parallel with the switching device 110a and a varistor 114b connected in parallel with the switching device 110b. Hereinafter, the varistor 114a and the varistor 114b may be collectively referred to as the varistor 114. In the SSSD 104, each of the switching devices 110 includes a semiconductor device 116a and a semiconductor device 116b, and the varistor 114 is connected in parallel across the semiconductor device 116a and the semiconductor device 116b of the corresponding switching device 110. It will be appreciated by those skilled in the art that Figure 5 The illustrated voltage clamp circuit 112 is exemplary and is not intended to be limiting. Thus, in accordance with the present disclosure, the voltage clamp circuit 112 may include one or more components for commutating current across the switching device 110.

[0082] When SSSD 104 is commanded to close or open, such as during normal operation, switching devices 110a and 110b may open and close simultaneously, thus causing SSSD 104 to behave like a single switch. However, in the event of a fault, such as a short circuit at any downstream circuit breaker 106, SSSD 104 may be operated to provide current limiting protection to allow downstream circuit breakers 106 time to open, thereby preventing loss of circuit breaker coordination. In this regard, when a fault current event is determined to have occurred, such as when the rate of rise of the fault current exceeds a defined rate-of-rise limit, one of switching devices 110 (e.g., one of switching devices 110a and 110b) may be opened to maintain the fault current at a specified fault current threshold. That is, in response to detecting a fault determined based on the fault current, one of switching devices 110 in SSSD 104 is configured to open to interrupt current flow at SSSD 104. For example, in some embodiments, the switching devices 110 are turned off to interrupt current flow across the switching devices 110 by simultaneously turning off the semiconductor devices 116 in the corresponding switching devices 110 .

[0083] When the switching device 110 opens, current is then commutated into the corresponding varistor 114 connected in parallel across the switching device 110, causing the voltage across the terminals of the switching device 110 to rise, depending on the IV characteristics of the voltage clamp circuit 112 or the varistor 114. That is, the voltage clamp circuit 112 and the selected varistor 114 include a fault current limiting level that is configured to maintain the voltage across the switching device 110 consistent with the voltage in the DC power circuit 102 while commutating the current for a defined period of time. That is, the period of time that one of the switching devices 110 in the SSSD 104 remains open to maintain the voltage across the switching device 110 consistent with the voltage in the DC power circuit 102 depends on the characteristics of the voltage clamp circuit 112.

[0084] One of the switching devices 110 opens for a defined period of time and maintains the voltage across the switching device 110 consistent with the voltage of the DC power circuit 102, allowing time for the affected downstream circuit breaker 106 to open and interrupt the electrical fault current on the corresponding feeder and protect the connected electrical load equipment. Once the downstream circuit breaker 106 has opened, the SSSD 104 can return to normal conditions by closing the opened switching device 110 to provide fault current limiting protection.

[0085] However, if the downstream circuit breaker 106 does not interrupt the fault within a defined time period (e.g., a maximum current limiting interval), the SSSD 104 (or a controller associated with implementing fault current limiting protection) assumes that the circuit breaker 106 failed to open, that the fault occurred between the SSSD 104 and the circuit breaker 106, or that the fault occurred on the DC distribution bus. In response, the SSSD 104 is controlled to interrupt the fault current by opening another switching device 110 in the SSSD 104. That is, in response to the failure of one or more circuit breakers 106 in the DC power circuit 102 to interrupt the current within the defined time period, another switching device 110 in the switching devices 110 also opens. The other switching device 110 that opens is configured to commutate the current to the varistor 114 connected in parallel with the switching device 110 and interrupt the current flow in the SSSD 104. When this occurs, a voltage is generated across the other switching device 110, and the current and voltage across the SSSD 104 effectively drop to zero, thereby interrupting the current supplied from the power source to the downstream electrical equipment. For example, upon determining that a fault event has occurred at one of the downstream circuit breakers 106, the switching device 110a may be opened first, and if the downstream circuit breaker 106 does not open within a predefined time period, the switching device 110b may also be opened to interrupt the current across the SSSD 104 and protect the electrical equipment connected to the DC power circuit 102 from damage.

[0086] According to some embodiments, to further extend the maximum current limit time, an additional control scheme may be applied using the SSSD 104. In this regard, if the switching device 110a is configured to open to perform current limiting, and the switching device 110b is configured to open to interrupt current flow if the circuit breaker 106 does not open during a predefined time period, the additional control scheme may include utilizing the varistor 114a to limit the current flow after the varistor 114b. That is, after the varistor 114a reaches the maximum current limit time t CLAfter the varistor 114 (e.g., varistor 114a and varistor 114b) has completed the current limiting operation, both the switching device 110a and the switching device 110b can be turned off to interrupt the fault. For example, if the corresponding downstream circuit breaker 106 fails to open during a predefined time period (e.g., a current limiting interval), both the switching device 110a and the switching device 110b can be turned off to interrupt the fault at the SSSD 104.

[0087] Those skilled in the art will appreciate that each switching element 110 in the SSSD 104 can be independently controlled to be turned on and off to close and open, respectively. Furthermore, each switching element 110 can include any combination of active turn-off semiconductor devices to perform current limiting and interruption operations according to the present disclosure.

[0088] Figure 6 is a schematic diagram illustrating a non-limiting example of a system 300 according to some embodiments. The system 300 may include a DC power circuit 302 having a ring network topology. The system 300 includes two power sources 108, SSSD 104a, SSSD 104b, circuit breakers 106a, 106b, and a through circuit breaker 106n. The system 300 also includes an electrical load 304 connected to a bus 306 of the DC power circuit 302 at corresponding respective terminals 308. As will be appreciated by those skilled in the art, Figure 6 The components and topology included in the illustrated system 300 are exemplary and are not intended to be limiting. That is, the DC power circuit 302 may include one or more other types of components, including but not limited to the SSSD 104, the circuit breaker 106, the power source 108, the electrical load 304, or any combination thereof, and may include components that are compatible with the system 300. Figure 6 Different configurations shown.

[0089] In system 300, SSSD 104 may be capable of providing fault current limiting protection for series-connected circuit breakers 106. In some embodiments, electrical loads 304 may be connected to bus 306 at respective terminals 308, and circuit breakers 106 may be associated with each of the feeders connected to bus 306 to provide fault current protection to electrical equipment connected on the respective lines.

[0090] In system 300, if there is a fault on the right side of circuit breaker 106b, SSSD 104a can limit the fault current to I th2 , to allow the circuit breaker 106b enough time to clear the fault. If the fault occurs near the power source 108a, the SSSD 104a can limit the fault current to a different level I th1 , to allow sufficient time for circuit breaker 106 to clear the fault. In this regard, within the same network of system 300, DC power circuit 302 maintains the upstream circuit breaker, but the downstream circuit breaker may be changed depending on the fault location. As one skilled in the art will appreciate, the current limit level may also vary depending on the fault location and fault current direction.

[0091] Figure 7 is a schematic diagram illustrating a non-limiting example of a system 400 according to some embodiments. System 400 can be a radial power system having two DC power sources 108 (e.g., power source 108a and power source 108b). System 400 includes SSSD 104a connected in series between power source 108a and circuit breaker 106, and SSSD 104b connected in series between power source 108b and circuit breaker 106. Circuit breaker 106 includes circuit breaker 106a, circuit breaker 106b, and a through-breaker 106n. In system 400, an electrical load (not shown) can be connected to a feeder associated with circuit breaker 106, which is connected to a DC bus 404.

[0092] In system 400, SSSD 104a and SSSD 104b are capable of fault current limiting protection. If there is a fault at power supply 108b, SSSD 104a can limit the fault current to I th2 , to allow SSSD 104b sufficient time to clear the fault. Correspondingly, if a fault occurs at, for example, power supply 108a, SSSD 104b may limit the fault current to a different level I th1 , to allow SSSD 104a sufficient time to clear the fault. Thus, in this network of system 400, SSSD 104a and SSSD 104b can act as upstream or downstream circuit breakers depending on the location of the fault. Additionally, SSSD 104a and SSSD 104b can also provide fault current limiting for all faults located after circuit breaker 106 (e.g., circuit breakers 106a, 106b, through 106n), where SSSD 104a and SSSD 104b are upstream circuit breakers.

[0093] System 400 may also include a controller 402. Controller 402 is configured to send command signals to SSSDs 104 and circuit breakers 106 to selectively turn SSSDs 104 and circuit breakers 106 on and off. In this regard, controller 402 is configured to selectively control the operation of FQSs 110 and corresponding semiconductor devices 116 in respective SSSDs 104 to maintain the current at the SSSDs 104 at a specific level for a defined period of time. That is, the controller selectively turns off switching devices 110 and corresponding semiconductor devices 116 therein using a single turn-off trigger rather than pulse width control.

[0094] The controller 402 may include a gate drive unit (not shown) that can command the SSSD 104, the circuit breaker 106, or any component thereof to independently open and close at separate timed moments. In this regard, the controller 402 provides digital commands to the correct gate drive unit at the correct time intervals to perform the fault current limiting function in accordance with the present disclosure. In some embodiments, the SSSD 104 and the circuit breaker 106 in the system 400 may include local controllers for monitoring parameters associated with the local equipment. Additionally, in some embodiments, each local controller may be in electronic communication with other local CB controllers, either directly or through a central high-level controller that coordinates fault current limiting protection in the DC circuit, or may not be in electronic communication with each other. It will be appreciated by those skilled in the art that the fault current limiting protection functionality described herein is an improvement over conventional control circuits configured to perform basic SSCB operations.

[0095] Those skilled in the art will appreciate that while controller 402 is shown as included in system 400, this is exemplary and not intended to be limiting. Thus, any system described herein may include a controller for controlling the operation of one or more components in the corresponding system to provide fault current limiting protection according to the present disclosure. For example, any of system 100, system 300, and system 400 may include controller 402 therein.

[0096] Figure 8 is a flow chart illustrating a method 500 according to some embodiments. Figure 9 is a graphical diagram illustrating the implementation of fault current limiting protection according to some embodiments. Figure 9 Common description.

[0097] Method 500 can be used to provide fault current limiting protection in a power circuit, such as a DC power circuit. The power circuit can include an upstream circuit breaker (CB), which is a SSSD and includes at least one switching device and a varistor connected in parallel across the at least one switching device. The SSSD can be located upstream of one or more circuit breakers and can be connected in series with the one or more circuit breakers.

[0098] In block 502, method 500 includes, in response to determining a fault at a circuit breaker in one or more circuit breakers and based on current reaching a threshold, opening at least one switching device for a defined time period to commutate current to a varistor and causing a voltage across the at least one switching device to increase. Figure 1 As shown, the SSSD may correspond to SSSD 104, and the circuit breaker may correspond to circuit breaker 106. According to some embodiments, Figure 2 As shown, the at least one switching device may correspond to the switching device 110, and the varistor may correspond to the voltage clamping circuit 112. In some embodiments, the voltage clamping circuit may correspond to the varistor 114.

[0099] In some embodiments, the at least one switching device may include a first switching device located at the first pole and a second switching device located at the second pole. Additionally, in some embodiments, turning off the at least one switch during a defined time period may include turning off one of the first switching device or the second switching device during a defined time period. Figure 2 , the first switching device may correspond to the switching device 110 a , and the second switching device may correspond to the switching device 110 b .

[0100] Reference Figure 9 , the SSSD is configured to limit the fault current 520 to I th When a fault occurs, the fault current 520 in the SSSD and downstream CB increases. If the fault current 520 reaches I peak , such as, for example, if no current limiting is provided, both the SSSD 104 and the circuit breaker 106 associated with the fault will trip open. At t1, a fault current 520 is sensed in the DC power circuit, the fault current 520 corresponding to I th2 At t2, when the fault current 520 reaches I th In some embodiments, in the fault current limiting mode, the SSSD limits the fault current 520 to I th .

[0101] At block 504, the method 500 includes opening a circuit breaker of one or more circuit breakers to clear the fault and interrupt current flow for a defined period of time. Figure 9 , at t3, the fault is cleared by disconnecting the downstream CB, so that the fault current in the DC power circuit drops to zero.

[0102] In block 506, method 500 includes closing at least one switching device in response to opening a circuit breaker in the one or more circuit breakers within a defined time period to place the power circuit in a normal operating state. That is, once fault current protection is achieved by opening the affected circuit breaker in the one or more circuit breakers, the SSSD can be switched to a closed state to resume normal operation and direct current from the corresponding power source to the downstream load devices still connected to the DC power circuit. Figure 1 , the power source may correspond to power source 108, and the electrical load device may be located downstream of circuit breaker 106 on the corresponding feeder.

[0103] The controller can be configured to perform the fault current limiting functionality of method 500, including controlling one or more components to perform the operations described at least in blocks 502, 504, and 506. The controller is configured to send a gate command signal to at least one switching device to selectively turn the at least one switching device on and off using a single turn-off trigger. In some embodiments, the controller does not utilize pulse width modulation to control the operation of the at least one switching device. In some embodiments, each of the SSSD and the circuit breaker can include a local controller configured to control the operation of the corresponding device and monitor parameters at the device. In some embodiments, the local controller can be in electronic communication with one or more other controllers to perform fault current protection. In other embodiments, the local controller can be in electronic communication with a higher-level host controller that coordinates the operation of the other devices to enable the performance of fault current limiting protection.

[0104] Figure 10 is a flow chart illustrating a method 700 according to some embodiments. Figure 11 is a graphical diagram illustrating the implementation of fault current limiting protection according to some embodiments. Figure 11 Common description.

[0105] According to some embodiments, method 700 may follow Figure 8 In some embodiments, the method 700 may be performed as follows: Figure 8 Block 504 of the method 700 is performed in a DC power circuit having a SSSD including a first switching device and a second switching device, and when an affected circuit breaker of one or more circuit breakers fails to open within a defined time period. In some embodiments, the first switching device may be located on a first pole and the second switching device may be located on a second pole.

[0106] When the at least one switching device includes a first switching device and a second switching device, opening the at least one switching device within the defined time period includes opening one of the first switching device or the second switching device within the defined time period. In block 702, method 700 includes, in response to a circuit breaker of the one or more circuit breakers failing to clear a fault within the defined time period, opening the other of the first switching device and the second switching device to commutate current to a varistor connected in parallel with the other of the first switching device and the second switching device to interrupt current flow at the SSSD.

[0107] Reference Figure 2 , one of the first switching device or the second switching device corresponds to one of the switching devices 110a or 110b. That is, when it is determined that a fault has occurred at a circuit breaker in one or more circuit breakers, one of the switching devices 110a or 110b is disconnected within a defined time period. In addition, referring back to Figure 2 The other of the first and second switching devices corresponds to the other of switching devices 110a and 110b that did not open when a fault was determined at the affected circuit breaker. That is, for example, assuming that switching device 110a opens in response to determining a fault at one of the affected downstream circuit breakers, switching device 110b opens in response to the affected downstream circuit breaker failing to clear the fault within a defined time period. In this regard, when the affected circuit breaker fails to interrupt the fault at the circuit breaker, the other of the first and second switching devices opens to interrupt current directed through the SSSD, thereby protecting other equipment connected to the DC power circuit.

[0108] Reference Figure 11 When a fault occurs, an electrical fault current 720 rises in the SSSD 104 and the circuit breaker 106. The SSSD 104 is configured to limit the fault current 720 to I th At t1, the SSSD 104 and the circuit breaker 106 sense a fault. In some embodiments, the fault may be sensed by a controller configured to perform current limiting protection. The maximum time period for the SSSD 104 to perform current limiting may be defined as between t2 and t4. At t2, the time at which the SSSD 104 enters current limiting mode may also correspond to a threshold value (I th). That is, one of the switching devices 110a and 110b at SSSD 104 may be opened. At t4, a maximum current limit time of SSSD 104 is indicated, which defines the maximum period of time that SSSD 104 waits for the affected circuit breaker 106 to clear the fault. After t4, the other of the switching devices 110a and 110b at SSSD 104 is opened to commutate current to varistor 114 connected in parallel with the other of the switching devices 110 and 110b, thereby interrupting the current flow at SSSD 104. In some embodiments, the controller may be configured to perform the fault current limiting functionality of method 700, including controlling one or more components to perform at least the operations described in block 702.

[0109] Figure 12 is a flow chart illustrating a method 900 of performing fault current limiting protection according to some embodiments.

[0110] Each of the first and second switches may include a first semiconductor device and a second semiconductor device, and method 900 includes sending an off signal to the first and second solid-state switches to open a corresponding one of the first and second switches at block 902. Method 900 may include sending an on signal to the first and second solid-state switches to close a corresponding one of the first and second switches at block 904.

[0111] For example, Figure 2 As shown, in a corresponding one of the switching devices 110, the first semiconductor device may correspond to one of the semiconductor device 116a and the semiconductor device 116b, and the second semiconductor device may correspond to the other of the semiconductor device 116a and the semiconductor device 116b. In some embodiments, the controller may be configured to perform the fault current limiting functionality of method 900, including controlling one or more components to perform at least the operations described in blocks 902 and 904.

[0112] Figure 13 is a diagram illustrating an embodiment of the Figure 1 Flowchart of performing fault current limiting protection in the system 100.

[0113] To provide fault current limiting protection in the system 100, the current (ie, the fault current) may be limited to a specific threshold level I th , so that I th >I thi , and I th th1 , where I thi ​is the fault current tripping threshold of the Ith CB (i.e., downstream CB), and I th1 is the fault current tripping threshold of the upstream CB. The upstream CB can keep the fault current at I th A predetermined period of time (defined time period) is provided to allow the downstream CB sufficient time to trip and clear the fault current. Disconnecting one of the switching devices 110 in the upstream CB is configured to commutate current to a varistor in the upstream CB, thereby increasing the voltage across the corresponding one of the switching devices 110 in the upstream CB, allowing the downstream CB time to open in response to the fault condition. In this regard, proper circuit breaker coordination is maintained between the upstream and downstream CBs, thereby improving the reliability of the DC power system.

[0114] If L f is the fault inductance, and V dc is the power supply voltage of the DC power circuit 102 protected by the SSSD 104, then the rate of rise of the fault current in the DC power circuit 102 may be:

[0115]

[0116] When the current is switched to the varistor 114 (VAR1) as the switching device 110 (FQS1) is turned off, a voltage V is generated across the varistor 114 (VAR1). MOV , and the rate of rise of the fault current in the DC power circuit 102 decreases to:

[0117]

[0118] The varistor 114 across each switching device 110 may be selected so that the fault current I f =I th (designed fault current limit level) at V MOV Close to or equal to V of DC power circuit 102 dc :V dc ≈V MOV By doing this:

[0119]

[0120] And the SSCB can remain in this state if the energy dissipated in the varistor 114 (VAR1) remains below the thermal limit of the varistor selected in the design. The power dissipation in the varistor 114 (VAR1) during the current limit interval is given by:

[0121]

[0122] Since V MOV and Ith In the current limiting interval t CL remains approximately the same throughout the duration of the current limit interval, so the energy E dissipated in the varistor 114 (VAR1) during the current limit interval MOV1(CL) is given as:

[0123]

[0124] If downstream circuit breaker 106 fails to interrupt the fault within a current-limiting interval (e.g., a defined time period), SSSD 104 (or a controller associated with implementing fault current limiting protection) assumes that circuit breaker 106 has failed, or that the fault has occurred on the DC distribution bus. In this case, SSSD 104 interrupts the fault by opening another switching device 110 (FQS2) among switching devices 110. That is, in response to a failure of semiconductor device 116 in one or more switching devices 116 in DC power circuit 102 to interrupt current within a defined time period, another switching device 110 among switching devices 110 opens. Opening another switching device 110 among switching devices 110 is configured to commutate current to varistor 114 connected in parallel with the other switching device 110 to interrupt current flow at SSSD 104. When this occurs, the fault current now commutates to varistor 114 (VAR2), generating a voltage across the other switching device 110 (FQS2).

[0125] When the current is fully commutated to the varistor 114 (VAR2), the fault di / dt becomes:

[0126]

[0127] In this case, the fault current in the DC power circuit 102 decreases rapidly to zero. During the current interruption, there may be some energy dissipation in the varistor 114 (VAR1), and it can be approximated by assuming that the fault current decreases linearly and the MOV voltage remains constant. The dissipated energy can be approximated as:

[0128]

[0129] The fault current interruption time t int Can be evaluated as:

[0130]

[0131] It can be seen that the energy dissipated in the varistor 114 (VAR1) is:

[0132]

[0133] The total energy dissipated in the varistor 114 (VAR1) is the sum of the energy dissipated during the current limiting phase and the current interruption phase. max , then the maximum current limit time of the design is given as:

[0134]

[0135] And for a given system design, it can be achieved by increasing E max To extend the maximum current limit time t CL .

[0136] According to some embodiments, in order to further extend the maximum current limit time, an additional control scheme may be applied to utilize the varistor 114 (VAR2) to limit the current after the varistor 14 (VAR2). CL Afterward, switching device 110 (FQS1) can be turned on and switching device 110 (FQS2) can be turned off. Consequently, varistor 114 (VAR1) is effectively shorted, and varistor 114 (VAR2) fails to dissipate energy for current limiting. Due to the presence of microhenry inductance in system 100 and DC power circuit 102, the dead time from switching device 110 (FQS1) to switching device 110 (FQS2) does not significantly affect the fault current. After both varistors 114 (e.g., varistors 114a and 114b) have performed current limiting operations, both switching device 110a and switching device 110b can be turned off to interrupt the fault. For example, if the corresponding circuit breaker 106 fails to open during a predefined time period (e.g., a current limiting interval), both switching device 110a and switching device 110b can be turned off to interrupt the fault at SSSD 104.

[0137] Those skilled in the art will appreciate that each switching device 110 in the SSSD 104 can be independently controlled to turn on and off. Each switching device 110 includes any combination of active turn-off semiconductor devices, and each switching device 110 includes a voltage clamping circuit connected in parallel with the switching device 110. It will also be appreciated that the system 100 can include sensor devices for detecting voltage, current, other characteristics, or any combination thereof to enable the system 100 to operate in accordance with the present disclosure.

[0138] All prior patents and publications cited herein are incorporated by reference in their entirety.

[0139] Throughout the specification and claims, unless the context clearly specifies otherwise, the following terms adopt the meanings clearly associated herein. Although possible, the phrases "in one embodiment," "in an embodiment," and "in some embodiments" as used herein do not necessarily refer to the same (multiple) embodiment(s). Furthermore, although possible, the phrases "in another embodiment" and "in some other embodiments" as used herein do not necessarily refer to different embodiments. All embodiments of the present disclosure are intended to be combinable without departing from the scope or spirit of the present disclosure.

[0140] As used herein, unless the context clearly indicates otherwise, the term "based on" is not exclusive and allows for being based on additional factors that are not described. In addition, throughout the specification, the meanings of "a," "an," and "the" include plural references. The meaning of "in..." includes "in..." and "on...".

[0141] As used herein, the term "between" does not necessarily require being positioned directly next to other elements. Generally, the term implies a configuration in which something is sandwiched between two or more other things. Meanwhile, the term "between" can describe something that is directly next to two opposing things. Therefore, in any one or more embodiments disclosed herein, a particular structural component positioned between two other structural elements may be:

[0142] being disposed directly between two other structural elements such that the particular structural component is in direct contact with both of the other structural elements;

[0143] being disposed directly adjacent to only one of the two other structural elements such that the particular structural component is in direct contact with only one of the two other structural elements;

[0144] indirectly disposed beside only one of the two other structural elements, such that the particular structural component is not in direct contact with only one of the other two structural elements, and there is another element juxtaposing the particular structural component with one of the two other structural elements;

[0145] indirectly disposed between two other structural elements, such that a particular structural component is not in direct contact with both other structural elements, and other features may be disposed therebetween; or

[0146] Any combination thereof.

[0147] All aspects

[0148] Various aspects are described below. It is to be understood that any one or more of the features listed in the following aspect(s) may be combined with any one or more of the other aspect(s).

[0149] Aspect 1. A device for providing fault current protection in a power circuit, the device comprising: a solid-state switching device (SSSD), comprising: at least one switching device, comprising: a first semiconductor device; a voltage clamping circuit, wherein the voltage clamping circuit is connected in parallel with the at least one switching device; and one or more circuit breakers, wherein the one or more circuit breakers are connected in series with the SSSD; wherein, in response to determining a fault at a circuit breaker in one or more circuit breakers, the operation of the at least one switching device is selectively controlled to maintain the current at a threshold value for a defined time period to enable the fault at the circuit breaker to be cleared.

[0150] Aspect 2. An apparatus according to any of the preceding aspects, wherein selectively controlling the operation of at least one switching device to maintain the current at a threshold within a defined time period includes: in response to the current reaching the threshold, disconnecting at least one switching device to commutate the current to a voltage clamping circuit and increasing the voltage across the at least one switching device; wherein the fault at the circuit breaker is determined based on the measured current at the circuit breaker exceeding a second threshold.

[0151] Aspect 3. An apparatus according to any of the preceding aspects, wherein the voltage clamping circuit includes a fault current limiting level configured to maintain a voltage across at least one switching device consistent with a voltage in the power circuit when commutating current during a defined time period.

[0152] Aspect 4. The apparatus according to any one of the preceding aspects, wherein the at least one switching device further comprises: a second semiconductor device; wherein the voltage clamping circuit comprises a varistor connected in parallel across the first semiconductor device and the second semiconductor device.

[0153] Aspect 5. The apparatus according to aspect 4, wherein the first semiconductor device and the second semiconductor device comprise a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), an integrated gate commutated thyristor (IGCT), a bipolar transistor, a Darlington transistor, a field effect transistor (FET), a silicon controlled rectifier (SCR), a thyristor, a triac, a unijunction transistor, a diode, or any combination thereof.

[0154] Aspect 6. The apparatus according to aspect 4 or 5, wherein the semiconductor device is defined to be connected in anti-series with the second semiconductor device; wherein the first semiconductor device and the second semiconductor device comprise MOSFETs.

[0155] Aspect 7. The apparatus according to aspect 4 or 5, wherein the first semiconductor device is connected in anti-parallel to the second semiconductor device; wherein the first semiconductor device and the second semiconductor device comprise IGCTs.

[0156] Aspect 8. An apparatus according to any of the preceding aspects, wherein at least one switching device includes: a first switching device, and a second switching device, wherein controlling the operation of the at least one switching device to maintain the current at a threshold during a defined time period further includes: in response to the current reaching the threshold, disconnecting one of the first switching device or the second switching device to commutate the current to a corresponding voltage clamping circuit, and increasing the voltage across one of the first switching device or the second switching device; and in response to a failure to clear a fault at the circuit breaker within a defined time period, disconnecting the other of the first switching device and the second switching device to commutate the current to a corresponding voltage clamping circuit, and interrupting the current at the SSSD; wherein the fault at the circuit breaker is determined based on the measured current at the circuit breaker exceeding the second threshold.

[0157] Aspect 9. The apparatus according to any one of the preceding aspects, further comprising: a controller, wherein the controller is configured to send a gate command signal to the at least one switching device to selectively turn on and off the at least one switching device using a single turn-off trigger.

[0158] Aspect 10. The apparatus of aspect 9, wherein the controller does not utilize pulse width modulation to control operation of the at least one switching device.

[0159] Aspect 11. A system for providing fault current protection in a power circuit, the system comprising: a solid-state switching device (SSSD), comprising: at least one switching device, comprising: a first semiconductor device, and a varistor connected in parallel with the at least one switching device; one or more circuit breakers; and wherein, in response to determining a fault at a circuit breaker in one or more circuit breakers, the operation of the at least one switching device is selectively controlled to maintain the current at a fault current trip threshold for a defined time period to enable clearing of the fault at the circuit breaker; wherein the varistor includes a fault current limit level and is configured to maintain a voltage across the at least one switching device consistent with a voltage in the power circuit when commutating the current during the defined time period.

[0160] Aspect 12. A system according to Aspect 11, wherein selectively controlling the operation of at least one switching device to maintain the current at a threshold during a defined time period includes: in response to the current reaching a fault current trip threshold, disconnecting at least one switching device to commutate the current to a variable resistor and increasing the voltage across the at least one switching device; wherein the fault at the circuit breaker is determined based on the measured current at the circuit breaker exceeding a second threshold.

[0161] Aspect 13. The system according to aspect 11 or 12, wherein the at least one switching device further comprises: a second semiconductor device, wherein the first semiconductor device and the second semiconductor device are connected in anti-series; wherein the first semiconductor device and the second semiconductor device comprise MOSFETs.

[0162] Aspect 14. The system according to aspect 11, 12, or 13, wherein at least one switching device further comprises: a second semiconductor device, wherein the first semiconductor device is anti-parallel connected with the second semiconductor device; wherein the first semiconductor device and the second semiconductor device comprise IGCTs.

[0163] Aspect 15. The system according to aspect 11, 12, 13, or 14, wherein at least one switching device comprises: a first switching device, and a second switching device; wherein the varistor comprises a second varistor connected in parallel with the first switching device and a second varistor connected in parallel with the second switching device.

[0164] Aspect 16. The system according to aspect 15, wherein controlling the operation of at least one switching device to maintain the current at a threshold value during a defined period further comprises: in response to the current reaching the fault current trip threshold, opening one of the first switching device or the second switching device to commutate the current to the corresponding one of the first varistor or the second varistor, and increasing the voltage across one of the first switching device or the second switching device; opening the circuit breaker in one or more circuit breakers to clear the fault within a defined period; and in response to opening the circuit breaker in one or more circuit breakers, closing one of the first switching device or the second switching device; wherein the fault current trip threshold comprises a level Ith, such that Ith > Ithi and Ith < Ith1, Ithi is the fault current trip threshold of the circuit breaker and Ith1 is the fault current trip threshold of the SSSD.

[0165] Aspect 17. The system according to aspect 15 or 16, wherein controlling the operation of at least one switching device to maintain the current at the fault current trip threshold during a defined period further comprises: in response to failure to clear the fault within the defined period, opening the other one of the first switching device and the second switching device to commutate the current to the corresponding first varistor or second varistor to interrupt the current at the SSSD.

[0166] Aspect 18. The system according to aspect 11, 12, 13, 14, 15, 16, or 17, further comprises: a controller, and wherein the controller is configured to send a gate command signal to at least one switching device to selectively turn on and off at least one switching device using a single turn-off trigger, and the controller does not utilize pulse width modulation to control the operation of at least one switching device.

[0167] Aspect 19. A method for providing fault protection in a power circuit, the power circuit including a solid-state switching device (SSSD), the SSSD including at least one switching device and a varistor connected in parallel across the at least one switching device, the SSSD being connected upstream of one or more circuit breakers, the method comprising: a controller, in response to determining a fault at a circuit breaker in one or more circuit breakers, based on current reaching a threshold, opening at least one switching device within a defined time period to commutate current to the varistor and increase voltage across the at least one switching device; opening the circuit breaker in one or more circuit breakers to clear the fault within a defined time period; and closing the at least one switching device by the controller in response to opening the circuit breaker in one or more circuit breakers and clearing the fault within a defined time period; wherein the controller is configured to send a gate command signal to the at least one switching device to selectively turn on and off the at least one switching device using a single turn-off trigger, and wherein the controller does not utilize pulse width modulation to control the operation of the at least one switching device.

[0168] Aspect 20. A method according to Aspect 19, wherein the at least one switching device includes a first switching device located on the first pole and a second switching device located on the second pole, and wherein disconnecting the at least one switching device within the defined time period includes disconnecting one of the first switching device or the second switching device within the defined time period, and wherein the method further includes: the controller, in response to failure to clear the fault within the defined time period, disconnecting the other switching device of the first switching device and the second switching device to commutate the current to a varistor connected in parallel with the other switching device of the first switching device and the second switching device to interrupt the current at the SSSD.

[0169] It is to be understood that changes in details, especially in matters of construction materials employed and the shapes, sizes and arrangements of parts may be made without departing from the scope of the present disclosure. The specification and described embodiments are examples, with the true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A device for providing fault current protection in a power circuit, the device comprising: Solid-state switching device SSSD, comprising: At least one switching device comprising: a first semiconductor device; Voltage clamp circuit, wherein the voltage clamping circuit is connected in parallel with the at least one switching device; and One or more circuit breakers, wherein the one or more circuit breakers are connected in series with the SSSD; wherein, in response to determining a fault at a circuit breaker of the one or more circuit breakers, operation of the at least one switching device is selectively controlled to maintain current at a threshold value for a defined time period to enable clearing of the fault at the circuit breaker.

2. The apparatus of claim 1 , wherein selectively controlling the operation of the at least one switching device to maintain the current at the threshold value for the defined time period comprises: in response to the current reaching the threshold, opening the at least one switching device to commutate the current to the voltage clamp circuit and causing a voltage across the at least one switching device to increase; Wherein the fault at the circuit breaker is determined based on a measured current at the circuit breaker exceeding a second threshold.

3. The apparatus of claim 1 , wherein the voltage clamping circuit includes a fault current limiting level configured to maintain a voltage across the at least one switching device consistent with a voltage in the power circuit when commutating the current during the defined time period.

4. The apparatus of claim 1 , wherein the at least one switching device further comprises: a second semiconductor device; The voltage clamping circuit includes a varistor connected in parallel across the first semiconductor device and the second semiconductor device.

5. The apparatus of claim 4, wherein the first semiconductor device and the second semiconductor device comprise a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), an integrated gate commutated thyristor (IGCT), a bipolar transistor, a Darlington transistor, a field effect transistor (FET), a silicon controlled rectifier (SCR), a thyristor, a triac, a unijunction transistor, a diode, or any combination thereof.

6. The apparatus of claim 4, wherein the first semiconductor device and the second semiconductor device are connected in anti-series; The first semiconductor device and the second semiconductor device include MOSFETs.

7. The apparatus of claim 4, wherein the first semiconductor device is connected in anti-parallel to the second semiconductor device; The first semiconductor device and the second semiconductor device include IGCTs.

8. The apparatus of claim 1 , wherein the at least one switching device comprises: a first switching device, and The second switching device, wherein controlling the operation of the at least one switching device to maintain the current at the threshold during the defined time period further comprises: In response to the current reaching the threshold, opening one of the first switching device or the second switching device to commutate the current to a corresponding voltage clamp circuit and cause a voltage across the one of the first switching device or the second switching device to increase; and In response to a failure to clear the fault at the circuit breaker within the defined time period, opening the other of the first switching device and the second switching device to commutate the current to the corresponding voltage clamping circuit and interrupt the current at the SSSD; Wherein the fault at the circuit breaker is determined based on a measured current at the circuit breaker exceeding a second threshold.

9. The apparatus according to claim 1, further comprising: controller, wherein the controller is configured to send a gate command signal to the at least one switching device to selectively turn on and off the at least one switching device using a single turn-off trigger.

10. The apparatus of claim 9, wherein the controller does not utilize pulse width modulation to control the operation of the at least one switching device.

11. A system for providing fault current protection in a power circuit, the system comprising: Solid-state switching device SSSD, comprising: At least one switching device comprising: a first semiconductor device, and a varistor connected in parallel with the at least one switching device; one or more circuit breakers; and wherein, in response to determining a fault at a circuit breaker of the one or more circuit breakers, selectively controlling operation of the at least one switching device to maintain the current at a fault current trip threshold for a defined time period to enable clearing of the fault at the circuit breaker; Wherein the varistor includes a fault current limiting level configured to maintain a voltage across the at least one switching device consistent with a voltage in the power circuit when commutating the current during the defined time period.

12. The system of claim 11 , wherein selectively controlling the operation of the at least one switching device to maintain the current at the threshold during the defined time period comprises: in response to the current reaching the fault current trip threshold, opening the at least one switching device to commutate the current to the varistor and causing the voltage across the at least one switching device to increase; Wherein the fault at the circuit breaker is determined based on a measured current at the circuit breaker exceeding a second threshold.

13. The system of claim 11 , wherein the at least one switching device further comprises: a second semiconductor device, wherein the first semiconductor device and the second semiconductor device are connected in anti-series; The first semiconductor device and the second semiconductor device include MOSFETs.

14. The system of claim 11 , wherein the at least one switching device further comprises: a second semiconductor device, wherein the first semiconductor device and the second semiconductor device are connected in anti-parallel; The first semiconductor device and the second semiconductor device include IGCTs.

15. The system of claim 11 , wherein the at least one switching device comprises: a first switching device, and a second switching device; The varistor includes a first varistor and a second varistor, the first varistor is connected in parallel with the first switching device, and the second varistor is connected in parallel with the second switching device.

16. The system of claim 15, wherein controlling the operation of the at least one switching device to maintain the current at the threshold during the defined time period further comprises: in response to the current reaching the fault current trip threshold, opening one of the first switching device or the second switching device to commutate the current to a corresponding one of the first varistor or the second varistor and causing a voltage across the one of the first switching device or the second switching device to increase; opening the circuit breaker of the one or more circuit breakers to clear the fault within the defined time period; as well as closing the one of the first switching device or the second switching device in response to opening the circuit breaker of the one or more circuit breakers; The fault current tripping threshold includes the level I th , so that I th >I thi , and I th th1 , I thi is the fault current trip threshold of the circuit breaker and I th1 is the fault current trip threshold of the SSSD.​ 17. The system of claim 16, wherein controlling the operation of the at least one switching device to maintain the current at the fault current trip threshold during the defined time period further comprises: In response to the fault not being cleared within the defined time period, opening the other of the first switching device and the second switching device to commutate the current to the corresponding first varistor or the second varistor to interrupt the current at the SSSD.

18. The system of claim 11, further comprising: controller, and wherein the controller is configured to send a gate command signal to the at least one switching device to selectively turn on and off the at least one switching device using a single turn-off trigger, wherein the controller does not utilize pulse width modulation to control the operation of the at least one switching device.

19. A method for providing fault protection in a power circuit, the power circuit comprising a solid-state switching device (SSSD), the SSSD comprising at least one switching device and a varistor, the varistor being connected in parallel across the at least one switching device, the SSSD being connected upstream of one or more circuit breakers, the method comprising: opening, by a controller, the at least one switching device for a defined time period in response to determining a fault at a circuit breaker of the one or more circuit breakers and based on the current reaching a threshold value to commutate the current to the varistor and cause a voltage across the at least one switching device to increase; opening, by the controller, the circuit breaker of the one or more circuit breakers to clear the fault within the defined time period; as well as closing, by the controller, the at least one switching device in response to opening the circuit breaker of the one or more circuit breakers and clearing the fault within the defined time period; wherein the controller is configured to send a gate command signal to the at least one switching device to selectively turn the at least one switching device on and off using a single turn-off trigger, and wherein the controller does not utilize pulse width modulation to control operation of the at least one switching device.

20. The method of claim 19, wherein the at least one switching device comprises a first switching device located at a first pole and a second switching device located at a second pole, and wherein opening the at least one switching device within the defined time period comprises opening one of the first switching device or the second switching device within the defined time period, and wherein the method further comprises: In response to the fault not being cleared within the defined time period, the controller opens the other of the first and second switching devices to commutate the current to the varistor connected in parallel with the other of the first and second switching devices to interrupt the current at the SSSD.

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