Positive and negative voltage cross-domain cross-coupling voltage level shifter and level shifting method
By designing a cross-domain cross-coupled voltage level shifter across the positive and negative voltage, the delay and power consumption problems of traditional shifters under low-power near-threshold power are solved, and effective conversion and low-power switching of near-threshold level signals are realized.
Patent Information
- Application Number
- CN202510547835.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-28
- Publication Date
- 2025-08-08
AI Technical Summary
Traditional cross-coupled voltage level shifters cannot work properly under low power near-threshold power supplies, with delay and power consumption problems, and cannot support effective conversion of the positive and negative voltage domains.
A positive and negative voltage cross-domain cross-coupling voltage level shifter is designed, and the input voltage is adjusted through the input control circuit, combined with the current limiting resistor and the cross-coupling circuit, the near-threshold level signal is converted, reducing switching delay and dynamic power consumption.
It realizes normal operation under near threshold voltage, avoids erroneous logic output, reduces switching delay and dynamic power consumption, and supports output conversion with high level positive high voltage and low level negative high voltage.
Smart Images
Figure CN120454712A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a positive-negative voltage cross-domain cross-coupling voltage level shifter and a level shifting method, belonging to the technical field of integrated circuits. Background Art
[0002] A voltage level shifter is a circuit used to convert a signal from one voltage level to another. It can convert the voltage level of an input signal into the desired output voltage level. In most memory chips, different voltages need to be applied to the device to adapt to different operating modes. This requires the high-voltage drive circuit to be able to transmit and switch between multiple voltage domains under digital control. As an important component of the high-voltage drive circuit, the voltage level shifter is typically used to transmit high-voltage signals from different operating modes in the analog transmission block. These high-voltage signals include positive high voltage and negative high voltage. For example, in a Flash-based integrated storage and computing chip, a voltage level shifter is often required to convert digital low-level control signals into high-voltage signals during operation. Therefore, the voltage level shifter needs to be able to transmit and switch between positive and negative voltage domains to meet the above requirements.
[0003] Furthermore, voltage level shifters are typically controlled by digital signals, with the high-level voltage of their input signals determined by the digital power supply. To meet low-power design requirements, systems and devices are increasingly being designed to use lower power supply voltages, with the digital power supply voltage gradually decreasing, even approaching the threshold voltage level. This requires the voltage level shifter to be able to jump from a voltage level close to the threshold voltage to the desired voltage level.
[0004] While traditional cross-coupled voltage level shifters can switch between positive and negative voltage domains, when a lower voltage level is applied to the input transistor, the transistor's pull-down capability weakens due to the smaller current, and its ability to resist the pull-up network is also weakened, resulting in an incorrect output logic result. Furthermore, traditional cross-coupled voltage level shifters also experience competition between the pull-up and pull-down transistors, leading to increased delays and power consumption. Furthermore, traditional cross-coupled voltage level shifters require additional circuitry to achieve bidirectional conversion. Therefore, traditional cross-coupled voltage level shifters cannot support conversion from near-threshold voltages to the desired voltage, limiting the use of low-power near-threshold supply voltage technology.
[0005] The positive and negative voltage cross-domain voltage level shifter in the prior art also has delay matching problems caused by the large difference in transmission delay between the high-side and low-side channels, as well as power consumption problems caused by noise coupling. Summary of the Invention
[0006] To address the above problems, the present invention proposes a positive-negative voltage cross-domain cross-coupling voltage level shifter, which has the advantages of simultaneously supporting positive and negative voltage domain conversion, reducing switching delay, and realizing near-threshold level signal conversion.
[0007] The present invention is achieved through the following technical solutions:
[0008] The voltage level shifter includes an input control circuit 1 , a PMOS cross-coupling circuit 2 , an NMOS cross-coupling circuit 3 , a current limiting resistor 4 and an output inverter circuit 5 .
[0009] The input control circuit 1 includes: a first inverter INV, a first PMOS transistor MP1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a first current source I1, a second current source I2, a first output terminal CTR1 of the input control circuit 1, and a second output terminal CTR2 of the input control circuit 1;
[0010] The first inverter INV is connected to the second positive power supply VDDL and the ground; the input end of the first inverter INV is connected to the input level signal IN; the output signal INN at the output end is simultaneously connected to the drain of the first PMOS transistor MP1, the drain of the first NMOS transistor MN1 and the gate of the fifth NMOS transistor MN5; the gate of the first PMOS transistor MP1 is grounded, and the source is connected to the source of the second NMOS transistor MN2; the gate of the first NMOS transistor MN1 is connected to the second positive power supply VDDL, and the source is simultaneously connected to the gate and drain of the fourth NMOS transistor MN4; the gate and drain of the second NMOS transistor MN2, the drain of the third NMOS transistor MN3 and the negative end of the first current source I1 are connected, and are collectively connected to the first output terminal CTR1 of the input control circuit 1; the third NMOS transistor MN3 is connected to the first output terminal CTR1 of the input control circuit 1. The gate of N3 is connected to the input level signal IN, the drain is simultaneously connected to the gate and drain of the second NMOS transistor MN2 and the negative terminal of the first current source I1, and the source is grounded. The gate and drain of the fourth NMOS transistor MN4 are simultaneously connected to the source of the first NMOS transistor MN1, and the source is simultaneously connected to the drain of the fifth NMOS transistor MN5 and the positive terminal of the second current source I2, and are collectively connected to the second output terminal CTR2 of the input control circuit 1. The gate of the fifth NMOS transistor MN5 is connected to the output terminal INN of the first inverter INV, the drain is simultaneously connected to the source of the fourth NMOS transistor MN4 and the positive terminal of the second current source I2, and the source is grounded. The positive terminal of the first current source I1 is connected to the first positive voltage power supply VDDHP; the negative terminal of the second current source I2 is connected to the first negative voltage power supply VDDHN.
[0011] The PMOS cross-coupling circuit 2 includes a first PMOS transistor circuit and a sixth NMOS transistor MN6; wherein the first PMOS transistor circuit includes a third PMOS transistor MP3, a fourth PMOS transistor MP4 and a fifth PMOS transistor MP5;
[0012] The source of the third PMOS transistor MP3 and the source of the fourth PMOS transistor MP4 are both connected to the first positive power supply VDDHP; the drain of the third PMOS transistor MP3 is connected to the drain of the sixth NMOS transistor MN6, and the drain of the fifth PMOS transistor MP5 is simultaneously connected to the source of the sixth PMOS transistor MP6 in the current-limiting resistor 4 and the gate of the seventh PMOS transistor MP7 in the output inverter 5; the gate of the sixth NMOS transistor MN6 is connected to the first output terminal CTR1 of the input control circuit 1, and the source is connected to the input level signal IN;
[0013] In the first PMOS transistor circuit: the gate of the third PMOS transistor MP3 is simultaneously connected to the drain of the fourth PMOS transistor MP4 and the source of the fifth PMOS transistor MP5, the drain is simultaneously connected to the gate of the fourth PMOS transistor MP4 and the drain of the sixth NMOS transistor MN6, and the source is connected to the first positive power supply VDDHP; the gate of the fourth PMOS transistor MP4 is also connected to the drain of the sixth NMOS transistor MN6, the drain is also connected to the source of the fifth PMOS transistor MP5, and the source is connected to the first positive power supply VDDHP; the gate of the fifth PMOS transistor MP5 is grounded, and the drain is respectively connected to the source of the sixth PMOS transistor MP6 in the current limiting resistor 4 and the gate of the seventh PMOS transistor MP7 in the output inverter 5;
[0014] The NMOS cross-coupling circuit 3 includes: a first NMOS transistor circuit and a second PMOS transistor MP2; wherein the first NMOS transistor circuit includes a seventh NMOS transistor MN7, an eighth NMOS transistor MN8 and a ninth NMOS transistor MN9;
[0015] The source of the seventh NMOS transistor MN7 and the source of the eighth NMOS transistor MN8 are both connected to the first negative power supply VDDHN; the drain of the seventh NMOS transistor MN7 is connected to the drain of the second PMOS transistor MP2, and the drain of the ninth NMOS transistor MN9 is connected to the drain of the sixth PMOS transistor MP6 in the current-limiting resistor 4 and the gate of the tenth NMOS transistor MN10 in the output inverter 5, respectively; the gate of the second PMOS transistor MP2 is connected to the second output terminal CTR2 of the input control circuit 1, the drain is connected to the source of the seventh NMOS transistor MN7, and the source is connected to the input level signal IN;
[0016] In the first NMOS transistor circuit: the gate of the seventh NMOS transistor MN7 is simultaneously connected to the drain of the eighth NMOS transistor MN8 and the source of the ninth NMOS transistor MN9, and the drain is simultaneously connected to the gate of the eighth NMOS transistor MN8 and the drain of the second PMOS transistor MP2; the gate of the eighth NMOS transistor MN8 is also connected to the drain of the second PMOS transistor MP2, and the drain is simultaneously connected to the gate of the seventh NMOS transistor MN7 and the source of the ninth NMOS transistor MN9; the gate of the ninth NMOS transistor MN9 is grounded, and the drain is respectively connected to the drain and gate of the sixth PMOS transistor MP6 in the current-limiting resistor 4 and the gate of the tenth NMOS transistor MN10 in the output inverter circuit 5;
[0017] The current limiting resistor 4 includes a sixth PMOS transistor MP6; the gate and drain of the sixth PMOS transistor MP6 are simultaneously connected to the drain of the ninth NMOS transistor MN9 and the gate of the tenth NMOS transistor MN10 in the output inverter 5, and the source is connected to the drain of the fifth PMOS transistor MP5 and the first input terminal of the output inverter 5;
[0018] The output inverter 5 includes a seventh PMOS transistor MP7, a tenth NMOS transistor MN10, and an output terminal OUT. The gate of the seventh PMOS transistor MP7 is connected to the drain of the fifth PMOS transistor MP5 and the source of the sixth PMOS transistor MP6 in the current-limiting resistor 4. The drain is also connected to the drain of the tenth NMOS transistor MN10 and the output OUT. The source is connected to the first positive power supply VDDHP. The gate of the tenth NMOS transistor MN10 is connected to the drain of the ninth NMOS transistor MN9 and the drain of the sixth PMOS transistor MP6 in the current-limiting resistor 4. The drain is also connected to the drain of the seventh PMOS transistor MP7 and the output OUT. The source is connected to the first negative power supply VDDHN.
[0019] The input control circuit 1, the PMOS cross-coupling circuit 2, and the output inverter circuit 5 are all connected to a first positive power supply VDDHP; the input control circuit 1, the NMOS cross-coupling circuit 3, and the output inverter circuit 5 are all connected to a first negative power supply VDDHN; the input terminal of the input control circuit 1 is connected to an input level signal IN; the first output terminal CTR1 of the input control circuit 1 is connected to the gate of the sixth NMOS transistor MN6; and the second output terminal CTR2 of the input control circuit 1 is connected to the gate of the second PMOS transistor MP2.
[0020] The source of the sixth NMOS transistor MN6 and the source of the second PMOS transistor MP2 are simultaneously connected to the input level signal IN;
[0021] The source of the sixth PMOS transistor MP6 in the current-limiting resistor 4 is connected to the drain of the fifth PMOS transistor MP5 and the gate of the seventh NMOS transistor MN7; the gate and drain of the sixth PMOS transistor MP6 are connected to the drain of the ninth NMOS transistor MN9 and the gate of the tenth NMOS transistor MN10.
[0022] The gate of the seventh PMOS transistor MP7 in the output inverter circuit 5 is connected to the drain of the fifth PMOS transistor MP5 and the source of the sixth PMOS transistor MP6 in the current-limiting resistor 4. The gate of the tenth NMOS transistor MN10 is connected to the drain of the ninth NMOS transistor MN9 and the drain of the sixth PMOS transistor MP6 in the current-limiting resistor 4. The output end of the output inverter circuit 5 is the output end of the positive-negative voltage cross-domain cross-coupling voltage level shifter, which outputs the converted output level signal OUT.
[0023] A second object of the present invention is to provide a level shifting method for a positive and negative voltage cross-domain cross-coupling voltage level shifter, the method specifically comprising:
[0024] When the input signal IN is equal to a low level, that is, the potential of the input signal IN is equal to the reference ground GND, the potential of the output signal INN of the first inverter INV is equal to the second positive voltage power supply VDDL, the first NMOS transistor MN1 and the third NMOS transistor MN3 are turned off, the first PMOS transistor MP1 and the fifth NMOS transistor MN5 are turned on, and the potential of the first output terminal CTR1 of the input control circuit 1 is equal to VDDL+V GS,MN2 The potential of the second output terminal CTR2 is equal to the reference ground GND, the second PMOS transistor MP2 is turned off, the sixth NMOS transistor MN6 is turned on, and its source potential is low. The PMOS cross-coupling circuit 2 outputs a high level, that is, the voltage value of the first positive power supply VDDHP. The output of the PMOS cross-coupling circuit 2 serves as the input of the output inverter circuit 5. The tenth NMOS transistor MN10 is turned on, and the output inverter circuit 5 outputs the first negative power supply VDDHN.
[0025] When the input signal IN is equal to a high level, that is, the potential of the input signal IN is equal to the second positive voltage power supply VDDL, the potential of the output signal INN of the first inverter INV is equal to the reference ground GND, the first PMOS transistor MP1 and the fifth NMOS transistor MN5 are turned off, the first NMOS transistor MN1 and the third NMOS transistor MN3 are turned on, the potential of the first output terminal CTR1 of the input control circuit 1 is equal to the reference ground GND, and the potential of the second output terminal CTR2 is equal to -V GS,MN4The sixth NMOS transistor MN6 is turned off, the second PMOS transistor MP2 is turned on, and its source potential is high. The NMOS cross-coupling circuit 3 outputs a low level, that is, the voltage value of the first negative power supply VDDHN. The output of the NMOS cross-coupling circuit 3 serves as the input of the output inverter circuit 5. The seventh PMOS transistor MP7 is turned on, and the output inverter circuit 5 outputs the first positive power supply VDDHP.
[0026] Furthermore, the voltage value of the first positive power supply VDDHP is greater than the voltage value of the second positive power supply VDDL; the voltage values of the second positive power supply VDDL are all greater than the threshold voltages of the third NMOS transistor MN3, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6, and the threshold voltages of these NMOS transistors are approximately 0.61V; the voltage value of the second positive power supply VDDL is greater than the threshold voltage of the second PMOS transistor MP2, and its threshold voltage is approximately 0.66V.
[0027] Cross-coupled circuit input stage switching delay t P The expression is:
[0028]
[0029] Among them, C L is the equivalent load capacitance of the input stage of the cross-coupled circuit, V DD is the voltage difference between the upper and lower power rails of the input stage, I Drive is the transient on-state current during the switching process of the input stage transistor. Take the input stage MN6 of the PMOS cross-coupling circuit 2 as an example.
[0030] I Drive The expression is:
[0031] I Drive =I Drive,MN6
[0032] Among them, I Drive,MN6 is the transient on-state current of the input stage NMOS tube MN6 during the switching process. Ignoring the channel length effect, I Drive,MN6 The expression is:
[0033]
[0034] Among them, μ N is the mobility of NMOS tube MN6, C OX is the oxide layer capacitance per unit area, V GSN is the gate-source voltage of NMOS tube MN6, V THN is the threshold voltage of NMOS tube MN6. Through the above analysis, we can know that increasing I Drive Can reduce the switching delay t P , and increase I DriveBy increasing the input stage transistor and V GS accomplish.
[0035] When the input level signal is low, that is, the potential of the input signal IN is equal to the reference ground GND, the CTR1 applied to the gate of the sixth NMOS transistor MN6 is raised to VDDL+V GS，MN2 The voltage level of the gate-source voltage difference V GSN Raise a V GS，MN2 The voltage level of the PMOS cross-coupling circuit 2 is accelerated to speed up the response, thereby solving the problem that the traditional cross-coupling voltage level shifter cannot work normally when the input level is low and the input voltage difference is close to the threshold voltage;
[0036] When the input level signal is high, that is, the potential of the input signal IN is equal to the second positive voltage power supply VDDL, the CTR2 applied to the gate of the second PMOS tube MP2 is reduced to -V GS，MN4 The voltage level of the gate-source voltage difference V GSP Raise a V GS，MN4 The voltage level of the NMOS cross-coupling circuit 3 is accelerated to speed up the response, thereby solving the problem that the cross-coupled voltage level shifter cannot work normally when the input level is high and the input voltage difference is close to the threshold voltage;
[0037] The beneficial effects of the present invention are:
[0038] (1) The present invention ensures that when the input level is low or high, the voltage of the first input terminal CTR1 of the input control circuit 1 is raised to VDDL+V GS，MN2 or reduce the voltage of the second output terminal CTR2 of the input control circuit 1 to -V GS，MN4 The voltage level of the cross-coupled voltage level shifter is solved to solve the problem that the cross-coupled voltage level shifter cannot work normally when the input level signal is close to the threshold voltage; it avoids the wrong logic output of the cross-coupled level conversion circuit with near-threshold input while also speeding up the switching speed.
[0039] (2) The present invention reduces the magnitude of the dynamic current during input level switching by introducing a current-limiting resistor, thereby reducing dynamic power consumption; uses the sixth NMOS transistor MN6 and the second PMOS transistor MP2 as transmission transistors to replace the inverter structure input stage to reduce switching delay; adds the ninth NMOS transistor MN9 and the fifth PMOS transistor MP5 as isolation transistors to avoid the risk of simultaneous conduction of positive and negative voltages, and realizes the conversion of an input level signal with a high level being near the threshold voltage and a low level being 0V to an output level signal with a high level being a positive high voltage and a low level being a negative high voltage.
[0040] (3) The present invention provides a positive-negative voltage cross-domain cross-coupling level converter. This improves upon the conventional cross-coupling structure by adding an input control circuit to increase the voltage difference of the cross-coupling input transistor, thereby achieving the conversion of an input level signal with a high level being near the threshold voltage and a low level being 0V to an output level signal with a high level being a positive high voltage and a low level being a negative high voltage. A current limiting resistor MP6 is added, which is a MOS resistor with a gate-drain short circuit, thereby reducing the magnitude of the dynamic current in the path between different power supplies during input level switching. Furthermore, a transmission transistor is used in place of the conventional inverter structure input stage to reduce switching delay. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] Figure 1 A circuit structure diagram of a positive and negative voltage cross-domain cross-coupling voltage level shifter is provided in the first embodiment of the present invention;
[0042] Figure 2 A schematic diagram of the circuit operation of a positive-negative voltage cross-domain cross-coupling voltage level shifter provided in the second embodiment of the present invention when the input signal IN is at a low level;
[0043] Figure 3 A schematic diagram of the circuit operation of a positive-negative voltage cross-domain cross-coupling voltage level shifter provided in the second embodiment of the present invention when the input signal IN is at a high level;
[0044] Figure 4 This is a simulation result diagram of a positive-negative voltage cross-domain cross-coupling voltage level shifter provided in the second embodiment of the present invention;
[0045] Figure 5 This is a simulation result diagram of traditional cross-coupling level shifting in the second embodiment of the present invention. DETAILED DESCRIPTION
[0046] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.
[0047] Example 1
[0048] This embodiment provides a positive and negative voltage cross-domain cross-coupling voltage level shifter. The circuit structure of the shifter is as follows: Figure 1 As shown:
[0049] The voltage level shifter includes an input control circuit 1 , a PMOS cross-coupling circuit 2 , an NMOS cross-coupling circuit 3 , a current limiting resistor 4 and an output inverter circuit 5 .
[0050] The input control circuit 1 includes: a first inverter INV, a first PMOS transistor MP1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a first current source I1, a second current source I2, a first output terminal CTR1 of the input control circuit 1, and a second output terminal CTR2 of the input control circuit 1;
[0051] The first inverter INV is connected to the second positive power supply VDDL and the ground; the input end of the first inverter INV is connected to the input level signal IN; the output signal INN at the output end is simultaneously connected to the drain of the first PMOS transistor MP1, the drain of the first NMOS transistor MN1, and the gate of the fifth NMOS transistor MN5; the gate of the first PMOS transistor MP1 is grounded, and the source is connected to the source of the second NMOS transistor MN2; the gate of the first NMOS transistor MN1 is connected to the second positive power supply VDDL, and the source is simultaneously connected to the gate and drain of the fourth NMOS transistor MN4; the gate and drain of the second NMOS transistor MN2, the drain of the third NMOS transistor MN3, and the negative end of the first current source I1 are connected, and are collectively connected to the first output terminal CTR1 of the input control circuit 1; the third NMOS transistor The gate of MN3 is connected to the input level signal IN, the drain is simultaneously connected to the gate and drain of the second NMOS transistor MN2, and the negative terminal of the first current source I1, and the source is grounded. The gate and drain of the fourth NMOS transistor MN4 are simultaneously connected to the source of the first NMOS transistor MN1, and the source is simultaneously connected to the drain of the fifth NMOS transistor MN5 and the positive terminal of the second current source I2, and are collectively connected to the second output terminal CTR2 of the input control circuit 1. The gate of the fifth NMOS transistor MN5 is connected to the output terminal of the first inverter INV, the drain is simultaneously connected to the source of the fourth NMOS transistor MN4 and the positive terminal of the second current source I2, and the source is grounded. The positive terminal of the first current source I1 is connected to the first positive voltage power supply VDDHP; the negative terminal of the second current source I2 is connected to the first negative voltage power supply VDDHN.
[0052] The PMOS cross-coupling circuit 2 includes a first PMOS transistor circuit and a sixth NMOS transistor MN6; wherein the first PMOS transistor circuit includes a third PMOS transistor MP3, a fourth PMOS transistor MP4 and a fifth PMOS transistor MP5;
[0053] The source of the third PMOS transistor MP3 and the source of the fourth PMOS transistor MP4 are both connected to the first positive power supply VDDHP; the drain of the third PMOS transistor MP3 is connected to the drain of the sixth NMOS transistor MN6; the drain of the fifth PMOS transistor MP5 is simultaneously connected to the source of the sixth PMOS transistor MP6 in the current-limiting resistor 4 and the gate of the seventh PMOS transistor MP7 in the output inverter 5; the gate of the sixth NMOS transistor MN6 is connected to the first output terminal CTR1 of the input control circuit 1, and the source is connected to the input level signal IN;
[0054] In the first PMOS transistor circuit: the gate of the third PMOS transistor MP3 is simultaneously connected to the drain of the fourth PMOS transistor MP4 and the source of the fifth PMOS transistor MP5, the drain is simultaneously connected to the gate of the fourth PMOS transistor MP4 and the drain of the sixth NMOS transistor MN6, and the source is connected to the first positive power supply VDDHP; the gate of the fourth PMOS transistor MP4 is also connected to the drain of the sixth NMOS transistor MN6, the drain is also connected to the source of the fifth PMOS transistor MP5, and the source is connected to the first positive power supply VDDHP; the gate of the fifth PMOS transistor MP5 is grounded, and the drain is respectively connected to the source of the sixth PMOS transistor MP6 in the current limiting resistor 4 and the gate of the seventh PMOS transistor MP7 in the output inverter 5;
[0055] The NMOS cross-coupling circuit 3 includes: a first NMOS transistor circuit and a second PMOS transistor MP2; wherein the first NMOS transistor circuit includes a seventh NMOS transistor MN7, an eighth NMOS transistor MN8 and a ninth NMOS transistor MN9;
[0056] The source of the seventh NMOS transistor MN7 and the source of the eighth NMOS transistor MN8 are both connected to the first negative power supply VDDHN; the drain of the seventh NMOS transistor MN7 is connected to the drain of the second PMOS transistor MP2, and the ninth NMOS transistor MN9 is respectively connected to the drain of the sixth PMOS transistor MP6 in the current-limiting resistor 4 and the gate of the tenth NMOS transistor MN10 in the output inverter 5; the gate of the second PMOS transistor MP2 is connected to the second output terminal CTR2 of the input control circuit 1, the drain is connected to the source of the seventh NMOS transistor MN7, and the source is connected to the input level signal IN;
[0057] In the first NMOS transistor circuit: the gate of the seventh NMOS transistor MN7 is simultaneously connected to the drain of the eighth NMOS transistor MN8 and the source of the ninth NMOS transistor MN9, and the drain is simultaneously connected to the gate of the eighth NMOS transistor MN8 and the drain of the second PMOS transistor MP2; the gate of the eighth NMOS transistor MN8 is also connected to the drain of the second PMOS transistor MP2, and the drain is simultaneously connected to the gate of the seventh NMOS transistor MN7 and the source of the ninth NMOS transistor MN9; the gate of the ninth NMOS transistor MN9 is grounded, and the drain is respectively connected to the drain and gate of the sixth PMOS transistor MP6 in the current-limiting resistor 4 and the gate of the tenth NMOS transistor MN10 in the output inverter circuit 5;
[0058] The current limiting resistor 4 includes a sixth PMOS transistor MP6; the gate and drain of the sixth PMOS transistor MP6 are simultaneously connected to the drain of the ninth NMOS transistor MN9 and the gate of the tenth NMOS transistor MN10 in the output inverter 5, and the source is connected to the drain of the fifth PMOS transistor MP5 and the first input terminal of the output inverter 5;
[0059] The output inverter 5 includes a seventh PMOS transistor MP7, a tenth NMOS transistor MN10, and an output terminal OUT. The gate of the seventh PMOS transistor MP7 is connected to the drain of the fifth PMOS transistor MP5 and one end of the current-limiting resistor 4. The drain is also connected to the drain of the tenth NMOS transistor MN10 and the output OUT. The source is connected to the first positive power supply VDDHP. The gate of the tenth NMOS transistor MN10 is connected to the drain of the ninth NMOS transistor MN9 and one end of the current-limiting resistor 4. The drain is connected to the drain of the seventh PMOS transistor MP7. The source is connected to the first negative power supply VDDHN.
[0060] The input control circuit 1, the PMOS cross-coupling circuit 2, and the output inverter circuit 5 are all connected to a first positive power supply VDDHP; the input control circuit 1, the NMOS cross-coupling circuit 3, and the output inverter circuit 5 are all connected to a first negative power supply VDDHN; a first input terminal CTR1 of the input control circuit 1 is connected to an input level signal IN; the first input terminal CTR1 of the input control circuit 1 is also connected to the gate of the sixth NMOS transistor MN6; a second output terminal CTR2 of the input control circuit 1 is connected to the gate of the second PMOS transistor MP2;
[0061] The source of the sixth NMOS transistor MN6 and the source of the second PMOS transistor MP2 are simultaneously connected to the input level signal IN;
[0062] The source of the sixth PMOS transistor MP6 in the current-limiting resistor 4 is connected to the drain of the fifth PMOS transistor MP5 and the gate of the seventh NMOS transistor MN7; the gate and drain of the sixth PMOS transistor MP6 are connected to the drain of the ninth NMOS transistor MN9 and the gate of the tenth NMOS transistor MN10.
[0063] The gate of the seventh PMOS transistor MP7 in the output inverter 5 is connected to the drain of the fifth PMOS transistor MP5, and the gate of the tenth NMOS transistor MN10 is connected to the drain of the ninth NMOS transistor MN9. The output end of the output inverter circuit 5 is the output end of the positive-negative voltage cross-domain cross-coupling voltage level shifter, which outputs the converted output level signal OUT.
[0064] Example 2
[0065] This embodiment provides a level shifting method for a positive and negative voltage cross-domain cross-coupled voltage level shifter. The method is implemented based on the positive and negative voltage cross-domain cross-coupled voltage level shifter provided in the first embodiment. The method specifically includes:
[0066] like Figure 2 As shown, when the input signal IN is equal to a low level, that is, the potential of the input signal IN is equal to the reference ground GND, the potential of the output signal INN of the first inverter INV is equal to the second positive voltage power supply VDDL, the first NMOS transistor MN1 and the third NMOS transistor MN3 are turned off, the first PMOS transistor MP1 and the fifth NMOS transistor MN5 are turned on, and the potential of the first output terminal CTR1 of the input control circuit 1 is equal to VDDL+V GS，MN2 The potential of the second output terminal CTR2 is equal to the reference ground GND, the second PMOS transistor MP2 is turned off, the sixth NMOS transistor MN6 is turned on, and its source potential is low. The PMOS cross-coupling circuit 2 outputs a high level, that is, the voltage value of the first positive power supply VDDHP. The output of the PMOS cross-coupling circuit 2 serves as the input of the output inverter circuit 5. The tenth NMOS transistor MN10 is turned on, and the output inverter circuit 5 outputs the first negative power supply VDDHN.
[0067] like Figure 3 As shown, when the input signal IN is equal to a high level, that is, the potential of the input signal IN is equal to the second positive voltage power supply VDDL, the potential of the output signal INN of the first inverter INV is equal to the reference ground GND, the first PMOS transistor MP1 and the fifth NMOS transistor MN5 are turned off, the first NMOS transistor MN1 and the third NMOS transistor MN3 are turned on, the potential of the first output terminal CTR1 of the input control circuit 1 is equal to the reference ground GND, and the potential of the second output terminal CTR2 is equal to -V GS，MN4 The sixth NMOS transistor MN6 is turned off, the second PMOS transistor MP2 is turned on, and its source potential is high. The NMOS cross-coupling circuit 3 outputs a low level, that is, the voltage value of the first negative power supply VDDHN. The output of the NMOS cross-coupling circuit 3 serves as the input of the output inverter 5. The seventh PMOS transistor MP7 is turned on, and the output inverter circuit 5 outputs the first positive power supply VDDHP.
[0068] In order to prove the effect of the method, the shifter and method provided by the present invention were verified through a verification experiment. The results are as follows: Figure 4 As shown in the figure, the verification experiment settings excite the first positive power supply voltage to 1.8V, the first negative power supply voltage to -1.8V, and the second positive power supply voltage to 0.7V. Given an input signal with a high level of 0.7V, a low level of 0V, and a pulse signal period of 2μs, the thresholds of the third NMOS transistor MN3, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 in the circuit are approximately 0.61V, and the threshold of the second PMOS transistor MP2 is approximately 0.66V. It can be seen that the circuit can correctly output 1.8V when the input signal is 0.7V, and correctly output -1.8V when the input signal is 0V.
[0069] The input control circuit 1 of the present invention is removed, the second positive voltage power supply VDDL is connected to CTR1, the ground signal is connected to CTR2, and the sizes of the other transistors remain unchanged. The simulation results are as follows: Figure 5 As shown. The input signal applied to the positive and negative voltage cross-domain level shifter is a pulse signal with a high level of 0.7V, a low level of 0V, and a period of 2μs; according to Figure 5 It can be seen that at points M1 and M2, when the input is 0.7V and 0V respectively, the corresponding error output is -1.8V represented by point M3.
[0070] Therefore, compared with the traditional cross-coupled level shifter which outputs erroneous logic when the input signal is near the threshold level, the circuit can correctly implement the switching between the two voltage domains.
[0071] The memory in the embodiments of the present application can be volatile memory or non-volatile memory, or can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct RAM bus random access memory (DR RAM). It should be noted that memory of the methods described herein is intended to comprise, but not be limited to, these and any other suitable types of memory.
[0072] The above is a detailed introduction to the positive and negative voltage cross-domain cross-coupled voltage level shifter and method proposed in the present invention, and the principles and implementation methods of the present invention are explained. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.
Claims
1. A positive and negative voltage cross-domain cross-coupling voltage level shifter, characterized in that: The shifter comprises: an input control circuit (1), a PMOS cross-coupling circuit (2), an NMOS cross-coupling circuit (3), a current limiting resistor (4) and an output inverter circuit (5); The input control circuit (1) comprises a first inverter INV, a first PMOS transistor MP1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a first current source I1, a second current source I2, a first output terminal CTR1 of the input control circuit 1, and a second output terminal CTR2 of the input control circuit 1; The input control circuit (1), the PMOS cross-coupling circuit (2), and the output inverter circuit (5) are all connected to a first positive voltage power supply VDDHP; the input control circuit (1), the NMOS cross-coupling circuit (3), and the output inverter circuit (5) are all connected to a first negative voltage power supply VDDHN; the first input terminal CTR1 of the input control circuit (1) is connected to an input level signal IN; the first input terminal CTR1 of the input control circuit (1) is also connected to the gate of the sixth NMOS transistor MN6; the second output terminal CTR2 of the input control circuit (1) is connected to the gate of the second PMOS transistor MP2; The source of the sixth NMOS transistor MN6 and the source of the second PMOS transistor MP2 are simultaneously connected to the input level signal IN; The source of the sixth PMOS transistor MP6 in the current limiting resistor (4) is simultaneously connected to the drain of the fifth PMOS transistor MP5 and the gate of the seventh NMOS transistor MN7; the gate and drain of the sixth PMOS transistor MP6 are simultaneously connected to the drain of the ninth NMOS transistor MN9 and the gate of the tenth NMOS transistor MN10; The gate of the seventh PMOS transistor MP7 in the output inverter circuit (5) is connected to the drain of the fifth PMOS transistor MP5, and the gate of the tenth NMOS transistor MN10 is connected to the drain of the ninth NMOS transistor MN9; the output terminal OUT of the output inverter circuit 5 is the output terminal of the positive-negative voltage cross-domain cross-coupling voltage level shifter, and outputs the converted output level signal.
2. The level shifter according to claim 1, wherein: The PMOS cross-coupling circuit (2) comprises: a first PMOS transistor circuit and a sixth NMOS transistor MN6; The first PMOS transistor circuit includes a third PMOS transistor MP3, a fourth PMOS transistor MP4 and a fifth PMOS transistor MP5; The NMOS cross-coupling circuit (3) comprises a first NMOS transistor circuit and a second PMOS transistor MP2; The first NMOS transistor circuit includes a seventh NMOS transistor MN7, an eighth NMOS transistor MN8 and a ninth NMOS transistor MN9; The current limiting resistor (4) includes a sixth PMOS transistor MP6; The output inverter circuit (5) comprises a seventh PMOS transistor MP7, a tenth NMOS transistor MN10 and an output level signal OUT.
3. The level shifter according to claim 2, wherein: In the input control circuit (1): The first inverter INV is connected to the second positive power supply VDDL and the ground; the input end of the first inverter INV is connected to the input level signal IN; the output signal INN at the output end is simultaneously connected to the drain of the first PMOS transistor MP1, the drain of the first NMOS transistor MN1, and the gate of the fifth NMOS transistor MN5; the gate of the first PMOS transistor MP1 is grounded, and the source is connected to the source of the second NMOS transistor MN2; the gate of the first NMOS transistor MN1 is connected to the second positive power supply VDDL, and the source is simultaneously connected to the gate and drain of the fourth NMOS transistor MN4; the gate and drain of the second NMOS transistor MN2, the drain of the third NMOS transistor MN3, and the negative end of the first current source I1 are connected, and are collectively connected to the first output terminal CTR1 of the input control circuit 1; the third NMOS transistor The gate of MN3 is connected to the input level signal IN, the drain is simultaneously connected to the gate and drain of the second NMOS transistor MN2 and the negative terminal of the first current source I1, and the source is grounded; the gate and drain of the fourth NMOS transistor MN4 are simultaneously connected to the source of the first NMOS transistor MN1, and the source is simultaneously connected to the drain of the fifth NMOS transistor MN5 and the positive terminal of the second current source I2, and are collectively connected to the second output terminal CTR2 of the input control circuit 1; the gate of the fifth NMOS transistor MN5 is connected to the output terminal of the first inverter INV, the drain is simultaneously connected to the source of the fourth NMOS transistor MN4 and the positive terminal of the second current source I2, and the source is grounded; the positive terminal of the first current source I1 is connected to the first positive voltage power supply VDDHP; and the negative terminal of the second current source I2 is connected to the first negative voltage power supply VDDHN.
4. The level shifter according to claim 3, wherein: In the PMOS cross-coupling circuit (2): The gate of the third PMOS transistor MP3 in the first PMOS transistor circuit is simultaneously connected to the drain of the fourth PMOS transistor MP4 and the source of the fifth PMOS transistor MP5, the drain is simultaneously connected to the gate of the fourth PMOS transistor MP4 and the drain of the sixth NMOS transistor MN6, and the source is connected to the first positive power supply VDDHP; the gate of the fourth PMOS transistor MP4 is also connected to the drain of the sixth NMOS transistor MN6, the drain is also connected to the source of the fifth PMOS transistor MP5, and the source is connected to the first positive power supply VDDHP; the gate of the fifth PMOS transistor MP5 is grounded, and the drain is respectively connected to the source of the sixth PMOS transistor MP6 in the current-limiting resistor 4 and the gate of the seventh PMOS transistor MP7 in the output inverter 5; The source of the third PMOS transistor MP3 and the source of the fourth PMOS transistor MP4 are both connected to the first positive power supply VDDHP; the drain of the third PMOS transistor MP3 is connected to the drain of the sixth NMOS transistor MN6; the drain of the fifth PMOS transistor MP5 is simultaneously connected to the source of the sixth PMOS transistor MP6 in the current-limiting resistor 4 and the gate of the seventh PMOS transistor MP7 in the output inverter 5; the gate of the sixth NMOS transistor MN6 is connected to the first output terminal CTR1 of the input control circuit 1, and the source is connected to the input level signal IN.
5. The level shifter according to claim 4, wherein: In the NMOS cross-coupling circuit (3): The gate of the seventh NMOS transistor MN7 in the first NMOS transistor circuit is simultaneously connected to the drain of the eighth NMOS transistor MN8 and the source of the ninth NMOS transistor MN9, and the drain is simultaneously connected to the gate of the eighth NMOS transistor MN8 and the drain of the second PMOS transistor MP2. The gate of the eighth NMOS transistor MN8 is also connected to the drain of the second PMOS transistor MP2, and the drain is simultaneously connected to the gate of the seventh NMOS transistor MN7 and the source of the ninth NMOS transistor MN9. The gate of the ninth NMOS transistor MN9 is grounded, and the drain is respectively connected to the drain and gate of the sixth PMOS transistor MP6 in the current-limiting resistor 4 and the gate of the tenth NMOS transistor MN10 in the output inverter circuit 5. The source of the seventh NMOS transistor MN7 and the source of the eighth NMOS transistor MN8 are both connected to the first negative power supply VDDHN; the drain of the seventh NMOS transistor MN7 is connected to the drain of the second PMOS transistor MP2, and the ninth NMOS transistor MN9 is respectively connected to the drain of the sixth PMOS transistor MP6 in the current-limiting resistor 4 and the gate of the tenth NMOS transistor MN10 in the output inverter 5; the gate of the second PMOS transistor MP2 is connected to the second output terminal CTR2 of the input control circuit 1, the drain is connected to the source of the seventh NMOS transistor MN7, and the source is connected to the input level signal IN.
6. The level shifter according to claim 5, wherein: In the output inverter circuit (5): The gate of the seventh PMOS transistor MP7 is connected to the drain of the fifth PMOS transistor MP5 and one end of the current-limiting resistor 4, the drain is also connected to the drain of the tenth NMOS transistor MN10 and the output OUT, and the source is connected to the first positive power supply VDDHP; the gate of the tenth NMOS transistor MN10 is connected to the drain of the ninth NMOS transistor MN9 and one end of the current-limiting resistor 4, the drain is connected to the drain of the seventh PMOS transistor MP7, and the source is connected to the first negative power supply VDDHN.
7. A method for realizing positive and negative voltage cross-domain cross-coupling voltage level shifting, characterized in that: The method is implemented based on the level shifter according to any one of claims 1 to 6 above; The method includes: when the input signal IN is equal to a low level, that is, the potential of the input signal IN is equal to the reference ground GND, the potential of the output signal INN of the first inverter INV is equal to the second positive voltage power supply VDDL; the first NMOS transistor MN1 and the third NMOS transistor MN3 are turned off, the first PMOS transistor MP1 and the fifth NMOS transistor MN5 are turned on, and the potential of the first output terminal CTR1 of the input control circuit 1 is equal to VDDL+V GS，MN2 , the potential of the second output terminal CTR2 is equal to the reference ground GND; the second PMOS transistor MP2 is turned off, the sixth NMOS transistor MN6 is turned on, and its source potential is low. The PMOS cross-coupling circuit 2 outputs a high level, that is, the voltage value of the first positive power supply VDDHP. The output of the PMOS cross-coupling circuit 2 serves as the input of the output inverter circuit 5. The tenth NMOS transistor MN10 is turned on, and the output inverter circuit 5 outputs the first negative power supply VDDHN, thereby converting the input signal IN from a low level to the output of the first negative power supply VDDHN. When the input signal IN is equal to a high level, that is, the potential of the input signal IN is equal to the second positive voltage power supply VDDL, the potential of the output signal INN of the first inverter INV is equal to the reference ground GND; the first PMOS transistor MP1 and the fifth NMOS transistor MN5 are turned off, the first NMOS transistor MN1 and the third NMOS transistor MN3 are turned on, the potential of the first output terminal CTR1 of the input control circuit 1 is equal to the reference ground GND, and the potential of the second output terminal CTR2 is equal to -V GS,MN4 The sixth NMOS transistor MN6 is turned off, the second PMOS transistor MP2 is turned on, and its source potential is high. The NMOS cross-coupling circuit 3 outputs a low level, that is, the voltage value of the first negative power supply VDDHN. The output of the NMOS cross-coupling circuit 3 serves as the input of the output inverter circuit 5. The seventh PMOS transistor MP7 is turned on, and the output inverter circuit 5 outputs the first positive power supply VDDHP, thereby realizing the transition of the input signal IN from a high level to the output of the first positive power supply VDDHP.
8. The method according to claim 7, characterized in that The method comprises: The voltage value of the first positive power supply VDDHP is greater than the voltage value of the second positive power supply VDDL; the voltage values of the second positive power supply VDDL are all greater than the threshold voltages of the third NMOS transistor MN3, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6, and the threshold voltage of the second PMOS transistor MP2; The threshold voltages of the third NMOS transistor MN3 , the fifth NMOS transistor MN5 , and the sixth NMOS transistor MN6 are 0.61V; and the threshold voltage of the second PMOS transistor MP2 is 0.66V.
9. A positive and negative voltage cross-domain cross-coupling voltage level shifter, characterized in that: The shifter is implemented based on the shifter described in any one of claims 1 to 6 and / or the method described in any one of claims 7 and 8, and is applied in power management systems, industrial control automation, medical electronics, and automotive electronics.