High-speed multichannel analog-to-digital converter with two-stage structure
Through a two-stage high-speed multi-channel analog-to-digital converter, the asynchronous successive approximation analog-to-digital converter and time interleaving technology are used to solve the problems of metastable state and mismatch at high sampling rates in traditional analog-to-digital converters, and efficient ultra-high-speed signal conversion is achieved.
Patent Information
- Application Number
- CN202510453265.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-11
- Publication Date
- 2025-08-08
AI Technical Summary
Traditional analog-to-digital converters have metastable problems and inter-channel mismatch problems at high sampling rates, which are difficult to meet the needs of ultra-high rates.
A high-speed multi-channel analog-to-digital converter with a two-stage structure, including a first-stage sampling module and a second-stage analog-to-digital converter, uses multiple parallel samplers and sub-analog-to-digital converters, combined with asynchronous successive approximation analog-to-digital converters and time interleaving technology, and isolates and allocates signals through voltage buffers to achieve high sampling rate and low power consumption.
It improves the working speed of each subchannel, reduces power consumption, expands application scenarios, ensures signal integrity and system stability at high frequencies, and meets the needs of ultra-high speeds.
Smart Images
Figure CN120454726A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of analog-to-digital converters, in particular to a high-speed multi-channel analog-to-digital converter with a two-stage structure. Background Art
[0002] In high-speed SerDes (Serializer / Deserializer) systems, the performance of the analog-to-digital converter (ADC) directly impacts overall system performance. ADCs primarily include successive approximation ADCs, parallel comparator ADCs, dual-integrator ADCs, and time-interleaved ADCs. Successive approximation ADCs (SAR ADCs) use a successive approximation approach to compare the input analog signal with a series of reference voltages, gradually approaching the final digital output value. Their advantages include a relatively simple circuit structure and low power consumption, making them suitable for medium-speed conversions and applications with medium sampling rates and resolutions. However, their conversion speed is limited by the successive comparison process, making them difficult to meet ultra-high sampling rate requirements. Synchronous SAR ADCs are prone to metastability at high frequencies, resulting in a decrease in signal-to-noise ratio. Parallel comparator ADCs (Flash ADCs) use multiple comparators to simultaneously compare the input signal with different reference voltages, achieving fast conversion speeds. Their advantage is extremely fast conversion speed, making them suitable for high-speed applications. However, they also come with high circuit complexity and power consumption. Resolution and accuracy are limited, leading to higher costs. A dual-integration ADC integrates the input signal and a reference voltage twice, converting the analog signal into a time interval, which is then converted into a digital signal using a counter. Its advantages include strong anti-interference capabilities and excellent stability. It is suitable for high-precision, low-speed scenarios. However, its main drawback is its slow conversion speed, making it difficult to meet the requirements of high-speed applications. A time-interleaved ADC (TI-ADC) uses multiple subchannels to operate in parallel in a time-interleaved manner, increasing the overall sampling rate. This significantly improves the sampling rate and is suitable for ultra-high-speed applications. However, inter-channel mismatches (such as clock skew and bandwidth mismatch) can cause harmonic distortion and affect linearity. Complex calibration circuits are required to correct for this mismatch, increasing system complexity and power consumption. Traditional synchronous successive approximation analog-to-digital converters (SAR ADCs) suffer from severe metastability issues at high sampling rates, resulting in a decrease in the signal-to-noise ratio (SNR), making them difficult to meet ultra-high-speed requirements. Furthermore, mismatches between subchannels in traditional time-interleaved ADCs can also affect overall system performance. Summary of the Invention
[0003] In view of the problems of metastability and mismatch in existing ADCs, the present invention provides a high-speed multi-channel analog-to-digital converter with a two-stage structure, the converter comprising:
[0004] The first-stage sampling module includes a plurality of parallel samplers for sampling an input analog signal, wherein each sampler samples the analog signal with a different time delay.
[0005] The second-stage analog-to-digital conversion module includes a plurality of parallel sub-analog-to-digital converters, and is used to convert the output signal of the first-stage sampling module into a digital signal.
[0006] Multiple voltage buffers are arranged between the first-stage sampling module and the second-stage analog-to-digital conversion module, and are used to isolate the signals between the first-stage sampling module and the second-stage analog-to-digital conversion module and distribute the output signal of the first-stage sampling module to the multiple sub-analog-to-digital converters of the second-stage analog-to-digital conversion module.
[0007] Preferably, each sub-analog-to-digital converter in the second-stage analog-to-digital conversion module is an asynchronous successive approximation analog-to-digital converter.
[0008] Preferably, the voltage buffer adopts a common source and common gate structure; the common source and common gate structure is composed of two MOS transistors, one as a common source M1 and the other as a common gate M2. The input signal is input through the gate of M1, and after being amplified by M1, a small signal current ii is output, which is then amplified by the common gate of M2 to generate an output current io.
[0009] Preferably, the first-stage sampling module includes 8 parallel samplers; the second-stage analog-to-digital conversion module includes 32 parallel sub-analog-to-digital converters; each sampler corresponds to 4 parallel sub-analog-to-digital converters.
[0010] Preferably, the converter performs conversion or sampling in a time-interleaved manner, specifically:
[0011] The input analog signal is input to the first-stage sampling module, and each sampler of the first-stage sampling module samples the input signal through the clock signal provided by the clock generator; wherein the clock generator provides a clock signal with a time offset to each sampler of the first-stage sampling module.
[0012] The output of the first stage sampler is input to a voltage buffer, which distributes the output signal of the first stage sampler to corresponding sub-ADCs.
[0013] Each sub-ADC receives a signal from the voltage buffer according to a sampling time of the sub-ADC provided by the clock generator, and performs analog-to-digital conversion on the received signal.
[0014] Preferably, the voltage buffer includes a multi-way output switch, and the clock generator provides clock signals with different phases to control the multi-way output switches in the voltage buffer.
[0015] This invention utilizes an asynchronous SAR architecture and a two-stage staircase sampling method to increase the operating speed of each subchannel while reducing power consumption and achieving a higher energy efficiency ratio. Furthermore, the two-stage sampling structure effectively reduces parasitic loading at the input, enabling the system to handle higher-frequency input signals and expanding its application scenarios. Highly linear common-source amplifier buffers isolate the two-stage signals, reducing inter-channel mismatch and ensuring signal integrity and system stability at high frequencies. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 The diagram shows the structure of a high-speed multi-channel analog-to-digital converter with a two-stage structure. DETAILED DESCRIPTION
[0017] In the embodiments of the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner to facilitate understanding.
[0018] It will be understood that the “embodiment” mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, the various embodiments throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It will be understood that in the various embodiments of the present application, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.
[0019] In the present invention, unless otherwise specified, the same or similar parts between the various embodiments can refer to each other. In the various embodiments of the present invention, and the various implementation methods / implementation methods / implementation methods in each embodiment, if there is no special explanation and logical conflict, the terms and / or descriptions between different embodiments and the various implementation methods / implementation methods / implementation methods in each embodiment are consistent and can be referenced to each other. The technical features in different embodiments and the various implementation methods / implementation methods / implementation methods in each embodiment can be combined to form new embodiments, implementation methods, implementation methods, or implementation methods according to their inherent logical relationships. The implementation methods of the present application described below do not constitute a limitation on the scope of protection of the present application.
[0020] The present invention provides a high-speed multi-channel analog-to-digital converter with a two-stage structure, the converter comprising:
[0021] The first-stage sampling module includes a plurality of parallel samplers for sampling an input analog signal, wherein each sampler samples the analog signal with a different time delay.
[0022] The second-stage analog-to-digital conversion module includes a plurality of parallel sub-analog-to-digital converters, and is used to convert the output signal of the first-stage sampling module into a digital signal.
[0023] Multiple voltage buffers are arranged between the first-stage sampling module and the second-stage analog-to-digital conversion module, and are used to isolate the signals between the first-stage sampling module and the second-stage analog-to-digital conversion module and distribute the output signal of the first-stage sampling module to the multiple sub-analog-to-digital converters of the second-stage analog-to-digital conversion module.
[0024] The first stage delays each sub-channel for a short period of time and transmits it to the second stage to achieve a higher sampling rate. The first stage distributes the input analog signal according to a certain time interval and does not perform analog-to-digital conversion operations. The analog-to-digital conversion operation is performed in the second stage.
[0025] The second stage consists of multiple asynchronous successive-ratio analog-to-digital converters connected in parallel. The first and second stages are isolated by voltage buffers. These buffers have three functions: 1) Signal isolation: They provide isolation between the first and second stages, preventing signal interference between them; 2) Signal distribution: They distribute the output signal of the first stage to the multiple analog-to-digital converters in the second stage; and 3) Time interleaving: They participate in the time interleaving control of the second stage, ensuring that each analog-to-digital converter is sampled at the correct time.
[0026] Each sub-channel uses an asynchronous successive approximation analog-to-digital converter (ADC). Traditional synchronous SAR ADCs can cause severe metastability issues, struggle to meet ultra-high sampling rate requirements, and further degrade the signal-to-noise ratio. Using an asynchronous SAR ADC allows each sub-channel to operate at higher speeds while also achieving lower power consumption and a smaller size.
[0027] Based on time interleaving, a two-stage stepped sampling method is employed. Compared to traditional direct sampling time interleaving, this method achieves a lower rate per subchannel and higher energy efficiency. It also effectively reduces input load and enables higher-frequency input. This method involves multiple first-stage samples, each of which is then distributed to multiple second-stage subchannel analog-to-digital converters.
[0028] Between the first and second sampling stages, a voltage buffer isolates the signals between the two stages and implements the second-stage time interleaving function. This design is crucial, serving as a connecting block between the upper and lower levels. This block utilizes a highly linear common-source amplifier architecture, meeting various speed and linearity requirements.
[0029] Between the two sampling stages, a voltage buffer plays a crucial role in signal isolation. Using a highly linear common-source amplifier architecture, the voltage buffer effectively isolates the signal between the first and second sampling stages, preventing signal interference and distortion. This isolation design ensures signal integrity and stability.
[0030] The voltage buffer also implements a second-level time interleaving function. This is achieved by controlling the signal sampling time, ensuring that the sampling times of each subchannel are staggered. This design enables a lower sampling rate for each subchannel, improving energy efficiency while effectively reducing input load and enabling higher-frequency input.
[0031] The voltage buffer circuit design uses a cascode structure, which consists of two MOS transistors: one serving as a common source (M1) and the other as a common gate (M2). The input signal passes through the gate of M1, where it is amplified to produce a small output current ii. This signal is then amplified by the common gate of M2, generating an output current io. This structure not only increases circuit gain but also improves bandwidth.
[0032] In one embodiment, the analog-to-digital converter provided by the present invention uses an 8-bit analog-to-digital converter with 32 sub-channels and a time-interleaved structure. Figure 1 shown.
[0033] Each sub-channel uses an asynchronous successive approximation analog-to-digital converter.
[0034] A two-stage sampling method is used. The first stage sampling consists of 8 channels, and each first-stage sample is distributed to 4 second-stage sub-channel analog-to-digital converters. Based on the above description and calculation, the number of sub-channels can be calculated to be 32.
[0035] Between the first-level sampling and the second-level sampling, a voltage buffer is used to isolate the signals between the two levels and realize the time interleaving function of the second level.
[0036] The output of each sub-ADC in the first stage is distributed to multiple (e.g., N) sub-ADCs in the next stage via a voltage buffer, forming the second-stage time interleaving. The voltage buffer integrates a multi-channel output switch that distributes the signal to the corresponding channel based on the clock phase of the second-stage sub-ADC. Multi-phase clock signals control the sampling and conversion of these modules, achieving finer-grained time interleaving.
[0037] The input signal is sampled with varying time delays by parallel samplers in the first stage. These samples are then converted to digital by multiple parallel sub-ADCs in the second stage. Voltage buffers isolate and distribute the signal between the two stages, while time interleaving is used to increase the overall sampling rate.
[0038] The first-level sampling module includes multiple parallel samplers for sampling the input analog signal. Each sampler samples the analog signal with a different time delay. In one embodiment, a clock generator provides each sampler with a clock signal with a precise phase offset. For example, if eight samplers are used, the reference clock signal is divided and phase-shifted to generate eight clock signals with uniform phase distribution, which respectively control the sampling moments of the eight samplers. In another embodiment, different sampling times are achieved by introducing delay lines of different lengths into the clock input path of each sampler, such as delay lines composed of capacitors, inductors, or digital logic.
[0039] The second-stage analog-to-digital conversion module includes multiple parallel sub-ADCs for converting the sampled signals output by the first-stage sampling module into digital signals. Preferably, each sub-ADC is an asynchronous successive approximation analog-to-digital converter. In one embodiment, after completing a conversion, each sub-ADC notifies the subsequent sub-ADC via a handshake signal. In another embodiment, local clock control is used.
[0040] The voltage buffer is located between the first-stage sampling module and the second-stage analog-to-digital conversion module, isolating the signals between the first-stage sampling module and the second-stage analog-to-digital conversion module to prevent subsequent circuits from interfering with the previous-stage sampling process. It is also used to distribute the output signal of the first-stage sampling module to the multiple sub-ADCs of the second-stage analog-to-digital conversion module. Preferably, the voltage buffer includes multiple output switches, and a clock generator provides clock signals of different phases to control these switches. Methods for distributing the output of a sampler to multiple sub-ADCs include but are not limited to: 1) the multiple output switches in the voltage buffer sequentially connect the output of a sampler to the corresponding sub-ADCs at different time intervals. The clock signals of different phases provided by the clock generator are used to control the switching timing of these switches. For example, if a sampler corresponds to four sub-ADCs, the switches will transmit sampled values to these four sub-ADCs within four different time slices. 2) the output of each sampler is connected to multiple parallel voltage buffers, and the output of each buffer is directly connected to a corresponding sub-ADC.
[0041] In one embodiment, time interleaving operates as follows: an analog signal is simultaneously input to each sampler in the first-stage sampling module. Each sampler samples the input signal based on a time-shifted clock signal provided by a clock generator. For example, if there are eight samplers, their sampling times are sequentially offset by a small time interval Δt. The output of the first-stage samplers is input to a voltage buffer, which distributes the output signal of each sampler to the corresponding sub-ADC. Each sub-ADC receives a signal from the voltage buffer based on the sampling time of the sub-ADC provided by the clock generator and performs analog-to-digital conversion on the received signal.
[0042] Although the present application has been described with reference to specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present application. Accordingly, this specification and the drawings are merely illustrative of the present application as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, those skilled in the art may make various modifications and variations to the present application without departing from the scope of the present application. Thus, the present application is intended to include such modifications and variations if they fall within the scope of the claims of the present application and their equivalents.
Claims
1. A high-speed multi-channel analog-to-digital converter with a two-stage structure, characterized in that: The converter comprises: A first-stage sampling module, the first-stage sampling module comprising a plurality of parallel samplers for sampling an input analog signal, wherein each sampler samples the analog signal with a different time delay; a second-stage analog-to-digital conversion module, the second-stage analog-to-digital conversion module comprising a plurality of parallel sub-analog-to-digital converters, configured to convert the output signal of the first-stage sampling module into a digital signal; Multiple voltage buffers are arranged between the first-stage sampling module and the second-stage analog-to-digital conversion module, and are used to isolate the signals between the first-stage sampling module and the second-stage analog-to-digital conversion module and distribute the output signal of the first-stage sampling module to the multiple sub-analog-to-digital converters of the second-stage analog-to-digital conversion module.
2. The converter according to claim 1, wherein Each sub-analog-to-digital converter in the second-stage analog-to-digital conversion module is an asynchronous successive approximation analog-to-digital converter.
3. The converter according to claim 1, wherein The voltage buffer adopts a common source and common gate structure; the common source and common gate structure consists of two MOS transistors, one as a common source M1 and the other as a common gate M2. The input signal is input through the gate of M1, and after being amplified by M1, a small signal current ii is output, which is then amplified by the common gate of M2 to generate an output current io.
4. The converter according to claim 1, wherein The first-stage sampling module includes 8 parallel samplers; the second-stage analog-to-digital conversion module includes 32 parallel sub-analog-to-digital converters; each sampler corresponds to 4 parallel sub-analog-to-digital converters.
5. The converter according to claim 1, wherein The converter performs conversion or sampling in a time-interleaved manner, specifically: The input analog signal is input to the first-stage sampling module, and each sampler of the first-stage sampling module samples the input signal using a clock signal provided by a clock generator; wherein the clock generator provides a clock signal with a time offset to each sampler of the first-stage sampling module; The output of the first stage sampler is input to a voltage buffer, which distributes the output signal of the first stage sampler to the corresponding sub-analog-to-digital converter; Each sub-ADC receives a signal from the voltage buffer according to a sampling time of the sub-ADC provided by the clock generator, and performs analog-to-digital conversion on the received signal.
6. The method according to claim 5, wherein The voltage buffer includes a multi-way output switch, and the clock generator provides clock signals with different phases to control the multi-way output switches in the voltage buffer.