Charge compensation circuit, direct charge transfer circuit and digital-to-analog converter

Abstract

The invention relates to a charge compensation circuit, a direct charge transfer circuit and a digital-to-analog converter. The charge compensation circuit comprises one or more compensation sub-circuits. The compensation sub-circuit comprises a first compensation switch and a charge buffer; the first end of the first compensation switch is used for accessing a first reference voltage or a second reference voltage of the direct charge transfer circuit; a second end of the first compensation switch is used for connecting a first differential output end of a fully differential operational amplifier of the direct charge transfer circuit; the first compensation switch is connected with the charge buffer, and the charge buffer is used for transmitting compensation charges obtained before and after the first compensation switch is closed to the second differential input end of the fully differential operational amplifier. According to the invention, the charge injection effect of a direct charge transfer circuit can be eliminated, and the SNDR performance of the Sigma-Delta digital-to-analog converter is effectively improved.

Description

Technical Field

[0001] The present application relates to the field of electronic circuits, and in particular to a charge compensation circuit, a direct charge transfer circuit, and a digital-to-analog converter. Background Art

[0002] The fundamental structure of a multi-bit Δ∑ (sigma-delta) digital-to-analog converter (DAC) is a direct charge transfer (DCT) stage, also known as a direct charge transfer circuit. If the operational amplifier (OPA) in the direct charge transfer circuit is an ideal amplifier and all switches are ideal, the DAC (digital-to-analog converter) can achieve high SNDR (signal-to-noise and distortion ratio) performance. This high SNDR performance is the primary reason for the widespread use of multi-bit Δ∑ DACs in the audio field.

[0003] However, in practical DCT-DAC circuits, the limited bandwidth, slew rate, and low-frequency noise of the operational amplifier (op amp) all degrade SNDR performance. Switch non-idealities in the circuit are particularly detrimental to SNDR performance. Among these switch non-idealities, the most challenging to eliminate is channel charge injection, which arises from the absorption and release of channel charge during the instantaneous turn-on and turn-off of the switch. Eliminating charge injection in DCT-DAC circuits has become a pressing issue in improving the performance of multi-bit Δ∑ digital-to-analog converters. Summary of the Invention

[0004] Based on this, it is necessary to provide a charge compensation circuit, a direct charge transfer circuit and a digital-to-analog converter that can eliminate the charge injection effect of the direct charge transfer circuit.

[0005] In a first aspect, in one embodiment, the present application provides a charge compensation circuit, which is applied to a direct charge transfer circuit of a Sigma-Delta digital-to-analog converter; the charge compensation circuit includes one or more compensation sub-circuits; the compensation sub-circuit includes a first compensation switch and a charge buffer;

[0006] The first end of the first compensation switch is used to access the first reference voltage or the second reference voltage of the direct charge transfer circuit; the second end of the first compensation switch is used to connect to the first differential output end of the fully differential operational amplifier of the direct charge transfer circuit;

[0007] The first compensation switch is connected to a charge buffer, which is used to transfer the compensation charge obtained before and after the first compensation switch is closed to the second differential input terminal of the fully differential operational amplifier; the compensation charge is used to offset the injected charge generated by the switch capacitor subarray connected to the first differential input terminal in the direct charge transfer circuit; the number of compensation subcircuits is the same as the number of switch capacitor subarrays connected to the first differential input terminal.

[0008] In one embodiment, the compensation sub-circuit further includes a second compensation switch and a third compensation switch;

[0009] One end of the second compensation switch is used to access the second reference voltage, and the other end of the second compensation switch is connected to the first end of the first compensation switch;

[0010] One end of the third compensation switch is used to access the first reference voltage, and the other end of the third compensation switch is respectively connected to the first end of the first compensation switch and the other end of the second compensation switch.

[0011] In one embodiment, the size of the second compensation switch and the third compensation switch are both smaller than the size of the first compensation switch.

[0012] In one embodiment, the charge buffer includes a first buffer switch; the charge compensation circuit further includes a fourth compensation switch;

[0013] One end of the fourth compensation switch is used to connect to the first differential output end, and the other end of the fourth compensation switch is connected to the second end of the first compensation switch;

[0014] One end of the first buffer switch is connected between the first end of the first compensation switch and the other end of the fourth compensation switch, and the other end of the first buffer switch is used to connect to the second differential input end.

[0015] In one embodiment, the size of the first buffer switch and the size of the fourth compensation switch are both smaller than the size of the first compensation switch.

[0016] In one embodiment, the charge buffer includes a second buffer switch; the charge compensation circuit further includes a DC blocking capacitor;

[0017] One end of the second buffer switch is connected to the first end of the first compensation switch, the other end of the second buffer switch is connected to one end of the DC blocking capacitor, and the other end of the DC blocking capacitor is used to connect to the second differential input end.

[0018] In one embodiment, the size of the second buffer switch is smaller than the size of the first compensation switch.

[0019] In a second aspect, in one embodiment, the present application provides a direct charge transfer circuit for use in a Sigma-Delta digital-to-analog converter; the direct charge transfer circuit includes: a first switched capacitor array, a second switched capacitor array, a fully differential operational amplifier, a first feedback capacitor, a second feedback capacitor, a first control switch, a second control switch, a third control switch, and a fourth control switch; the first switched capacitor array and the second switched capacitor array each include an equal number of switched capacitor sub-arrays;

[0020] Each switched capacitor sub-array in the first switched capacitor array is connected to a non-inverting input terminal of a fully differential operational amplifier via a second control switch, one end of the first control switch is used to connect to a second reference voltage, and the other end of the first control switch is connected between each switched capacitor sub-array in the first switched capacitor array and the second control switch; the first switched capacitor array is also connected to an inverting output terminal of the fully differential operational amplifier, a first reference voltage, a second reference voltage, and a digital signal to be converted.

[0021] Each switched capacitor sub-array in the second switched capacitor array is connected to an inverting input terminal of a fully differential operational amplifier via a fourth control switch; one end of the third control switch is used to connect to a second reference voltage, and the other end of the third control switch is connected between each switched capacitor sub-array in the second switched capacitor array and the fourth control switch; the second switched capacitor array is also connected to a non-inverting output terminal of the fully differential operational amplifier, the first reference voltage, the second reference voltage, and a digital signal to be converted;

[0022] One end of the first feedback capacitor is connected to the non-inverting input terminal, and the other end of the first feedback capacitor is connected to the inverting output terminal; one end of the first feedback capacitor is connected to the inverting input terminal, and the other end of the first feedback capacitor is connected to the non-inverting output terminal;

[0023] The direct charge transfer circuit further includes two charge compensation circuits as described in any one of the embodiments of the first aspect: one charge compensation circuit is connected to the non-inverting input terminal, and the other charge compensation circuit is connected to the inverting input terminal;

[0024] Among them, the charge compensation circuit connected to the inverting input terminal uses the non-inverting input terminal as the first differential input terminal and the inverting input terminal as the second differential input terminal; the charge compensation circuit connected to the non-inverting input terminal uses the inverting input terminal as the first differential input terminal and the non-inverting input terminal as the second differential input terminal.

[0025] In one embodiment, the switch capacitor subarray includes a first sampling switch, a second sampling switch, a third sampling switch, and an integrating capacitor;

[0026] One end of the first sampling switch is connected to the first reference voltage, and the other end of the first sampling switch is respectively connected to one end of the integration capacitor, the other end of the second sampling switch, and the other end of the third sampling switch;

[0027] One end of the second sampling switch is connected to the second reference voltage, and the other end of the second sampling switch is also connected to one end of the integration capacitor and the other end of the third sampling switch;

[0028] When the switch capacitor sub-array is connected to the non-inverting input terminal, one end of the third sampling switch is connected to the inverting output terminal, the other end of the third sampling switch is connected to one end of the integrating capacitor, and the other end of the integrating capacitor is connected to the non-inverting input terminal through the second control switch;

[0029] When the switch capacitor subarray is connected to the inverting input terminal, one end of the third sampling switch is connected to the non-inverting output terminal, the other end of the third sampling switch is connected to one end of the integrating capacitor, and the other end of the integrating capacitor is connected to the inverting input terminal through the fourth control switch.

[0030] In a third aspect, in one embodiment, the present application provides a digital-to-analog converter comprising a direct charge transfer circuit as described in any one of the embodiments of the second aspect.

[0031] The charge compensation circuit, direct charge transfer circuit, and digital-to-analog converter described above are characterized in that the charge compensation circuit obtains a compensation charge equal in magnitude to the injected charge generated by the switch capacitor subarray connected to the first differential input terminal in the direct charge transfer circuit through the first compensation switch in the compensation subcircuit, and transmits the compensation charge to the second differential input terminal of the fully differential operational amplifier to offset the injected charge generated by the corresponding switch capacitor subarray, thereby effectively improving the SNDR performance of the Sigma-Delta digital-to-analog converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 is a schematic structural diagram of a conventional direct charge transfer circuit in one embodiment;

[0034] Figure 2 is a schematic structural diagram of a charge compensation circuit in one embodiment;

[0035] Figure 3 is a control timing sequence of a first compensation switch of a P array in one embodiment;

[0036] Figure 4 The control timing of the first compensation switch of the N array in one embodiment;

[0037] Figure 5 is a schematic structural diagram of another charge compensation circuit in one embodiment;

[0038] Figure 6 is a schematic structural diagram of yet another charge compensation circuit in one embodiment;

[0039] Figure 7 is a schematic structural diagram of a direct charge transfer circuit in one embodiment;

[0040] Figure 8 1 is a schematic structural diagram of yet another charge compensation circuit in one embodiment;

[0041] Figure 9 is a schematic structural diagram of another direct charge transfer circuit in one embodiment;

[0042] Figure 10 is a schematic structural diagram of yet another direct charge transfer circuit in one embodiment;

[0043] Figure 11 FIG. 4 is a schematic structural diagram of yet another direct charge transfer circuit in an embodiment. DETAILED DESCRIPTION

[0044] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0046] It will be understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor without departing from the scope of this application. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0047] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0048] It is understood that “at least one” refers to one or more, “a plurality” refers to two or more, and “at least a portion of an element” refers to a portion or all of an element.

[0049] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0050] For a multi-bit Δ∑ DAC (i.e., a multi-bit Sigma-Delta DAC), due to its small step size and low out-of-band noise power, its residual power decreases exponentially with the number of bits N retained after truncation. Therefore, the switched capacitor filter circuit of this type of DAC can be implemented with a relatively simple structure.

[0051] Specifically, the basic structure of a multi-bit Sigma-Delta DAC is a direct charge transfer stage (or direct charge transfer circuit). It is understandable that if the operational amplifier (OPA) in the direct charge transfer circuit is an ideal amplifier and all switches are ideal switches, the DAC can achieve a high signal-to-noise and distortion ratio (SNDR) performance. This is the main reason why Sigma-Delta DACs are widely used in the audio field.

[0052] However, in traditional DCT-DAC circuits, the limited bandwidth, conversion rate and low-frequency noise of the op amp will reduce the SNDR, and the non-ideal factors of the switches in the circuit have a particularly prominent impact on the SNDR performance.

[0053] Non-ideal factors in switches include channel charge injection, harmonic distortion caused by clock feedthrough, and an elevated noise floor due to KT / C noise from the switch capacitor. Specifically, of the three non-ideal factors mentioned above: KT / C noise is unavoidable and can only be reduced by increasing the area (i.e., increasing the size of the capacitor plates); while clock feedthrough has a significant impact, it originates from the gate-drain and gate-source overlap capacitance of the MOS switch. This capacitance is fixed and independent of the bias voltage on either side of the switch, causing the error to manifest as a fixed offset. This offset can be offset by the PMOS and NMOS transmission gates (although there may be a slight mismatch) or completely offset by a fully differential circuit; channel charge injection is the most difficult to eliminate, originating from the absorption and release of channel charge by the switch at the moment of turn-on or turn-off. Current methods for mitigating this charge injection effect include using dummy switches, CMOS complementary switches, parallel delay switches, or fully differential circuits.

[0054] However, in practical applications, none of the aforementioned methods can completely or significantly mitigate the effects of charge injection. The main reason for the difficulty in eliminating this charge injection effect is that the channel charge is a function of parameters such as the supply voltage, signal voltage, and even the body effect coefficient. Even the impedances on the left and right sides of the switch significantly affect the proportion of channel charge redistribution. Analysis of methods for mitigating this charge injection effect reveals that dummy switches can only be implemented with equal distribution of channel charge; CMOS complementary switches can only operate with a single input signal voltage (roughly half the supply voltage); parallel delay switches can only mitigate charge injection during a portion of the switch's OFF state, but not during the ON state; and fully differential circuit structures can only eliminate fixed offsets, not differential charge injection. Furthermore, while reducing the size of MOS switches can reduce injected charge, this also results in reduced circuit speed.

[0055] In order to make the application scenarios, technical objectives and advantages of the technical solutions of this application clearer, Figure 1 As shown, Figure 1 Given the traditional m bit (2 m =M) is analyzed. The specific analysis is as follows:

[0056] The operational amplifier OPA is a fully differential operational amplifier, the first feedback capacitor Cfbp and the second feedback capacitor Cfbn are the same feedback capacitors, and the first switched capacitor array (ie, P array) and the second switched capacitor array (ie, N array) each include M switched capacitor sub-arrays.

[0057] Cpi and Cni represent the integrating capacitors in the i-th (i=1, 2, ..., M) switched capacitor subarray in the first and second switched capacitor arrays. These capacitors are of equal magnitude and can be set to C0. S1pi, S2pi, and S3pi represent the three sampling switches in the i-th (i=1, 2, ..., M) switched capacitor subarray in the P array: S1pi is the first sampling switch in the P array, S2pi is the second sampling switch in the P array, and S3pi is the third sampling switch in the P array. Similarly, S1ni, S2ni, and S3ni represent the three switches in the i-th (i=1, 2, ..., M) switched capacitor subarray in the N array: S1ni is the first sampling switch in the N array, S2ni is the second sampling switch in the N array, and S3ni is the third sampling switch in the N array. It can be assumed that the signals on the left and right sides of the third sampling switch S3pi in the P array are EPi and FPi, respectively, and the signals on the left and right sides of the third sampling switch S3ni in the N array are ENi and FNi, respectively.

[0058] Furthermore, S4p and S5p are the first and second control switches, respectively, at the P-terminal (i.e., the circuit on the side of the non-inverting input terminal VINP of the fully differential amplifier OPA). S4p and S5p also serve as the two master switches for the P-terminal circuit. S4n and S5n are the first and second control switches, respectively, at the N-terminal (i.e., the circuit on the side of the inverting input terminal VINN of the fully differential amplifier OPA). S4n and S5n also serve as the two master switches for the N-terminal. The differential signals output by the fully differential operational amplifier OPA are VOUTP and VOUTN at the non-inverting and inverting output terminals, respectively.

[0059] like Figure 1 As shown, the node signals of the Cpi and Cni capacitors in parallel are SUMP and SUMN respectively, and the node signals of the OPA input are VINP and VINN respectively. In the above DCT-DAC circuit, the circuit is mainly controlled by a clock signal divided into two phases. Specifically, a pair of differential clock signals with a phase difference of 180 degrees is used. and To control DCT. The slightly delayed signal is , The slightly delayed signal is , the above and It is used to avoid S5p and S3pi, as well as S5n and S3ni from being turned on and off at the same time. In this way, the effect of charge injection from S5p and S5n can be eliminated. Figure 1 VREFP and VREFN shown are a first reference voltage (ie, a positive reference voltage) and a second reference voltage (ie, a negative reference voltage), respectively. Figure 1DP1~DP shown M and DN1~DN M All are digital signals to be converted, DN1~DN M It is DP1~DP M In actual application, DP1~DP M It can represent the digital signal data output by the modulator.

[0060] The charge injection effects caused by multiple transmission gate switches in the above DCT are different: In the stage, the charge injection effect caused by S4p and S4n can be completely eliminated by the differential circuit structure of DCT. Specifically, before and after the S4p and S4n switches are turned on and off, the voltage on the left and right sides remains at VREFN, which actually manifests as common-mode interference that can be eliminated by the differential circuit; the charge injection effect caused by S1pi, S2pi and S1ni, S2ni will not cause problems during the switch-on process, because these charges will be directly absorbed by VREFP or VREFN. In the switch-off process, since S4p and S4n have been turned off in advance, the right sides of Cpi and Cni The common points SUMP and SUMN of the switches are floating, causing most of the switch channel charge to be injected into the parasitic capacitance of the node to ground. Only a small portion of the charge can be injected into Cpi and Cni, causing their differential voltage to jump momentarily. This jump mainly depends on the ratio between the parasitic capacitance and the inherent capacitance, which is very small in practical applications. The charge injection effect caused by S5p and S5n can also be completely eliminated by the differential circuit. Before and after the S5p and S5n switches are turned on and off, the voltages on the left and right sides remain at VREFN, so it also manifests as common-mode interference that can be eliminated by the differential circuit.

[0061] It should be noted that in Figure 1 In the direct charge transfer circuit 10 shown, the switches that have the greatest impact on harmonic distortion due to charge injection are S3pi and S3ni, i.e., the third sampling switches. The specific analysis is as follows:

[0062] For the P array, S5p is already turned on before S3pi is turned on, and the voltage of SUMP is VREFN. Before the rising edge arrives, the node FPi on the left side of Cpi has been charged to VREFP or VREFN, and the voltage of the node EPi on the left side of the third sampling switch is VOUTP, which is a voltage that changes with the DAC output. When the rising edge arrives, the S3pi switch opens, and the channels on the left and right sides of the transmission gate switch need to absorb or release charges. Part of the charge is absorbed or released from VOUTP, and part of the charge is absorbed or released from the plate on the left side of Cpi. Since VOUTP is the output of the operational amplifier, its impedance is very low, and its absorption or release of charge will not have any effect on VOUTP. However, the charge absorbed or released from the plate on the left side of Cpi will cause a large change in the charge on the capacitor Cpi. Unfortunately, the charge absorbed or released by the plate on the left side of Cpi is related to the voltage of the current node FPi on the left side of Cpi ( Before the arrival of the node is charged to VREFP or VREFN, depending on the DP i and DN i ), and is also related to the current VOUTP voltage (S3pi goes from closed to open, with the voltages before and after being VREFP / VREFN and VOUTP respectively, and its charge change is proportional to the voltage difference before and after).

[0063] For the N array, S5n is already turned on before S3ni is turned on, and the voltage of SUMN is VREFN. Before the rising edge arrives, the node FNi on the left side of Cni has been charged to VREFP or VREFN, and the voltage of the node ENi on the left side of the third sampling switch is VOUTN, which is a voltage that changes with the DAC output. When the rising edge arrives, the S3ni switch opens, and the channels on the left and right sides of the transmission gate switch need to absorb or release charges. Part of the charge is absorbed or released from VOUTN, and part of the charge is absorbed or released from the left plate of capacitor Cni. Since VOUTN is the output terminal of the operational amplifier, its impedance is very low, and its absorption or release of charge will not have any effect on VOUTN; however, the charge absorbed or released from the left plate of capacitor Cni will cause a large change in the amount of charge on capacitor Cni. Unfortunately, the charge absorbed or released from the left plate of capacitor Cni is related to the voltage of the current node FNi to the left of Cni ( Before the arrival of the node is charged to VREFP or VREFN, depending on the DP i and DN i ), and is also related to the current VOUTN voltage (the switch S3ni switches from closed to open, with the voltages before and after being VREFP / VREFN and VOUTN respectively, and its charge change is proportional to the voltage difference before and after).

[0064] Since the charge injection effect of the third sampling switch is not only related to the currently input DPi and DNi signals, but also to the current voltages of VOUTP and VOUTN, and the charge injection directions on the P side and the N side are opposite, the traditional direct charge transfer circuit 10 cannot eliminate the nonlinear charge injection effect of the switch through a differential circuit.

[0065] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0066] In one embodiment, Figure 2 As shown, the present application provides a charge compensation circuit 20, which is applied to Figure 1 The direct charge transfer circuit 10 of the Sigma-Delta digital-to-analog converter shown in FIG. 1 includes one or more compensation subcircuits 202 ; the compensation subcircuit 202 includes a first compensation switch S3Ci and a charge buffer 204 ;

[0067] The first terminal APi of the first compensation switch S3Ci is used to connect to the second reference voltage VREFN or the second reference voltage of the direct charge transfer circuit 10; the second terminal BPi of the first compensation switch S3Ci is used to connect to the first differential output terminal VOUT1 of the fully differential operational amplifier OPA of the direct charge transfer circuit 10;

[0068] The first compensation switch S3Ci is connected to the charge buffer 204, which is used to transfer the compensation charge obtained before and after the first compensation switch S3Ci is closed to the second differential input terminal VIN2 of the fully differential operational amplifier OPA; the compensation charge is used to offset the injected charge generated by the switch capacitor sub-array connected to the first differential input terminal VIN1 in the direct charge transfer circuit 10; the number of compensation sub-circuits is the same as the number of switch capacitor sub-arrays connected to the first differential input terminal VIN1.

[0069] It can be understood that the compensation charges acquired before and after the first compensation switch S3Ci is closed are charges absorbed or injected before and after the first compensation switch S3Ci is closed.

[0070] In some examples, the first compensation switch S3Ci can be connected to the third sampling switch ( Figure 1The transmission gate switches (S3pi and S3ni) are identical in size. In this embodiment of the present application, the switch dimensions can be the ratio of the width-to-length ratios of NMOS or PMOS components. Furthermore, since transmission gate switches do not distinguish between left and right polarity, the corresponding features described above regarding the first terminal APi and the second terminal BPi of the first compensation switch S3Ci are effectively interchangeable, and the implementation principles after the interchange are the same as before the interchange, so further description is omitted.

[0071] In practical applications, when the first differential input terminal VIN1 is the non-inverting input terminal VINP of the fully differential operational amplifier OPA (i.e., the second terminal BPi of the first compensation switch S3Ci is connected to the non-inverting input terminal VINP), the first differential output terminal VOUT1 corresponds to the inverting output terminal VOUTP of the fully differential operational amplifier OPA; when the first differential input terminal VIN1 is the inverting input terminal VINN of the fully differential operational amplifier OPA (i.e., the second terminal BPi of the first compensation switch S3Ci is connected to the inverting input terminal VINN), the first differential output terminal VOUT1 corresponds to the non-inverting output terminal VOUTN of the fully differential operational amplifier OPA.

[0072] Specifically, the control timing of the charge compensation circuit in the embodiment of the present application in practical applications is as follows: Figure 3 and Figure 4 The specific analysis is as follows:

[0073] For the circuit on the P array side of the direct charge transfer circuit, the second end of the first compensation switch S3Cpi is connected to the non-inverting input terminal VINP of the fully differential operational amplifier OPA, and the size of the first compensation switch S3Cpi is the same as that of the third sampling switch S3pi of the P array.

[0074] In the charging phase of the direct charge transfer circuit, that is, When the third sampling switch S3pi of the P array is closed, the right node FPi of the third sampling switch S3pi of the P array will be charged to VREFP or VREFN. The voltage of the right node FPi actually depends on the input DP i Signal and DN i Signal (DP i and DN i The left node EPi of the third sampling switch S3pi of the P array is connected to the inverting output terminal VOUTP of the fully differential operational amplifier.

[0075] Based on the operating state of the third sampling switch S3pi of the P array, as shown in FIG. Figure 3 As shown, Figure 3 is the control timing of the first compensation switch S3Cpi of the P array. In the charging phase, the first compensation switch S3Cpi of the P array is disconnected, and the first terminal APi of the first compensation switch S3Cpi is charged to the same voltage VREFP or VREFN as the right node FPi of the third sampling switch S3pi of the P array (depending on the input DP i Signal and DN i Signal); the second terminal BPi of the first compensation switch S3Cpi of the P array is charged to the same voltage VOUTP as the left node EPi of the third sampling switch S3pi of the P array. In practice, however, the transmission gate switch does not distinguish between left and right polarities, and the left and right described above can be interchanged. Therefore, during the charging phase, the voltages at the nodes on both sides of the first compensation switch S3Cpi of the P array and the voltages at the nodes on both sides of the third sampling switch S3pi of the P array remain the same.

[0076] In the integration stage of the direct charge transfer circuit, that is, When the third sampling switch S3pi of the P array is closed, the voltages at the right node FPi and the left node EPi of the third sampling switch S3pi of the P array are both equal to the voltage VOUTP of the inverting output terminal of the fully differential operational amplifier. At this time, the first compensation switch S3Cpi of the P array is also turned on, and the voltages at the first terminal APi and the second terminal BPi of the first compensation switch S3Cpi of the P array are both charged to VOUTP. Therefore, during the integration phase, the voltages at the first and second terminals of the first compensation switch S3Cpi of the P array and the voltages at the left and right nodes of the third sampling switch S3pi of the P array remain the same. In other words, the charge absorbed or injected by the first compensation switch S3Cpi of the P array and the third sampling switch S3pi of the P array are equal before and after the third sampling switch S3pi of the P array is closed. The charge buffer 204 transfers the charge absorbed or injected before and after the first compensation switch S3Cpi of the P array to the inverting input terminal VINN of the fully differential operational amplifier OPA in a 1:1 ratio. Based on the preceding analysis, it can be understood that the charge absorbed or injected before and after the closure of the third sampling switch S3pi of the P array is transferred to the circuit's SUMP node and ultimately to the non-inverting input terminal VINP of the fully differential operational amplifier (the two are short-circuited after S5p is closed). Furthermore, the first compensation switch S3Cpi of the P array injects a charge of the same magnitude into VINN. For the differential output VOUTP-VOUTN, the injected charge from the non-inverting input terminal VINP and the compensation charge from the inverting input terminal VINN appear as common-mode signals, and thus have no impact on the THD+N (Total Harmonic Distortion + Noise) and SNDR of the differential output signal VOUTP-VOUTN.

[0077] Based on the same principles described above, the compensation of the injected charge of the N array is analyzed. For the circuit on the N array side of the direct charge transfer circuit, the second end of the first compensation switch is connected to the inverting input of the fully differential operational amplifier. The size of the first compensation switch S3Cni of the N array is the same as the third sampling switch S3Ni of the N array. Due to the symmetrical structure of the direct charge transfer circuit, the sizes of the first compensation switch S3Cni of the N array, the first compensation switch S3Cpi of the P array, the third sampling switch S3Ni of the N array, and the third sampling switch S3Pi of the P array are all the same.

[0078] In the charging phase of the direct charge transfer circuit, that is, When the third sampling switch S3ni of the N array is closed, the right node FNi of the third sampling switch S3ni of the N array is charged to VREFP or VREFN. The voltage of the right node FNi actually depends on the current DP i Signal and DN i signals (both of which are logically inverted), and the left node ENi of the third sampling switch S3ni of the N array is connected to the non-inverting output terminal VOUTN of the fully differential operational amplifier.

[0079] Based on the operating state of the third sampling switch S3ni of the above N array, as shown Figure 4 As shown, Figure 4 is the control timing of the first compensation switch S3Cni of the N array. In the charging phase, the first compensation switch S3Cni of the N array is disconnected, and the first terminal ANi of the first compensation switch S3Cni of the N array is charged to the same voltage VREFP or VREFN as the right node FNi of the third sampling switch S3ni of the N array (depending on the input DP i Signal and DN i Signal); the second terminal BNi of the first compensation switch S3Cni of the N array is charged to the same voltage VOUTN as the left node ENi of the third sampling switch S3ni of the N array. In practice, however, the transmission gate switch does not distinguish between left and right polarities, and the left and right described above can be interchanged. Therefore, during the charging phase, the voltages at the nodes on both sides of the first compensation switch S3Cni of the N array and the voltages at the nodes on both sides of the third sampling switch S3ni of the N array remain the same.

[0080] In the integration stage of the direct charge transfer circuit, that is, When the third sampling switch S3ni of the N array is closed, the voltages at the right node FNi and the left node ENi of the third sampling switch S3ni of the N array are both VOUTN. At this time, the first compensation switch S3Cni of the N array is also turned on, and the voltages at the first terminal ANi and the second terminal BNi of the first compensation switch S3Cni of the N array are both charged to VOUTN. Therefore, during the integration phase, the voltages at the nodes on both sides of the first compensation switch S3Cni of the N array and the voltages at the left and right nodes of the third sampling switch S3ni of the N array remain the same. In other words, the charge absorbed or injected by the first compensation switch S3Cni of the N array and the third sampling switch S3ni of the N array are equal before and after the third sampling switch S3ni of the N array is closed. The charge buffer transfers the charge absorbed or injected before and after the first compensation switch S3Cni of the N array to the non-inverting input terminal VINP of the fully differential operational amplifier OPA in a 1:1 ratio. Based on the preceding analysis, it can be understood that the charge absorbed or injected before and after the closure of the third sampling switch S3ni of the N array is transferred to the circuit's SUMP node and ultimately to the inverting input terminal VINN of the fully differential operational amplifier (the two are short-circuited after S5n is closed). Furthermore, the first compensation switch S3Cni of the N array injects a charge of the same magnitude into VINP. For the differential output VOUTP-VOUTN, the injected charge input from the inverting input terminal VINN and the compensation charge input from the non-inverting input terminal VINP appear as common-mode signals and have no effect on the THD+N and SNDR of the differential output signal VOUTP-VOUTN.

[0081] The charge compensation circuit of the present application obtains a compensation charge equal in magnitude to the injected charge generated by the switched capacitor subarray connected to the first differential input terminal of the direct charge transfer circuit through a first compensation switch in the compensation subcircuit, and transmits this compensation charge to the second differential input terminal of the fully differential operational amplifier, thereby compensating for the injected charge generated by the switched capacitor subarray, thereby effectively improving the SNDR performance of the Sigma-Delta digital-to-analog converter. In addition, simulation results show that the total harmonic distortion (THD) of a conventional direct charge transfer circuit without the charge compensation circuit of the present application is -80 dB. However, after the charge compensation circuit of the present application is adopted in the direct charge transfer circuit, the total harmonic distortion of the direct charge transfer circuit can be reduced to -100 dB. Therefore, the charge compensation circuit of the present application can significantly improve the THD index of the digital-to-analog converter and enhance the SNDR performance.

[0082] In one embodiment, Figure 5 As shown, the compensation sub-circuit 202 further includes a second compensation switch Ss3i and a third compensation switch Ss4i;

[0083] One end of the second compensation switch Ss3i is used to connect to the second reference voltage VREFN, and the other end of the second compensation switch Ss3i is connected to the first end of the first compensation switch S3Ci;

[0084] One end of the third compensation switch Ss4i is used to access the first reference voltage VREFP, and the other end of the third compensation switch Ss4i is respectively connected to the first end of the first compensation switch S3Ci and the other end of the second compensation switch Ss3i.

[0085] I understand. Figure 5 Only the second compensation switch Ss3i and the third compensation switch Ss4i of one compensation sub-circuit 202 of the charge compensation circuit are shown, and the other compensation sub-circuits 202 are provided with the second compensation switch Ss3i and the third compensation switch Ss4i with the same structural relationship.

[0086] Specifically, the embodiments of the present application are applied to Figure 1 As an example of the direct charge transfer circuit shown in FIG. 1 , the control timing of the second compensation switch is the same as the control timing of the first sampling switch of the P array and the N array (ie ), the control timing of the third compensation switch is the same as the control timing of the second sampling switches S2pi and S2ni of the P array and the N array (i.e. ), by controlling the on-off of the second compensation switch Ss3i and the third compensation switch Ss4i, it can be selected whether the first reference voltage or the second reference voltage is connected to the first end of the first compensation switch S3Ci.

[0087] In one embodiment, the size of the second compensation switch and the third compensation switch are both smaller than the size of the first compensation switch.

[0088] Exemplarily, the second compensation switch and the third compensation switch may be formed using switch elements with the smallest aspect ratio under the current process.

[0089] Specifically, by reducing the size of the second compensation switch and the third compensation switch, additional charge injection introduced by the second compensation switch and the third compensation switch can be avoided, and since the parasitic capacitance of each node of the charge compensation circuit is very small, the size reduction of the above switches does not affect the lower charge flow speed of the charge compensation circuit.

[0090] In one embodiment, Figure 6 As shown, the charge buffer includes a first buffer switch Ss2i; the charge compensation circuit further includes a fourth compensation switch Ss1i;

[0091] One end of the fourth compensation switch Ss1i is used to connect to the first differential output terminal VOUT1, and the other end of the fourth compensation switch Ss1i is connected to the second end of the first compensation switch S3Ci;

[0092] One end of the first buffer switch Ss2i is connected between the first end of the first compensation switch S3Ci and the other end of the fourth compensation switch Ss1i, and the other end of the first buffer switch Ss2i is connected to the second differential input terminal VIN2.

[0093] Among them, when the second differential input terminal VIN2 is the non-inverting input terminal VINP of the fully differential operational amplifier (that is, the second end of the first compensation switch S3Ci is connected to the non-inverting input terminal VINP), the second differential output terminal corresponds to the inverting output terminal of the fully differential operational amplifier; when the second differential input terminal VIN2 is the inverting input terminal VINN of the fully differential operational amplifier (that is, the second end of the first compensation switch S3Ci is connected to the inverting input terminal VINN), the second differential output terminal corresponds to the non-inverting output terminal VOUTN of the fully differential operational amplifier OPA.

[0094] Specifically, the embodiment of the present application is applied to Figure 1 As an example, the direct charge transfer circuit shown in FIG. 1 and the charge compensation circuit control the access voltage of the first end of the first compensation switch through the second compensation switch and the third compensation switch, as shown in FIG. Figure 7 As shown, Figure 7 The dotted boxes in the middle show the actual circuit structures of a compensation sub-circuit in the P array and the N array respectively. The specific implementation process is as follows:

[0095] For a switched capacitor subarray of a P array, stage, The logic and The logic is consistent, but Relative to There will be a slight delay, but it can be considered the same signal in analysis.

[0096] exist In the phase, the voltage of the first terminal APi of the first compensation switch of the P array is connected to the first reference voltage VREFP or the second reference voltage VREFN (depending on the current DP) by one of the second compensation switch Ssp3i and the third compensation switch Ssp4i. i Signal and DN i The P array receives a signal (a voltage signal), which is the same as the voltage at the FPi node of the third sampling switch S3pi of the current P array. Simultaneously, the second terminal BPi of the first compensation switch of the P array is connected to the inverting output terminal VOUTP of the fully differential operational amplifier via the fourth compensation switch Ssp1i of the P array. The first buffer switch Ssp2i (i.e., the charge buffer) of the P array is disconnected, and the first compensation switch S3Cpi of the P array is also disconnected. Optionally, the second compensation switch Ssp3i, the third compensation switch Ssp4i, the fourth compensation switch Ssp1i, and the first buffer switch Ssp2i are all ultra-small switches.

[0097] exist In the stage, the second compensation switch Ssp3i of the P array, the third compensation switch Ssp4i of the P array and the fourth compensation switch Ssp1i of the P array are disconnected, the first compensation switch S3Cpi of the P array and the first buffer switch Ssp2i of the P array are closed, and the first end APi and the second end BPi of the first compensation switch of the P array are connected to the inverting input terminal VINN by the first buffer switch Ssp2i of the P array and the compensation charge absorbed or injected by the first compensation switch is transferred to the inverting input terminal VINN.

[0098] Similarly, for a switched capacitor subarray of an N array, stage, The logic and The logic is consistent, but Relative to There will be a slight delay, but it can be considered the same signal in analysis.

[0099] exist In the phase, the voltage of the first terminal ANi of the first compensation switch of the P array is connected to the first reference voltage VREFP or the second reference voltage VREFN (depending on the current DP) by one of the second compensation switch Ssn3i and the third compensation switch Ssn4i. i Signal and DN i The N-array's first sampling switch S3ni is connected to the same voltage as the FNi node of the third sampling switch S3ni. Simultaneously, the second terminal BNi of the N-array's first compensation switch is connected to the non-inverting output terminal VOUTN of the fully differential operational amplifier via the fourth compensation switch Ssn1i. The N-array's first buffer switch Ssn2i (i.e., the charge buffer) is disconnected, as is the first compensation switch S3Cni of the N-array. Optionally, the second compensation switch Ssn3i, the third compensation switch Ssn4i, the fourth compensation switch Ssn1i, and the first buffer switch Ssn2i are all ultra-small switches.

[0100] exist In the first stage, the second compensation switch Ssn3i of the N array, the third compensation switch Ssn4i of the N array, and the fourth compensation switch Ssn1i of the N array are opened, the first compensation switch S3Cni of the N array and the first buffer switch Ssn2i of the N array are closed, and the first terminal ANi and the second terminal BNi of the first compensation switch of the N array are connected to the non-inverting input terminal VINP by the first buffer switch Ssn2i of the N array, and the compensation charge absorbed or injected by the first compensation switch is transferred to the non-inverting input terminal VINP.

[0101] In one embodiment, the size of the first buffer switch and the size of the fourth compensation switch are both smaller than the size of the first compensation switch.

[0102] Specifically, the second compensation switch, third compensation switch, fourth compensation switch and first buffer switch of the P array and N array can adopt switches with the minimum aspect ratio of the current minimum process, so as to avoid the above compensation switches introducing additional charge injection as much as possible.

[0103] In one embodiment, Figure 8 As shown, the charge buffer includes a second buffer switch Ss5i; the charge compensation circuit also includes a DC blocking capacitor Cci;

[0104] One end of the second buffer switch Ss5i is connected to the first end of the first compensation switch S3Ci, the other end of the second buffer switch Ss5i is connected to one end of the DC blocking capacitor Cci, and the other end of the DC blocking capacitor Cci is connected to the second differential input terminal VIN2.

[0105] Among them, when the second differential input terminal VIN2 is the non-inverting input terminal VINP of the fully differential operational amplifier (that is, the second end of the first compensation switch S3Ci is connected to the non-inverting input terminal VINP), the second differential output terminal corresponds to the inverting output terminal of the fully differential operational amplifier; when the second differential input terminal VIN2 is the inverting input terminal VINN of the fully differential operational amplifier (that is, the second end of the first compensation switch S3Ci is connected to the inverting input terminal VINN), the second differential output terminal corresponds to the non-inverting output terminal VOUTN of the fully differential operational amplifier OPA.

[0106] Specifically, the embodiment of the present application is applied to Figure 1 As an example, the direct charge transfer circuit shown in FIG. 1 and the charge compensation circuit control the access voltage of the first end of the first compensation switch through the second compensation switch and the third compensation switch, as shown in FIG. Figure 9 As shown, Figure 9 The dotted boxes in the middle show the actual circuit structures of a compensation sub-circuit in the P array and the N array respectively. The specific implementation process is as follows:

[0107] For a switched capacitor subarray of a P array, stage, Logical AND Same, just There is a slight delay, which can be considered and is the same signal. During this phase, the voltage at the first terminal APi of the first compensation switch of the P array is connected to the first reference voltage VREFP or the second reference voltage VREFN (depending on the currently input DPi and DNi signals) by either the second compensation switch Ssp3i or the third compensation switch Ssp4i of the P array. This means that the voltage at the first terminal APi of the first compensation switch of the P array is the same as the voltage at the FPi node of the third sampling switch S3pi of the P array. Simultaneously, the second terminal BPi of the first compensation switch of the P array is connected to the inverting output terminal VOUTP of the fully differential operational amplifier. Furthermore, the second buffer switch Ssp5i of the P array is disconnected, as is the first compensation switch S3Cpi of the P array. Optionally, the second compensation switch Ssp3i, the third compensation switch Ssp4i, and the second buffer switch Ssp5i of the P array are all ultra-small switches.

[0108] exist In the first stage, the second compensation switch Ssp3i and the third compensation switch Ssp4i of the P array are disconnected, the first compensation switch S3Cpi of the P array and the second buffer switch Ssp5i of the P array are closed, and the node voltage of the first terminal APi of the first compensation switch is short-circuited to the inverting output terminal VOUTP. At the same time, the compensation charge absorbed or injected into the APi node can be injected into the inverting input terminal VINN of the fully differential operational amplifier through the DC blocking capacitor Ccpi of the P array.

[0109] Similarly, for a switched capacitor subarray of an N array, stage, in which Logical AND Same, just There is a slight delay, which can be considered and is the same signal. During this phase, the voltage at the first terminal ANi of the first compensation switch of the N array is connected to the first reference voltage VREFP or the second reference voltage VREFN (depending on the currently input DPi and DNi signals) via either the second compensation switch Ssn3i or the third compensation switch Ssn4i of the N array. This means that the voltage at the first terminal ANi of the first compensation switch of the N array is the same as the voltage at the FNi node of the third sampling switch S3ni of the N array. Simultaneously, the second terminal BNi of the first compensation switch of the N array is connected to the non-inverting output terminal VOUTN of the fully differential operational amplifier. Furthermore, the second buffer switch Ssn5i is disconnected, as is the first compensation switch S3Cni of the N array. Optionally, the second compensation switch Ssn3i, the third compensation switch Ssn4i, and the second buffer switch Ssn5i are all ultra-small switches.

[0110] exist In the first stage, the second compensation switch Ssn3i and the third compensation switch Ssn4i of the N array are opened, the first compensation switch S3cni of the N array and the second buffer switch Ssn5i of the N array are closed, and the node voltage of the first end ANi of the first compensation switch is short-circuited to VOUTN. At the same time, the compensation charge absorbed or injected into the ANi node is injected into the non-inverting input terminal VINP of the fully differential operational amplifier through the DC blocking capacitor Ccni of the N array.

[0111] In one embodiment, the size of the second buffer switch is smaller than the size of the first compensation switch.

[0112] Exemplarily, the second compensation switch, third compensation switch, fourth compensation switch and second buffer switch of the P array and N array can adopt switches with the minimum aspect ratio of the current minimum process, so as to avoid the above compensation switches introducing additional charge injection as much as possible.

[0113] In one embodiment, Figure 10 As shown, the present application provides a direct charge transfer circuit 30, which is applied to a Sigma-Delta digital-to-analog converter; the direct charge transfer circuit 30 includes: a first switched capacitor array (an array consisting of M switched capacitor sub-arrays 40 on the circuit side of the non-inverting input terminal of the fully differential operational amplifier OPA in the figure), a second switched capacitor array (an array consisting of M switched capacitor sub-arrays 40 on the circuit side of the inverting input terminal of the fully differential operational amplifier OPA in the figure), a fully differential operational amplifier OPA, a first feedback capacitor Cfbp, a second feedback capacitor Cfbn, a first control switch S4p, a second control switch S5p, a third control switch S4n, and a fourth control switch S5n; the first switched capacitor array and the second switched capacitor array each include the same number of switched capacitor sub-arrays 40;

[0114] Each switched capacitor sub-array 40 in the first switched capacitor array is connected to the non-inverting input terminal VINP of the fully differential operational amplifier OPA via a second control switch S5p. One end of the first control switch S4p is used to connect to the second reference voltage VREFN, and the other end of the first control switch S4p is connected between each switched capacitor sub-array 40 in the first switched capacitor array and the second control switch S5p. The first switched capacitor array is also connected to the inverting output terminal VOUTP of the fully differential operational amplifier OPA, the first reference voltage VREFP, the second reference voltage VREFN, and the digital signal to be converted.

[0115] Each switched capacitor sub-array 40 in the second switched capacitor array is connected to the inverting input terminal VINN of the fully differential operational amplifier OPA via a fourth control switch S5n. One end of the third control switch S4n is used to connect to the second reference voltage VREFN, and the other end of the third control switch S4n is connected between each switched capacitor sub-array 40 in the second switched capacitor array and the fourth control switch S5n. The second switched capacitor array is also connected to the non-inverting output terminal VOUTN of the fully differential operational amplifier OPA, the first reference voltage VREFP, the second reference voltage VREFN, and the digital signal to be converted.

[0116] One end of the first feedback capacitor Cfbp is connected to the non-inverting input terminal VINP, and the other end of the first feedback capacitor Cfbp is connected to the inverting output terminal VOUTP; one end of the first feedback capacitor Cfbp is connected to the inverting input terminal VINN, and the other end of the first feedback capacitor Cfbp is connected to the non-inverting output terminal VOUTN;

[0117] The direct charge transfer circuit further includes two charge compensation circuits as described in any one of the above embodiments: one charge compensation circuit is connected to the non-inverting input terminal VINP, and the other charge compensation circuit is connected to the inverting input terminal VINN;

[0118] Among them, the charge compensation circuit connected to the inverting input terminal VINN uses the non-inverting input terminal VINP as the first differential input terminal and the inverting input terminal VINN as the second differential input terminal; the charge compensation circuit connected to the non-inverting input terminal VINP uses the inverting input terminal VINN as the first differential input terminal and the non-inverting input terminal VINP as the second differential input terminal.

[0119] In one embodiment, Figure 11 As shown, the switch capacitor subarray 40 includes a first sampling switch S1i, a second sampling switch S2i, a third sampling switch S3i and an integrating capacitor Ci;

[0120] One end of the first sampling switch S1i is connected to the first reference voltage VREFP, and the other end of the first sampling switch S1i is respectively connected to one end of the integral capacitor Ci, the other end of the second sampling switch S2i, and the other end of the third sampling switch S3i;

[0121] One end of the second sampling switch S2i is connected to the second reference voltage VREFN, and the other end of the second sampling switch S2i is also connected to one end of the integration capacitor Ci and the other end of the third sampling switch S3i;

[0122] When the switch capacitor sub-array 40 is connected to the non-inverting input terminal VINP, one end of the third sampling switch S3i is connected to the inverting output terminal VOUTP, and the other end of the third sampling switch S3i is connected to one end of the integrating capacitor Ci, and the other end of the integrating capacitor Ci is connected to the non-inverting input terminal VINP via the second control switch S5p.

[0123] When the switched capacitor subarray 40 is connected to the inverting input terminal VINN, one end of the third sampling switch S3i is connected to the non-inverting output terminal VOUTN, the other end of the third sampling switch S3i is connected to one end of the integrating capacitor Ci, and the other end of the integrating capacitor Ci is connected to the inverting input terminal VINN via the fourth control switch S5n.

[0124] It should be noted that the specific definition of the direct charge transfer circuit in the embodiment of the present application can refer to the specific definition of the charge compensation circuit in the above embodiments, such as the control timing of each switch in each direct charge transfer circuit and Figure 1 The switch control timing shown is the same and will not be repeated here.

[0125] In one embodiment, the present application provides a digital-to-analog converter, comprising the direct charge transfer circuit as described in any one of the above embodiments. Specifically, the digital-to-analog converter is a Sigma-Delta digital-to-analog converter.

[0126] In the description of this specification, reference to the terms "some embodiments" or "other embodiments" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0127] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0128] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A charge compensation circuit, characterized in that: A direct charge transfer circuit applied to a Sigma-Delta digital-to-analog converter; the charge compensation circuit comprises one or more compensation subcircuits; the compensation subcircuits comprise a first compensation switch and a charge buffer; The first end of the first compensation switch is used to access the first reference voltage or the second reference voltage of the direct charge transfer circuit; the second end of the first compensation switch is used to connect to the first differential output end of the fully differential operational amplifier of the direct charge transfer circuit; The first compensation switch is connected to the charge buffer, and the charge buffer is used to transmit the compensation charge acquired before and after the first compensation switch is closed to the second differential input terminal of the fully differential operational amplifier; The compensation charge is used to offset the injected charge generated by the switch capacitor subarray connected to the first differential input terminal in the direct charge transfer circuit; The number of the compensation sub-circuits is the same as the number of the switch capacitor sub-arrays connected to the first differential input terminal.

2. The charge compensation circuit according to claim 1, wherein: The compensation sub-circuit further includes a second compensation switch and a third compensation switch; One end of the second compensation switch is used to access the second reference voltage, and the other end of the second compensation switch is connected to the first end of the first compensation switch; One end of the third compensation switch is used to access the first reference voltage, and the other end of the third compensation switch is respectively connected to the first end of the first compensation switch and the other end of the second compensation switch.

3. The charge compensation circuit according to claim 2, wherein: The sizes of the second compensation switch and the third compensation switch are both smaller than that of the first compensation switch.

4. The charge compensation circuit according to claim 1 or 2, characterized in that: The charge buffer includes a first buffer switch; the charge compensation circuit also includes a fourth compensation switch; One end of the fourth compensation switch is used to connect to the first differential output end, and the other end of the fourth compensation switch is connected to the second end of the first compensation switch; One end of the first buffer switch is connected between the first end of the first compensation switch and the other end of the fourth compensation switch, and the other end of the first buffer switch is used to connect to the second differential input end.

5. The charge compensation circuit according to claim 4, characterized in that: The size of the first buffer switch and the size of the fourth compensation switch are both smaller than the size of the first compensation switch.

6. The charge compensation circuit according to claim 1 or 2, characterized in that: The charge buffer includes a second buffer switch; the charge compensation circuit also includes a DC blocking capacitor; One end of the second buffer switch is connected to the first end of the first compensation switch, the other end of the second buffer switch is connected to one end of the DC blocking capacitor, and the other end of the DC blocking capacitor is connected to the second differential input end.

7. The charge compensation circuit according to claim 6, wherein: A size of the second buffer switch is smaller than a size of the first compensation switch.

8. A direct charge transfer circuit, characterized in that: Applied to Sigma-Delta digital-to-analog converters; The direct charge transfer circuit includes: a first switched capacitor array, a second switched capacitor array, a fully differential operational amplifier, a first feedback capacitor, a second feedback capacitor, a first control switch, a second control switch, a third control switch, and a fourth control switch; the first switched capacitor array and the second switched capacitor array each include the same number of switched capacitor sub-arrays; Each switched capacitor sub-array in the first switched capacitor array is connected to a non-inverting input terminal of the fully differential operational amplifier via the second control switch, one end of the first control switch is used to connect to a second reference voltage, and the other end of the first control switch is connected between each switched capacitor sub-array in the first switched capacitor array and the second control switch; the first switched capacitor array is also connected to an inverting output terminal of the fully differential operational amplifier, a first reference voltage, a second reference voltage, and a digital signal to be converted, respectively; Each switched capacitor sub-array in the second switched capacitor array is connected to the inverting input terminal of the fully differential operational amplifier via the fourth control switch; one end of the third control switch is used to connect to the second reference voltage, and the other end of the third control switch is connected between each switched capacitor sub-array in the second switched capacitor array and the fourth control switch; the second switched capacitor array is also connected to the non-inverting output terminal of the fully differential operational amplifier, the first reference voltage, the second reference voltage, and the digital signal to be converted; One end of the first feedback capacitor is connected to the non-inverting input terminal, and the other end of the first feedback capacitor is connected to the inverting output terminal; one end of the first feedback capacitor is connected to the inverting input terminal, and the other end of the first feedback capacitor is connected to the non-inverting output terminal; The direct charge transfer circuit further comprises two charge compensation circuits according to any one of claims 1 to 7: one of the charge compensation circuits is connected to the non-inverting input terminal, and the other of the charge compensation circuits is connected to the inverting input terminal; Among them, the charge compensation circuit connected to the inverting input terminal uses the non-inverting input terminal as the first differential input terminal and the inverting input terminal as the second differential input terminal; the charge compensation circuit connected to the non-inverting input terminal uses the inverting input terminal as the first differential input terminal and the non-inverting input terminal as the second differential input terminal.

9. The direct charge transfer circuit according to claim 8, characterized in that: The switch capacitor subarray includes a first sampling switch, a second sampling switch, a third sampling switch and an integrating capacitor; One end of the first sampling switch is connected to the first reference voltage, and the other end of the first sampling switch is respectively connected to one end of the integration capacitor, the other end of the second sampling switch, and the other end of the third sampling switch; One end of the second sampling switch is connected to the second reference voltage, and the other end of the second sampling switch is also connected to one end of the integration capacitor and the other end of the third sampling switch; When the switch capacitor sub-array is connected to the non-inverting input terminal, one end of the third sampling switch is connected to the inverting output terminal, the other end of the third sampling switch is connected to one end of the integration capacitor, and the other end of the integration capacitor is connected to the non-inverting input terminal via the second control switch; When the switch capacitor sub-array is connected to the inverting input terminal, one end of the third sampling switch is connected to the non-inverting output terminal, the other end of the third sampling switch is connected to one end of the integrating capacitor, and the other end of the integrating capacitor is connected to the inverting input terminal through the fourth control switch.

10. A digital-to-analog converter, characterized in that: Comprising the direct charge transfer circuit as claimed in claim 8 or 9.

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