Serial-to-parallel conversion circuit and serial-to-deserial circuit
Through the design of the serial-parallel conversion circuit, the clock frequency division and data cache module are used to solve the problem of insufficient selectivity of the output data of the existing SIPO circuit, and parallel data output with multiple bit widths is realized to meet the diversified needs of SERDES.
Patent Information
- Application Number
- CN202510350523.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-24
- Publication Date
- 2025-08-08
AI Technical Summary
The existing SIPO circuit has insufficient in the bit width selectivity of output data, which is difficult to meet the SERDES requirements for multiple bit widths.
The serial-parallel conversion circuit is adopted, including a first deserialization module, a second deserialization module and a clock frequency division module, and selective outputs of multiple parallel data bit widths are realized through clock frequency division and data cache.
The selectivity of parallel data bit width is increased, and parallel data with multiple bit widths can be output to meet the SERDES requirements for different bit widths.
Smart Images
Figure CN120454738A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of data transmission, and more specifically, to a serial-to-parallel conversion circuit and a serial-to-deserialization circuit. Background Art
[0002] In the development of field-programmable gate arrays (FPGAs), high-speed serializer / deserializer (SERDES) circuits are a key component, often used to handle high-speed communications. The serial-in to parallel-out (SIPO) converter deserializes the input serialized data and outputs parallel data and a clock, based on the required rate, bit width, latency, and power consumption of the SERDES receiver.
[0003] SIPO circuits are available in full-rate and half-rate configurations. With the increasing demand for data transmission rates, the half-rate configuration offers significant advantages in terms of timing, power consumption, and circuit structure. While this configuration ensures the accuracy of deserialization results to a large extent by performing step-by-step deserialization of data, it does, however, offer limited flexibility in output data bit width. Summary of the Invention
[0004] The present application proposes a serial-to-parallel conversion circuit and a serial-to-deserialization circuit to improve the above-mentioned defects.
[0005] In the first aspect, the present application provides a serial-to-parallel conversion circuit, comprising: a first deserialization module, a second deserialization module and a clock frequency division module; the first output end of the clock frequency division module is connected to the first input end of the first deserialization module, and the second output end of the clock frequency division module is connected to the second input end of the first deserialization module, the first output end is used to output a Q-divided clock signal, and the second output end is used to output a 2Q-divided clock signal, where Q is a positive integer, and the first deserialization module is used to convert R-bit-wide serial data into 2R-bit-wide parallel data, where R is a positive integer; the second deserialization module includes a temporary storage module, a selection module and a trigger module, and the output end of the first deserialization module is connected to the temporary module The first input end of the block is connected, the second output end is connected to the second input end of the temporary storage module, the temporary storage module is used to cache the first data of M bit width, M is greater than 2R and is an integer multiple of 2R; the output end of the temporary storage module is connected to the input end of the selection module, the control end of the selection module is used to receive a first control signal, the output end of the selection module is connected to the first input end of the trigger module, the selection module is used to output second data according to the first control signal, the second data is part of the first data; the third output end of the clock division module is connected to the second input end of the trigger module, and the output end of the trigger module is used to output each bit of the second data in parallel.
[0006] Optionally, for a possible implementation, it also includes: an AND gate; the fourth output end of the clock division module is connected to the first input end of the AND gate, the second input end of the AND gate is used to receive a second control signal, and the output end of the AND gate is connected to the control end of the selection module, for outputting a first control signal to the selection module, wherein the clock signal output by the third output end corresponds to the second control signal.
[0007] Optionally, for a possible implementation, the temporary storage module has M temporary storage output terminals arranged in sequence; the selection module has N multiplexers arranged in sequence, the N temporary storage output terminals arranged in sequence starting from the first are respectively connected to the first input terminals of the N multiplexers arranged in sequence, the N temporary storage output terminals arranged in sequence starting from the (MN)th are respectively connected to the second input terminals of the N multiplexers arranged in sequence, and the signal control terminals of the N multiplexers arranged in sequence are connected to the output terminal of the AND gate; the trigger module includes N first triggers, the output terminals of the N multiplexers arranged in sequence are respectively connected to the first input terminals of the N first triggers, and the third output terminal of the clock division module is respectively connected to the second input terminals of the N first triggers.
[0008] Optionally, for a possible implementation, the output end of the first deserialization module is 4 parallel output ends, the temporary storage module has 4 groups of sub-modules, the data input end of each group of sub-modules is respectively connected to the 4 parallel output ends, and each group of sub-modules has 3 temporary storage output ends.
[0009] Optionally, for a possible implementation, each of the sub-modules includes three second triggers connected in series, the clock signal end of each second trigger is connected to the second output end, and the data output end of each second trigger is the temporary storage output end of the temporary storage module.
[0010] Optionally, for a possible implementation, each of the sub-modules includes a third trigger and a fourth trigger connected in series, the clock signal end of the third trigger and the clock signal end of the fourth trigger are both connected to the third output end, and the data input end and data output end of the third trigger, as well as the data output end of the fourth trigger are all temporary storage output ends of the temporary storage module.
[0011] Optionally, for a possible implementation, the fourth output terminal outputs a 10Q frequency-divided clock signal, and when the second control signal is at a low level, the third output terminal outputs a 4Q frequency-divided clock signal, and when the second control signal is at a high level, the third output terminal outputs a 5Q frequency-divided clock signal.
[0012] Optionally, for a possible implementation, it also includes: an adjustment module, the output end of the trigger module is connected to the input end of the adjustment module, and the output end of the adjustment module is used to output in parallel each bit of the target data of the target bit width determined by the first order in the second data when the bit width of the second data is greater than the target bit width, wherein the first order is the order from low bit to high bit.
[0013] Optionally, for a possible implementation, M is 12, N is 10, and the target bit width is 8 or 10.
[0014] In the second aspect, the present application also provides a serial deserialization circuit, comprising: a continuous-time linear equalizer, a decision feedback equalizer and the aforementioned serial-to-parallel conversion circuit; the output end of the continuous-time linear equalizer is connected to the input end of the decision feedback equalizer, and the output end of the decision feedback equalizer is connected to the data input end of the serial-to-parallel conversion circuit.
[0015] The present application provides a serial-to-parallel conversion circuit, comprising: a first deserialization module, a second deserialization module and a clock frequency division module; the first output end of the clock frequency division module is connected to the first input end of the first deserialization module, the second output end of the clock frequency division module is connected to the second input end of the first deserialization module, the first output end is used to output a Q-divided clock signal, the second output end is used to output a 2Q-divided clock signal, Q is a positive integer, the first deserialization module is used to convert R-bit-width serial data into 2R-bit-width parallel data, R is a positive integer; the second deserialization module includes a temporary storage module, a selection module and a trigger module, the output end of the first deserialization module is connected to the temporary storage module The first input end is connected, the second output end is connected to the second input end of the temporary storage module, the temporary storage module is used to cache the first data of M bit width, M is greater than 2R and is an integer multiple of 2R; the output end of the temporary storage module is connected to the input end of the selection module, the control end of the selection module is used to receive a first control signal, the output end of the selection module is connected to the first input end of the trigger module, the selection module is used to output second data according to the first control signal, the second data is part of the first data; the third output end of the clock division module is connected to the second input end of the trigger module, and the output end of the trigger module is used to output each bit of the second data in parallel.
[0016] The output of the first deserialization module is connected to the first input of the temporary storage module. The temporary storage module stores the data output by the first deserialization module to facilitate transmission of the cached data to the selection module. The output of the selection module is connected to the first input of the trigger module. The selection module outputs the second data in response to the first control signal. The output of the trigger module outputs each bit of the second data in parallel, thereby achieving parallel output of each bit of the second data. The second data is a portion of the first data, and the bit width of the second data can be set in various ways, thereby achieving multiple selectivity of the output data bit width.
[0017] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0019] Figure 1 A schematic diagram of an existing serial-to-parallel conversion circuit is shown;
[0020] Figure 2 A schematic diagram of the structure of a serial-to-parallel conversion circuit provided in an embodiment of the present application is shown;
[0021] Figure 3 A schematic structural diagram of a serial-to-parallel conversion circuit according to another embodiment of the present application is shown;
[0022] Figure 4 A schematic structural diagram of a serial-to-parallel conversion circuit provided in another embodiment of the present application is shown;
[0023] Figure 5 shows a timing diagram of a serial-to-parallel conversion circuit provided in an embodiment of the present application;
[0024] Figure 6 A timing diagram of a serial-to-parallel conversion circuit provided in another embodiment of the present application is shown. DETAILED DESCRIPTION
[0025] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for which protection is claimed, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work fall within the scope of protection of the present application.
[0026] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.
[0027] In the development of field-programmable gate arrays (FPGAs), high-speed serializer / deserializer (SERDES) circuits are a key component, often used to handle high-speed communications. The serial-in to parallel-out (SIPO) converter deserializes the input serialized data and outputs parallel data and a clock, based on the required rate, bit width, latency, and power consumption of the SERDES receiver.
[0028] SIPO circuits are divided into full-rate and half-rate structures. As the demand for data transmission rate continues to increase, the half-rate structure has shown sufficient advantages in timing, power consumption, circuit structure, etc. The basic working principle of the half-rate SIPO structure is as follows: Figure 1 As shown. In one parallel cycle, after N serial clock cycles, the serial data is sequentially transferred to each register (FF0', FF1', FF2', ..., FFN') for shift storage. When the parallel clock rises, parallel data with a bit width of N is output. Although this structure can ensure the correctness of the deserialization result to a great extent by deserializing the data step by step. However, the output data bit width of this structure is poorly selectable. For example, the output data bit width required by SERDES is 8, 10, 16, 20...64, 80 bits, while the traditional SIPO structure is limited by the data bit width selectivity after serial-to-parallel conversion, and can only provide 8, 16...64 bits of parallel data, which is relatively rigid and difficult to meet the output data bit width requirements of SERDES.
[0029] Therefore, in an embodiment of the present application, a serial-to-parallel conversion circuit is provided to solve or partially solve the above-mentioned problems.
[0030] See also Figure 2 , which shows a structural block diagram of a serial-to-parallel conversion circuit provided in an embodiment of the present application, including:
[0031] A first deserialization module 120 , a second deserialization module 130 and a clock frequency division module 110 .
[0032] The first output end 111 of the clock frequency division module is connected to the first input end 121 of the first deserialization module, and the second output end 112 of the clock frequency division module is connected to the second input end 122 of the first deserialization module. The first output end 111 is used to output a Q-divided clock signal, and the second output end 112 is used to output a 2Q-divided clock signal, where Q is a positive integer. The first deserialization module 120 is used to convert serial data with an R-bit width into parallel data with a 2R-bit width, where R is a positive integer.
[0033] The second deserialization module 130 includes a temporary storage module 140, a selection module 150 and a trigger module 160. The output end 123 of the first deserialization module is connected to the first input end 141 of the temporary storage module, and the second output end 112 is connected to the second input end 142 of the temporary storage module. The temporary storage module is used to cache the first data with an M-bit width, where M is greater than 2R and is an integer multiple of 2R.
[0034] The output end 143 of the temporary storage module is connected to the input end 151 of the selection module, the control end 152 of the selection module is used to receive a first control signal, the output end 153 of the selection module is connected to the first input end 161 of the trigger module, and the selection module is used to output second data according to the first control signal, and the second data is part of the first data.
[0035] The third output terminal 113 of the clock frequency dividing module is connected to the second input terminal 162 of the trigger module. The output terminal 163 of the trigger module is used to output each bit of the second data in parallel.
[0036] It should be noted that the clock divider module can convert the input high-frequency clock signal into one or more lower-frequency clock signals to meet the clock frequency requirements of different modules or devices. For example, a 100MHz clock signal can be divided into 50MHz and 25MHz clock signals.
[0037] In the embodiment of the present application, clock division can be achieved through a counter, a phase-locked loop, a programmable logic circuit or a dedicated clock division chip.
[0038] As an embodiment, the clock division module includes a counter, which counts at the rising edge or falling edge of each input clock signal. When the count value reaches a preset division coefficient, the counter is reset and triggers the flipping of the output signal, thereby generating a divided clock signal.
[0039] As an implementation method, the clock division module includes a phase-locked loop, which divides the input clock signal through internal components such as a pre-divider, a phase frequency detector, a charge pump, a filter, and a voltage-controlled oscillator to generate the required output frequency and obtain a divided clock signal.
[0040] As an implementation method, in FPGA design, the frequency division logic is written in hardware description language, and the frequency division is achieved by combining counters and logic gates. This method is highly flexible and can be customized according to specific needs.
[0041] It should be noted that the deserialization module is used to convert serial data into parallel data. The working principle of serial-to-parallel conversion is as follows: Figure 1As shown, after N serial clock cycles, N bits of serial data are stored in N registers respectively. When the rising edge or falling edge of the parallel clock arrives, each register outputs data at the same time, thereby achieving the purpose of converting serial data into parallel data.
[0042] In this embodiment, the first output of the clock divider module outputs a Q-divided clock signal to the first input of the first deserialization module, and the second output of the clock divider module outputs a 2Q-divided clock signal to the second input of the first deserialization module. Therefore, the first deserialization module can convert R-bit-width serial data into 2R-bit-width parallel data based on the received Q-divided clock signal and the 2Q-divided clock signal. For example, if the bit width of the serial data input to the first deserialization module is 2 bits, the bit width of the parallel data output by the first deserialization module is 4 bits.
[0043] It should be noted that the output of the first deserialization module is connected to the first input of the temporary storage module. The temporary storage module stores the data output by the first deserialization module to facilitate transmission of the cached data to the selection module. The output of the selection module is connected to the first input of the trigger module, and the selection module outputs the second data in response to the first control signal. The output of the trigger module outputs each bit of the second data in parallel, thereby achieving parallel output of each bit of the second data. The second data is part of the first data. To this end, the bit width of the second data can be set in multiple ways, enabling multiple selectivity of the output data bit width.
[0044] As an implementation method, the bit width of the parallel data transmitted from the first deserialization module to the temporary storage module is 4 bits, the bit width of the first data is 12 bits, and the bit width of the second data is 10 bits. Then, 10-bit parallel data can be output through the trigger module. Based on 10 bits, parallel data with bit widths of 20 bits, 40 bits, 80 bits, etc. can also be obtained. Compared with the exponentially growing bit widths that can only output 8 bits, 16 bits, 32 bits, etc., the serial-to-parallel conversion circuit of the present application increases the selectivity of the output bit width of the parallel data.
[0045] As an alternative implementation, see Figure 2 The serial-to-parallel conversion circuit further includes: an AND gate 170; the fourth output terminal 114 of the clock frequency division module is connected to the first input terminal 171 of the AND gate, the second input terminal 172 of the AND gate is used to receive the second control signal, and the output terminal 173 of the AND gate is connected to the control terminal 152 of the selection module, for outputting the first control signal to the selection module, wherein the clock signal output by the third output terminal corresponds to the second control signal.
[0046] It can be known that the first control signal is used to control the selection module to output the second data, and the second data is part of the first data. The first control signal can be manually input or pre-set. The first control signal can also be obtained by the AND gate receiving the second control signal and the clock signal output by the fourth output terminal.
[0047] As an implementation method, the AND gate obtains a first control signal based on the clock signal output from the fourth output terminal of the clock division module and the second control signal. If the signal output from the fourth output terminal is a high level and the second control signal is a high level signal, the first control signal is a high level signal, and the selection module outputs the data corresponding to the high level signal as the second data; otherwise, the first control signal is a low level signal, and the selection module outputs the data corresponding to the low level signal as the second data.
[0048] It should be noted that the second control signal is a control signal corresponding to the target bit width, and the user can input the second control signal through the display or button. For example, if the second control signal is a high-level signal, it indicates that the target bit width is 10 bits, and if the second control signal is a low-level signal, it indicates that the target bit width is 8 bits.
[0049] As an alternative implementation, see Figure 3 The serial-to-parallel conversion circuit further includes: an adjustment module 180, the output end 163 of the trigger module is connected to the input end 181 of the adjustment module, and the output end 182 of the adjustment module is used to output in parallel each bit of the target data of the target bit width determined by the first order in the second data when the bit width of the second data is greater than the target bit width, wherein the first order is an order from low bit to high bit.
[0050] When the bit width of the second data is the same as the target bit width, the parallel data output by the trigger module will not be processed. If the bit width of the second data is greater than the target bit width, it means that the required bit width is smaller than the bit width of the data output by the trigger module, and part of the second data needs to be used as the target data. To this end, the second data needs to be screened to obtain the target data. The data output by the trigger module needs to be processed by the adjustment module to obtain each bit of the target data of the target bit width determined by the first sequence in the second data and output in parallel, so as to realize the output of parallel data of the target bit width.
[0051] As an optional embodiment, the adjustment module includes multiple N triggers, each data output end of the trigger module is connected to the data input end of the N triggers in sequence, and the target data can be filtered out by controlling the clock signal of the N triggers in the adjustment module.
[0052] As an implementation method, the bit width of the second data is i, the adjustment module includes i triggers, the target bit width is j, i and j are positive integers, and j is less than i, each data output end of the trigger module is connected to the data input end of the i trigger in sequence, after the clock signal control, the first j triggers in the adjustment module are triggered, and the j+1th trigger to the ith trigger are not triggered, so that the i-bit width parallel data output by the trigger module can be converted into j-bit width parallel data.
[0053] As an implementation method, filtering logic is written in a hardware description language so that each bit of the target data of the target bit width determined by the first sequence in the second data is valid and the other data is invalid, thereby also achieving parallel data of the target bit width.
[0054] As an exemplary embodiment, the second data includes D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, and D11, a total of 12 bits of data, and the target bit width is 10 bits. Then, 10 data are determined as target data in order from low to high, and the adjustment module determines the target data as D0, D1, D2, D3, D4, D5, D6, D7, D8, and D9, and then outputs the target data D0D1D2D3D4D5D6D7D8D9 in parallel.
[0055] As an exemplary embodiment, the second data includes D0, D1, D2, D3, D4, D5, D6, D7, D8, and D9, a total of 10 bits of data, and the target bit width is 8 bits. Then, 8 data are determined as target data in order from low to high, and the adjustment module determines the target data as D0, D1, D2, D3, D4, D5, D6, and D7, and then outputs the target data D0D1D2D3D4D5D6D7 in parallel.
[0056] As an optional implementation, the temporary storage module has M temporary storage output terminals arranged in sequence.
[0057] The selection module has N multiplexers arranged in sequence, the N temporary output terminals arranged in sequence starting from the first are respectively connected to the first input terminals of the N multiplexers arranged in sequence, the N temporary output terminals arranged in sequence starting from the (MN)th are respectively connected to the second input terminals of the N multiplexers arranged in sequence, and the signal control terminals of the N multiplexers arranged in sequence are connected to the output terminal of the AND gate.
[0058] The trigger module includes N first triggers, the output ends of N sequentially arranged multiplexers are respectively connected to the first input ends of the N first triggers, and the third output end of the clock division module is respectively connected to the second input ends of the N first triggers.
[0059] It should be noted that when the first control signal is a low-level signal, that is, the N multiplexers receive a low-level signal, the selection module transmits the data output by the first N temporary output terminals of the temporary storage module to the N first triggers respectively, that is, the data output by the first N temporary output terminals of the temporary storage module is used as the second data, and the clock signal output by the third output terminal of the clock division module controls the N first triggers to output the second data in parallel.
[0060] When the first control signal is a high-level signal, that is, the N multiplexers receive a high-level signal, the selection module transmits the data output from the N temporary storage output terminals of the temporary storage module, which are arranged in sequence starting from the (MN)th, to the N first triggers respectively, that is, the data output from the N temporary storage output terminals, which are arranged in sequence starting from the (MN)th, are used as the second data, and the clock signal output from the third output terminal of the clock division module controls the N first triggers to output the second data in parallel.
[0061] As an optional implementation, M is 12, N is 10, and the target bit width is 8 or 10.
[0062] It should be noted that the first trigger can be a D trigger, a T trigger, an RS trigger or a JK trigger, which is not specifically limited here.
[0063] As an optional implementation, the output end of the first deserialization module is 4 parallel output ends, the temporary storage module has 4 groups of sub-modules, the data input end of each group of sub-modules is respectively connected to the 4 parallel output ends, and each group of sub-modules has 3 temporary storage output ends.
[0064] It should be noted that the output terminals of the first deserialization module are four parallel output terminals, indicating that the first deserialization module outputs 4 bits of parallel data. This 4-bit parallel data can then be serial-to-parallel converted to obtain parallel data greater than 4 bits. To this end, the temporary storage module has four groups of submodules, each group of submodules is used to receive 1 bit of parallel data output by the first deserialization module. Each group of submodules has three temporary storage output terminals, meaning that the temporary storage module has a total of 12 temporary storage output terminals. The temporary storage module can store up to 12 bits of data, meaning that M is 12.
[0065] As an exemplary embodiment, the temporary storage module includes a trigger for storing the parallel data output by the first deserialization module.
[0066] As an optional implementation, each of the submodules includes three second flip-flops connected in series, the clock signal end of each second flip-flop is connected to the second output end, and the data output end of each second flip-flop is the temporary storage output end of the temporary storage module.
[0067] As an embodiment, each sub-module includes three second triggers connected in series, namely a first-level trigger, a second-level trigger and a third-level trigger. After a first parallel clock cycle, the first group of parallel data output by the first deserialization module is transmitted to the data output end of the first-level trigger. The parallel clock cycle is provided for the second output end of the clock division module. After a second parallel clock cycle, the first group of parallel data output by the first deserialization module is transmitted to the data output end of the second-level trigger. At the same time, the second group of parallel data output by the first deserialization module is transmitted to the data output end of the first-level trigger. After a third parallel clock cycle, the first group of parallel data output by the first deserialization module is transmitted to the data output end of the third-level trigger. At the same time, the second group of parallel data output by the first deserialization module is transmitted to the data output end of the second-level trigger, and the third group of parallel data output by the first deserialization module is transmitted to the data output end of the first-level trigger.
[0068] It can be seen that after three parallel clock cycles, the first group of parallel data, the second group of parallel data and the third group of parallel data of the first deserialization module are respectively transmitted to the three second triggers of each sub-module in turn, and the output end of each second trigger is the temporary storage output end of the temporary storage module. The temporary storage module can cache 12 bits of data, and the selection module is connected to the temporary storage output end of the temporary storage module. The temporary storage module can output parallel data to the selection module, and the maximum bit width of the parallel data is 12 bits.
[0069] It should be noted that the second trigger can be a D trigger, a T trigger, an RS trigger or a JK trigger, which is not specifically limited here.
[0070] As an optional embodiment, each of the sub-modules includes a third trigger and a fourth trigger connected in series, the clock signal end of the third trigger and the clock signal end of the fourth trigger are both connected to the third output end, the data input end and the data output end of the third trigger, and the data output end of the fourth trigger are all temporary storage output ends of the temporary storage module.
[0071] As an embodiment, the output end of the first deserialization module retains a first group of parallel data. After a first parallel clock cycle, the first group of parallel data output by the first deserialization module is transmitted to the data output end of the third trigger, and the data input end of the third trigger retains a second group of parallel data. The parallel clock cycle is provided for the second output end of the clock division module. After a second parallel clock cycle, the first group of parallel data output by the first deserialization module is transmitted to the data output end of the fourth trigger. At the same time, the second group of parallel data output by the first deserialization module is transmitted to the data output end of the third trigger, and the data input end of the third trigger retains a third group of parallel data.
[0072] Thus, after two parallel clock cycles, the first set of parallel data, the second set of parallel data, and the third set of parallel data of the first deserialization module are transmitted sequentially to the data input and data output of the third trigger, and the data output of the fourth trigger, respectively. The temporary storage module can then cache 12 bits of data. The input of the selection module is connected to the temporary storage output of the temporary storage module, and the temporary storage module can output parallel data to the selection module. The maximum bit width of the parallel data is 12 bits. By caching 12 bits of first data only through the third and fourth triggers, the number of triggers in the temporary storage module is reduced, thereby reducing the circuit footprint and manufacturing cost.
[0073] It should be noted that the third trigger and the fourth trigger can be a D trigger, a T trigger, an RS trigger or a JK trigger, which is not specifically limited here.
[0074] As an optional implementation manner, the control end of the clock frequency division module is connected to the second input end of the AND gate.
[0075] When the second control signal is at a low level, the third output terminal outputs a 4Q frequency-divided clock signal. When the second control signal is at a high level, the third output terminal outputs a 5Q frequency-divided clock signal.
[0076] As an optional embodiment, the clock division module includes a selector, the control end of the selector is the control end of the clock division module, and is used to receive a second control signal. When the second control signal is at a low level, the selector selects the low-order input, so that the third output end outputs a 4Q divided clock signal. When the second control signal is at a high level, the selector selects the high-order input, so that the third output end outputs a 5Q divided clock signal.
[0077] When the second control signal is low, the first control signal is also low, and the selection module outputs data from the N temporary storage output terminals in the temporary storage module, which are arranged in sequence starting from the first one. When the second control signal is high, and the fourth output terminal of the clock frequency division module is low, the selection module outputs data from the N temporary storage output terminals in the temporary storage module, which are arranged in sequence starting from the first one. When the second control signal is high, and the fourth output terminal of the clock frequency division module is high, the selection module outputs data from the N temporary storage output terminals in the temporary storage module, which are arranged in sequence starting from the first one (MN).
[0078] As an alternative embodiment, see Figure 3The initial clock signal CLK_IN is input to the clock frequency division module 110, which divides the input clock signal CLK_IN into CLK_DIV1 (divided by 1), CLK_DIV2 (divided by 2), CLK_DIV4 (divided by 4), CLK_DIV5 (divided by 5), and CLK_DIV10 (divided by 10). The frequency of the CLK_DIV1 clock signal is the same as the frequency of the clock signal CLK_IN, the frequency of the CLK_DIV2 clock signal is 1 / 2 times the frequency of the clock signal CLK_IN, the frequency of the CLK_DIV4 clock signal is 1 / 4 times the frequency of the clock signal CLK_IN, the frequency of the CLK_DIV5 clock signal is 1 / 5 times the frequency of the clock signal CLK_IN, and the frequency of the CLK_DIV10 clock signal is 1 / 10 times the frequency of the clock signal CLK_IN. The first output terminal of the clock divider module outputs the clock signal CLK_DIV1, the second output terminal of the clock divider module outputs the clock signal CLK_DIV2, the third output terminal of the clock divider module outputs the clock signal CLK_DIV4 / 5, and the fourth output terminal of the clock divider module outputs the clock signal CLK_DIV10.
[0079] The first deserialization module receives 2-bit serial input data DIN <0> and DIN <1> , and receives clock signals CLK_DIV1 and CLK_DIV2, wherein the clock signal CLK_DIV1 is used to control the transmission of 2-bit serial data, and the clock signal CLK_DIV2 is used to control the transmission of the output 4-bit parallel data, that is, in one CLK_DIV2 clock cycle, the first deserialization module outputs 4-bit parallel data to the second deserialization module.
[0080] The second deserialization module 130 includes a temporary storage module 140, a selection module 150, and a trigger module 160. Each submodule of the temporary storage module includes a third trigger FF3 and a fourth trigger FF4 connected in series. It should be noted that the first deserialization module outputs 4-bit parallel data through 4 triggers. For this reason, the output end of the first deserialization module stores the transmitted parallel data. For this reason, the data receiving end of each third trigger FF3 stores 1 bit of parallel data. After the first CLK_DIV2 clock cycle, the first group of parallel data output by the first deserialization module is transmitted to the data output end of the third trigger FF3 ( Figure 4 D4 <4> ,D4 <5> ,D4 <6> ,D4 <7> ), and the second set of parallel data output by the first deserialization module is transmitted to the data input terminal of the third flip-flop FF3 ( Figure 4 D4 <8> ,D4 <9> ,D4 <10> ,D4 <11> ), for this reason, after the second CLK_DIV2 clock cycle, the first set of parallel data output by the first deserialization module is transmitted to the data output terminal of the fourth flip-flop FF4 ( Figure 4 D4 <0> ,D4 <1> ,D4 <2> ,D4 <3> ), and the second set of parallel data output by the first deserialization module is transmitted to the data output terminal of the third flip-flop FF3 ( Figure 4 D4 <4> ,D4 <5> ,D4 <6> ,D4 <7> ), the third set of parallel data output by the first deserialization module is transmitted to the data input terminal of the third flip-flop FF3 ( Figure 4 D4 <8> ,D4 <9> ,D4 <10> ,D4 <11> ), that is, through two CLK_DIV2 clock cycles, the temporary storage module caches 12 bits of data.
[0081] It should be noted that the selection module 150 includes 10 multiplexers MUX<0:9> arranged in sequence, the first input ends of the 10 multiplexers are respectively connected to the 10 temporary output ends D4<0:9>, the second input ends of the 10 multiplexers are respectively connected to the 10 temporary output ends D4<2:11>, and the 10 multiplexer signal control ends are connected to the output end of the AND gate for receiving the first control signal SHIFT_EN. Each multiplexer is respectively connected to the corresponding temporary output end.
[0082] As an example, the first input terminal of the first multiplexer and the temporary output terminal D4 <0> Connect the second input of the first multiplexer to the temporary output D4 <2> Connect the first input of the second multiplexer to the temporary output D4 <1> Connect the second input of the second multiplexer to the temporary output D4 <3> Similarly, the first input terminal of the 10th multiplexer is connected to the temporary output terminal D4. <9> Connect the second input terminal of the 10th multiplexer to the temporary output terminal D4 <11> When the first control signal SHIFT_EN is a low-level signal, the data output by the ten multiplexers MUX<0:9> is the data output by the temporary output terminals D4<0:9>. When the first control signal SHIFT_EN is a high-level signal, the data output by the ten multiplexers MUX<0:9> is the data output by the temporary output terminals D4<2:11>.
[0083] It should be noted that the data output by the 10 multiplexers MUX<0:9> are respectively transmitted to the data input terminals of the 10 first flip-flops FF<0:9>. The clock signal receiving terminals of the 10 first flip-flops FF<0:9> receive the clock signal CLK_DIV4 / 5 output by the third output terminal of the clock frequency division module. When the rising edge or falling edge of the clock signal arrives, the first flip-flop outputs the data output by the 10 multiplexers MUX<0:9> in parallel, and the parallel data output by the second deserialization module is D_OUT<0:9>. Serial data can be converted into 10-bit parallel data, and then 20-bit, 40-bit, and 80-bit parallel data can be obtained based on the 10-bit parallel data. Compared with the exponentially increasing bit widths such as 8-bit, 16-bit, and 32-bit that can only be output, the serial-to-parallel conversion circuit of the present application increases the selectivity of the output bit width of the parallel data.
[0084] As an optional implementation, the fourth output terminal of the clock frequency dividing module outputs the CLK_DIV10 clock signal, and the second control signal EN is input to the clock frequency dividing module 110 to control the clock signal output by the third output terminal of the clock frequency dividing module. The timing diagram of data transmission is as follows: Figure 5 As shown, when the second control signal EN is a low level signal, the third output terminal outputs the CLK_DIV4 clock signal, and when the second control signal EN is a high level signal, the third output terminal outputs the CLK_DIV5 clock signal.
[0085] Specifically, when the second control signal EN is a low-level signal, the second input terminal of the AND gate receives the second control signal EN, and the first control signal SHIFT_EN outputted by the output terminal of the AND gate is also low-level. The outputs of the ten multiplexers MUX<0:9> are the data outputted by the temporary output terminals D4<0:9>. Consequently, the data outputted by the trigger module is also the data outputted by the temporary output terminals D4<0:9>.
[0086] Specifically, when the second control signal EN is a low level signal and the first control signal SHIFT_EN jumps to a low level signal, the data input terminal of the third flip-flop FF3 stores the first set of parallel data D0, D1, D2, and D3, that is, Figure 4 Temporary output D4 in <8> , Temporary output terminal D4 <9> , Temporary output terminal D4 <10> , Temporary output terminal D4 <11> The output data is D0, D1, D2, and D3 in sequence.
[0087] When the rising edge of the first clock cycle of CLK_DIV2 comes, the first set of parallel data D0D1D2D3 output by the first deserialization module is transmitted to the data output end of the third flip-flop FF3, that is, Figure 4Temporary output D4 in <4> , Temporary output terminal D4 <5> , Temporary output terminal D4 <6> , Temporary output terminal D4 <7> The data are D0, D1, D2, D3 in sequence, and the data input terminal of the third flip-flop FF3 stores the second set of parallel data D4D5D6D7, that is, Figure 4 Temporary output D4 in <8> , Temporary output terminal D4 <9> , Temporary output terminal D4 <10> , Temporary output terminal D4 <11> The output data is D4, D5, D6, and D7 in sequence.
[0088] When the rising edge of the second clock cycle of CLK_DIV2 comes, the first set of parallel data D0D1D2D3 output by the first deserialization module is transmitted to the data output end of the fourth flip-flop FF4, that is, Figure 4 Temporary output D4 in <0> , Temporary output terminal D4 <1> , Temporary output terminal D4 <2> , Temporary output terminal D4 <3> The data are D0, D1, D2, and D3 in sequence. The second set of parallel data D4D5D6D7 output by the first deserialization module is transmitted to the data output terminal of the third flip-flop FF3, that is, Figure 4 Temporary output D4 in <4> , Temporary output terminal D4 <5> , Temporary output terminal D4 <6> , Temporary output terminal D4 <7> The data are D4, D5, D6, and D7 in sequence, and the data input terminal of the third flip-flop FF3 stores the third set of parallel data D8D9D10D11, which is Figure 4 Temporary output D4 in <8> , Temporary output terminal D4 <9> , Temporary output terminal D4 <10> , Temporary output terminal D4 <11> The data are D8, D9, D10, and D11 respectively.
[0089] At this point, the 12 temporary outputs of the temporary storage module output the corresponding data D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, and D11, respectively. The data output by the 10 multiplexers MUX<0:9> is the data at the temporary output D4<0:9>. In other words, the data output by the 10 multiplexers MUX<0:9> is D0, ..., D7, D8, D9. At the rising edge of the CLK_DIV4 clock cycle, the parallel data output by the trigger module is D0 ..., D7, D8, D9. The first 8 bits of data are valid, resulting in D_OUT<0:9> being D0 ..., D700. Similarly, at the rising edge of the next CLK_DIV4 clock cycle, the parallel data output by the trigger module is D8 ..., D1500. This converts the serial data into 8-bit parallel data, ensuring correct data conversion.
[0090] As an optional implementation, the fourth output terminal of the clock frequency dividing module outputs the CLK_DIV10 clock signal, and the second control signal EN is input to the clock frequency dividing module 110 to control the clock signal output by the third output terminal of the clock frequency dividing module. The timing diagram of data transmission is as follows: Figure 6 As shown, since the third output terminal outputs the CLK_DIV5 clock signal, and since the second input terminal of the AND gate receives the second control signal EN, when the second control signal EN is a high-level signal, the third output terminal outputs the CLK_DIV5 clock signal, and the first control signal SHIFT_EN is the same as the CLK_DIV10 clock signal, that is, the first control signal SHIFT_EN is a periodically changing high and low level signal.
[0091] When the second control signal EN is high and the first control signal SHIFT_EN is low, the data output by the ten multiplexers MUX<0:9> is the data of the temporary output terminals D4<0:9>. Consequently, the data output by the trigger module is also the data output by the temporary output terminals D4<0:9>. When the second control signal EN is high and the first control signal SHIFT_EN is high, the data output by the ten multiplexers MUX<0:9> is the data of the temporary output terminals D4<2:11>. Consequently, the data output by the trigger module is also the data output by the temporary output terminals D4<2:11>.
[0092] Specifically, such as Figure 6 As shown, after the second control signal EN jumps to a high level signal and the first control signal SHIFT_EN is a high level signal, the data input terminal of the third flip-flop FF3 stores the first set of parallel data D0D1D2D3, that is, Figure 4 Temporary output D4 in <8> , Temporary output terminal D4 <9> , Temporary output terminal D4 <10> , Temporary output terminal D4 <11> The data are D0, D1, D2, and D3 in sequence.
[0093] When the rising edge of the first clock cycle of CLK_DIV2 comes, the first set of parallel data D0D1D2D3 output by the first deserialization module is transmitted to the data output end of the third flip-flop FF3, that is, Figure 4 Temporary output D4 in <4> , Temporary output terminal D4 <5> , Temporary output terminal D4 <6> , Temporary output terminal D4 <7> The data are D0, D1, D2, D3 in sequence, and the data input terminal of the third flip-flop FF3 stores the second set of parallel data D4D5D6D7, that is, Figure 4 Temporary output D4 in <8> , Temporary output terminal D4 <9> , Temporary output terminal D4 <10> , Temporary output terminal D4 <11> The data are D4, D5, D6, and D7 respectively.
[0094] When the rising edge of the second clock cycle of CLK_DIV2 comes, the first set of parallel data D0D1D2D3 output by the first deserialization module is transmitted to the data output end of the fourth flip-flop FF4, that is, Figure 4 Temporary output D4 in <0> , Temporary output terminal D4 <1> , Temporary output terminal D4 <2> , Temporary output terminal D4 <3> The data are D0, D1, D2, and D3 in sequence. The second set of parallel data D4D5D6D7 output by the first deserialization module is transmitted to the data output terminal of the third flip-flop FF3, that is, Figure 4 Temporary output D4 in <4> , Temporary output terminal D4 <5> , Temporary output terminal D4 <6> , Temporary output terminal D4 <7> The data are D4, D5, D6, and D7 in sequence, and the data input terminal of the third flip-flop FF3 stores the third set of parallel data D8D9D10D11, which is Figure 4 Temporary output D4 in <8> , Temporary output terminal D4 <9> , Temporary output terminal D4 <10> , Temporary output terminal D4 <11> The data are D8, D9, D10, and D11 respectively.
[0095] When the rising edge of the third clock cycle of CLK_DIV2 comes, the second set of parallel data D4D5D6D7 transmitted by the first deserialization module is transmitted to the data output end of the fourth flip-flop FF4, that is, Figure 4 Temporary output D4 in <0> , Temporary output terminal D4 <1> , Temporary output terminal D4 <2> , Temporary output terminal D4 <3> The data are D4, D5, D6, and D7 in sequence. The third set of parallel data D8D9D10D11 output by the first deserialization module is transmitted to the data output terminal of the third flip-flop FF3, that is, Figure 4 Temporary output D4 in <4> , Temporary output terminal D4 <5> , Temporary output terminal D4 <6> , Temporary output terminal D4 <7> The data of the third flip-flop FF3 are D8, D9, D10, and D11 respectively, and the data input terminal of the third flip-flop FF3 stores the third set of parallel data D12, D13, D14, and D15, that is, Figure 4 Temporary output D4 in <8> , Temporary output terminal D4 <9> , Temporary output terminal D4 <10> , Temporary output terminal D4 <11> The data are D12, D13, D14, and D15 respectively.
[0096] At this time, the 12 temporary output terminals of the temporary storage module correspond to the output data bits D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, and D15 respectively. At this time, the first control signal SHIFT_EN is a low-level signal. The data output by the 10 multiplexers MUX<0:9> is the data output by the temporary output terminal D4<0:9>, that is, the data output by the 10 multiplexers MUX<0:9> is D4, ... D12, D13. When the rising edge of the CLK_DIV5 clock cycle arrives, the parallel data D_OUT<0:9> output by the trigger module is D4D5...D11D12D13.
[0097] Similarly, when the rising edge of the next CLK_DIV5 clock cycle arrives, the first control signal SHIFT_EN is a high-level signal, and the data output by the 10 multiplexers MUX<0:9> is the data output by the temporary output terminal D4<2:11>, that is, the data output by the 10 multiplexers MUX<0:9> is D14, ..., D22, D23. When the rising edge of the CLK_DIV5 clock cycle arrives, the parallel data D_OUT<0:9> output by the trigger module is D14D15...D21D22D23, which can realize the conversion of serial data into 10-bit parallel data and ensure the correct conversion of data.
[0098] The present application can convert serial data into parallel data with a larger bit width through a second control signal, an AND gate, a selection module and a trigger module. Moreover, the serial-to-parallel conversion circuit based on the present application can choose to convert into parallel data with different bit widths. One circuit can realize the selection of multiple bit widths, saving the cost of the serial-to-parallel conversion circuit and improving the applicable scenarios of the serial-to-parallel conversion circuit.
[0099] As an optional embodiment, the present application also proposes a serial deserialization circuit, comprising: a continuous-time linear equalizer, a decision feedback equalizer, and the aforementioned serial-to-parallel conversion circuit; the output end of the continuous-time linear equalizer is connected to the input end of the decision feedback equalizer, and the output end of the decision feedback equalizer is connected to the data input end of the serial-to-parallel conversion circuit.
[0100] It should be noted that the continuous time linear equalizer (CTLE) is used to equalize the received analog signal to compensate for the frequency response characteristics of the channel and improve the signal quality by enhancing the high-frequency components of the signal and suppressing low-frequency noise.
[0101] The decision feedback equalizer (DEF) includes a slicer and a feedback circuit. The DFE is used to further equalize the signal processed by the CTLE to eliminate inter-symbol interference (ISI).
[0102] Specifically, under the control of a clock signal, the slicer samples the input signal to the DEF, generating a digital signal and transmitting it to the feedback circuit. Based on the previously determined digital signal, the feedback circuit estimates the interference (ISI) generated by the current digital signal in the channel. The feedback circuit generates a signal that is opposite to the estimated interference and adds it to the current digital signal, thereby canceling the ISI and improving signal quality. After multiple judgments and feedback, the DEF obtains a digital signal that meets the requirements and transmits it to the serial-to-parallel conversion circuit, which then outputs more accurate parallel data.
[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A serial-to-parallel conversion circuit, characterized in that: include: A first deserialization module, a second deserialization module, and a clock frequency division module; The first output end of the clock frequency division module is connected to the first input end of the first deserialization module, and the second output end of the clock frequency division module is connected to the second input end of the first deserialization module. The first output end is used to output a Q-divided clock signal, and the second output end is used to output a 2Q-divided clock signal, where Q is a positive integer. The first deserialization module is used to convert serial data with an R-bit width into parallel data with a 2R-bit width, where R is a positive integer. The second deserialization module includes a temporary storage module, a selection module, and a trigger module. The output end of the first deserialization module is connected to the first input end of the temporary storage module, and the second output end is connected to the second input end of the temporary storage module. The temporary storage module is used to cache the first data with a width of M bits, where M is greater than 2R and is an integer multiple of 2R; The output end of the temporary storage module is connected to the input end of the selection module, the control end of the selection module is used to receive a first control signal, the output end of the selection module is connected to the first input end of the trigger module, and the selection module is used to output second data according to the first control signal, where the second data is part of the first data; The third output terminal of the clock frequency dividing module is connected to the second input terminal of the trigger module, and the output terminal of the trigger module is used to output each bit of the second data in parallel.
2. The serial-to-parallel conversion circuit according to claim 1, wherein: Also includes: AND gate; The fourth output end of the clock division module is connected to the first input end of the AND gate, the second input end of the AND gate is used to receive a second control signal, and the output end of the AND gate is connected to the control end of the selection module, so as to output a first control signal to the selection module, wherein the clock signal output by the third output end corresponds to the second control signal.
3. The serial-to-parallel conversion circuit according to claim 2, wherein: The temporary storage module has M temporary storage output terminals arranged in sequence; The selection module comprises N sequentially arranged multiplexers, wherein the N temporary storage output terminals arranged sequentially starting from the first are respectively connected to the first input terminals of the N sequentially arranged multiplexers, and the N temporary storage output terminals arranged sequentially starting from the (MN)th are respectively connected to the second input terminals of the N sequentially arranged multiplexers, and the signal control terminals of the N sequentially arranged multiplexers are connected to the output terminal of the AND gate; The trigger module includes N first triggers, the output ends of N sequentially arranged multiplexers are respectively connected to the first input ends of the N first triggers, and the third output end of the clock division module is respectively connected to the second input ends of the N first triggers.
4. The serial-to-parallel conversion circuit according to claim 3, wherein: The output end of the first deserialization module is 4 parallel output ends. The temporary storage module has 4 groups of submodules. The data input end of each group of submodules is respectively connected to the 4 parallel output ends. Each group of submodules has 3 temporary storage output ends.
5. The serial-to-parallel conversion circuit according to claim 4, wherein: Each of the submodules includes three second flip-flops connected in series, a clock signal terminal of each second flip-flop is connected to the second output terminal, and a data output terminal of each second flip-flop is a temporary storage output terminal of the temporary storage module.
6. The serial-to-parallel conversion circuit according to claim 4, wherein: Each of the sub-modules includes a third trigger and a fourth trigger connected in series, the clock signal end of the third trigger and the clock signal end of the fourth trigger are both connected to the third output end, the data input end and the data output end of the third trigger, and the data output end of the fourth trigger are all temporary storage output ends of the temporary storage module.
7. The serial-to-parallel conversion circuit according to claim 6, wherein: The fourth output terminal outputs a 10Q frequency-divided clock signal. When the second control signal is at a low level, the third output terminal outputs a 4Q frequency-divided clock signal. When the second control signal is at a high level, the third output terminal outputs a 5Q frequency-divided clock signal.
8. The serial-to-parallel conversion circuit according to claim 1, wherein: Also includes: An adjustment module, wherein the output end of the trigger module is connected to the input end of the adjustment module, and the output end of the adjustment module is used to output in parallel each bit of the target data of the target bit width determined by the first order in the second data when the bit width of the second data is greater than the target bit width, wherein the first order is the order from low bit to high bit.
9. The serial-to-parallel conversion circuit according to claim 8, wherein: M is 12, N is 10, and the target bit width is 8 or 10.
10. A serial deserialization circuit, characterized in that: include: A continuous-time linear equalizer, a decision feedback equalizer, and a serial-to-parallel conversion circuit as described in claims 1-9; The output end of the continuous time linear equalizer is connected to the input end of the decision feedback equalizer, and the output end of the decision feedback equalizer is connected to the data input end of the serial-to-parallel conversion circuit.