Embedded gateway system
By introducing data prefetch circuits into network processors, the problem of traditional network processors waiting time in dynamic random access memory is solved, and more efficient data processing efficiency is achieved.
Patent Information
- Application Number
- CN202410175720.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-07
- Publication Date
- 2025-08-08
AI Technical Summary
When traditional network processors use dynamic random access memory for data access, they lead to waste of processor resources and long waiting time.
Data prefetch circuit is used to read data from slow memory in advance and write to high-speed memory for subsequent use by the processor to reduce waiting time.
By using data prefetch circuit, the processor's pause time waiting for data is significantly reduced and data processing efficiency is improved.
Smart Images
Figure CN120455205A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to data processing in an embedded gateway system, and in particular to an embedded gateway system which improves the data access efficiency of a processor by assisting a data prefetch circuit. Background Art
[0002] A network processing unit (NPU) is a high-speed programmable processor specifically designed for network packet processing (e.g., network packet forwarding). It possesses features and architecture specifically designed to accelerate the processing efficiency of network packets. For example, a network processor can be implemented using a RISC-V processor. Traditional network devices typically use external memory to store data to be processed by the RISC-V processor, such as using dynamic random access memory (DRAM) to store packet data. Therefore, the RISC-V processor needs to perform data access operations on the DRAM. However, a single data access operation to the DRAM takes a long time, and during this time, the RISC-V processor stalls while waiting for the DRAM access operation to complete, wasting processor resources. Summary of the Invention
[0003] One of the objectives of the present invention is to provide an embedded gateway system that improves the data access efficiency of a processor with the assistance of a data prefetch circuit.
[0004] In one embodiment of the present invention, an embedded gateway system is disclosed. The embedded gateway system includes a processor, a first memory, a second memory, and a data prefetch circuit. The processor is used to execute a first program. The first memory is used to store a first data. The first and second memories are external memories of the processor, and the access delay of the second memory is lower than the access delay of the first memory. The data prefetch circuit is used to perform a first data prefetch operation on the first memory, read a first prefetch data from the first memory and write the first prefetch data to the second memory, wherein before the processor executes a data access program code segment of the first program and needs to access the first data, the first data prefetch operation reads the first data from the first memory as the first prefetch data, and puts the first prefetch data into the second memory. When the processor processes the program code and needs the first data, it reads from the second memory, which can achieve more efficient reading efficiency.
[0005] In another embodiment of the present invention, an embedded gateway system is disclosed. The embedded gateway system includes a RISC-V processor, a first memory, a second memory, and a data prefetch circuit. The RISC-V processor is used to execute a first program. The first memory is used to store a first data. The access delay of the second memory is lower than the access delay of the first memory. The data prefetch circuit is used to perform a first data prefetch operation on the first memory, read a first prefetch data from the first memory and write the first prefetch data to the second memory, wherein before the RISC-V processor executes the data access program code segment of the first program and needs to access the first data, the first data prefetch operation reads the first data from the first memory as the first prefetch data, and puts the first prefetch data into the second memory. When the RISC-V processor processes the program code and needs the first data, it reads from the second memory, which can achieve more efficient reading efficiency.
[0006] Compared to the processor's access operation to slow memory (such as dynamic random access memory), which takes a lot of time, the processor can quickly access the required data through fast memory (such as static random access memory), thereby significantly reducing the processor's pause time waiting for data, thereby effectively improving the processor's data processing performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 FIG. 1 is a schematic diagram of an embedded gateway system with a data pre-fetching mechanism according to an embodiment of the present invention.
[0008] Figure 2 for Figure 1 The flowchart of data processing of the embedded gateway system with data pre-fetching mechanism is shown.
[0009] Figure 3 FIG. 4 is a schematic diagram of another embedded gateway system with a data pre-fetching mechanism according to an embodiment of the present invention.
[0010] Figure 4 for Figure 3 The flowchart of data processing of the embedded gateway system with data pre-fetching mechanism is shown.
[0011]
Explanation of symbols
[0012] 100, 300: Embedded Gateway System
[0013] 102, 302: Processor
[0014] 104, 106: Memory
[0015] 108: Data prefetch circuit
[0016] 110: Register array
[0017] 112, REG: Register
[0018] PROG_1, PROG_2, PROG_1', PROG_2': program
[0019] C1_1, C1_2, C2_1, C3_1, C4_1, C5_1, C1_2, C2_2, C3_2, C4_2, C3_1': program code segment
[0020] TP_1, TP_2: time points
[0021] IP_1, IP_2: Insertion point
[0022] D_1, D_i, D_j, D_n: data
[0023] PF_1, PF_2: data prefetch operation
[0024] S202, S204, S206, S208, S402, S404, S406, S408, S410: Steps DETAILED DESCRIPTION
[0025] Certain words are used in the specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different terms to refer to the same component. This specification and claims do not use differences in name as a way to distinguish components, but rather use differences in the functions of the components as the criterion for distinction. The terms "including" and "comprising" mentioned throughout the specification and claims are open-ended terms and should be interpreted as "including but not limited to". In addition, the term "coupled" or "coupled" includes any direct and indirect electrical connection means. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices and connection means.
[0026] See also Figure 1 , Figure 1Schematic diagram of an embedded gateway system with a data prefetching mechanism according to an embodiment of the present invention. The embedded gateway system 100 includes a processor 102, a plurality of memories 104, 106, and a data prefetching circuit 108. For example, the embedded gateway system 100 is a network device, and the processor 102 can be used as a network processor to process network data packets received by a network card or a network chip of the network device to assist in data packet forwarding. For example, the processor 102 can be implemented using a RISC-V processor. However, this is only for illustrative purposes and not as a limitation of the present invention. In fact, any processor using Figure 1 The embedded gateway systems of the shown architecture all fall within the scope of the present invention. Figure 1 Only components related to the present invention are shown. In practice, the embedded gateway system 100 may also include other components to implement specified functions.
[0027] Memories 104 and 106 are external memories of processor 102 (for example, memories 104 and 106 are not integrated into the same die as processor 102), and the access latency of memory 106 is lower than the access latency of memory 104. In other words, memory 106 is a high-speed memory, while memory 104 is a low-speed memory. For example, memory 104 can be a dynamic random access memory, and memory 106 can be a static random access memory (SRAM). The data prefetch circuit 108 is a hardware circuit with data prefetch capability, and is used to perform a data prefetch operation on the memory 104, read prefetched data from the memory 104, and write the prefetched data to the memory 106. As shown in the figure, the memory 104 can be used to store multiple data D_1, ..., D_i, D_j, ..., D_n. The data prefetch circuit 108 can read data D_1 as prefetched data for one data prefetch operation and write data D_1 to the memory 106 for subsequent use by the processor 102. The data prefetch circuit 108 can also read data D_i as prefetched data for another data prefetch operation and write data D_i to the memory 106 for subsequent use by the processor 102. Compared to the time-consuming nature of each access operation by processor 102 to a slow memory (e.g., memory 104), processor 102 can quickly access required data through a fast memory (e.g., memory 106). This significantly reduces the pause time of processor 102 waiting for data, thereby effectively improving the data processing performance of processor 102. In short, the present invention can at least solve the problem of data waiting pause time encountered in applications where the memory is external to the processor, thereby reducing the pause time.
[0028] In this embodiment, the processor 102 executes the program PROG_1 to perform data processing (eg, data packet processing), and further executes the program PROG_2 to determine when to instruct the data prefetch circuit 108 to start a data prefetch operation, such as Figure 1 As shown, program PROG_1 includes multiple code segments, such as C1_1, C2_1, C3_1, C4_1, C5_1, C1_2, C2_2, C3_2, and C4_2. Code segments C1_1 and C1_2 are data prefetch code segments inserted by program PROG_2. Code segments C3_1 and C3_2 are data access code segments. Code segments C2_1, C5_1, and C2_2 handle data processing operations other than data prefetch and data access. In addition, code segments C4_1 and C4_2 are code segments that wait for data access to complete. Before the processor 102 executes the data access code segment C3_1 of the program PROG_1 and needs to access the data D_1 at time TP_1, the data prefetch code segment C1_1 preceding the data access code segment C3_1 is first executed to instruct the data prefetch circuit 108 to initiate a data prefetch operation PF_1, thereby reading the data D_1 from the memory 104 as prefetch data for the data prefetch operation PF_1 and writing the data D_1 to the memory 106. Similarly, before the processor 102 executes the data access code segment C3_2 of the program PROG_1 and needs to access the data D_i at time TP_2, the data prefetch code segment C1_2 preceding the data access code segment C3_2 is first executed to instruct the data prefetch circuit 108 to initiate a data prefetch operation PF_2, thereby reading the data D_i from the memory 104 as prefetch data for the data prefetch operation PF_2 and writing the data D_i to the memory 106.
[0029] When the processor 102 executes the data access code segment C3_1 of the program PROG_1 and needs to access data D_1, if data D_1 has been prefetched and is already present in the memory 106, the processor 102 can quickly access the required data D_1 through the memory 106. Since the memory 106 is a fast memory (e.g., static random access memory), the pause time when the processor 102 executes the code segment C4_1 and waits for the data access to complete is significantly reduced. Similarly, when the processor 102 executes the data access code segment C3_2 of the program PROG_1 and needs to access data D_i, if data D_i has been prefetched and is already present in the memory 106, the processor 102 can quickly access the required data D_i through the memory 106. Since the memory 106 is a fast memory (e.g., static random access memory), the pause time when the processor 102 executes the code segment C4_2 and waits for the data access to complete is significantly reduced.
[0030] Since the data prefetch circuit 108 is a hardware circuit, it has a register array 110 that serves as a communication interface between the hardware and software. The register array 110 may include a plurality of registers (labeled "REG") 112 for storing a plurality of parameters for the data prefetch operation. For example, the parameter Reg_Slow_Addr indicates the starting memory address of the data to be prefetched (e.g., D_1 or D_i) in the memory 104, the parameter Reg_Start indicates whether the data prefetch operation is to be started, and the parameter Reg_Status indicates the execution status of the data prefetch operation (e.g., whether the data prefetch operation is completed).
[0031] Please also refer to Figure 1 and Figure 2 , Figure 2 for Figure 1 The flowchart of data processing of the embedded gateway system 100 with data pre-fetching mechanism is shown. If the same results can be obtained, the steps do not have to be completely followed. Figure 2 In step S202, the processor 102 executes a data prefetch program code segment (e.g., C1_1 or C1_2) in the program PROG_1 to instruct the data prefetch circuit 108 to initiate a data prefetch operation (e.g., PF_1 or PF_2) to prefetch data (e.g., D_1 or D_i) required for a subsequent data access program code segment (e.g., C3_1 or C3_2).
[0032] In step S204, the processor 102 executes the subsequent code segment (e.g., C2_1 or C2_2) of the data prefetch code segment (e.g., C1_1 or C1_2) to perform other processing. In step S206, the processor 102 executes the data access code segment (e.g., C3_1 or C3_2) to check whether the required data (e.g., D_1 or D_i) has been prefetched and is present in the memory 106. If the required data (e.g., D_1 or D_i) has been prefetched and is present in the memory 106, the processor 102 executes the data access code segment (e.g., C3_1 or C3_2) to quickly access the required data (e.g., D_1 or D_i) through the memory 106, without having to slowly access the required data through the memory 104 (step S208).
[0033] As previously described, program PROG_2 inserts data prefetch code segments C1_1 and C1_2 into program PROG_1. In this embodiment, program PROG_2 determines the insertion points IP_1 and IP_2 of the data prefetch code segments C1_1 and C1_2 in program PROG_1, respectively, based on certain time delay parameters. By appropriately setting the insertion points IP_1 and IP_2, the data prefetch operation can be performed to write the required data (e.g., D_1 or D_i) to the memory 106 exactly at the time point (e.g., TP_1 or TP_2) (or, the data prefetch operation can be performed before the time point (e.g., TP_1 or TP_2)). In this way, the processor 102 can achieve optimal data processing performance through the data prefetch mechanism.
[0034] For example, appropriate settings for insertion points IP_1 and IP_2 can be found by referring to multiple time delay parameters t_prefetch and t_code. Processor 102 is further configured to execute program PROG_2 to measure the execution time required for each data prefetch operation to obtain the time delay parameter t_prefetch. In other words, through multiple measurements, an average execution time t_prefetch_avg (e.g., the average of 1000 measurement results), a maximum execution time t_prefetch_max (e.g., the maximum of the 1000 measurement results), and a minimum execution time t_prefetch_min (e.g., the minimum of the 1000 measurement results) of the data prefetch operation can be obtained. In this embodiment, the time delay parameter t_prefetch can use the average execution time t_prefetch_avg, but the present invention is not limited thereto. Please note that due to the characteristics of the storage device itself, the time delay parameter t_prefetch will not be a fixed value.
[0035] Furthermore, the processor 102 is configured to execute the program PROG_2 to measure the execution time required by the processor 102 to execute different numbers of program code lines in the program PROG_1 to obtain a plurality of time delay parameters. For example, the time delay parameter t_code_100 represents the execution time required to execute 100 lines of program code, the time delay parameter t_code_120 represents the execution time required to execute 120 lines of program code, the time delay parameter t_code_150 represents the execution time required to execute 150 lines of program code, and so on. For a single fixed function, the program code segment is almost constant, and therefore, the execution time required for the program code is also substantially constant.
[0036] To determine the insertion point of the data prefetch code segment in program PROG_1, it is necessary to find a value of the time delay parameter t_code (e.g., one of t_code_100, t_code_120, and t_code_150) that satisfies the following condition: t_code > t_prefetch. The found time delay parameter t_code determines the number of program code lines that should elapse between the insertion point of the data prefetch code segment (e.g., IP_1 or IP_2) and the time point of the subsequent data access code segment (e.g., TP_1 or TP_2). In other words, the location of the insertion point in program PROG_1 can be determined based on the number of program code lines corresponding to the found time delay parameter t_code.
[0037] Assuming each data prefetch operation accesses 16 bytes of data, the measurement statistics for 1000 data prefetch operations are shown in the table below. Note that the amount of data prefetched per data prefetch operation can be determined based on actual design requirements. For example, each data prefetch operation can access 64 bytes of data or 32 bytes of data.
[0038] Table 1
[0039] project Avg Max Min t_prefetch(ns) 160 483.75 143.75
[0040] In addition, the measurement statistics of the execution time required for different numbers of program code lines can be shown in the following table.
[0041] Table 2
[0042] Number of lines 100 120 150 t_code(ns) 125 156.25 202.5
[0043] If the time delay parameter t_prefetch is measured using the average execution time t_prefetch_avg, the lead (i.e., t_code - t_prefetch_avg) will have different values for the required execution time of different program code lines (e.g., t_code_100, t_code_120, and t_code_150), as shown in the following table.
[0044] Table 3
[0045] Number of lines 100 120 150 t_code(ns) 125 156.25 202.5 t_prefetch(ns) 160 160 160 Advance -35 -3.75 42.5 Set insertion point? no no yes
[0046] Basically, as long as the lead is not a negative value, the insertion point can be set based on the number of program code lines corresponding to the corresponding time delay parameter t_code. In this example, the insertion point of the data prefetch code segment (e.g., IP_1 or IP_2) can be set 150 lines before the data read code segment at the time point (e.g., TP_1 or TP_2). Please note that the above is merely an example and not a limitation of the present invention. If the execution time required by processor 102 to execute other program code lines (e.g., lines 130 and 140) in program PROG_1 is additionally measured, a time delay parameter t_code that is greater than and closest to the time delay parameter t_prefetch can be found, thereby obtaining the optimal location of the data prefetch code segment insertion point (e.g., IP_1 or IP_2).
[0047] For the same execution path, the processor may need to access multiple related data when processing data. However, when the storage address intervals of the multiple related data in the slow memory are large and cannot be completed through a single data prefetch operation, multiple data prefetch operations can be initiated through multi-channel parallel processing to read the multiple related data.
[0048] See also Figure 3 , Figure 3Schematic diagram of another embedded gateway system with a data prefetch mechanism according to an embodiment of the present invention. The main difference between the embedded gateway systems 100 and 300 is that the processor (e.g., a network processor implemented as a RISC-V processor) 302 executes program PROG_1' to perform data processing (e.g., packet data processing), and the data access program code segment C3_1' in program PROG_1' needs to access data D_1 and data D_i. In addition, the processor 302 executes program PROG_2' to determine to insert the data prefetch program code segment C1_1 and the data prefetch program code segment C1_2 into program PROG_1' in sequence. In this way, when the processor 302 executes the data access program code segment C3_1' and needs to access data Before the time point TP_1 of D_1 and D_i, the processor 302 executes the data prefetch program code segment C1_1 to instruct the data prefetch circuit 108 to perform a data prefetch operation PF_1 to read data D_1 from the memory 104 as prefetch data and write the data D_1 to the memory 106. In addition, the processor 302 executes the data prefetch program code segment C1_2 to instruct the data prefetch circuit 108 to perform a data prefetch operation PF_2 to read data D_i from the memory 104 as prefetch data and write the data D_i to the memory 106. The execution time of the data prefetch operation PF_1 partially overlaps with the execution time of the data prefetch operation PF_2.
[0049] Please also refer to Figure 3 and Figure 4 , Figure 4 for Figure 3 The flowchart of data processing of the embedded gateway system 300 with data pre-fetching mechanism is shown. If the same results can be obtained, the steps do not have to be completely followed. Figure 4In step S402, the processor 302 executes the data prefetch code segment C1_1 in the program PROG_1' to instruct the data prefetch circuit 108 to initiate a data prefetch operation PF_1 to pre-fetch the first data D_1 required for the subsequent data access code segment C3_1'. In step S404, the processor 302 executes the data prefetch code segment C1_2 in the program PROG_1' to instruct the data prefetch circuit 108 to initiate a data prefetch operation PF_2 to pre-fetch the second data D_i required for the subsequent data access code segment C3_1'. The execution time of the data prefetch operation PF_1 partially overlaps with the execution time of the data prefetch operation PF_2. In step S406, the processor 102 executes the subsequent code segment C2_1 of the data prefetch code segments C1_1 and C1_2 to perform other processing. In step S408, the processor 102 executes the data access code segment C3_1′ to check whether the two required data D_1 and D_i have been pre-fetched and are present in the memory 106. If the required data D_1 and D_i have been pre-fetched and are present in the memory 106, the processor 102 executes the data access code segment C3_1′ to quickly access the required data D_1 and D_i through the memory 106, without having to access the required data more slowly through the memory 104 (step S410).
[0050] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. An embedded gateway system, comprising: a processor for executing a first program; A first memory, configured to store first data; a second memory, wherein the first and second memories are external memories of the processor, and an access delay of the second memory is lower than an access delay of the first memory; and The data prefetch circuit is configured to perform a first data prefetch operation on the first memory, reading first prefetched data from the first memory and writing the first prefetched data to the second memory, wherein the first data prefetch operation reads the first data from the first memory as the first prefetched data before the processor executes the data access program code section of the first program and needs to access the first data. 2 . The embedded gateway system as claimed in claim 1 , wherein the first data pre-fetching operation completes the operation of writing the first data into the second memory at or before the time point. 3 . The embedded gateway system as claimed in claim 1 , wherein the first memory is a dynamic random access memory, and the second memory is a static random access memory. The embedded gateway system as claimed in claim 1 , wherein the processor serves as a network processor.
5. The embedded gateway system as claimed in claim 1, wherein the processor is a RISC-V processor.
6. The embedded gateway system as claimed in claim 1 , wherein the processor is further configured to execute a second program to insert a data prefetch program code segment into the first program; the processor executes the data prefetch program code segment before the data access program code segment to instruct the data prefetch circuit to initiate the first data prefetch operation.
7. The embedded gateway system as claimed in claim 6, wherein the processor is further configured to execute the second program to measure the execution time required for the first data prefetch operation to obtain a first time delay parameter, and determine an insertion point of the data prefetch program code segment into the first program based at least on the first time delay parameter.
8. The embedded gateway system as claimed in claim 7, wherein the processor is further configured to execute the second program to measure the execution time required by the processor to execute different numbers of program code lines in the first program to obtain a plurality of second time delay parameters, and determine the insertion point of the data prefetch program code segment into the first program based on at least one second time delay parameter among the plurality of second time delay parameters that is greater than the first time delay parameter.
9. The embedded gateway system as claimed in claim 6, wherein the processor is further configured to execute the second program to measure the execution time required for the processor to execute different numbers of program code lines in the first program to obtain a plurality of time delay parameters respectively, and determine the insertion point of the data prefetch program code segment into the first program at least based on the plurality of time delay parameters.
10. The embedded gateway system as claimed in claim 1 , wherein the first memory is further configured to store second data; the data prefetch circuit is further configured to perform a second data prefetch operation on the first memory, reading the second prefetched data from the first memory and writing the second prefetched data to the second memory; before the processor executes the data access program code segment and needs to access the second data, the second data prefetch operation reads the second data from the first memory as the second prefetched data; and execution time of the first data prefetch operation and execution time of the second data prefetch operation partially overlap.
11. An embedded gateway system comprising: A RISC-V processor, configured to execute a first program; A first memory, configured to store first data; a second memory, wherein an access delay of the second memory is lower than an access delay of the first memory; as well as A data prefetch circuit is used to perform a first data prefetch operation on the first memory, read first prefetched data from the first memory and write the first prefetched data to the second memory, wherein before the RISC-V processor executes the data access program code segment of the first program and needs to access the first data, the first data prefetch operation reads the first data from the first memory as the first prefetched data. 12 . The embedded gateway system as claimed in claim 11 , wherein the first data pre-fetching operation completes the operation of writing the first data into the second memory at or before the time point. 13 . The embedded gateway system as claimed in claim 11 , wherein the first memory is a dynamic random access memory, and the second memory is a static random access memory.
14. The embedded gateway system as claimed in claim 11, wherein the RISC processor serves as a network processor.
15. The embedded gateway system as claimed in claim 11, wherein the RISC-V processor is further configured to execute a second program to insert a data prefetch program code segment into the first program; the RISC-V processor executes the data prefetch program code segment before the data access program code segment to instruct the data prefetch circuit to initiate the first data prefetch operation.
16. The embedded gateway system as claimed in claim 15, wherein the RISC-V processor is further configured to execute the second program to measure the execution time required for the first data prefetch operation to obtain a first time delay parameter, and determine an insertion point of the data prefetch program code segment into the first program based at least on the first time delay parameter.
17. The embedded gateway system as claimed in claim 16, wherein the RISC-V processor is further configured to execute the second program to measure the execution time required for the RISC-V processor to execute different numbers of program code lines in the first program to obtain a plurality of second time delay parameters, and determine an insertion point of the data prefetch program code segment into the first program based on at least one second time delay parameter among the plurality of second time delay parameters that is greater than the first time delay parameter.
18. The embedded gateway system as claimed in claim 15, wherein the RISC-V processor is further configured to execute the second program to measure the execution time required by the RISC-V processor to execute different numbers of program code lines in the first program to obtain a plurality of time delay parameters respectively, and determine the insertion point of the data prefetch program code segment into the first program at least based on the plurality of time delay parameters.
19. The embedded gateway system as claimed in claim 11, wherein the first memory is further used to store second data; the data prefetch circuit is further used to perform a second data prefetch operation on the first memory, reading the second prefetched data from the first memory and writing the second prefetched data to the second memory; before the RISC-V processor executes the data access program code segment and needs to access the second data, the second data prefetch operation reads the second data from the first memory as the second prefetched data; and the execution time of the first data prefetch operation and the execution time of the second data prefetch operation partially overlap.