Memory device with high electrical conductivity

Abstract

The invention discloses a memory device with high electrical conductivity, and aims to solve the problem of limited reasoning precision caused by insufficient electrical conductivity of a multi-valued memory device in a current CIM (common information model) system. The memory comprises a substrate, a source electrode, two lightly doped drain electrodes, two bit lines, two floating gates, a control gate, two selection gates, an erase gate, a first intermediate dielectric layer, a second intermediate dielectric layer, a top dielectric layer and an isolation layer. The source electrode is configured in the middle of the substrate, and the two lightly doped drain electrodes are configured on the two sides of the substrate respectively; the control gate is arranged right above the source electrode, and the two floating gates are arranged on the two sides of the control gate respectively to half wrap the control gate; the two selection gates are arranged on the outer sides of the two floating gates respectively. According to the invention, the problem of nonlinearity of conductivity in multi-valued storage is solved, and while the compatibility with the traditional NOR Flash process is maintained, the linearity, stability and precision of the conductivity are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of high-end memory, and in particular to a memory device with high electrical conductivity. Background Art

[0002] In the field of memory technology, compute-integrated memory (CIM) technology is considered a key solution to breaking through the "memory wall" and "power wall" bottlenecks of the traditional von Neumann architecture. It is particularly valuable in high-performance computing scenarios such as artificial intelligence and big data processing. Among current high-end memory technologies, new non-volatile memories such as magnetoresistive RAM (MRAM), resistive random access RAM (RRAM), and phase-change memory (PCM) have attracted considerable attention due to their high speed and low power consumption. However, these technologies still face significant challenges in multi-value storage applications: the resistance switching linearity of magnetoresistive RAM is limited by the difficulty of controlling the anisotropy of the magnetic material; the random formation of conductive filaments in RRAM leads to a discrete conductivity distribution; and the crystalline-amorphous transition process in PCM is susceptible to thermal perturbations and lacks stability. These issues make it difficult to achieve high-precision conductivity control in multi-value storage scenarios for high-end memories, severely restricting their practical application in CIM systems.

[0003] Although traditional floating gate Flash memory devices have advantages such as non-volatility and high integration, their defects of insufficient electrical conductivity have become increasingly prominent under the demand for high-density multi-value storage. Specifically, the single regulation of the floating gate length and channel parameters leads to uneven electric field distribution, the charge injection process exhibits nonlinear characteristics, and the distinction between storage states is reduced. For example, in neural network reasoning tasks, insufficient electrical conductivity will cause the accumulation of weight quantization errors, which will limit the reasoning accuracy (such as less than 90%). In contrast, the lack of parameter collaborative optimization capabilities of existing Flash devices makes it difficult to improve charge injection uniformity by comprehensively adjusting key parameters such as floating gate structure and doping distribution. In addition, although high-end memories such as RRAM and PCM have advantages in speed or durability, their intrinsic nonlinear characteristics also limit the improvement of multi-value storage accuracy, and long-term cyclic operation is prone to exacerbated performance degradation due to material degradation.

[0004] Therefore, there is an urgent need for a new memory architecture that can break through the existing technological bottlenecks. It is compatible with the process advantages of traditional Flash devices, and can significantly improve electrical conductivity through innovative structural design and coordinated parameter control, providing CIM systems with high-precision, high-reliability multi-value storage solutions. Summary of the Invention

[0005] The purpose of the present invention is to address the shortcomings of the existing technology by providing a memory device with high electrical conductivity. This is intended to solve the problem of insufficient electrical conductivity of multi-value memory devices in current CIM systems, which leads to limited inference accuracy. The present invention innovatively and collaboratively regulates the key parameter of a new NOR flash device, the floating gate length, to achieve precise control of the device channel length, electric field distribution, and charge injection process. This device optimization effectively improves the electrical conductivity of multi-value storage. When executing CIM simulation tasks, inference accuracy is significantly improved, reaching greater than 92%.

[0006] A memory device with high electrical conductivity comprises a substrate, a source SRC, two lightly doped drains LDD, two bit lines BL, two floating gates FG, a control gate CG, two select gates SG, an erase gate EP, a first interlayer dielectric layer, a second interlayer dielectric layer, a top dielectric layer, and an isolation layer; the source SRC is disposed in the middle of the substrate, the two lightly doped drains LDD are disposed on either side of the substrate, and the two bit lines BL are disposed outside the two lightly doped drains LDD; the two floating gates FG, the control gate CG, and the two select gates SG are disposed above the substrate;

[0007] The control gate CG is arranged directly above the source SRC, and two floating gates FG are respectively arranged on both sides of the control gate CG; two select gates SG are respectively arranged on the outsides of the two floating gates FG;

[0008] A first intermediate dielectric layer is provided between the floating gate FG and the control gate CG, and the first intermediate dielectric layer wraps the bottom and sidewalls of the control gate CG; a second intermediate dielectric layer is provided between the select gate SG and the floating gate FG;

[0009] A bottom dielectric layer is provided between the substrate and the floating gate FG, the control gate CG, and the select gate SG, and a top dielectric layer is provided between the erase gate EP and the floating gate FG, the control gate CG, and the select gate SG;

[0010] Preferably, an isolation layer is further provided above the select gate SG, and the isolation layer is located below the top dielectric layer;

[0011] Preferably, the two floating gates FG half-wrap the control gate CG;

[0012] Preferably, the head of the floating gate FG has a sharp corner, and the sharp corner is covered by the top dielectric layer and the erase gate;

[0013] Preferably, the two floating gates FG are of an axisymmetric structure, both of which are L-shaped structures, comprising a first longitudinal arm and a first transverse arm perpendicular to each other, the head of the first longitudinal arm having a sharp corner, the bottom of which is connected to one end of the first transverse arm, and the other end of the first transverse arm pointing to the control gate CG; the control gate CG is of a T-shaped structure, comprising a second longitudinal arm and a second transverse arm perpendicular to each other, the head of the second longitudinal arm being connected to the midpoint of the second transverse arm; the second transverse arm of the control gate CG is located above the first transverse arms of the two floating gates FG, and the second longitudinal arm of the control gate CG is located between the first transverse arms of the two floating gates FG;

[0014] Preferably, the height of the floating gate FG is greater than that of the control gate CG and the select gate SG.

[0015] Preferably, the floating gate FG, the control gate CG, and the select gate SG satisfy the following requirements:

[0016]

[0017] Among them, w SG represents the width of the select gate SG, represents the length of the first lateral arm of the floating gate FG, represents the first longitudinal arm width of the control gate CG.

[0018] The beneficial effects of the present invention include at least:

[0019] The present invention adopts a coordinated layout of the floating gate FG and the control gate CG, in which the lateral arm of the floating gate points to the longitudinal arm of the control gate, forming a symmetrical electric field channel. This design disperses the charge injection path through geometric matching, avoiding local electric field concentration, significantly improving the uniformity of the electric field distribution, and reducing the nonlinear error of charge injection. The semi-wrapped design of the floating gate to the control gate expands the coupling area between the gates, making the control gate's regulation of the floating gate charge more linear, improving the discreteness of the conductivity difference between storage states, and significantly improving the discrimination of multi-value storage. By controlling the width of the control gate longitudinal arm and the length of the floating gate lateral arm, the edge electric field distortion can be suppressed, and the linear response range of the charge injection amount with the control voltage can be expanded.

[0020] The present invention completely covers the tip of the floating gate with the top dielectric layer and the erase gate, thereby avoiding charge leakage caused by electric field concentration at the tip, reducing the electrical conductivity attenuation rate, and ensuring the long-term stability of multi-value storage.

[0021] This invention solves the problem of electrical conductivity nonlinearity in multi-value storage. While maintaining compatibility with traditional NOR Flash processes, it achieves significant improvements in electrical conductivity, stability, and accuracy, providing a reliable hardware foundation for high-precision reasoning in CIM systems in scenarios such as artificial intelligence and edge computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of the new floating gate memory structure;

[0023] Figure 2 This is a diagram showing how high-linearity devices improve inference accuracy when running the CIFAR-10 task on the CIM simulation platform dnn+neurosim v2.0 equipped with VGG-8.

[0024] Markings in the figure: 1. substrate; 2. source; 3. lightly doped drain; 4. bit line; 5. control gate; 5-1. second longitudinal arm; 5-2. second lateral arm; 6. floating gate; 6-1. first longitudinal arm; 6-2. first lateral arm; 7. select gate; 8. erase gate; 9. first intermediate dielectric layer; 10. second intermediate dielectric layer; 11. bottom dielectric layer; 12. top dielectric layer; 13. isolation layer. DETAILED DESCRIPTION

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] See attached Figure 1 This embodiment provides a memory device with high electrical conductivity, specifically a 1.5T split-gate floating gate 6 type memory, including a substrate 1, a source SRC 2, two lightly doped drains LDD 3, two bit lines BL 4, two floating gates FG 6, a control gate CG 5, two select gates SG 7, an erase gate EP 8, a first interlayer dielectric layer 9, a second interlayer dielectric layer 10, a top dielectric layer 12, and an isolation layer 13; the source SRC 2 is arranged in the middle of the substrate 1, the two lightly doped drains LDD 3 are respectively arranged on both sides of the substrate 1, and the two bit lines BL 4 are respectively arranged outside the two lightly doped drains LDD 3; the two floating gates FG 6, the control gate CG 5, and the two select gates SG 7 are all arranged above the substrate 1.

[0027] The control gate CG 5 is arranged just above the source SRC 2 , and two floating gates FG 6 are respectively arranged on both sides of the control gate CG 5 to half-wrap the control gate CG 5 ; two select gates SG 7 are respectively arranged on the outside of the two floating gates FG 6 .

[0028] A first interlayer dielectric layer 9 is provided between the floating gate FG 6 and the control gate CG 5 , and the first interlayer dielectric layer 9 wraps the bottom and sidewalls of the control gate CG 5 ; a second interlayer dielectric layer 10 is provided between the select gate SG 7 and the floating gate FG 6 .

[0029] A bottom dielectric layer 11 is provided between the substrate 1 and the floating gate FG 6 , the control gate CG 5 , and the select gate SG 7 . A top dielectric layer 12 is provided between the erase gate EP 8 and the floating gate FG 6 , the control gate CG 5 , and the select gate SG 7 .

[0030] In one embodiment, the substrate 1 is made of silicon; the first intermediate dielectric layer 9 and the second intermediate dielectric layer 10 are made of ONO; the top dielectric layer 12 and the bottom dielectric layer 11 are made of oxide, such as silicon oxide; and the isolation layer 13 is made of TEOS.

[0031] In one embodiment, an isolation layer 13 is further disposed above the select gate SG 7 , and the isolation layer 13 is located below the top dielectric layer 12 .

[0032] In one embodiment, the B ion doping concentration of the lightly doped drain LDD 3 is 1e13-1e14.

[0033] In one embodiment, the top of the floating gate FG 6 has a sharp corner, and the sharp corner is covered by the top dielectric layer 12 and the erase gate 8 .

[0034] In one embodiment, the two floating gates FG 6 are of axially symmetrical structure; the floating gate FG 6 is of L-shaped structure, comprising a first longitudinal arm 6-1 and a first transverse arm 6-2 perpendicular to each other, the head of the first longitudinal arm 6-1 having a sharp corner, the bottom of which is connected to one end of the first transverse arm 6-2, and the other end of the first transverse arm 6-2 pointing to the control gate CG 5; the control gate CG 5 is of T-shaped structure, comprising a second longitudinal arm 5-1 and a second transverse arm 5-2 perpendicular to each other, the head of the second longitudinal arm 5-1 being connected to the midpoint of the second transverse arm 5-2; the second transverse arm 5-2 of the control gate CG 5 is located above the first transverse arms 6-2 of the two floating gates FG 6, and the second longitudinal arm 5-1 of the control gate CG 5 is located between the first transverse arms 6-2 of the two floating gates FG 6.

[0035] In one embodiment, the height of the floating gate FG 6 is greater than that of the control gate CG 5 and the select gate SG 7 .

[0036] In one embodiment, the floating gate FG 6, the control gate CG 5, and the select gate SG 7 satisfy:

[0037]

[0038] Among them, w SG represents the width of the select gate SG, represents the length of the first lateral arm of the floating gate FG, represents the first longitudinal arm width of the control gate CG.

[0039] The present invention focuses on breaking through the performance bottleneck of traditional Flash memory devices in multi-value storage applications, and is committed to developing a high-linearity multi-value storage CIM Flash implementation method based on parameter collaborative control. Specifically, it involves using the collaborative control of key parameters of semiconductor memory devices to achieve high-linearity multi-value storage, so as to improve the technical field of Flash storage in the computing and storage integration (CIM) system when executing tasks. Its core goal is to solve the problems of poor electrical conductivity and lack of coordination in parameter control in traditional technologies, thereby significantly improving the reasoning accuracy and overall application performance of CIM systems in complex tasks in cutting-edge fields such as artificial intelligence and big data processing. Specifically, it includes:

[0040] (1) The memory is modeled using TCAD simulation software to obtain a device simulation model.

[0041] (2) applying a read voltage Vr (e.g., 6 V) to the device simulation model to obtain electrical properties of the device simulation model; the electrical properties include the on-resistance and off-resistance of the device;

[0042] Applying a pulse voltage to the device simulation model to obtain the conductivity parameters of the device simulation model; then calculating the linear relationship between the number of pulses and the conductivity parameters; the pulse parameters include pulse width (10 ns) and pulse height;

[0043] (3) Parameter setting of CIM simulation platform dnn+neurosim v2.0

[0044] 3-1 Update the parameters closely related to the device characteristics in the Param.cpp file to the electrical results of the device simulation model.

[0045] By accurately setting these parameters, the present invention enables the simulation platform to truly reflect the electrical characteristics of the new floating gate 6-type memory designed by the present invention under different working conditions, laying the foundation for subsequent accurate simulation of CIM system performance.

[0046] 3-2 Update the nonlinearity of the train.py file to a linear relationship between the number of pulses and the conductivity parameter.

[0047] In the train.py file, the present invention sets parameters related to nonlinearity for the graph neural network training process. Properly setting these parameters has a significant impact on the network's learning ability, convergence speed, and ultimate inference accuracy. By fine-tuning the nonlinearity-related parameters, the network's image feature extraction and classification performance is optimized, matching them with the characteristics of the high-linearity memory device of the present invention, and fully leveraging the performance advantages of the CIM system.

[0048] (4) The adjusted CIM simulation platform dnn+neurosim is equipped with a graph neural network (such as the convolutional neural network VGG-8), and then the graph neural network is used to perform image classification tasks.

[0049] Step (1) Use the TCAD tool and perform a series of simulations for 32-state storage requirements. In the TCAD simulation environment, for the floating gate FG6 structure, the polysilicon material parameters, including carrier mobility, bandgap width, etc., are accurately set to meet the actual process characteristics. Based on the optimal floating gate 6 length range of 90-100nm obtained from previous experiments and theoretical analysis, the FG length is accurately defined in the simulation model to ensure that the length tolerance is controlled within an extremely small range to simulate the actual manufacturing accuracy. By adjusting the simulation parameters such as temperature, pressure and gas flow in the FG growth process, the polysilicon deposition process is optimized, and a high-quality and well-uniform floating gate 6 structure is simulated and grown, laying the foundation for subsequent charge storage and transfer characteristic simulations. Within this range, the electric field distribution between the floating gate 6 and the channel is highly optimized, and the hot electron injection is uniform, effectively avoiding nonlinear problems such as concentrated or uneven charge injection. This enables the device conductivity to achieve high linearity under 32-state storage, providing a more stable and high-quality data storage foundation for the CIM system, and strongly supporting its reasoning application in complex tasks (such as the CIFAR-10 image classification task), with an inference accuracy of over 92%. Figure 2 .

[0050] The present invention innovatively inserts a lightly doped drain LDD 3 with a B ion doping concentration of 1e13-1e14 in the region connecting the source 2 and the channel. Using an ion implantation simulation module, parameters such as the implantation of impurity type B ions with a doping concentration of 1e13-1e14 and the implantation energy (18-20keV) are set to simulate the ion implantation process. The LDD structure acts as an electric field "buffer", effectively dispersing the high electric field at the edge of the source 2, avoiding charge injection anomalies, and solving the key problem of poor linearity of traditional devices. At the same time, the impact damage of hot carriers on the gate top dielectric layer 12 is significantly reduced. After 10 9 After multiple cycle tests, the device performance stability is excellent, ensuring the long-term stability of multi-value storage linearity, meeting the needs of long-term, high-intensity storage and computing tasks, and broadening the application prospects of CIM systems in industries, medical care and other fields with extremely high reliability requirements.

[0051] Step (2) During the device simulation process, an adaptive pulse programming strategy module is constructed. Using the feedback control algorithm, the amplitude, width and number of pulses are dynamically adjusted according to the real-time conductivity state and storage requirements of the storage unit. For example, in the initial stage, a high voltage (such as 6V) and narrow pulse width (10ns) pulse is first applied for rapid charge injection. Then, according to the feedback of the conductivity change of the storage unit, the pulse parameters of low voltage (such as 4V) and wide pulse width (50ns) are adaptively adjusted to achieve precise control of the charge injection amount and improve the linearity of multi-value storage. High voltage narrow pulses quickly inject a large amount of charge to establish the storage state foundation, and low voltage wide pulses finely adjust the charge distribution. Under the synergistic effect of the two pulses, the nonlinearity of charge injection is effectively reduced, the conductivity linearity is significantly improved, and the storage state distinction is significantly improved. This provides a reliable data storage foundation for high-precision reasoning of CIM systems and plays a key role in complex tasks such as artificial intelligence.

[0052] An intelligent system based on feedback control circuits monitors device operating status and storage requirements in real time. When storing high-density data, it automatically increases pulse amplitude and width to ensure sufficient charge injection. In scenarios requiring extremely high storage accuracy, such as high-precision neural network training, pulse parameters are fine-tuned for more precise charge control. This real-time adaptive adjustment further improves the linearity of multi-value storage.

[0053] After completing the process control and programming strategy simulation in steps (1)-(2) above, the present invention conducts a comprehensive simulation analysis of the device's electrical performance. The focus is on how the conductance value changes with the storage state, and a curve showing the relationship between the conductance value and the storage state is plotted using simulation data. After statistics and analysis of a large amount of simulation data, an electrical conductivity index is calculated. The results show that in a multi-value storage scenario, compared to traditional structures, the device designed by the present invention achieves high electrical conductivity, intuitively demonstrating the effectiveness of optimizing the process and programming strategy through TCAD simulation in improving device performance.

[0054] The present invention adopts DNN+Neurosim v2.0 as the CIM simulation platform, which integrates advanced deep learning simulation functions and efficient neuromorphic computing simulation modules. Its core advantage is that it can accurately simulate the performance of the integrated computing and storage (CIM) system when performing complex neural network tasks. The convolutional neural network VGG-8 architecture is selected. This architecture has good feature extraction and classification capabilities in the field of image recognition and is suitable for performing the CIFAR-10 image classification task. This task contains 60,000 color images of 10 different categories and has high requirements for the generalization ability and accuracy of the model. The TCAD simulation parameters are used as input and the reasoning accuracy of the task is output. By comparing the reasoning accuracy data under different linearities, it is clearly found that as the device electrical conductivity increases, the reasoning accuracy shows a significant upward trend, which effectively verifies the positive role of high linearity in improving the reasoning accuracy of the CIM system in complex tasks, further proving the effectiveness and application value of the present invention.

[0055] The above embodiments are not limitations of the present invention, and the present invention is not limited to the above embodiments. As long as the requirements of the present invention are met, they belong to the protection scope of the present invention.

Claims

1. A memory device with high electrical conductivity, characterized in that: The invention comprises a substrate (1), a source (2), two lightly doped drains (3), two bit lines (4), two floating gates (6), a control gate (5), two selection gates (7), an erase gate (8), a first intermediate dielectric layer (9), a second intermediate dielectric layer (10), a top dielectric layer (12), and an isolation layer (13); the source (2) is arranged in the middle of the substrate (1), the two lightly doped drains (3) are respectively arranged on both sides of the substrate (1), and the two bit lines (4) are respectively arranged outside the two lightly doped drains (3); the two floating gates (6), a control gate (5), and two selection gates (7) are all arranged above the substrate (1); The control gate (5) is arranged directly above the source (2), and two floating gates (6) are respectively arranged on both sides of the control gate (5); and two selection gates (7) are respectively arranged on the outsides of the two floating gates (6); A first intermediate dielectric layer (9) is provided between the floating gate (6) and the control gate (5), and the first intermediate dielectric layer (9) wraps the bottom and sidewalls of the control gate (5); a second intermediate dielectric layer (10) is provided between the select gate (7) and the floating gate (6); A bottom dielectric layer (11) is provided between the substrate (1) and the floating gate (6), the control gate (5), and the select gate (7); and a top dielectric layer (12) is provided between the erase gate (8) and the floating gate (6), the control gate (5), and the select gate (7).

2. The memory device with high electrical conductivity according to claim 1, wherein: An isolation layer (13) is also provided above the selection gate (7), and the isolation layer (13) is located below the top dielectric layer (12).

3. The memory device with high electrical conductivity according to claim 1, wherein: Two floating gates (6) half-wrap the control gate (5).

4. The memory device with high electrical conductivity according to claim 1, wherein: The head of the floating gate (6) has a sharp corner, and the sharp corner is covered by a top dielectric layer (12) and an erase gate (8).

5. The memory device with high electrical conductivity according to claim 1, wherein: The height of the floating gate (6) is greater than that of the control gate (5) and the selection gate (7).

6. The memory device with high electrical conductivity according to claim 1, wherein: The two floating gates (6) are of axisymmetric structure.

7. The memory device with high electrical conductivity according to claim 6, characterized in that: The floating gate (6) is an L-shaped structure, comprising a first longitudinal arm (6-1) and a first transverse arm (6-2) perpendicular to each other, the head of the first longitudinal arm (6-1) having a sharp corner, the bottom of the first longitudinal arm (6-1) being connected to one end of the first transverse arm (6-2), and the other end of the first transverse arm (6-2) pointing to the control gate (5).

8. The memory device with high electrical conductivity according to claim 7, characterized in that: The control gate (5) is a T-shaped structure, comprising a second longitudinal arm (5-1) and a second transverse arm (5-2) perpendicular to each other, wherein the head of the second longitudinal arm (5-1) is connected to the midpoint of the second transverse arm (5-2); the second transverse arm (5-2) of the control gate (5) is located above the first transverse arms (6-2) of the two floating gates (6), and the second longitudinal arm (5-1) of the control gate (5) is located between the first transverse arms (6-2) of the two floating gates (6).

9. The memory device with high electrical conductivity according to claim 8, characterized in that: The floating gate (6), the control gate (5), and the select gate (7) satisfy the following requirements: Among them, w SG represents the width of the selection gate (7), represents the length of the first lateral arm (6-2) of the floating gate (6), Indicates the width of the second longitudinal arm (5-1) of the control grid (5).

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