Semiconductor device and preparation method thereof, and storage system

Abstract

The invention provides a semiconductor device, a preparation method thereof and a storage system, relates to the technical field of semiconductors, and is used for improving the heat dissipation capability of the semiconductor device. The semiconductor device comprises a plurality of chips and at least one bonding dielectric layer. The plurality of chips are stacked along the thickness direction of the chips. And the at least one bonding dielectric layer is located between the two adjacent chips. Materials of the bonding dielectric layer at least comprise a first material and a second material, and the heat conductivity of the second material is larger than that of the second material. The semiconductor device is used for realizing data reading and writing operations.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and a storage system. Background Art

[0002] With the continuous advancement of semiconductor technology, the number of chips within semiconductor devices continues to increase. The heat generated by these multiple chips is difficult to dissipate and dissipate, leading to heat accumulation and impacting semiconductor device performance. Summary of the Invention

[0003] In one aspect, a semiconductor device is provided, comprising: a plurality of chips and at least one bonding dielectric layer. The plurality of chips are stacked along the thickness direction of the chips. The bonding dielectric layer is located between two adjacent chips. The bonding dielectric layer is composed of at least a first material and a second material, wherein the thermal conductivity of the second material is greater than the thermal conductivity of the first material.

[0004] In some embodiments, the bonding dielectric layer extends in a direction perpendicular to the thickness of the chip.

[0005] In some embodiments, the bonding dielectric layer includes: a plurality of first sub-layers and a plurality of second sub-layers alternately stacked along the thickness direction of the chip; the material of the first sub-layer includes: the first material; the material of the second sub-layer includes: the second material.

[0006] In some embodiments, in the bonding dielectric layer, each second sub-layer is located between any two adjacent first sub-layers.

[0007] In some embodiments, in the same bonding dielectric layer, a thickness of the first sub-layer adjacent to the chip is greater than or equal to a thickness of the second sub-layer.

[0008] In some embodiments, in the same bonding dielectric layer, the thickness of the first sub-layer located between two adjacent second sub-layers is greater than or equal to the thickness of the first sub-layer adjacent to the chip.

[0009] In some embodiments, the first sublayer adjacent to the chip in the bonding dielectric layer is used to achieve bonding between the chip and the second sublayer, and the first sublayer between two adjacent second sublayers is used to achieve bonding between two adjacent chips.

[0010] In some embodiments, a ratio of the sum of the thicknesses of the plurality of second sub-layers to the sum of the thicknesses of the plurality of first sub-layers is greater than or equal to 1:10 and less than or equal to 1:2.

[0011] In some embodiments, in the bonding dielectric layer, the second material is doped into the first material.

[0012] In some embodiments, the thermal conductivity of the second material is greater than or equal to 10 W / m*K.

[0013] In some embodiments, the first material comprises a bonding material; and the second material comprises a thermally conductive material.

[0014] In some embodiments, the second material includes at least one of silicon nitride, aluminum oxide, and silicon carbide.

[0015] In some embodiments, the first material includes silicon oxide.

[0016] In some embodiments, the semiconductor device further includes: a plurality of conductive pillars passing through the chip; the conductive pillars are used to connect two adjacent chips.

[0017] In some embodiments, the semiconductor device further includes: a plurality of conductive pillars, wherein the conductive pillars penetrate at least two adjacent chips and a bonding dielectric layer between the two adjacent chips; the conductive pillars are used to connect the two adjacent chips.

[0018] On the other hand, a method for preparing a semiconductor device is provided, the method comprising: providing a plurality of chips; the plurality of chips comprising a first chip and a second chip; forming a bonding dielectric sublayer on the first chip and the second chip, respectively; the material of the bonding dielectric sublayer comprising at least a first material and a second material, the thermal conductivity of the second material being greater than the thermal conductivity of the first material; and bonding the first chip to the second chip based on the bonding dielectric sublayer on the first chip and the bonding dielectric sublayer on the second chip.

[0019] In some embodiments, forming a bonding medium sublayer on the first chip and the second chip includes at least: forming a first sublayer on each of the chips; forming a second sublayer on the first sublayer; and forming a first sublayer on the second sublayer.

[0020] In some embodiments, forming a bonding medium sublayer on the first chip and the second chip includes: forming the bonding medium sublayer on the first chip and the second chip using a plasma enhanced chemical vapor deposition process; in the bonding medium sublayer, the second material is doped into the first material.

[0021] In some embodiments, the reaction gas used to form the bonding medium sub-layer includes silane, nitrogen, and nitrous oxide.

[0022] On the other hand, a storage system is provided, comprising: a controller, and a semiconductor device as described in any one of the above embodiments; wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, etc. involved in the embodiments of the present disclosure.

[0024] Figure 1 is a structural diagram of an electronic device according to some embodiments of the present disclosure;

[0025] Figure 2 is a structural diagram of a storage system according to some embodiments of the present disclosure;

[0026] Figure 3 is a structural diagram of a semiconductor device according to some embodiments of the present disclosure;

[0027] Figure 4 is a structural diagram of another semiconductor device according to some embodiments of the present disclosure;

[0028] Figure 5 is a structural diagram of another semiconductor device according to some embodiments of the present disclosure;

[0029] Figure 6 is a structural diagram of another semiconductor device according to some embodiments of the present disclosure;

[0030] Figure 7 is a structural diagram of another semiconductor device according to some embodiments of the present disclosure;

[0031] Figure 8 is a flow chart of a method for preparing a semiconductor device according to some embodiments of the present disclosure;

[0032] Figures 9 to 13 are structural diagrams corresponding to various steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0033] Figure 14 is a step diagram of another method for preparing a semiconductor device according to some embodiments of the present disclosure;

[0034] Figure 15A simplified structural diagram of a plasma chemical vapor deposition device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0035] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0036] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "horizontal", "inside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0037] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0038] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0039] When describing some embodiments, the term "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0040] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0041] like Figure 1 As shown, some embodiments of the present disclosure provide an electronic device 3000, which can include any device capable of storing data, such as a mobile phone, desktop computer, tablet computer, laptop computer, server, etc. The electronic device 3000 can include a storage system 1000 configured to implement data storage, as described below, and a circuit board 2000 electrically connected to the storage system. The circuit board 2000 is used to provide electrical signals, etc. to the storage system 1000.

[0042] like Figure 2 As shown, some embodiments of the present disclosure provide a storage system 1000. The storage system 1000 is used in the above-mentioned electronic device 3000. The storage system 1000 includes a semiconductor device 100 and a controller 200. The controller 200 is coupled to the semiconductor device 100 and is used to control the semiconductor device 100 to store data.

[0043] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into various types of electronic products, such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other electronic devices with memory.

[0044] In some examples, the storage system 1000 includes a controller 200 and a semiconductor device 100. The storage system 1000 can be integrated into a memory card, for example. The memory card includes one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS card.

[0045] In other examples, such as Figure 2 As shown, the memory system 1000 includes a controller 200 and a plurality of semiconductor devices 100 .

[0046] Illustratively, the storage system 1000 includes a controller 200 and four semiconductor devices 100. The storage system 1000 may be integrated into a solid state drive (SSD), for example.

[0047] In some examples, in storage system 1000, controller 200 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0048] In other examples, in the storage system 1000 , the controller 200 is configured to operate in a high duty cycle environment SSD or eMMC, which is used for data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0049] In some examples, the controller 200 may be configured to manage data stored in the semiconductor device 100 and communicate with an external device (eg, a host).

[0050] In some examples, the controller 200 may also be configured to control operations of the semiconductor device 100 , such as read, erase, and program operations.

[0051] In some examples, the controller 200 may also be configured to manage various functions regarding data stored or to be stored in the semiconductor device 100 , including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling.

[0052] In some examples, the controller 200 is also configured to process an error correction code regarding data read from or written to the semiconductor device 100 .

[0053] It is easy to understand that the controller 200 may also perform any other suitable functions, such as formatting the semiconductor device 100. For another example, the controller 200 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0054] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Mini Interface (SCSI) protocol, Enhanced Minidisk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0055] The controller 200 may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.

[0056] like Figure 3 As shown, some embodiments of the present disclosure provide a semiconductor device 100 that can be used in the storage system of the above embodiments. The semiconductor device 100 includes: a plurality of chips 10 and at least one bonding dielectric layer 20.

[0057] The plurality of chips 10 are stacked along the thickness direction of the chip 10 .

[0058] It is understandable that Figure 3 In FIG. 1 , X is a first direction, Y is a second direction, and Z is a third direction. The third direction Z is the thickness direction of the chip 10 . The first direction X and the second direction Y are both perpendicular to the third direction Z. The first direction X and the second direction Y form an angle, which may be 90°.

[0059] For example, the semiconductor device 100 may be a DRAM (Dynamic Random Access Memory), a CIS (Complementary Metal-Oxide-Semiconductor Transistor Image Sensor), an HMC (Hybrid Memory Cube), or the like.

[0060] The at least one bonding dielectric layer 20 is located between two adjacent chips 10 , so that the two adjacent chips 10 are bonded via the bonding dielectric layer 20 .

[0061] For example, among the multiple chips 10 in the semiconductor device 100 , one bonding dielectric layer 20 is disposed between every two adjacent chips 10 .

[0062] For another example, among the multiple chips 10 in the semiconductor device 100, in a portion of the chips 10, the above-mentioned bonding medium layer 20 is arranged between every two adjacent chips 10; in another portion of the chips 10, other film layers are arranged between every two adjacent chips 10, and the other film layers are used to achieve bonding between the chips 10.

[0063] The bonding dielectric layer 20 comprises at least a first material and a second material. The first material is used to achieve bonding between the chips 10. Heat is inevitably generated during operation of the semiconductor device 100. The second material is used to dissipate heat between the chips 10. The thermal conductivity of the second material is greater than that of the first material. This improves the heat dissipation of the semiconductor device 100 and prevents heat accumulation within the chips 10 that could affect the performance of the semiconductor device 100.

[0064] The material of the bonding dielectric layer 20 may also include other materials in addition to the first material and the second material mentioned above.

[0065] The semiconductor device 100 provided by the embodiments of the present disclosure includes a plurality of chips 10 stacked in a thickness direction, and a bonding dielectric layer 20 located between two adjacent chips 10. The bonding dielectric layer 20 is further configured to include a first material and a second material, and the thermal conductivity of the second material is configured to be greater than the thermal conductivity of the first material. This allows the thermal conductivity of the bonding dielectric layer 20 to be greater, allowing the heat between the two adjacent chips 10 to be diffused and discharged in a timely manner, thereby improving the heat dissipation effect of the semiconductor device 100 and preventing heat from accumulating inside the chips 10 and affecting the performance of the semiconductor device 100.

[0066] The sizes of the multiple chips 10 in the semiconductor device 100 may be equal or unequal. The following description takes the case where the sizes of the multiple chips 10 are equal and the orthographic projections of the chips 10 on the plane where the bonding dielectric layer 20 is located as an example.

[0067] It is understandable that there are various structures of the bonding dielectric layer 20 , which can be configured according to actual needs, and the embodiments of the present disclosure do not limit this.

[0068] For example, Figure 3 As shown, the bonding dielectric layer 20 extends in a direction perpendicular to the thickness of the chip 10 .

[0069] For example, the two chips 10 described above include a first chip 11 and a second chip 12, wherein the first chip 11 is located on the second chip 12, and the bonding dielectric layer 20 is located between the first chip 11 and the second chip 12. The bonding dielectric layer 20 covers the surface of the second chip 12 on the side closest to the first chip 11. Alternatively, the orthographic projection of the bonding dielectric layer 20 on the plane where the second chip 12 is located coincides with the orthographic projection of the first chip 11 on the plane where the second chip 12 is located.

[0070] Thus, part of the heat can be transferred and diffused from the chip 10 to the corresponding bonding dielectric layer 20, so that the heat can be transferred not only longitudinally between two adjacent chips 10 (the longitudinal direction here can refer to Figure 3 The transmission and diffusion in the third direction Z) can also be realized in the lateral direction through the bonding dielectric layer 20 (the lateral direction here can refer to Figure 3 The transmission and diffusion in the first direction X and the second direction Y) increases the heat dissipation path of the heat, further improving the heat dissipation capacity of the semiconductor device 100.

[0071] In some examples, such as Figure 4 As shown, the bonding dielectric layer 20 includes: a plurality of first sub-layers 21 and a plurality of second sub-layers 22 alternately stacked along the thickness direction of the chip 10 .

[0072] For example, along the thickness direction of the chip 10 , the following layers are stacked in sequence: a first sub-layer 21 , a second sub-layer 22 , a first sub-layer 21 , a second sub-layer 22 , and so on.

[0073] For example, the multiple first sub-layers 21 and the multiple second sub-layers 22 are directly opposite to each other along the thickness direction of the chip 10 , or the orthographic projections of the multiple first sub-layers 21 and the multiple second sub-layers 22 on the plane where the chip 10 is located overlap.

[0074] The material of the first sub-layer 21 includes: the first material mentioned above. The material of the second sub-layer 22 includes: the second material mentioned above.

[0075] Thus, the first sublayer 21 comprising the first material can achieve bonding between two adjacent chips 10, and the second sublayer 22 comprising the second material is used to improve the heat dissipation capability of the bonding dielectric layer 20 and the semiconductor device 100. Furthermore, the provision of the entire second sublayer 22 comprising the second material can make the thermal conductivity at different locations between the two adjacent chips 10 roughly uniform, which is beneficial for improving the heat dissipation capability of the chips 10 and the semiconductor device 100.

[0076] For example, Figure 4 As shown, in the bonding dielectric layer 20 , each second sub-layer 22 is located between any two adjacent first sub-layers 21 .

[0077] For example, the bonding dielectric layer 20 may include: a first sub-layer 21 , a second sub-layer 22 , a first sub-layer 21 , a second sub-layer 22 , and a first sub-layer 21 , which are sequentially stacked on the chip 10 .

[0078] Therefore, the first sublayer 21 in the bonding dielectric layer 20 is adjacent to or in contact with the chip 10 , thereby ensuring the bonding strength between the chip 10 and the bonding dielectric layer 20 , and improving the heat dissipation effect of the semiconductor device 100 by utilizing the second sublayer 22 .

[0079] For example, in the bonding dielectric layer 20, the first sublayer 21 located between the chip 10 and the second sublayer 22 is used to achieve bonding between the chip 10 and the second sublayer 22. The first sublayer 21 located between two adjacent second sublayers 22 is used to achieve bonding between the first sublayer 21 and the chip 10 through the connection between the first sublayer 21, the adjacent second sublayer 22, and the chip 10, thereby achieving bonding between the two adjacent chips 10. This increases the bonding strength between the second sublayer 22 and the chip 10, and also increases the bonding strength between the two chips 10, thereby ensuring the bonding strength between the chips 10.

[0080] It is understood that within the same bonding dielectric layer 20, the thicknesses of the first sub-layers 21 may be equal or unequal; the thicknesses of the first sub-layer 21 and the second sub-layer 22 may be equal or unequal. The thicknesses of the first sub-layers 21 in different bonding dielectric layers 20 may be equal or unequal; the thicknesses of the second sub-layers 22 in different bonding dielectric layers 20 may be equal or unequal.

[0081] like Figure 4 As shown, in the same bonding dielectric layer 20 , the thickness of the first sub-layer 21 adjacent to the chip 10 is greater than or equal to the thickness of the second sub-layer 22 .

[0082] For example, in the bonding dielectric layer 20, the thickness of the first sublayer 21 adjacent to the chip 10 is greater than the thickness of the second sublayer 22. This ensures the bonding strength of the first sublayer 21 to the adjacent chip 10 and the second sublayer 22. Furthermore, the sum of the thicknesses of the multiple first sublayers 21 in the bonding dielectric layer 20 is relatively large, resulting in a high proportion (e.g., mass ratio) of the first sublayer 21 in the bonding dielectric layer 20, thereby ensuring a certain bonding strength between adjacent chips 10.

[0083] For another example, the thickness of the first sub-layer 21 adjacent to the chip 10 is equal to the thickness of the second sub-layer 22. This helps to increase the proportion (e.g., mass ratio) of the second sub-layer 22 in the bonding dielectric layer 20, thereby improving the heat dissipation capability of the semiconductor device 100.

[0084] like Figure 4 As shown, in the same bonding dielectric layer 20 , the thickness of the first sub-layer 21 located between two adjacent second sub-layers 22 is greater than or equal to the thickness of the first sub-layer 21 adjacent to the chip 10 .

[0085] For example, in the bonding dielectric layer 20 , the thickness of the first sub-layer 21 located between two adjacent second sub-layers 22 is greater than the thickness of the first sub-layer 21 adjacent to the chip 10 .

[0086] As can be seen from the above, the first sublayer 21 located between two adjacent second sublayers 22 is used to achieve bonding between two adjacent chips 10. Therefore, the above setting can ensure the bonding strength of the chip 10; it can also make the sum of the thicknesses of multiple first sublayers 21 in the bonding medium layer 20 relatively large, so that the proportion (for example, mass ratio) of the first sublayer 21 in the bonding medium layer 20 is high, thereby further ensuring that there is a certain bonding strength between adjacent chips 10.

[0087] For another example, the thickness of the first sub-layer 21 located between two adjacent second sub-layers 22 is equal to the thickness of the first sub-layer 21 adjacent to the chip 10 .

[0088] Therefore, the above configuration is also beneficial for increasing the proportion (eg, mass ratio) of the second sub-layer 22 in the bonding dielectric layer 20 , and is beneficial for improving the heat dissipation capability of the semiconductor device 100 .

[0089] Illustratively, the ratio of the sum of the thicknesses of the plurality of second sub-layers 22 to the sum of the thicknesses of the plurality of first sub-layers 21 is greater than or equal to 1:10 and less than or equal to 1:2.

[0090] For example, in the same bonding dielectric layer 20, the ratio of the sum of the thicknesses of the multiple second sub-layers 22 to the sum of the thicknesses of the multiple first sub-layers 21 is greater than or equal to 1:10 and less than or equal to 1:7; or, greater than or equal to 1:7 and less than or equal to 1:5; or, greater than or equal to 1:6 and less than or equal to 1:4; or, greater than or equal to 1:8 and less than or equal to 1:2.

[0091] For example, in the same bonding dielectric layer 20 , the ratio of the sum of the thicknesses of the plurality of second sub-layers 22 to the sum of the thicknesses of the plurality of first sub-layers 21 is 1:10, 1:9, 1:7, 1:6, 1:3 or 1:2.

[0092] Thus, in the bonding dielectric layer 20 , the ratio of the sum of the thicknesses of the plurality of second sub-layers 22 to the sum of the thicknesses of the plurality of first sub-layers 21 can be within a reasonable range, thereby ensuring that the average thermal conductivity of the entire bonding dielectric layer 20 is improved while ensuring the bonding strength of the semiconductor device 100 .

[0093] It can be understood that, among the multiple bonding dielectric layers 20 of the semiconductor device 100, the ratio of the sum of the thicknesses of the multiple second sub-layers 22 in one bonding dielectric layer 20 to the sum of the thicknesses of the multiple first sub-layers 21 is in the range of G; the ratio of the sum of the thicknesses of the multiple second sub-layers 22 in another bonding dielectric layer 20 to the sum of the thicknesses of the multiple first sub-layers 21 is in the range of H, and the above G and H can be the same or different. The ratio of the sum of the thicknesses of the multiple second sub-layers 22 in one bonding dielectric layer 20 to the sum of the thicknesses of the multiple first sub-layers 21 is G1, and the ratio of the sum of the thicknesses of the multiple second sub-layers 22 in another bonding dielectric layer 20 to the sum of the thicknesses of the multiple first sub-layers 21 is G2. The above G1 and G2 can be equal or unequal. The embodiments of the present disclosure are not limited to this, and can be set according to actual needs.

[0094] For example, in the semiconductor device 100 , the ratio of the sum of the thicknesses of the plurality of second sub-layers 22 to the sum of the thicknesses of the plurality of first sub-layers 21 ranges from 1:10 to 1:7, 1:7 to 1:5, 1:6 to 1:4, or 1:8 to 1:2.

[0095] In other examples, such as Figure 5 As shown, in the bonding dielectric layer 20, the second material is doped in the first material.

[0096] For example, the mass proportion of the second material in the bonding dielectric layer 20 is smaller than the mass proportion of the first material in the bonding dielectric layer 20 .

[0097] For example, the second material is uniformly doped in the first material to form the bonding dielectric layer 20 .

[0098] By adopting the above-mentioned setting method, the second material with higher thermal conductivity is doped into the first material, so that the thermal conductivity of the bonding medium layer 20 composed of the first material and the second material is improved, so that the heat dissipation capacity of the chip 10 and the semiconductor device 100 is improved, and the bonding strength of the semiconductor device 100 can be guaranteed.

[0099] Exemplarily, the thermal conductivity of the second material is greater than or equal to 10 W / m*K.

[0100] For example, the thermal conductivity of the second material may be 10 W / m*K, 20 W / m*K, 30 W / m*K, 50 W / m*K, 100 W / m*K, or 120 W / m*K.

[0101] This is beneficial for improving the overall thermal conductivity of the bonding dielectric layer 20 , thereby improving the heat dissipation capability of the semiconductor device 100 .

[0102] In some examples, the second material includes at least one of silicon nitride, aluminum oxide, and silicon carbide.

[0103] For example, the second material may be silicon nitride, aluminum oxide, or silicon carbide.

[0104] For another example, the second material may be silicon nitride and aluminum oxide, the second material may also be silicon nitride and silicon carbide, the second material may also be aluminum oxide and silicon carbide, etc.

[0105] The thermal conductivity of silicon nitride is approximately 20 W / m*K, the thermal conductivity of aluminum oxide is approximately 35 W / m*K, and the thermal conductivity of silicon carbide is approximately 120 W / m*K. Therefore, the second material comprising at least one of silicon nitride, aluminum oxide, and silicon carbide can increase the thermal conductivity of the bonding dielectric layer 20. During heat transfer from the chip 10 to the bonding dielectric layer 20, the heat can be effectively conducted or diffused from the bonding dielectric layer 20, thereby improving the heat dissipation capabilities of the chip 10 and the semiconductor device 100 and preventing heat accumulation from affecting the performance of the semiconductor device 100.

[0106] Exemplarily, the first material includes silicon oxide.

[0107] The thermal conductivity of silicon oxide is approximately 1.4 W / m*K. Silicon oxide has good bonding properties.

[0108] Therefore, the first material has low thermal conductivity, and the addition of the second material with high thermal conductivity improves the overall thermal conductivity of the bonding dielectric layer 20. After the silicon oxide and the second material form the bonding dielectric layer 20, the bonding dielectric layer 20 can be guaranteed to have strong bonding strength.

[0109] In some examples, such as Figure 6As shown, the semiconductor device 100 further includes: a plurality of conductive pillars 30 penetrating the chip 10. The conductive pillars 30 are used to connect two adjacent chips 10.

[0110] For example, the conductive pillars 30 are filled in TSVs (Through Si Vias) that penetrate the chip 10. The conductive pillars 30 may be made of metal, thereby providing a certain heat dissipation capability.

[0111] For example, each conductive pillar 30 only passes through one chip 10. In this case, the bonding method between two adjacent chips 10 in the semiconductor device 100 can be hybrid bonding.

[0112] The plurality of conductive pillars 30 can also serve as heat transfer channels of the semiconductor device 100 along the thickness direction of the chip 10 , thereby improving the heat dissipation capability of the semiconductor device 100 .

[0113] In other examples, such as Figure 7 As shown, the semiconductor device 100 further includes: a plurality of conductive pillars 30. The conductive pillars 30 penetrate at least two adjacent chips 10 and the bonding dielectric layer 20 between the two adjacent chips 10. The conductive pillars 30 are used to connect the two adjacent chips 10.

[0114] For example, one conductive pillar 30 may pass through a plurality of sequentially adjacent chips 10. In this case, the bonding method between two adjacent chips 10 in the semiconductor device 100 may be direct bonding.

[0115] The plurality of conductive pillars 30 may also serve as heat transfer channels of the semiconductor device 100 along the thickness direction of the chip 10 , thereby improving the heat dissipation capability of the semiconductor device 100 .

[0116] In addition, Figure 6 and Figure 7 In the semiconductor device 100 shown, due to the provision of the bonding dielectric layer 20 , the number of conductive pillars 30 used solely for heat dissipation can be reduced to a certain extent, the distribution density of the conductive pillars 30 can be reduced, and the preparation cost and design difficulty of the semiconductor device 100 can be reduced.

[0117] Some embodiments of the present disclosure also provide a method for preparing a semiconductor device 100, which can be used to prepare the semiconductor device 100 in the above embodiment. Figure 8 1 shows a flow chart of a method for manufacturing a semiconductor device 100. It should be understood that Figure 8 The steps shown are not exclusive, and other steps may be performed before, after, or between any of the steps shown. In addition, some of the steps may be performed simultaneously, or may be performed in different steps. Figure 8Executed in the order shown.

[0118] The above preparation method is schematically described below with reference to the accompanying drawings. Figure 8 As shown, the preparation method includes: A100~A300.

[0119] A100, such as Figure 9 As shown, a plurality of chips 10 are provided. The plurality of chips 10 include a first chip 11 and a second chip 12.

[0120] For example, the sizes of the plurality of chips 10 may be equal or unequal.

[0121] A200, such as Figure 10 or Figure 12 As shown, bonding dielectric sub-layers 23 are formed on the first chip 11 and the second chip 12 respectively. The bonding dielectric sub-layers 23 are made of at least a first material and a second material, wherein the thermal conductivity of the second material is greater than that of the first material.

[0122] For example, the structure of the bonding dielectric sub-layer 23 on the first chip 11 and the bonding dielectric sub-layer 23 on the second chip 12 may be the same or different.

[0123] For example, before forming the bonding dielectric sub-layer 23 , the chip 10 may be thinned, which is beneficial to the lightweight and thin design of the semiconductor device 100 .

[0124] A300, such as Figure 11 or Figure 13 As shown, the first chip 11 and the second chip 12 are bonded based on the bonding dielectric sub-layer 23 on the first chip 11 and the bonding dielectric sub-layer 23 on the second chip 12 .

[0125] For example, after the second chip 12 and the bonding dielectric sublayer 23 thereon are turned upside down, the bonding dielectric sublayer 23 on the first chip 11 is bonded to the bonding dielectric sublayer 23 on the second chip 12 to form the above-mentioned bonding dielectric layer 20 .

[0126] The method for preparing the semiconductor device 100 provided in the embodiment of the present disclosure forms a bonding dielectric sublayer 23 on the first chip 11 and the second chip 12. The material of the bonding dielectric sublayer 23 includes at least a first material and a second material. The thermal conductivity of the second material is greater than the thermal conductivity of the first material. Based on the bonding dielectric sublayer 23, the first chip 11 and the second chip 12 are bonded to prepare the semiconductor device 100. The second material in the bonding dielectric sublayer 23 can be utilized to make the thermal conductivity of the bonding dielectric layer 20 larger. As a result, the heat between the two adjacent chips 10 can be promptly diffused and discharged through the second material with higher thermal conductivity, thereby improving the heat dissipation effect of the semiconductor device 100 and preventing heat from accumulating inside the chip 10 and affecting the performance of the semiconductor device 100.

[0127] There are many methods for forming the bonding medium sub-layer 23 , which can be selected according to actual needs, and the embodiments of the present disclosure do not limit this.

[0128] In some examples, in the above A200 , a bonding dielectric sub-layer 23 is formed on the first chip 11 and the second chip 12 , including at least: A210 ˜ A230 .

[0129] A210, such as Figure 14 As shown in (a), a first sub-layer 21 is formed on each chip 10 .

[0130] For example, a high density plasma chemical vapor deposition (HDP CVD) process may be used to form the first sub-layer 21 on the chip 10. The material of the first sub-layer 21 may be the aforementioned silicon oxide.

[0131] A220, such as Figure 14 As shown in (b), the second sub-layer 22 is formed on the first sub-layer 21.

[0132] For example, a high-density plasma chemical vapor deposition process may be used to form the second sub-layer 22 on the first sub-layer 21. The material of the second sub-layer 22 may be the silicon nitride.

[0133] A230, such as Figure 14 As shown in (c), the first sub-layer 21 is formed on the second sub-layer 22.

[0134] Of course, the second sub-layer 22 , the first sub-layer 21 , the second sub-layer 22 , the first sub-layer 21 , and so on may be formed in sequence on the first sub-layer 21 .

[0135] By adopting the above-mentioned preparation method, the bonding dielectric sublayer 23 formed includes a plurality of first sublayers 21 and a plurality of second sublayers 22 stacked in sequence. The first sublayer 21 in the bonding dielectric sublayer 23 has a bonding effect, and the second sublayer 22 has a good thermal conductivity, thereby improving the heat dissipation capacity of the semiconductor device 100; and the formed bonding dielectric sublayer 23 extends in a thickness direction perpendicular to the chip 10, so that the heat generated by the chip 10 and the semiconductor device 100 during operation can be dissipated laterally through the bonding dielectric layer 20 (the horizontal direction here can refer to Figure 3 The transmission and diffusion in the first direction X and the second direction Y) increases the heat dissipation path of the heat, further improving the heat dissipation capacity of the semiconductor device 100.

[0136] The thickness of the first sub-layer 21 and the thickness of the second sub-layer 22 can be determined by referring to the description in the above embodiments of the present disclosure, and will not be repeated here.

[0137] In other examples, in the above-mentioned A200, forming the bonding dielectric sublayer 23 on the first chip 11 and the second chip 12 includes: using a plasma enhanced chemical vapor deposition (PECVD) process to form the bonding dielectric sublayer 23 on the first chip 11 and the second chip 12. In the bonding dielectric sublayer 23, the second material is doped in the first material.

[0138] By adopting the above-mentioned preparation method, the bonding dielectric sub-layer 23 can not only have a bonding function, but also have a good thermal conductivity, thereby improving the heat dissipation capability of the semiconductor device 100 .

[0139] For example, the second material may be silicon nitride, the first material may be silicon oxide, and silicon nitride is doped in the silicon oxide.

[0140] Taking the example that the second material may be silicon nitride and the first material may be silicon oxide, the reaction gases for forming the bonding dielectric sub-layer 23 include: silane, nitrogen and nitrous oxide.

[0141] Figure 15 The figure shows a simplified structural diagram of a plasma chemical vapor deposition device 40. The device includes: a plurality of gas cylinders 41, an air intake system 42, an ionization mechanism 43, a wafer tray 44, a vacuum device 45, a reaction chamber 46, etc.

[0142] For example, the vacuum pumping device 45 can evacuate the reaction chamber 46 and control the vacuum level within the reaction chamber 46. Reactive gases can be stored in different gas cylinders 41. The reactive gases can enter the ionization mechanism 43 through the gas inlet system 42, and after being ionized, enter the reaction chamber 46. The chips 10 can be placed on a wafer tray 44.

[0143] The reaction gas may generate silicon oxide doped with silicon nitride in the reaction chamber 46 . The silicon oxide doped with silicon nitride is deposited on the surface of the chip 10 to form a bonding dielectric sub-layer 23 .

[0144] The above-mentioned preparation method can make the preparation of the bonding medium sub-layer 23 relatively simple, which is helpful to simplify the preparation process.

[0145] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: A plurality of chips are stacked along the thickness direction of the chip; At least one bonding dielectric layer is located between two adjacent chips; the bonding dielectric layer comprises at least a first material and a second material, and the thermal conductivity of the second material is greater than the thermal conductivity of the first material.

2. The semiconductor device according to claim 1, wherein The bonding dielectric layer extends in a direction perpendicular to the thickness of the chip.

3. The semiconductor device according to claim 1, wherein The bonding dielectric layer includes: a plurality of first sub-layers and a plurality of second sub-layers alternately stacked along the thickness direction of the chip; The material of the first sub-layer includes: the first material; the material of the second sub-layer includes: the second material.

4. The semiconductor device according to claim 3, wherein In the bonding dielectric layer, each second sub-layer is located between any two adjacent first sub-layers.

5. The semiconductor device according to claim 4, wherein In the same bonding dielectric layer, the thickness of the first sub-layer adjacent to the chip is greater than or equal to the thickness of the second sub-layer.

6. The semiconductor device according to claim 4, wherein In the same bonding dielectric layer, the thickness of the first sub-layer located between two adjacent second sub-layers is greater than or equal to the thickness of the first sub-layer adjacent to the chip.

7. The semiconductor device according to claim 3, wherein In the bonding dielectric layer, a first sublayer adjacent to the chip, used to achieve bonding between the chip and the second sublayer; The first sublayer located between two adjacent second sublayers is used to achieve bonding between the two adjacent chips.

8. The semiconductor device according to claim 3, wherein The ratio of the sum of the thicknesses of the plurality of second sub-layers to the sum of the thicknesses of the plurality of first sub-layers is greater than or equal to 1:10 and less than or equal to 1:

2.

9. The semiconductor device according to claim 1, wherein In the bonding dielectric layer, the second material is doped into the first material.

10. The semiconductor device according to claim 1, wherein The thermal conductivity of the second material is greater than or equal to 10 W / m*K.

11. The semiconductor device according to claim 1, wherein The first material includes a bonding material; the second material includes a thermally conductive material.

12. The semiconductor device according to any one of claims 1 to 9, wherein: The second material includes at least one of silicon nitride, aluminum oxide, and silicon carbide.

13. The semiconductor device according to any one of claims 1 to 9, wherein: The first material includes silicon oxide.

14. The semiconductor device according to claim 1, wherein The semiconductor device further includes: a plurality of conductive pillars penetrating the chip; the conductive pillars are used to connect two adjacent chips.

15. The semiconductor device according to claim 1, wherein The semiconductor device further includes: a plurality of conductive pillars, wherein the conductive pillars penetrate at least two adjacent chips and a bonding dielectric layer between the two adjacent chips; the conductive pillars are used to connect the two adjacent chips.

16. A method for preparing a semiconductor device, characterized in that: The preparation method comprises: Providing a plurality of chips; the plurality of chips include a first chip and a second chip; forming bonding dielectric sublayers on the first chip and the second chip respectively; the bonding dielectric sublayers include at least a first material and a second material, wherein the thermal conductivity of the second material is greater than the thermal conductivity of the first material; The first chip and the second chip are bonded based on the bonding medium sub-layer on the first chip and the bonding medium sub-layer on the second chip.

17. The preparation method according to claim 16, characterized in that Forming a bonding dielectric sublayer on the first chip and the second chip at least includes: forming a first sub-layer on each of the chips; forming a second sublayer on the first sublayer; A first sub-layer is formed on the second sub-layer.

18. The preparation method according to claim 16, characterized in that Forming a bonding medium sublayer on the first chip and the second chip, comprising: The bonding medium sub-layer is formed on the first chip and the second chip by using a plasma enhanced chemical vapor deposition process; in the bonding medium sub-layer, the second material is doped into the first material.

19. The preparation method according to claim 18, characterized in that The reaction gas for forming the bonding medium sub-layer includes silane, nitrogen and nitrous oxide.

20. A storage system, characterized in that: The storage system includes: a controller, and the semiconductor device according to any one of claims 1 to 15; wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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