Schottky diode and manufacturing method thereof

Abstract

The invention discloses a Schottky diode and a manufacturing method thereof, the Schottky diode comprises a substrate, an epitaxial layer, a cathode layer, a plurality of first ion implantation regions, a plurality of first grooves, a second barrier metal layer and an anode layer, the plurality of first ion implantation regions and the plurality of first grooves are arranged in a main junction region, a first ion implantation region is arranged at the bottom of the first groove, a PN junction is formed between the first ion implantation region and the epitaxial layer, a second ion implantation region is arranged at the bottom of the first groove, a PN junction is formed between the second ion implantation region and the epitaxial layer, and a first barrier metal layer is arranged on the side wall of the first groove; the second barrier metal layer is arranged on one side, far away from the substrate, of the epitaxial layer, is positioned in the main junction region and is connected with the first ion implantation region and the first barrier metal layer; the anode layer is disposed on the second barrier metal layer. Through the above design, the reverse leakage current of the Schottky diode can be greatly reduced, and the forward conduction voltage drop of the Schottky diode can be reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor device technology, and in particular to a Schottky diode and a method for manufacturing the same. Background Art

[0002] Schottky diodes are made by depositing metal on the surface of a semiconductor to form a metal-semiconductor contact Schottky barrier or a silicide Schottky barrier. Due to their low on-state voltage drop and fast switching frequency, they are widely used as power rectifiers in switching power supplies or other switching devices requiring high-speed power.

[0003] Because the barrier height of the Schottky junction is lower than that of the PN junction, the Schottky diode has a lower conduction voltage drop than the PN junction diode when forward conducting. In addition, due to the mirror force of the Schottky diode under the action of reverse voltage, the Schottky diode has a large reverse leakage current, which easily leads to a reduced service life of the diode device. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a Schottky diode capable of reducing reverse leakage current and a method for manufacturing the same.

[0005] The embodiment of the present application discloses a Schottky diode, which includes a substrate, an epitaxial layer, a cathode layer, a plurality of first ion implantation regions, a plurality of first trenches, a second barrier metal layer and an anode layer, wherein the substrate is a first high-concentration doped layer, the epitaxial layer is arranged on the substrate, and the epitaxial layer is a first low-concentration doped layer; wherein the epitaxial layer is divided into a main junction region and a terminal region, and the main junction region and the terminal region are arranged in parallel; the cathode layer is arranged on a side of the substrate away from the epitaxial layer; a plurality of first ion implantation regions are arranged in the main junction region, and the first ion implantation region and the epitaxial layer are spaced apart from each other. a plurality of first trenches are arranged in the main junction area, the first ion implantation area and the first trenches are arranged in parallel, a second ion implantation area is provided at the bottom of the first trench, a PN junction is formed between the second ion implantation area and the epitaxial layer; and a first barrier metal layer is provided on the sidewall of the first trench, the first barrier metal layer is connected to the second ion implantation area; the second barrier metal layer is arranged on a side of the epitaxial layer away from the substrate, is located in the main junction area, and is connected to the first ion implantation area and the first barrier metal layer; the anode layer is arranged on the second barrier metal layer.

[0006] Optionally, the Schottky diode further includes a second trench, an isolation layer and a passivation layer, the second trench being arranged in the terminal region, a third ion implantation region being provided at the bottom of the second trench, and the isolation layer being arranged on the sidewalls of the second trench and the third ion implantation region; the passivation layer being arranged on a side of the epitaxial layer away from the substrate, located in the terminal region, and the orthographic projection of the passivation layer on the substrate does not overlap with the orthographic projection of the second trench on the substrate.

[0007] Optionally, the isolation layer and the passivation layer are formed by a synchronous process.

[0008] Optionally, the first ion implantation region is a planar structure.

[0009] Optionally, the first trench is filled with a metal block, the bottom of the metal block is connected to the second ion implantation region, the side of the metal block is connected to the first barrier metal layer, and the top of the metal block is connected to the second barrier metal layer.

[0010] Optionally, the metal block includes a first metal layer, a second metal layer and a third metal layer stacked in sequence, the first metal layer is connected to the second ion injection area, the third metal layer is connected to the second barrier metal layer, and the sides of the first metal layer, the second metal layer and the third metal layer are connected to the first barrier metal layer; the first metal layer is made of metal titanium material, the second metal layer is made of metal nickel material, the third metal layer is made of metal silver material, and the first barrier metal layer and the second barrier metal layer are both made of titanium silicide material.

[0011] Optionally, the depth and width of the first injection region are both less than 0.5um, the depth of the first groove is 1.5um-3um, the width of the first groove is 0.5um-2um, and the distance between the first ion injection region and the first groove is 1.5um-2.5um.

[0012] Optionally, the number of the first ion implantation regions and the first trenches is the same, and the first ion implantation regions and the first trenches are staggered one by one.

[0013] The present application also discloses a method for manufacturing a Schottky diode, which is used to manufacture the Schottky diode described above. The method comprises the following steps:

[0014] Selecting a silicon wafer, wherein the silicon wafer has a first high-concentration doped substrate and a first low-concentration doped epitaxial layer;

[0015] forming a first barrier layer pattern on the epitaxial layer;

[0016] Etching the epitaxial layer to form a plurality of first trenches in the main junction region of the epitaxial layer;

[0017] Processing the pattern of the first barrier layer to expose the area where the first ion implantation area is located on the main junction area of the epitaxial layer;

[0018] forming a second barrier layer pattern on the first barrier layer pattern;

[0019] Performing ion implantation on the area where the first ion implantation area is located and the bottom of the first trench to form a first ion implantation area and a second ion implantation area;

[0020] forming a passivation layer in a terminal region of the epitaxial layer;

[0021] etching away the first barrier layer pattern and the second barrier layer pattern located in the main junction region of the epitaxial layer;

[0022] forming a second barrier metal layer on a side of the epitaxial layer away from the substrate, and forming a first barrier metal layer on a sidewall of the first trench;

[0023] forming an anode layer on the second barrier metal layer; and

[0024] A cathode layer is formed on a side of the substrate away from the epitaxial layer.

[0025] Optionally, in the step of forming a second barrier layer pattern on the first barrier layer pattern, a second barrier layer is deposited on the first barrier layer pattern and the second barrier layer is etched so that the second barrier layer pattern located on the sidewalls of the first trench and the sidewalls of the region where the first ion implantation region is located is retained.

[0026] The beneficial effects of the embodiments of the present application are as follows: the embodiments of the present application set a first ion implantation region and a first trench having a second ion implantation region in the main junction region, so that a PN junction is formed between the first ion implantation region and the epitaxial layer, and a PN junction is also formed between the bottom of the first trench and the epitaxial layer; moreover, the embodiments of the present application also set a first barrier metal layer on the side wall of the first trench, and set a second barrier metal layer connecting the first barrier metal layer and the first ion implantation region on the epitaxial layer, so that a Schottky junction is formed between the first barrier metal layer and the epitaxial layer on the side, and a Schottky junction is also formed between the second barrier metal layer and the epitaxial layer directly in contact with the bottom.

[0027] Through the above design, when the Schottky diode is in reverse cutoff, the PN junction formed in the first ion implantation region is extended and connected to the PN junction formed at the bottom of the first trench to form a depletion region. This depletion region shields the Schottky barrier, avoiding the disadvantage of high reverse leakage current caused by the Schottky barrier, thereby reducing the leakage level of the Schottky barrier. Therefore, the embodiments of the present application can shield the Schottky barrier in reverse cutoff, reducing the reverse leakage current of the Schottky diode.

[0028] The embodiment of the present application can also use the Schottky junction formed between the first barrier metal layer and the epitaxial layer on the side and the Schottky junction formed between the second barrier metal layer and the epitaxial layer at the bottom. Since the Schottky junctions at these two locations have the characteristics of low barrier height, the forward conduction voltage drop of the Schottky diode is reduced.

[0029] In addition, when the Schottky diode is conducted in the forward direction, the PN junction formed in the first ion implantation region and the PN junction formed at the bottom of the first trench are not conducted, and the forward current flows through the Schottky junction between the second barrier metal layer and the epitaxial layer at the bottom and the Schottky junction between the first barrier metal layer and the epitaxial layer on the side. Since the Schottky between the first barrier metal layer and the epitaxial layer on the side is located on the side wall of the first trench, the forward current is also conducted at the side wall of the first trench, thereby increasing the conduction area of the forward current and further reducing the forward conduction voltage drop of the Schottky diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive work. In the drawings:

[0031] Figure 1 It is a schematic diagram of a Schottky diode with a PN junction;

[0032] Figure 2 It is a schematic diagram of a trench Schottky diode;

[0033] Figure 3 is a schematic diagram of a Schottky diode provided in an embodiment of the present application;

[0034] Figure 4 is a schematic diagram of another Schottky diode provided in an embodiment of the present application;

[0035] Figure 5 yes Figure 4 A magnified schematic diagram of point A in the middle;

[0036] Figure 6 This is a schematic diagram of the current flow through a Schottky diode when it is conducting in the forward direction.

[0037] Figure 7 This is a schematic diagram of the depletion region of a Schottky diode in reverse cutoff;

[0038] Figure 8 is a schematic diagram of another Schottky diode provided in an embodiment of the present application;

[0039] Figure 9 This is a flow chart of a method for manufacturing a Schottky diode provided in an embodiment of the present application.

[0040] Among them, 10, Schottky diode; 11, barrier layer; 12, ion implantation region; 13, trench; 14, polysilicon layer; 15, insulating layer; 100, substrate; 200, epitaxial layer; 210, main junction region; 220, terminal region; 300, cathode layer; 400, first ion implantation region; 500, first trench; 510, second ion implantation region; 520, first barrier metal layer; 530, metal block; 531, first metal layer; 532, second metal layer; 533, third metal layer; 600, second barrier metal layer; 700, anode layer; 800, second trench; 810, isolation layer; 820, third ion implantation region; 900, passivation layer. DETAILED DESCRIPTION

[0041] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative. However, the present application can be implemented in many alternative forms and should not be construed as being limited to the embodiments described herein.

[0042] In addition, unless otherwise expressly specified or limited, the terms "connected" and "connection" should be understood in a broad sense, and may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0043] Since the lower the Schottky barrier height in the Schottky diode, the smaller the on-state voltage drop, the greater the reverse leakage current. In order to reduce the reverse leakage current of the Schottky diode and increase the service life of the Schottky diode, the present application provides a Schottky diode with a PN junction, such as Figure 1As shown, the Schottky diode 10 includes a cathode layer 300, a substrate 100, and an epitaxial layer 200, which are arranged in sequence from bottom to top. The substrate 100 is a first high-concentration doped layer, and the epitaxial layer 200 is a first low-concentration doped layer. On the side of the epitaxial layer 200 away from the substrate 100, multiple ion implantation regions 12 are formed on the epitaxial layer 200 by ion implantation. Then, a barrier layer 11 is formed on the surface of the epitaxial layer 200, an anode layer 700 is formed on the barrier layer 11, and a passivation layer 900 is formed on the surface of the epitaxial layer 200 except for the barrier layer 11. The first high-concentration doped layer is an N-type high-concentration doped layer, the first low-concentration doped layer is an N-type low-concentration doped layer, and the ion implantation region 12 is a P-type ion implantation region. Conversely, it is also feasible that the first high-concentration doped layer is a P-type high-concentration doped layer, the first low-concentration doped layer is a P-type low-concentration doped layer, and the ion implantation region 12 is an N-type ion implantation region.

[0044] Through the above design, a PN junction is formed between the ion implantation region 12 and the epitaxial layer 200, and a Schottky junction is formed between the barrier layer 11 and the epitaxial layer 200. Due to the diffusion movement of free electrons and the drift movement caused by the internal electric field, a very thin charge region, namely the depletion region (also called the space charge region), is formed in the middle of the PN junction. When the Schottky diode 10 is in reverse cutoff, the PN junction expands, so that the depletion regions formed between adjacent PN junctions are connected, resulting in shielding the Schottky junction formed between the barrier layer 11 and the epitaxial layer 200. As a result, the Schottky junction is inoperative when the Schottky diode 10 is in reverse cutoff, thereby avoiding the problem of increased reverse leakage current.

[0045] Although the Schottky barrier height is low, the Schottky barrier can be used to reduce the on-state voltage drop, but when Figure 1 When the Schottky diode 10 is forward-conducting, the PN junction does not participate in the forward conduction, thereby reducing the surface conduction area of the Schottky diode 10. However, an excessively large area of the ion implantation region 12 increases the conduction voltage drop. Furthermore, the increased diffusion depth of the PN junction causes the ion implantation region 12 to diffuse more laterally, further reducing the surface conduction area of the Schottky diode 10. This prevents the PN junction from increasing in depth, thereby reducing the reverse voltage and thus reducing the reverse leakage current.

[0046] The present application also provides a trench type Schottky diode, wherein the Schottky diode is specifically a trench MOS Schottky (trench MOS barrier SKY, TMBS), such as Figure 2As shown, the Schottky diode 10 includes a cathode layer 300, a substrate 100, and an epitaxial layer 200, arranged sequentially from bottom to top. The substrate 100 is a first high-concentration doped layer, and the epitaxial layer 200 is a first low-concentration doped layer. Multiple trenches 13 are provided on the epitaxial layer 200 on a side away from the substrate 100. An insulating layer 15 made of an insulating material is provided on the sidewalls and bottom of the trenches 13. A polysilicon layer 14 is filled in the trenches 13. The top of the polysilicon layer 14 is flush with the top of the epitaxial layer 200. The insulating layer 15 separates the polysilicon layer 14 from the epitaxial layer 200. A barrier layer 11 is then formed on the surface of the epitaxial layer 200. An anode layer 700 is formed on the surface of the barrier layer 11. A passivation layer 900 is formed on the surface of the epitaxial layer 200, excluding the barrier layer 11.

[0047] Among them, the first high-concentration doping layer is an N-type high-concentration doping layer, and the first low-concentration doping layer is an N-type low-concentration doping layer; conversely, it is also feasible that the first high-concentration doping layer is a P-type high-concentration doping layer and the first low-concentration doping layer is a P-type low-concentration doping layer.

[0048] pass Figure 2 In the design, a MOS barrier is formed between the polysilicon layer 14 and the barrier layer 11, and a Schottky junction is formed between the epitaxial layer 200 and the barrier layer 11. When the Schottky diode 10 is in reverse cutoff mode, the depletion regions between the MOS barriers in adjacent trenches 13 are connected, thereby shielding the Schottky junction formed between the epitaxial layer 200 and the barrier layer 11. This renders the Schottky junction inoperative during reverse cutoff, thereby avoiding the problem of increased reverse leakage current.

[0049] Currently, the on-state voltage drop can be reduced by using a Schottky junction with a lower barrier height and reducing the resistivity of the epitaxial wafer. However, because the sidewalls and bottom of the trench 13 are covered with the insulating layer 15, the trench 13 does not participate in the forward conduction, thereby reducing the conduction area on the surface of the epitaxial layer 200. However, the large area of the trench 13 actually increases the on-state voltage drop. At the same time, when conducting at the same reverse voltage, the depletion region of the MOS barrier in the trench 13 expands less than the depletion region of the PN junction, and the Schottky barrier region requires a smaller spacing. This results in a reduction in the surface conduction area of the Schottky diode 10, which in turn increases the forward conduction voltage drop.

[0050] In order to reduce the forward conduction voltage drop and the reverse leakage current so that the Schottky diode 10 can achieve an ultra-low voltage drop effect, the embodiment of the present application provides a Schottky diode 10, such as Figure 3As shown, the Schottky diode 10 includes a substrate 100, an epitaxial layer 200, a cathode layer 300, a plurality of first ion implantation regions 400, a plurality of first trenches 500, a second barrier metal layer 600 and an anode layer 700. The substrate 100 is a first high-concentration doped layer, which is specifically obtained by high-concentration doping of a silicon wafer; the epitaxial layer 200 is arranged on the substrate 100, and the epitaxial layer 200 is a first low-concentration doped layer, which is specifically obtained by low-concentration doping of the other side of the silicon wafer, or bonding two doped silicon wafers to obtain a substrate 100 and epitaxial layer 200 structure.

[0051] The epitaxial layer 200 is divided into a main junction area 210 and a terminal area 220. The main junction area 210 and the terminal area 220 are arranged in parallel. It can be understood that the main junction area 210 is the core area of the Schottky diode 10, and the terminal area 220 is the area in the Schottky diode 10 used to protect the main junction area 210 to prevent the voltage from being concentrated in the main junction area 210 and causing the main junction area 210 to be broken down.

[0052] The cathode layer 300 can be made of conductive metal material and is arranged on the side of the substrate 100 away from the epitaxial layer 200; a plurality of first ion implantation regions 400 are arranged in the main junction region 210, and a PN junction is formed between the first ion implantation region 400 and the adjacent epitaxial layer 200 portion; a plurality of first trenches 500 are also arranged in the main junction region 210, and the first ion implantation region 400 and the first trench 500 are arranged in parallel. It can be understood that the first ion implantation region 400 and the first trench 500 are both located on the same side of the epitaxial layer 200, and the first ion implantation region 400 and the first trench 500 are spaced apart from each other.

[0053] In which, a second ion implantation region 510 is provided at the bottom of the first trench 500, and a PN junction is also formed between the second ion implantation region 510 and a portion of the adjacent epitaxial layer 200, and a first barrier metal layer 520 is provided on the sidewall of the first trench 500, and the first barrier metal layer 520 is connected to the second ion implantation region 510; the second barrier metal layer 600 is arranged on the side of the epitaxial layer 200 away from the substrate 100, located in the main junction region 210, and the second barrier metal layer 600 is also connected to the first ion implantation region 400 and the first barrier metal layer 520 at the same time; the anode layer 700 can be made of conductive metal material and is arranged on the second barrier metal layer 600.

[0054] Among them, the first high-concentration doped layer is an N-type high-concentration doped layer, the first low-concentration doped layer is an N-type low-concentration doped layer, the first ion implantation area 400 is a P-type ion implantation area, and the second ion implantation area 510 is also a P-type ion implantation area; conversely, the first high-concentration doped layer is a P-type high-concentration doped layer, the first low-concentration doped layer is a P-type low-concentration doped layer, the first ion implantation area 400 is an N-type ion implantation area, and the second ion implantation area 510 is an N-type ion implantation area is also feasible.

[0055] In the embodiment of the present application, a first ion implantation region 400 and a first trench 500 having a second ion implantation region 510 are provided in the main junction region 210, so that a PN junction is formed between the first ion implantation region 400 and the epitaxial layer 200, and a PN junction is also formed between the bottom of the first trench 500 and the epitaxial layer 200; moreover, in the embodiment of the present application, a first barrier metal layer 520 is provided on the side wall of the first trench 500, and a second barrier metal layer 600 connecting the first barrier metal layer 520 and the first ion implantation region 400 is provided on the epitaxial layer 200, so that a Schottky junction is formed between the first barrier metal layer 520 and the epitaxial layer 200 on the side, and a Schottky junction is also formed between the second barrier metal layer 600 and the epitaxial layer 200 directly in contact with the bottom.

[0056] Combine Figure 3 、 Figure 6 and Figure 7 As shown, Figure 6 The dotted line in the figure represents the direction of the forward current. Through the above design, when the Schottky diode 10 is in reverse cutoff, the PN junction formed by the first ion implantation region 400 is extended and connected to the PN junction formed at the bottom of the first trench 500 to form a depletion region Q. This depletion region Q shields the Schottky barrier, avoiding the disadvantage of high reverse leakage current caused by the Schottky barrier, thereby reducing the leakage level of the Schottky barrier. Therefore, the embodiment of the present application can shield the Schottky barrier during reverse cutoff, reduce the reverse leakage current of the Schottky diode 10, and improve the service life of the Schottky diode 10.

[0057] The embodiment of the present application can also use the Schottky junction formed between the first barrier metal layer 520 and the side epitaxial layer 200 and the Schottky junction formed between the second barrier metal layer 600 and the bottom epitaxial layer 200. Since the Schottky junctions at these two locations have the characteristics of low barrier height, the forward conduction voltage drop of the Schottky diode 10 is reduced.

[0058] In addition, when the Schottky diode 10 is conducted in the forward direction, the PN junction formed at the bottom of the first ion implantation region 400 and the first trench 500 is not conducted, and the forward current flows through the Schottky junction between the second barrier metal layer 600 and the epitaxial layer 200 at the bottom and the Schottky junction between the first barrier metal layer 520 and the epitaxial layer 200 on the side. Since the Schottky junction between the first barrier metal layer 520 and the epitaxial layer 200 on the side is located on the side wall of the first trench 500, the forward current is also conducted at the side wall of the first trench 500, thereby increasing the conduction area of the forward current and further reducing the forward conduction voltage drop of the Schottky diode 10.

[0059] In some embodiments, the depth of the first ion implantation region 400 is lower than the depth of the first trench 500. The first ion implantation region 400 can even be a planar structure, that is, the top of the first ion implantation region 400 is flush with the epitaxial layer 200. Alternatively, the first ion implantation region 400 forms a slightly recessed structure on the surface of the epitaxial layer 200, so that only a PN junction can be formed in the first ion implantation region 400, and a large amount of barrier metal material is prevented from being deposited into the first ion implantation region 400 during the formation of the second barrier metal layer 600, resulting in an increase in the material cost of the barrier metal. The first trench 500 has sufficient depth to accommodate the barrier material to form a Schottky junction.

[0060] In some embodiments, the number of the first ion implantation regions 400 and the number of the first trenches 500 are the same, thereby preventing the conduction area from being affected during forward conduction, thereby affecting the forward conduction voltage drop. Furthermore, the first ion implantation regions 400 and the first trenches 500 are staggered one by one, i.e., there is a first ion implantation region 400 between any two adjacent first trenches 500, and there is a first trench 500 between any two adjacent first ion implantation regions 400. Through the above design, during reverse cutoff, the PN junction formed by the first ion implantation region 400 and the PN junction formed at the bottom of the first trench 500 can form a continuous depletion region, completely shielding the Schottky barrier and reducing the leakage level of the Schottky barrier.

[0061] like Figure 4As shown, in some embodiments, the interior of the first trench 500 is further filled with a metal block 530. The bottom of the metal block 530 is connected to the second ion implantation region 510, the side of the metal block 530 is connected to the first barrier metal layer 520, and the top of the metal block 530 is connected to the second barrier metal layer 600. In this embodiment, by adding the metal block 530 inside the first trench 500, the second barrier metal layer 600 above the first trench 500 is supported to ensure the flatness of the second barrier metal layer 600, thereby preventing electrons and holes from leaking through defects or uneven areas, thereby increasing leakage current. In addition, the metal block 530 can also increase the electrical conduction effect between the second barrier metal layer 600 and the first barrier metal layer 520, as well as the electrical conduction effect between the second barrier metal layer 600 and the second ion implantation region 510.

[0062] Specifically, the metal block 530 adopts a three-layer metal stacking structure, and the metal block 530 specifically includes a first metal layer 531, a second metal layer 532 and a third metal layer 533 stacked in sequence, the first metal layer 531 is connected to the second ion injection area 510, the third metal layer 533 is connected to the second barrier metal layer 600, and the sides of the first metal layer 531, the second metal layer 532 and the third metal layer 533 are connected to the first barrier metal layer 520; the first metal layer 531 adopts metal titanium material, the second metal layer 532 adopts metal nickel material, the third metal layer 533 adopts metal silver material, and the first barrier metal layer 520 and the second barrier metal layer 600 both adopt titanium silicide material. By adopting a layered design for the metal block 530 and a material design for the three metal layers, it is possible to create smaller stresses between the first metal layer 531 and the second metal layer 532, between the second metal layer 532 and the third metal layer 533, between the third metal layer 533 and the second barrier metal layer 600, and between the first barrier metal layer 520 and other metal structures, thereby avoiding defects such as voids between the film layers during heating.

[0063] Furthermore, this embodiment uses a low-height barrier instead of a high-height barrier, further reducing the forward voltage drop. Specifically, this embodiment uses a first barrier metal layer 520 and a second barrier metal layer 600 made of titanium. Compared to barrier metal materials such as nickel or platinum, this embodiment achieves a significantly reduced forward voltage drop while minimizing the increase in reverse leakage current.

[0064] In addition, the first barrier metal layer 520 and the second barrier metal layer 600 may be formed through a simultaneous process to improve process efficiency.

[0065] Of course, in other embodiments, the metal block 530 may also be made of a single metal material, or may be designed with only two or more stacked metal layers.

[0066] In some embodiments, the first barrier metal layer 520 located on the side wall of the first trench 500 can adopt a larger width so that the first barrier metal layer 520 and the second barrier metal layer 600 have a larger contact area without affecting the conductive effect. At this time, the metal block 530 can be omitted from the first trench 500.

[0067] like Figure 5 As shown, in some embodiments, the depth d and width S of the first ion implantation region 400 are both less than 0.5um, the depth D of the first groove 500 is 1.5um-3um, the width M of the first groove 500 is 0.5um-2um, and the spacing P between the first ion implantation region 400 and the first groove 500 is 1.5um-2.5um.

[0068] In this embodiment, since the width S of the first ion implantation region 400 and the width M of the first trench 500 are both inactive regions, they need to be as small as possible to increase the surface Schottky region width per unit area (i.e., the spacing P between the first ion implantation region 400 and the first trench 500). Through experimental calculation and analysis, the inventors found that, while meeting process requirements and performance, by reducing the width S of the first ion implantation region 400 to less than 0.5 μm and reducing the width M of the first trench 500 to 0.5 μm-2 μm, the spacing P between the first ion implantation region 400 and the first trench 500 can achieve the ideal effect, i.e., 1.5 μm-2.5 μm, thereby meeting the surface Schottky region width per unit area.

[0069] The greater the depth D of the first trench 500, the larger the forward conduction area of the sidewall of the first trench 500 and the lower the voltage drop. However, too great a depth will lead to a decrease in the reverse cutoff voltage. Based on these two considerations, in this embodiment, the depth D of the first trench 500 is set to 1.5um-3um, so that the forward conduction area is larger and the reverse cutoff voltage is avoided from being reduced.

[0070] As a further embodiment, the depth of the first ion implantation region 400 is 0, the width of the first ion implantation region 400 is 0.5um, the depth of the first groove 500 is 1.5um, the width of the first groove 500 is 0.8um, and the distance between the first ion implantation region 400 and the first groove 500 is 2um.

[0071] like Figure 8As shown, in some embodiments, the Schottky diode 10 further includes a second trench 800, an isolation layer 810 and a passivation layer 900, the second trench 800 is arranged in the terminal area 220, a third ion implantation area 820 is provided at the bottom of the second trench 800, and the isolation layer 810 is arranged on the sidewall of the second trench 800 and the third ion implantation area 820; the passivation layer 900 is arranged on the side of the epitaxial layer 200 away from the substrate 100, located in the terminal area 220, and the orthographic projection of the passivation layer 900 on the substrate 100 does not overlap with the orthographic projection of the second trench 800 on the substrate 100.

[0072] In this embodiment, a PN junction is formed between the third ion implantation region 820 and the epitaxial layer 200, so that the bottom of the second trench 800 also has a PN junction to ensure that the voltage does not drop, avoiding the accumulation of an electric field on the surface of the main junction region 210, which may lead to the risk of breakdown of the main junction region 210.

[0073] Moreover, the isolation layer 810 and the passivation layer 900 may be formed by a simultaneous process to improve the process efficiency of the Schottky diode 10 .

[0074] like Figure 9 As shown, the embodiment of the present application further provides a method for manufacturing a Schottky diode, which is used to manufacture the Schottky diode as described above, and the manufacturing method includes the steps of:

[0075] S1: Select a silicon wafer, wherein the silicon wafer has a first high-concentration doped substrate and a first low-concentration doped epitaxial layer;

[0076] S2: forming a first barrier layer pattern on the epitaxial layer;

[0077] S3: etching the epitaxial layer to form a plurality of first trenches in the main junction region of the epitaxial layer;

[0078] S4: processing the pattern of the first barrier layer to expose the area where the first ion implantation area is located on the main junction area of the epitaxial layer;

[0079] S5: forming a second barrier layer pattern on the first barrier layer pattern;

[0080] S6: performing ion implantation on the area where the first ion implantation area is located and the bottom of the first trench to form a first ion implantation area and a second ion implantation area;

[0081] S7: forming a passivation layer in the terminal region of the epitaxial layer;

[0082] S8: etching away the first barrier layer pattern and the second barrier layer pattern located in the main junction region of the epitaxial layer;

[0083] S9: forming a second barrier metal layer on a side of the epitaxial layer away from the substrate, and forming a first barrier metal layer on a sidewall of the first trench;

[0084] S10: forming an anode layer on the second barrier metal layer;

[0085] S11: forming a cathode layer on a side of the substrate away from the epitaxial layer.

[0086] The above method can not only quickly produce a Schottky diode, but also the produced Schottky diode has the characteristics of very small reverse leakage current, good performance and long service life.

[0087] As a specific example, when a 50V Schottky diode is used, in step S1, the total thickness of the silicon wafer is 625um, the height of the epitaxial layer is 6um, and the resistivity of the silicon wafer is 0.6Ω.cm; wherein, the first high-concentration doping is N-type high-concentration doping, the first low-concentration doping is N-type low-concentration doping, and the doping is phosphorus ions, of course, it can also be arsenic ions or antimony ions.

[0088] In step S2, a first barrier layer composed of silicon dioxide is first deposited on the side of the epitaxial layer away from the substrate. The thickness of the first barrier layer can be 0.5um. Then, the first barrier layer is etched to obtain a first barrier layer pattern. The first barrier layer pattern exposes the area where the first groove is located on the epitaxial layer. Of course, the area where the second groove of the terminal area is located can also be exposed at the same time.

[0089] In step S3 , the area not blocked by the first barrier layer pattern may be etched by photolithography to form a first trench and a second trench with a depth of 1.5 μm on the epitaxial layer.

[0090] In step S5, a second barrier layer is first deposited as a whole layer. The second barrier layer is made of Si3N4 material and has a thickness of 0.2 μm. Furthermore, when etching the second barrier layer, the second barrier layer pattern is retained on the sidewalls of the first trench and the sidewalls of the region where the first ion implantation region is located. This narrows the width of the first trench and the first ion implantation region, which is beneficial to the continuity of the depletion region.

[0091] In step S6, boron ions are implanted into the area where the first ion implantation region is located and the bottom of the first trench at an ion implantation energy of 100 KeV. An annealing process is then performed at 900 degrees Celsius for 30 minutes to form a PN junction. While implanting boron ions into the area where the first ion implantation region is located and the bottom of the first trench, boron ions can also be implanted into the bottom of the second trench to reduce process time.

[0092] In step S7, a 1µm thick passivation structure composed of silicon dioxide is deposited directly on the entire epitaxial layer. The passivation structure in the main junction region is then etched away, leaving a passivation layer located only in the terminal region. The first and second barrier layer patterns are then etched away, leaving only the first ion implantation region and the first trench in the main junction region, as well as the second ion implantation region at the bottom of the first trench. It should be noted that the first and second barrier layer patterns are etched using different process methods. Furthermore, the passivation structure can be etched simultaneously with the first barrier layer pattern to improve process efficiency.

[0093] In step S9, the first barrier metal layer and the second barrier metal layer are made of the same material, both of which are formed by first depositing titanium metal and then annealing to form silicide, namely titanium silicide; since the first barrier metal layer and the second barrier metal layer are formed in a synchronous process, the process time is further reduced.

[0094] The Schottky diode prepared using this example has a reverse breakdown voltage of over 56 V, a reverse leakage current of 30 microamperes, and a forward conduction voltage drop that is 20% lower than that of the trench MOS Schottky structure. It can be seen that the Schottky diode provided in the embodiment of the present application can significantly reduce the forward conduction voltage drop.

[0095] It should be noted that the limitations on the various steps involved in this solution do not limit the order of the steps without affecting the implementation of the specific solution. The steps written in front can be executed first, later, or even simultaneously. The solutions of different embodiments can be combined and applied without conflict. As long as this solution can be implemented, it should be regarded as falling within the scope of protection of this application.

[0096] The above content is a further detailed description of the present application in conjunction with specific optional implementation methods, and the specific implementation of the present application cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, they can make several simple deductions or substitutions without departing from the concept of the present application, which should be considered to fall within the scope of protection of the present application.

Claims

1. A Schottky diode, characterized in that: include: a substrate, wherein the substrate is a first high-concentration doped layer; an epitaxial layer, the epitaxial layer being disposed on the substrate and being a first low-concentration doped layer; wherein the epitaxial layer is divided into a main junction region and a terminal region, the main junction region and the terminal region being disposed in parallel; a cathode layer, disposed on a side of the substrate away from the epitaxial layer; a plurality of first ion implantation regions, arranged in the main junction region, wherein a PN junction is formed between the first ion implantation region and the epitaxial layer; A plurality of first trenches are provided in the main junction region, the first ion implantation region and the first trenches are arranged in parallel, a second ion implantation region is provided at the bottom of the first trench, a PN junction is formed between the second ion implantation region and the epitaxial layer; and a first barrier metal layer is provided on the sidewall of the first trench, the first barrier metal layer is connected to the second ion implantation region; a second barrier metal layer, disposed on a side of the epitaxial layer away from the substrate, located in the main junction region, and connected to the first ion implantation region and the first barrier metal layer; and The anode layer is arranged on the second barrier metal layer.

2. The Schottky diode according to claim 1, wherein: The Schottky diode further includes a second trench, an isolation layer, and a passivation layer, wherein the second trench is provided in the terminal region, a third ion implantation region is provided at the bottom of the second trench, and the isolation layer is provided on the sidewalls of the second trench and the third ion implantation region; The passivation layer is arranged on a side of the epitaxial layer away from the substrate and located in the terminal region, and an orthographic projection of the passivation layer on the substrate does not overlap with an orthographic projection of the second trench on the substrate.

3. The Schottky diode according to claim 2, wherein: The isolation layer and the passivation layer are formed by a simultaneous process.

4. The Schottky diode according to claim 1, wherein: The first ion implantation region is a planar structure.

5. The Schottky diode according to claim 1, wherein: The first trench is filled with a metal block, the bottom of the metal block is connected to the second ion implantation region, the side of the metal block is connected to the first barrier metal layer, and the top of the metal block is connected to the second barrier metal layer.

6. The Schottky diode according to claim 5, wherein: The metal block includes a first metal layer, a second metal layer, and a third metal layer stacked in sequence, the first metal layer is connected to the second ion implantation region, the third metal layer is connected to the second barrier metal layer, and the side surfaces of the first metal layer, the second metal layer, and the third metal layer are connected to the first barrier metal layer; The first metal layer is made of titanium, the second metal layer is made of nickel, the third metal layer is made of silver, and both the first barrier metal layer and the second barrier metal layer are made of titanium silicide.

7. The Schottky diode according to claim 1, wherein: The depth and width of the first injection region are both less than 0.5um, the depth of the first groove is 1.5um-3um, the width of the first groove is 0.5um-2um, and the distance between the first ion injection region and the first groove is 1.5um-2.5um.

8. The Schottky diode according to claim 1, wherein: The number of the first ion implantation regions and the number of the first trenches are the same, and the first ion implantation regions and the first trenches are staggered one by one.

9. A method for manufacturing a Schottky diode, for manufacturing the Schottky diode according to any one of claims 1 to 8, characterized in that: The production method comprises the steps of: Selecting a silicon wafer, wherein the silicon wafer has a first high-concentration doped substrate and a first low-concentration doped epitaxial layer; forming a first barrier layer pattern on the epitaxial layer; Etching the epitaxial layer to form a plurality of first trenches in the main junction region of the epitaxial layer; Processing the pattern of the first barrier layer to expose the area where the first ion implantation area is located on the main junction area of the epitaxial layer; forming a second barrier layer pattern on the first barrier layer pattern; Performing ion implantation on the area where the first ion implantation area is located and the bottom of the first trench to form a first ion implantation area and a second ion implantation area; forming a passivation layer in a terminal region of the epitaxial layer; etching away the first barrier layer pattern and the second barrier layer pattern located in the main junction region of the epitaxial layer; forming a second barrier metal layer on a side of the epitaxial layer away from the substrate, and forming a first barrier metal layer on a sidewall of the first trench; forming an anode layer on the second barrier metal layer; as well as A cathode layer is formed on a side of the substrate away from the epitaxial layer.

10. The method for manufacturing a Schottky diode according to claim 9, wherein: In the step of forming a second barrier layer pattern on the first barrier layer pattern, a second barrier layer is deposited on the first barrier layer pattern and etched so that the second barrier layer pattern located on the sidewalls of the first trench and the sidewalls of the region where the first ion implantation region is located is retained.

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