Semiconductor device

Abstract

A semiconductor device includes: a substrate including a fin-type active region and a device spacer layer configured to cover both sidewalls of the fin-type active region; a pair of nanosheet stacks, each nanosheet stack including a lower nanosheet stack disposed on the fin-type active region and an upper nanosheet stack disposed on the lower nanosheet stack; an intermediate insulating layer disposed between the lower nanosheet stack and the upper nanosheet stack; a nanosheet partition wall disposed between the pair of nanosheet stacks and extending in a first horizontal direction; and a pair of gate lines extending in a second horizontal direction on the pair of nanosheet stacks, in which nanosheet partition walls separate respective lower nanosheet stacks of the pair of nanosheet stacks from each other in the second horizontal direction.

Description

Technical Field

[0001] The present disclosure provides a semiconductor device. Background Art

[0002] Due to the development of electronic technology, the demand for high-integration semiconductor devices is increasing, and semiconductor device scaling is ongoing. This scaling can lead to short-channel effects in transistors, which can reduce the reliability of integrated circuit devices. To reduce short-channel effects, multi-gate semiconductor devices, such as nanosheet transistors, have been proposed. Summary of the Invention

[0003] Some aspects of the present disclosure provide semiconductor devices with improved operating characteristics.

[0004] According to some implementations of the present disclosure, a semiconductor device is provided, comprising: a substrate including a fin-type active area and a device separation layer configured to cover two sidewalls of the fin-type active area; a pair of nanosheet stacks, each including a lower nanosheet stack arranged on the fin-type active area and an upper nanosheet stack arranged on the lower nanosheet stack; an intermediate insulating layer arranged between the lower nanosheet stack and the upper nanosheet stack; a nanosheet separation wall arranged between the pair of nanosheet stacks and extending in a first horizontal direction; and a pair of gate lines extending in a second horizontal direction on the pair of nanosheet stacks, wherein the nanosheet separation wall separates the corresponding lower nanosheet stacks in the pair of nanosheet stacks from each other in the second horizontal direction.

[0005] According to some implementations of the present disclosure, a semiconductor device is provided, which includes: a substrate including a fin-type active area and a device separation layer configured to cover two sidewalls of the fin-type active area; a pair of nanosheet stacks, each including a lower nanosheet stack arranged on the fin-type active area and an upper nanosheet stack arranged on the lower nanosheet stack; an intermediate insulating layer arranged between the lower nanosheet stack and the upper nanosheet stack; a nanosheet separation wall arranged between the pair of nanosheet stacks and extending in a first horizontal direction; a gate separation spacer arranged on one sidewall of the two sidewalls of each upper nanosheet stack respectively included in the pair of nanosheet stacks, which is relatively far away from the nanosheet separation wall in a second horizontal direction; and a pair of gate lines extending in a second horizontal direction on the pair of nanosheet stacks, wherein the nanosheet separation wall separates the lower nanosheet stacks included in the pair of nanosheet stacks from each other in the second horizontal direction.

[0006] According to some embodiments of the present disclosure, a semiconductor device is provided, comprising: a substrate comprising a fin-type active region and a device separation layer, the device separation layer being configured to cover two sidewalls of the fin-type active region and being arranged in a device separation trench; a pair of nanosheet stacks, each comprising a lower nanosheet stack arranged on the fin-type active region and an upper nanosheet stack arranged on the lower nanosheet stack; an intermediate insulating layer arranged between the lower nanosheet stack and the upper nanosheet stack; a nanosheet separation wall arranged between the pair of nanosheet stacks and extending in a first horizontal direction; a residual insulating material arranged on a lower end edge of a sidewall of the device separation trench adjacent to the pair of nanosheet stacks in a second horizontal direction; a gate separation spacer arranged between each upper nanosheet stack respectively included in the pair of nanosheet stacks; on one of the two side walls that is relatively far away from the nanosheet separation wall in the second horizontal direction; a pair of gate lines extending in the second horizontal direction on the pair of nanosheet stacks and comprising a first metal layer, a second metal layer and a third metal layer; and a gate cutting structure comprising a first gate cutting structure configured to separate the upper nanosheet stacks included in the pair of nanosheet stacks from each other in the second horizontal direction and a second gate cutting structure configured to separate another pair of nanosheet stacks adjacent to the pair of nanosheet stacks from the pair of nanosheet stacks in the second horizontal direction, wherein the nanosheet separation wall separates the lower nanosheet stacks respectively included in the pair of nanosheet stacks from each other in the second horizontal direction, and the third metal layer comprises a lower gate metal layer and an upper gate metal layer separated from each other by a gate separation spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The foregoing and other embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a schematic top view of an example of a semiconductor device according to some implementations;

[0009] Figure 2A It is along Figure 1 A cross-sectional view of the semiconductor device taken along line X1-X1';

[0010] Figure 2B It is along Figure 1 A cross-sectional view of the semiconductor device taken along line Y1-Y1';

[0011] Figure 3 is a cross-sectional view of an example of a semiconductor device according to some implementations;

[0012] Figure 4 is a cross-sectional view of an example of a semiconductor device according to some implementations; and

[0013] Figures 5A to 26D is a cross-sectional view illustrating an example of a method of manufacturing a semiconductor device according to some implementations. DETAILED DESCRIPTION

[0014] Hereinafter, examples are described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same constituent elements, and repeated descriptions thereof are omitted.

[0015] Figure 1 is a schematic top view of a semiconductor device 100 according to some implementations. Figure 2A It is along Figure 1 1 is a cross-sectional view of the semiconductor device 100 taken along line X1 - X1 ′ in FIG. Figure 2B It is along Figure 1 1 is a cross-sectional view of the semiconductor device 100 taken along line Y1 - Y1 ′ in FIG.

[0016] Reference Figure 1 、 Figure 2A and Figure 2B The semiconductor device 100 may include a substrate 102 having a fin-type active area FA, a plurality of gate lines GL, a plurality of nanosheet stacks NSS, and a plurality of nanosheet partition walls 122 .

[0017] The semiconductor device 100 may include a plurality of logic cells. Each of the plurality of logic cells may include a plurality of circuit elements (such as transistors and registers) and may be configured in various ways. The logic cells may constitute, for example, an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, an XNOR gate, an inverter (INV), an adder (ADD), a buffer (BUF), a delay (DLY), a filter (FIL), a multiplexer (MXT / MXIT), an OR / AND INV (OAI), an AND / OR (AO) INV (AOI), a D flip-flop, a reset flip-flop, a master-slave flip-flop, a latch, etc., and may constitute a standard unit that performs a logic function.

[0018] Substrate 102 may include a Group IV semiconductor (such as silicon (Si) and germanium (Ge)), a Group IV-IV compound semiconductor (such as silicon germanium (SiGe) and silicon carbide (SiC)), or a Group III-V compound semiconductor (such as gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The terms "SiGe," "SiC," "GaAs," "InAs," and "InP," etc., used herein, refer to materials containing the elements included in each term, but do not indicate a stoichiometric relationship. Substrate 102 may include a conductive region, such as an impurity-doped well or impurity-doped structure.

[0019] The device separation layer 112 may be formed in a device separation layer trench 112T formed in the substrate 102. The device separation layer 112 may cover both sidewalls of the fin-type active area FA. The device separation layer 112 may include, for example, an oxide layer, a nitride layer, or a combination thereof. The residual insulating material 124 may be disposed at the lower edges of both sidewalls of the device separation layer trench 112T adjacent to the nanosheet stack NSS in the second horizontal direction (Y direction). The residual insulating material 124 may include the following reference to Figure 5A 、 Figure 5B 、 Figure 6A and Figure 6B The material that is not removed and remains during the formation process of the nano-sheet partition walls 122 is described. Therefore, the residual insulating material 124 may substantially include the same material as the nano-sheet partition walls 122.

[0020] The fin type active regions FA may protrude in a vertical direction (Z direction) from an upper surface of the substrate 102. The fin type active regions FA may extend parallel to each other in a first horizontal direction (X direction).

[0021] The plurality of gate lines GL may extend parallel to one another on the fin active area FA in a second horizontal direction (Y direction). The plurality of nanosheet stacks NSS may be arranged on the fin active area FA in a region where the fin active area FA and the plurality of gate lines GL intersect. The plurality of nanosheet stacks NSS may be arranged to form rows and columns in a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0022] Each of the plurality of nanosheet stacks NSS may include a lower nanosheet stack NSSb disposed on the fin-type active area FA and an upper nanosheet stack NSSb disposed on the lower nanosheet stack NSSb. The lower nanosheet stack NSSb may include a first nanosheet Nb1 and a second nanosheet Nb2 sequentially stacked on the fin-type active area FA, and the upper nanosheet stack NSSb may include a third nanosheet Nt1 and a fourth nanosheet Nt2 sequentially stacked on the lower nanosheet stack NSSb. The first nanosheet Nb1, the second nanosheet Nb2, the third nanosheet Nt1, and the fourth nanosheet Nt2 may each include a Group IV semiconductor (such as Si and Ge), a Group IV-IV compound semiconductor (such as SiGe and SiC), or a Group III-V compound semiconductor (such as GaAs, InAs, and InP). Each of the first nanosheet Nb1, the second nanosheet Nb2, the third nanosheet Nt1, and the fourth nanosheet Nt2 may include a channel region (not shown). In some implementations, the first nanosheet Nb1, the second nanosheet Nb2, the third nanosheet Nt1, and the fourth nanosheet Nt2 have substantially the same thickness in the vertical direction (Z direction). In some implementations, at least some of the first nanosheet Nb1, the second nanosheet Nb2, the third nanosheet Nt1, and the fourth nanosheet Nt2 have different thicknesses in the vertical direction (Z direction).

[0023] exist Figure 2A and Figure 2B , each of the lower nanosheet stack NSSb and the upper nanosheet stack NSSt is shown as including two nanosheets, but the number of nanosheets is not limited thereto. For example, each of the lower nanosheet stack NSSb and the upper nanosheet stack NSSt may include one, three, or more than three nanosheets.

[0024] In some implementations, each of the first nanosheet Nb1, second nanosheet Nb2, third nanosheet Nt1, and fourth nanosheet Nt2 included in the lower nanosheet stack NSSb and the upper nanosheet stack NSSt has the same size in a first horizontal direction (X direction). In some implementations, at least some of the first nanosheet Nb1, second nanosheet Nb2, third nanosheet Nt1, and fourth nanosheet Nt2 included in the lower nanosheet stack NSSb and the upper nanosheet stack NSSt have different sizes from one another in the first horizontal direction (X direction). For example, in the first horizontal direction (X direction), the length of each of the first nanosheet Nb1 and the second nanosheet Nb2, the third nanosheet Nt1, and the fourth nanosheet Nt2, which are relatively close to the upper surface of the fin active area FA, can be shorter than the length of the third nanosheet Nt1 and the fourth nanosheet Nt2, which are relatively far from the upper surface of the fin active area FA.

[0025] The intermediate insulating layer MDI may be disposed between the lower nano-sheet stack NSSb and the upper nano-sheet stack NSSt. The intermediate insulating layer MDI may include an insulating material.

[0026] The plurality of nanosheet partition walls 122 may extend parallel to one another in a first horizontal direction (X direction). Each of the plurality of nanosheet partition walls 122 may protrude from the upper surface of the substrate 102 in a vertical direction (Z direction). Both sidewalls of each nanosheet partition wall 122 may contact the fin-type active area FA, the lower nanosheet stack NSSb, and the intermediate insulating layer MDI. A pair of nanosheet stacks NSS facing each other in a second horizontal direction (Y direction) may be spaced apart from one another in the second horizontal direction (Y direction) with a nanosheet partition wall 122 therebetween. In some implementations, the lower surface of the nanosheet partition wall 122 is at the same vertical level as the upper surface of the substrate 102. In some implementations, the upper surface of the nanosheet partition wall 122 is at a higher vertical level than the lower surface of the intermediate insulating layer MDI and at a lower vertical level than the upper surface of the intermediate insulating layer MDI. In some implementations, the nanosheet partition wall 122 comprises an insulating material. For example, the insulating material may include SiCN, SiBCN, or a combination thereof.

[0027] A gate spacer 126 may be disposed on one of the two sidewalls of each of a pair of upper nanosheet stacks NSSt that is relatively distant from one nanosheet partition wall 122 in the second horizontal direction (Y direction). The pair of upper nanosheet stacks NSSt are disposed on a pair of lower nanosheet stacks NSSb, which include the one nanosheet partition wall 122 therebetween and are spaced apart from each other in the second horizontal direction (Y direction). The gate spacers 126 may extend parallel to each other in the first horizontal direction (X direction). In some implementations, the lower surface of the gate spacer 126 is at a higher vertical level than the lower surface of the middle insulating layer MDI and at a lower vertical level than the upper surface of the middle insulating layer MDI. In some implementations, the gate spacer 126 is at a higher vertical level than each of the upper surface of the upper gate metal layer GMt and the upper surface of the lower gate metal layer GMb. The upper gate metal layer GMt and the lower gate metal layer GMb may be insulated from each other by the gate spacer 126. In some implementations, the gate spacer 126 comprises an insulating material. The insulating material may include, for example, SiCN, SiBCN, or a combination thereof. In some implementations, the gate spacer 126 comprises substantially the same material as the nanosheet partition wall 122. For example, the gate spacer 126 and the nanosheet partition wall 122 may comprise SiCN.

[0028] The plurality of gate lines GL may include a first gate metal layer 140 b, a second gate metal layer 140 t, and a third gate metal layer GM. The first gate metal layer 140 b (sometimes referred to as "first metal layer 140 b") may be disposed between the fin active area FA and the first nanosheet Nb1, between the first nanosheet Nb1 and the second nanosheet Nb2, and between the second nanosheet Nb2 and the intermediate insulating layer MDI. The second gate metal layer 140 t (sometimes referred to as "second metal layer 140 t") may be disposed between the intermediate insulating layer MDI and the third nanosheet Nt1, and between the third nanosheet Nt1 and the fourth nanosheet Nt2. The third gate metal layer GM (sometimes referred to as "third metal layer GM") may include a lower gate metal layer GMb and an upper gate metal layer GMt. The lower gate metal layer GMb may cover the one sidewall of each of the pair of lower nanosheet stacks NSSb, which includes the one nanosheet partition wall 122 therebetween and is spaced apart from each other in the second horizontal direction (Y direction), out of the two sidewalls. The upper gate metal layer GMt may cover the one sidewall of each of the pair of upper nanosheet stacks NSSt, respectively disposed on the pair of lower nanosheet stacks NSSb, which is relatively close to the one nanosheet partition wall 122 in the second horizontal direction (Y direction), and may cover the upper surface of the fourth nanosheet Nt2. The lower gate metal layer GMb and the upper gate metal layer GMt may be spaced apart from each other in the second horizontal direction (Y direction) with the gate separation spacer 126 therebetween.

[0029] The third metal layer GM may include, for example, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a combination thereof. For example, the third metal layer GM may include Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, or a combination thereof, but is not limited thereto.

[0030] The first metal layer 140b may include a metal doped with a p-type dopant, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a combination thereof. For example, the first metal layer 140b may include Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, or a combination thereof doped with a p-type dopant. The p-type dopant may include, for example, boron (B).

[0031] The second metal layer 140 t may include a metal doped with an n-type dopant, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a combination thereof. For example, the second metal layer 140 t may include Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, or a combination thereof doped with an n-type dopant. The n-type dopant may include, for example, arsenic (As) or phosphorus (P).

[0032] The first metal layer 140b and the lower gate metal layer GMb may constitute a gate connected to a lower nanosheet stack NSSb, and the second metal layer 140t and the upper gate metal layer GMt may constitute another gate connected to an upper nanosheet stack NSSt arranged on the lower nanosheet stack NSSb. Therefore, the lower gate metal layer GMb and the upper gate metal layer GMt may be insulated from each other by the gate separation spacer 126, and the insulated lower gate metal layer GMb and the upper gate metal layer GMt may constitute separate gates.

[0033] First spacers 142b may be disposed on both sidewalls of the first metal layer 140b, and second spacers 142t may be disposed on both sidewalls of the second metal layer 140t. Each of the first spacers 142b and the second spacers 142t may extend parallel to each other in the second horizontal direction (Y direction). Each of the first spacers 142b and the second spacers 142t may include, for example, a nitride (e.g., silicon nitride).

[0034] The gate insulating layer 130 may be disposed between the fin active area FA and the first nanosheet Nb1, between each of the first and second nanosheets Nb1 and Nb2 and the first metal layer 140b, between each of the first and second nanosheets Nb1 and Nb2 and the lower gate metal layer GMb, between the first metal layer 140b and the intermediate insulating layer MDI, between the second metal layer 140t and the intermediate insulating layer MDI, between each of the third and fourth nanosheets Nt1 and Nt2 and the second metal layer 140t, and between each of the third and fourth nanosheets Nt1 and Nt2 and the upper gate metal layer GMt. Furthermore, the gate insulating layer 130 may cover at least a portion of the upper surface of the nanosheet partition wall 122 and at least a portion of the surface of the gate separation spacer 126.

[0035] In some implementations, the gate insulating layer 130 includes a silicon oxide layer, a silicon oxynitride layer, a high-k dielectric layer having a higher dielectric constant than the silicon oxide layer, or a combination thereof. The high-k dielectric layer may include a metal oxide or a metal oxynitride. For example, the high-k dielectric layer may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0036] A gate capping layer 150 may be disposed on the third metal layer GM of the gate line GL. The gate capping layer 150 may cover the upper surface of the third metal layer GM. The gate capping layer 150 may extend on the third metal layer GM in the second horizontal direction (the Y direction). In some implementations, the gate capping layer 150 includes silicon nitride or silicon oxynitride.

[0037] The first gate spacer CLD1 and the second gate spacer CLD2 may be sequentially arranged on both sidewalls of the third metal layer GM and the gate cover layer 150. The first gate spacer CLD1 and the second gate spacer CLD2 may cover both sidewalls of the third metal layer GM and the gate cover layer 150. The first gate spacer CLD1 and the second gate spacer CLD2 may extend in a second horizontal direction (Y direction) on the substrate 102.

[0038] In some implementations, each of the first gate spacer CLD1 and the second gate spacer CLD2 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or a combination thereof.

[0039] The gate-cut structure CT may extend in a first horizontal direction (X direction). The gate-cut structure CT may cut at least a portion of adjacent gate lines GL (e.g., extend between them). The gate-cut structure CT may include a first gate-cut structure CTn and a second gate-cut structure CTw. The first gate-cut structure CTn may penetrate the gate cap layer 150 and the upper gate metal layer GMt to extend in the vertical direction (Z direction). The first gate-cut structure CTn may contact the upper surface of the nanosheet partition wall 122 on its bottom surface. The first gate-cut structure CTn may cut the upper gate metal layer GMt between a pair of upper nanosheet stacks NSSt, respectively disposed on a pair of lower nanosheet stacks NSSb, each including a nanosheet partition wall 122 therebetween and spaced apart in the second horizontal direction (Y direction). The second gate-cut structure CTw may penetrate the gate cap layer 150 and the lower gate metal layer GMb to extend in the vertical direction (Z direction). The second gate-cut structure CTw may contact the upper surface of the device partition layer 112 on its bottom surface. The second gate-cut structure CTw may cut the lower gate metal layer GMb between a pair of nanosheet stacks NSS (e.g., including NSSt and NSSb) and another pair of nanosheet stacks NSS adjacent to the pair of nanosheet stacks NSS. The pair of nanosheet stacks NSS include a nanosheet partition wall 122 and are spaced apart from each other in the second horizontal direction (Y direction). The first gate-cut structure CTn and the second gate-cut structure CTw may include, for example, silicon nitride.

[0040] In some implementations, the second horizontal length of the first gate cutting structure CTn is less than the second horizontal length of the second gate cutting structure CTw. For example, the second horizontal length of the first gate cutting structure CTn may be approximately 5 nm to approximately 10 nm, and the second horizontal length of the second gate cutting structure CTw may be approximately 15 nm to approximately 35 nm.

[0041] The lower source / drain region SDb may be arranged between lower nanosheet stacks NSSb spaced apart from each other in the first horizontal direction (X direction), and the upper source / drain region SDt may be arranged between upper nanosheet stacks NSSt arranged on the lower nanosheet stacks NSSb. The lower source / drain region SDb may extend into the fin-type active area FA. The lower source / drain region SDb may be connected to both ends of the lower nanosheet stack NSSb, and the upper source / drain region SDt may be connected to both ends of the upper nanosheet stack NSSt. In some implementations, the lower source / drain region SDb and the upper source / drain region SDt include, but are not limited to, a doped Si layer, a doped SiGe layer, a doped Ge layer, a doped SiC layer, or a doped InGaAs layer. In some implementations, the lower source / drain region SDb and the upper source / drain region SDt include dopants of different conductivity types. For example, the lower source / drain region SDb may include an n-type dopant, and the upper source / drain region SDt may include a p-type dopant. The lower source / drain region SDb may form an n-type metal oxide semiconductor (NMOS) transistor together with the lower nanosheet stack NSSb, and the upper source / drain region SDt may form a p-type metal oxide semiconductor (PMOS) transistor together with the upper nanosheet stack NSSt.

[0042] The first etch stop layer CESL1 may cover the surface of the lower source / drain region SDb. The second etch stop layer CESL2 (refer to Figure 26D ) may cover the surface of the upper source / drain region SDt. Each of the first etch stop layer CESL1 and the second etch stop layer CESL2 may include, for example, a nitride layer. The first interlayer insulating layer FO1 may be disposed on the first etch stop layer CESL1 and may cover the first etch stop layer CESL1. The second interlayer insulating layer FO2 (refer to Figure 26D ) may be disposed on and cover the second etch stop layer CESL2. Each of the first interlayer insulating layer FO1 and the second interlayer insulating layer FO2 may include, for example, silicon oxide or an insulating material having a lower dielectric constant than silicon oxide. In some implementations, each of the first interlayer insulating layer FO1 and the second interlayer insulating layer FO2 includes a tetraethyl orthosilicate (TEOS) layer or an ultra-low dielectric constant (ULK) layer having an ultra-low dielectric constant K of approximately 2.2 to approximately 2.4. The ULK layer may include a SiOC layer or a SiCOH layer.

[0043] A plurality of gate contacts CB may penetrate the gate cover layer 150 to contact the third metal layer GM of the gate line GL. Each of the plurality of gate contacts CB may include a first gate contact CBb and a second gate contact CBt. The first gate contact CBb may contact the lower gate metal layer GMb, and the second gate contact CBt may contact the upper gate metal layer GMt. The first gate contact CBb may be connected to the gate including the lower gate metal layer GMb and the first metal layer 140b, and the second gate contact CBt may be connected to the gate including the upper gate metal layer GMt and the second metal layer 140t.

[0044] The plurality of source / drain contacts CA may penetrate the second interlayer insulating layer FO2 (refer to Figure 26D ) and / or the first interlayer insulating layer FO1 to contact the upper source / drain region SDt or the lower source / drain region SDb. Each of the plurality of source / drain contacts CA may include a first source / drain contact CAb and a second source / drain contact CAt. The first source / drain contact CAb may penetrate the first interlayer insulating layer FO1 and the second interlayer insulating layer FO2 to contact the lower source / drain region SDb. The second source / drain contact CAt may penetrate the second interlayer insulating layer FO2 to contact the upper source / drain region SDt.

[0045] In some implementations, each of the plurality of gate contacts CB and the plurality of source / drain contacts CA includes a metal, a conductive metal nitride, or a combination thereof. For example, each of the plurality of gate contacts CB and the plurality of source / drain contacts CA may include a metal material (such as W, Al, Cu, Ti, Ta, Ru, Mn, and Co), a metal nitride (such as TiN, TaN, CoN, and WN), or an alloy (e.g., a conductive alloy) (such as cobalt tungsten phosphide (CoWP), cobalt tungsten boron (CoWB), and cobalt tungsten boron phosphide (CoWBP)).

[0046] Contact cutting structure CX (refer to Figure 26D ) may penetrate the second interlayer insulating layer FO2 and may contact the upper surface of the first interlayer insulating layer FO1. The second source / drain contacts CAt may be horizontally spaced apart from each other with the contact cut structure CX therebetween. The contact cut structure CX may include, for example, silicon nitride.

[0047] The semiconductor device 100 may include a nanosheet partition wall 122 disposed between a pair of nanosheet stacks NSS and gate separation spacers 126 disposed on both sidewalls of the pair of nanosheet stacks NSS. The pair of nanosheet stacks NSS may be separated from each other by the nanosheet partition wall 122 to improve parasitic capacitance of the semiconductor device 100. Furthermore, since the upper gate metal layer GMt is separated by the gate separation spacer 126, each of the lower nanosheet stack NSSb and the upper nanosheet stack NSSt included in the nanosheet stack NSS can be connected to a separate gate. Therefore, in some implementations, the operating characteristics of the semiconductor device 100 may be improved.

[0048] Figure 3 is a cross-sectional view of the semiconductor device 100a. Figure 3 The components of the semiconductor device 100a shown are similar to those of Figure 1 、 Figure 2A and Figure 2B Components of semiconductor device 100 are shown in , so the following primarily describes the differences; the characteristics of semiconductor device 100a are the same as those described for semiconductor device 100, except where the context indicates otherwise or suggests otherwise.

[0049] Reference Figure 3 , the semiconductor device 100a may have Figure 1 、 Figure 2A and Figure 2B The configuration of the semiconductor device 100 shown in is substantially similar to that of except that the semiconductor device 100a includes a gate cutting structure CT1 including a first gate cutting structure CTn and a second gate cutting structure CTw1 and includes a vertical via VV penetrating the second gate cutting structure CTw1.

[0050] The semiconductor device 100a may include a vertical via VV that penetrates the second gate cut structure CTw1 and extends in a vertical direction (Z direction). The second gate cut structure CTw1 and the vertical via VV may extend into the device isolation layer 112. The vertical via VV may include, for example, a conductive metal. For example, the vertical via VV may include W. In some implementations, the second horizontal length of the vertical via VV is approximately 10 nm. The vertical via VV may provide an electrical connection path between transistors included in the semiconductor device 100a.

[0051] Figure 4 is a cross-sectional view of the semiconductor device 100b. Figure 4 The components of the semiconductor device 100b shown in FIG. Figure 1 、 Figure 2A and Figure 2BComponents of the semiconductor device 100 are shown in , so the following primarily describes the differences; the characteristics of the semiconductor device 100b are the same as those described for the semiconductor device 100, except where the context indicates otherwise or suggests otherwise.

[0052] Reference Figure 4 , the semiconductor device 100b may have Figure 1 、 Figure 2A and Figure 2B The configuration of the semiconductor device 100 shown in FIG. 1 is substantially similar to that of the semiconductor device 100 except that the gate separation spacer 126 is not included (see FIG. 2 ). Figure 2B ) besides.

[0053] Semiconductor device 100b may not include gate separation spacers 126. Therefore, third metal layer GM1 may not be separated by gate separation spacers 126. Since third metal layer GM1 is not separated, first metal layer 140b, second metal layer 140t, and third metal layer GM1 may together form a single gate. A lower nanosheet stack NSSb and an upper nanosheet stack NSSt disposed on the lower nanosheet stack NSSb may share a single gate including first metal layer 140b, second metal layer 140t, and third metal layer GM1. The single gate including first metal layer 140b, second metal layer 140t, and third metal layer GM1 may be connected to gate contact CB1.

[0054] Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 9D 、 Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 14C 、 Figure 15A 、 Figure 15B 、 Figure 15C 、 Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 17A 、 Figure 17B 、 Figure 17C 、 Figure 18A 、 Figure 18B 、 Figure 18C 、 Figure 19A 、 Figure 19B 、 Figure 20A 、 Figure 20B 、 Figure 21A 、 Figure 21B 、 Figure 22A 、 Figure 22B 、 Figure 23A 、 Figure 23B 、 Figure 23C 、 Figure 24A 、 Figure 24B 、 Figure 24C 、 Figure 25A 、 Figure 25B 、 Figure 25C 、 Figure 25D 、 Figure 26A 、 Figure 26B 、 Figure 26C and Figure 26D 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device (eg, semiconductor device 100 ). Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19A 、 Figure 20A 、 Figure 21A 、 Figure 22A 、 Figure 23A 、 Figure 24A 、 Figure 25A and Figure 26A It is along Figure 1 A cross-sectional view taken along line X1-X1'; Figure 9B 、 Figure 10B 、 Figure 12B 、 Figure 14B 、 Figure 15B 、 Figure 16B 、 Figure 17B 、 Figure 18B 、 Figure 23B 、 Figure 24B 、 Figure 25B and Figure 26B It is along Figure 1 A cross-sectional view taken along line X2-X2'; Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 9C 、 Figure 10C 、 Figure 18C 、 Figure 19B 、 Figure 21B 、 Figure 22B 、 Figure 23C 、 Figure 24C 、 Figure 25C and Figure 26C It is along Figure 1 A cross-sectional view taken along line Y1-Y1'; Figure 9D 、 Figure 10D 、 Figure 12C 、 Figure 13B 、 Figure 14C 、 Figure 15C 、 Figure 17C 、 Figure 25D and Figure 26D It is along Figure 1 A cross-sectional view taken along line Y2-Y2'.

[0055] Reference Figure 5A and Figure 5B First, a plurality of sacrificial layers 104 and a plurality of lower nanosheet semiconductor layers NSb may be alternately stacked on a substrate 102. After forming a middle sacrificial layer MDS, a plurality of sacrificial layers 104 and a plurality of upper nanosheet semiconductor layers NSt may be alternately stacked on the middle sacrificial layer MDS. Each of the plurality of sacrificial layers 104, the plurality of lower nanosheet semiconductor layers NSb, the plurality of upper nanosheet semiconductor layers NSt, and the middle sacrificial layer MDS may extend parallel to the upper surface of the substrate 102.

[0056] Next, after forming a plurality of hard mask patterns on the stacked structure of the plurality of sacrificial layers 104, the plurality of lower nanosheet semiconductor layers NSb, the plurality of upper nanosheet semiconductor layers NSt, and the middle sacrificial layer MDS, the plurality of sacrificial layers 104, the plurality of lower nanosheet semiconductor layers NSb, the plurality of upper nanosheet semiconductor layers NSt, and the middle sacrificial layer MDS can be patterned using the plurality of hard mask patterns as etching masks, and a portion of the semiconductor substrate 102 exposed between the patterned products can be removed to form a plurality of device isolation layer trenches 112T and a plurality of isolation recesses 122T. Each of the plurality of hard mask patterns can include nitride. For example, each of the plurality of hard mask patterns can include silicon nitride. After forming the plurality of device isolation layer trenches 112T and the plurality of isolation recesses 122T, the plurality of hard mask patterns can be removed.

[0057] Each of the plurality of device separation layer trenches 112T and the plurality of separation recesses 122T may extend in a first horizontal direction (X direction). In some implementations, the plurality of device separation layer trenches 112T and the plurality of separation recesses 122T are formed to be alternately arranged in a second horizontal direction (Y direction).

[0058] Next, an insulating material layer 120M may be formed to fill the plurality of separation recesses 122T and cover the surface of the substrate 102, the surfaces of the plurality of sacrificial layers 104, the surfaces of the plurality of lower nanosheet semiconductor layers NSb, the surfaces of the plurality of upper nanosheet semiconductor layers NSt, and the surface of the middle sacrificial layer MDS. The insulating material layer 120M may include, for example, SiCN, SiBCN, or a combination thereof.

[0059] Reference Figure 6A and Figure 6B ,from Figure 5A and Figure 5B The resulting product can remove the insulating material layer 120M (refer to Figure 5A ) to form a nanosheet partition wall 122 filling each of the plurality of partition recesses 122T. The nanosheet partition wall 122 can be formed by removing a portion of the insulating material layer 120M using, for example, an etch-back process. The portion of the insulating material layer 120M that is not removed using the etch-back process may remain at the lower edge of each of the plurality of device separation layer trenches 112T. The insulating material remaining at the lower edge of each of the plurality of device separation layer trenches 112T may be referred to as residual insulating material 124. The upper surface of the nanosheet partition wall 122 formed using the etch-back process may be at a lower vertical level than the upper surface of the middle sacrificial layer MDS, and may be at a higher vertical level than the lower surface of the middle sacrificial layer MDS.

[0060] Reference Figure 7A and Figure 7B ,from Figure 6A and Figure 6B As a result, the plurality of device separation layer trenches 112T may be filled with an insulating material to form a device separation layer 112. In this case, the upper surface of the formed device separation layer 112 may be at a lower vertical level than the upper surface of the middle sacrificial layer MDS, and may be at a higher vertical level than the lower surface of the middle sacrificial layer MDS.

[0061] Next, an insulating material layer 126M covering the surface of each of the device separation layer 112, the plurality of sacrificial layers 104, the plurality of upper nanosheet semiconductor layers NSt, and the middle sacrificial layer MDS may be formed. The insulating material layer 126M may include, for example, SiCN, SiBCN, or a combination thereof.

[0062] Reference Figure 8A and Figure 8B ,from Figure 7A and Figure 7B A portion of the insulating material layer 126M may be removed to form the gate separation spacer 126. Next, a portion of the device separation layer 112 may be removed so that the upper surface of the device separation layer 112 is at the same vertical level as the upper surface of the fin type active region FA.

[0063] In some implementations, the reference to Figure 7A and Figure 7B Described process and reference Figure 8A and Figure 8B In this case, the gate separation spacer 126 may not be formed, and .... Figure 6A and Figure 6B After the process described below, refer to Figures 9A to 26D The process described can form Figure 4 The semiconductor device 100b is shown.

[0064] Reference Figure 9A 、 Figure 9B 、 Figure 9C and Figure 9D , in from Figure 8A and Figure 8B After sequentially forming a dummy gate electrode DPCP and a plurality of hard mask patterns HM from the resulting product, the dummy gate electrode DPCP can be patterned by using the plurality of hard mask patterns HM as etching masks. The upper surface of the sacrificial layer 104 at the uppermost end and the upper surface of the device separation layer 112 can be exposed by the patterned dummy gate electrode DPCP.

[0065] The plurality of hard mask patterns HM may extend in the second horizontal direction (Y direction) and may be formed spaced apart from each other in the first horizontal direction (X direction). Each of the plurality of hard mask patterns HM may include nitride. For example, each of the plurality of hard mask patterns HM may include silicon nitride. The plurality of dummy gate electrodes DPCP, respectively patterned by the plurality of hard mask patterns HM, may each extend in the second horizontal direction (Y direction) and may be formed spaced apart from each other in the first horizontal direction (X direction). The dummy gate electrodes DPCP may include, for example, but are not limited to, polysilicon.

[0066] Reference Figure 10A 、 Figure 10B 、 Figure 10C and Figure 10D ,from Figure 9A 、 Figure 9B 、 Figure 9C and Figure 9DThe resulting product may form a first gate spacer CLD1 covering the side surfaces of the plurality of dummy gate electrodes DPCP and the side surfaces of the plurality of hard mask patterns HM. Next, an anisotropic etching process may be performed to remove a portion of the stacked structure of the plurality of sacrificial layers 104, the plurality of lower nanosheet semiconductor layers NSb, the plurality of upper nanosheet semiconductor layers NSt, and the middle sacrificial layer MDS, thereby forming first, second, third, and fourth nanosheets Nb1, Nb2, Nt1, and Nt2 below the spaces between the stacked structure of the plurality of dummy gate electrodes DPCP and the plurality of hard mask patterns HM. A plurality of source / drain trenches SDT may be defined in the spaces between the first, second, third, and fourth nanosheets Nb1, Nb2, Nt1, and Nt2. In the process of forming the first to fourth nanosheets Nb1, Nb2, Nt1, and Nt2, a portion of the fin active area FA may be removed to form the first recess RS1, and a portion of the nanosheet partition wall 122 may be removed to form the second recess RS2.

[0067] Next, the middle sacrificial layer MDS may be removed, and an middle insulating layer MDI may be formed by filling a space where the middle sacrificial layer MDS has been removed with an insulating material.

[0068] Reference Figure 11A and Figure 11B ,from Figure 10A 、 Figure 10B 、 Figure 10C and Figure 10D The resulting product can form a spin-on hard mask SOH to fill a portion of the multiple source / drain trenches SDT, a first recess RS1 formed by removing a portion of the fin-type active area FA, and a second recess RS2 formed by removing a portion of the nanosheet partition wall 122, and a portion of the spin-on hard mask SOH can be removed so that the upper surface of the spin-on hard mask SOH is at a vertical level lower than the upper surface of the intermediate insulating layer MDI, and the upper surface of the spin-on hard mask SOH is at a vertical level higher than the lower surface of the intermediate insulating layer MDI.

[0069] Next, a portion of a sidewall of each of the plurality of sacrificial layers 104 formed on the intermediate insulating layer MDI may be recessed, and a second spacer 142 t filling the recessed space may be formed.

[0070] Reference Figure 12A 、 Figure 12B and Figure 12C ,from Figure 11A and Figure 11BThe spin-on hard mask SOH can be removed, a portion of the sidewall of each of the plurality of sacrificial layers 104 formed below the intermediate insulating layer MDI can be recessed, and an insulating material layer 142bM filling the recessed space can be formed. The insulating material layer 142bM can include, for example, silicon nitride.

[0071] Reference Figure 13A and Figure 13B ,from Figure 12A 、 Figure 12B and Figure 12C The resulting product can be formed into a lower source / drain region SDb by epitaxial growth from both side surfaces of each of the first nanosheet Nb1 and the second nanosheet Nb2. The lower source / drain region SDb may include, for example, an embedded SiGe structure (including a plurality of epitaxially grown SiGe layers), an epitaxially grown Si layer, or an epitaxially grown SiC layer.

[0072] Reference Figure 14A 、 Figure 14B and Figure 14C ,from Figure 13A and Figure 13B The resulting product may form a first etch stop layer CESL1 covering the surface of the lower source / drain region SDb and at least a portion of the upper surface of the device separation layer 112. The first etch stop layer CESL1 may cover the second recess RS2 formed in the nanosheet separation wall 122. The first etch stop layer CESL1 may include, for example, a silicon nitride layer.

[0073] Reference Figure 15A 、 Figure 15B and Figure 15C ,from Figure 14A 、 Figure 14B and Figure 14C As a result, a first interlayer insulating layer FO1 covering the first etch stop layer CESL1 may be formed. Next, after a portion of the first interlayer insulating layer FO1 is removed, an upper surface of the first interlayer insulating layer FO1 may be at substantially the same vertical level as an upper surface of the middle insulating layer MDI. The first interlayer insulating layer FO1 may include, for example, silicon oxide.

[0074] Reference Figure 16A 、 Figure 16B and Figure 16C ,from Figure 15A 、 Figure 15B and Figure 15CThe resulting product can be used to form an upper source / drain region SDt by epitaxial growth from both side surfaces of each of the third nanosheet Nt1 and the fourth nanosheet Nt2. The upper source / drain region SDt may include, for example, an embedded SiGe structure (including multiple epitaxially grown SiGe layers), an epitaxially grown Si layer, or an epitaxially grown SiC layer. Next, a second etch-stop layer CESL2 may be formed covering the surface of the upper source / drain region SDt. The second etch-stop layer CESL2 may include, for example, a silicon nitride layer. Next, a second interlayer insulating layer FO2 may be formed on the second etch-stop layer CESL2. The second interlayer insulating layer FO2 may include, for example, silicon oxide.

[0075] Reference Figure 17A 、 Figure 17B and Figure 17C ,from Figure 16A 、 Figure 16B and Figure 16C The resulting product may remove a portion of the second interlayer insulating layer FO2, and may form an upper insulating layer ILD filling the space where the portion of the second interlayer insulating layer FO2 has been removed. The upper insulating layer ILD may cover the upper surface of the second interlayer insulating layer FO2. The upper insulating layer ILD may include, for example, silicon nitride.

[0076] Reference Figure 18A 、 Figure 18B and Figure 18C ,from Figure 17A 、 Figure 17B and Figure 17C The resulting product may be removed from a portion of the upper insulating layer ILD, and the patterned dummy gate electrode DPCP may be removed (refer to Figure 17A ) and the plurality of hard mask patterns HM (refer to Figure 17A ) to form a first gate space GS1. A portion of the upper insulating layer ILD may be removed by, for example, a chemical mechanical polishing (CMP) process. The first gate space GS1 may expose at least a portion of the upper surface of the uppermost sacrificial layer 104 among the plurality of sacrificial layers 104 and the upper surface of the device isolation layer 112.

[0077] Reference Figure 19A and Figure 19B ,from Figure 18A 、 Figure 18B and Figure 18C The resulting product is obtained by removing the plurality of sacrificial layers 104 (referring to Figure 18A), a second gate space GS2 and a third gate space GS3 may be formed, and the first gate space GS1, the second gate space GS2 and the third gate space GS3 may be interconnected. In some implementations, in order to selectively remove the plurality of sacrificial layers 104 (refer to Figure 18A ), the first nanosheet Nb1, the second nanosheet Nb2, the third nanosheet Nt1 and the fourth nanosheet Nt2 and the plurality of sacrificial layers 104 (refer to Figure 18A ) between the plurality of sacrificial layers 104. For example, a liquid or gaseous etchant may be used to selectively remove the plurality of sacrificial layers 104. In some implementations, a CH3COOH-based etchant may be used to selectively remove the plurality of sacrificial layers 104, such as an etchant solution containing a mixture of CH3COOH, HNO3, and HF, or an etchant solution containing a mixture of CH3COOH, H2O2, and HF, but is not limited thereto.

[0078] Next, a gate insulating layer 130 covering a surface of each of the first, second, third, and fourth nanosheets Nb1, Nb2, Nt1, and Nt2 exposed by the first, second, and third gate spaces GS1, GS2, and GS3 may be formed.

[0079] In some implementations, when performing a reference Figure 19A and Figure 19B After the described process, a process of forming a dipole material layer is performed, the dipole material layer covering at least a portion of the gate insulating layer 130 exposed by the second gate space GS2 and the third gate space GS3. For example, the dipole material layer can be formed on the gate insulating layer 130, covering at least one of the pair of lower nanosheet stacks NSSb or the pair of upper nanosheet stacks NSSt, the pair of lower nanosheet stacks NSSb or the pair of upper nanosheet stacks NSSt being spaced apart from each other with the nanosheet partition wall 122 therebetween.

[0080] Reference Figure 20A and Figure 20B ,from Figure 19A and Figure 19B The resulting product may form a metal oxide layer 140tM filling the second gate space GS2. The metal oxide layer 140tM may be formed, for example, by using a deposition process. The metal oxide layer 140tM may include, for example, aluminum oxide.

[0081] Reference Figure 21A and Figure 21B ,from Figure 20A and Figure 20B The resulting product can form a third gate space GS3 (refer to Figure 20A). The first metal layer 140b can be formed, for example, using a deposition process. The portion of the first metal layer 140b formed using the deposition process that extends beyond the third gate space GS3 can be removed using an etch-back process, leaving only the first metal layer 140b filling the third gate space GS3. The first metal layer 140b can include, for example, a metal doped with a p-type dopant.

[0082] Reference Figure 22A and Figure 22B ,from Figure 21A and Figure 21B The resulting product can be removed to fill the second gate space GS2 (refer to Figure 19A ) of the metal oxide layer 140tM (reference Figure 21A ), a filler may be formed from which the metal oxide layer 140tM is removed (refer to Figure 21A ) of the second gate space GS2 (refer to Figure 21A ) of the second metal layer 140t. The metal oxide layer 140tM (refer to Figure 21A ) can be removed, for example, using a wet etching process. The second metal layer 140t can be formed, for example, by a deposition process. The portion of the second metal layer 140t formed by the deposition process that extends beyond the second gate space GS2 can be removed using an etch-back process, leaving only the second metal layer 140t that fills the second gate space GS2. The second metal layer 140t can include, for example, a metal doped with an n-type dopant.

[0083] Reference Figure 23A 、 Figure 23B and Figure 23C ,from Figure 22A and Figure 22B The resulting product can form a first gate space GS1 (refer to Figure 22A ) of the third metal layer GM. The third metal layer GM can be formed by using, for example, a deposition process. The third metal layer GM may include, for example, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a combination thereof.

[0084] Reference Figure 24A 、 Figure 24B and Figure 24C ,from Figure 23A 、 Figure 23B and Figure 23CThe resulting product may be formed by removing a portion of the third metal layer GM, and then forming a gate capping layer 150 to fill the space where the portion of the third metal layer GM was removed. The gate capping layer 150 may cover the upper surface of the third metal layer GM. The gate capping layer 150 may include, for example, silicon nitride. The third metal layer GM formed as described above may include an upper gate metal layer GMt and a lower gate metal layer GMb separated from each other by a gate separation spacer 126.

[0085] Reference Figure 25A 、 Figure 25B 、 Figure 25C and Figure 25D ,from Figure 24A 、 Figure 24B and Figure 24C The resulting product can remove the upper insulating layer ILD (refer to Figure 24A ), a portion of the gate cap layer 150, a portion of the first gate spacer CLD1 and a portion of the second gate spacer CLD2. The upper insulating layer ILD (refer to Figure 24A ), a portion of the gate cap layer 150, a portion of the first gate spacer CLD1, and a portion of the second gate spacer CLD2 can be removed by using, for example, a chemical mechanical polishing (CMP) process. Figure 24A ) can be completely removed by using a CMP process.

[0086] Next, a first gate cutting structure CTn that penetrates the gate capping layer 150 and the upper gate metal layer GMt and extends in the vertical direction (Z direction) and a second gate cutting structure CTw that penetrates the gate capping layer 150 and the lower gate metal layer GMb and extends in the vertical direction (Z direction) may be formed. The first gate cutting structure CTn may contact the upper surface of the nanosheet partition wall 122 on its bottom surface, and the second gate cutting structure CTw may contact the upper surface of the device separation layer 112 on its bottom surface.

[0087] In some implementations, when performing the above reference Figure 25A 、 Figure 25B 、 Figure 25C and Figure 25D After the described process, a vertical via VV (refer to FIG. Figure 3 ) process. In this case, the following reference can be made Figure 26A 、 Figure 26B 、 Figure 26C and Figure 26D The process described is to manufacture Figure 3 The semiconductor device 100a is shown.

[0088] Reference Figure 26A 、 Figure 26B 、 Figure 26C and Figure 26D ,from Figure 25A 、 Figure 25B 、 Figure 25C and Figure 25D The resulting product can form a contact cut structure CX that penetrates the second interlayer insulating layer FO2 and extends in the vertical direction (Z direction). The contact cut structure CX can contact the first interlayer insulating layer FO1 on its bottom surface. Next, a first source / drain contact CAb that penetrates the first and second interlayer insulating layers FO1 and FO2 and extends in the vertical direction (Z direction) and a second source / drain contact CAt that penetrates the second interlayer insulating layer FO2 and extends in the vertical direction (Z direction) can be formed. The first source / drain contact CAb can contact the lower source / drain region SDb on its bottom surface, and the second source / drain contact CAt can contact the upper source / drain region SDt on its bottom surface.

[0089] Next, from Figure 26A 、 Figure 26B 、 Figure 26C and Figure 26D The resulting product can be manufactured by forming a first gate contact CBb and a second gate contact CBt that penetrate the gate cap layer 150 and extend in the vertical direction (Z direction). Figure 1 、 Figure 2A and Figure 2B The semiconductor device 100 is shown.

[0090] Although the present disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of the protection claimed. Certain features described in the present disclosure in the context of different implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately in multiple implementations or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, in some cases one or more features from a combination may be deleted from that combination, and the combination may be directed to a sub-combination or a variation of a sub-combination.

[0091] While various examples have been shown and described with particularity, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

[0092] This application claims priority from Korean Patent Application No. 10-2024-0019835 filed on February 8, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device comprising: A substrate comprising a pair of fin-type active regions and a device separation layer covering sidewalls of the pair of fin-type active regions; a pair of nanosheet stacks, respectively arranged on the pair of fin-type active regions, wherein each nanosheet stack in the pair of nanosheet stacks comprises a lower nanosheet stack arranged on a corresponding fin-type active region in the pair of fin-type active regions and an upper nanosheet stack arranged on the lower nanosheet stack; an intermediate insulating layer disposed between the lower nanosheet stack and the upper nanosheet stack of each nanosheet stack in the pair of nanosheet stacks; a nanosheet partition wall disposed between the pair of nanosheet stacks and extending in a first horizontal direction; as well as A pair of gate lines, on the pair of nanosheet stacks, The nanosheet partition wall separates the lower nanosheet stacks in the pair of nanosheet stacks from each other in a second horizontal direction.

2. The semiconductor device according to claim 1, The upper surface of the nanosheet partition wall is at a lower vertical level than the upper surface of the intermediate insulating layer and at a higher vertical level than the lower surface of the intermediate insulating layer.

3. The semiconductor device according to claim 1, The device separation layer is disposed in a device separation trench formed in the substrate, and residual insulating material is disposed on a lower edge of a sidewall of the device separation trench adjacent to the pair of nanosheet stacks in the second horizontal direction. 4 . The semiconductor device according to claim 3 , wherein the nanosheet partition walls and the residual insulating material comprise the same material.

5. The semiconductor device according to claim 1 , further comprising: a first gate cutting structure, separating the upper nanosheet stacks in the pair of nanosheet stacks from each other in the second horizontal direction; and a second gate cutting structure, separating another pair of nanosheet stacks adjacent to the pair of nanosheet stacks from the pair of nanosheet stacks in the second horizontal direction; The length of the first gate cutting structure in the second horizontal direction is smaller than the length of the second gate cutting structure in the second horizontal direction.

6. The semiconductor device according to claim 5, wherein: The bottom surface of the first gate cutting structure contacts the upper surface of the nanosheet partition wall, and A bottom surface of the second gate cutting structure contacts the device separation layer. 7 . The semiconductor device according to claim 5 , further comprising a vertical via extending vertically into the second gate cutting structure. 8 . The semiconductor device according to claim 1 , wherein the lower nanosheet stack and the upper nanosheet stack included in a first nanosheet stack of the pair of nanosheet stacks are connected to a gate contact.

9. A semiconductor device comprising: A substrate comprising a pair of fin-type active regions and a device separation layer covering sidewalls of the pair of fin-type active regions; a pair of nanosheet stacks, respectively arranged on the pair of fin-type active regions, wherein each nanosheet stack in the pair of nanosheet stacks comprises a lower nanosheet stack arranged on a corresponding fin-type active region in the pair of fin-type active regions and an upper nanosheet stack arranged on the lower nanosheet stack; an intermediate insulating layer disposed between the lower nanosheet stack and the upper nanosheet stack of each nanosheet stack in the pair of nanosheet stacks; a nanosheet partition wall disposed between the pair of nanosheet stacks and extending in a first horizontal direction; a gate separation spacer disposed on a first sidewall of a first nanosheet stack in the pair of nanosheet stacks, wherein the first sidewall is opposite to a second sidewall of the first nanosheet stack, and wherein the second sidewall is closer to the second nanosheet stack in the pair of nanosheet stacks than the first sidewall; as well as A pair of gate lines, on the pair of nanosheet stacks, The nanosheet partition wall separates the lower nanosheet stacks of the pair of nanosheet stacks from each other in a second horizontal direction. 10 . The semiconductor device of claim 9 , wherein an upper surface of the gate separation spacer is at a higher vertical level than an upper surface of the first nanosheet stack. 11 . The semiconductor device according to claim 9 , wherein a lower surface of the gate separation spacer is at a lower vertical level than an upper surface of the intermediate insulating layer and at a higher vertical level than a lower surface of the intermediate insulating layer. 12 . The semiconductor device according to claim 9 , wherein the gate separation spacer and the nanosheet separation wall comprise the same material.

13. The semiconductor device according to claim 9, wherein the lower nanosheet stack of the first nanosheet stack includes a first nanosheet and a second nanosheet, wherein the upper nanosheet stack of the first nanosheet stack includes a third nanosheet and a fourth nanosheet, The pair of gate lines comprises: a first metal layer disposed between the fin-type active region corresponding to the first nanosheet stack and the first nanosheet, between the first nanosheet and the second nanosheet, and between the second nanosheet and the intermediate insulating layer; a second metal layer disposed between the intermediate insulating layer and the third nanosheet and between the third nanosheet and the fourth nanosheet, and The third metal layer includes a lower gate metal layer and an upper gate metal layer separated from each other by the gate separation spacer.

14. The semiconductor device according to claim 13, wherein The lower nanosheet stack of the first nanosheet stack is electrically connected to a first gate contact in contact with the lower gate metal layer, and the upper nanosheet stack of the first nanosheet stack is electrically connected to a second gate contact in contact with the upper gate metal layer. 15 . The semiconductor device according to claim 9 , wherein an upper surface of the nanosheet partition wall is at a lower vertical level than an upper surface of the intermediate insulating layer and at a higher vertical level than a lower surface of the intermediate insulating layer.

16. The semiconductor device according to claim 9, wherein: The device separation layer is arranged in a device separation trench formed in the substrate, Residual insulating material is disposed on lower end edges of sidewalls of the device separation trench adjacent to the pair of nanosheet stacks in the second horizontal direction, and The residual insulating material includes the same material as that of the nanosheet partition walls.

17. The semiconductor device according to claim 9, further comprising: a first gate cutting structure separating the upper nanosheet stacks of the pair of nanosheet stacks from each other in the second horizontal direction; and a second gate cutting structure, separating another pair of nanosheet stacks adjacent to the pair of nanosheet stacks from the pair of nanosheet stacks in the second horizontal direction; wherein the bottom surface of the first gate cutting structure contacts the upper surface of the nanosheet partition wall, wherein the second gate cutting structure contacts the device separation layer, and The length of the first gate cutting structure in the second horizontal direction is smaller than the length of the second gate cutting structure in the second horizontal direction. 18 . The semiconductor device of claim 17 , further comprising a vertical via configured to extend into the second gate cutting structure and the device separation layer.

19. A semiconductor device comprising: a substrate comprising a pair of fin-type active regions and a device separation layer covering sidewalls of the pair of fin-type active regions, wherein the device separation layer is arranged in a device separation trench; a pair of nanosheet stacks, respectively arranged on the pair of fin-type active regions, wherein each nanosheet stack in the pair of nanosheet stacks comprises a lower nanosheet stack arranged on a corresponding fin-type active region in the pair of fin-type active regions and an upper nanosheet stack arranged on the lower nanosheet stack; an intermediate insulating layer disposed between the lower nanosheet stack and the upper nanosheet stack of each nanosheet stack in the pair of nanosheet stacks; a nanosheet partition wall disposed between the pair of nanosheet stacks and extending in a first horizontal direction; Residual insulating material is disposed on a lower edge of a sidewall of the device separation trench adjacent to the pair of nanosheet stacks in a second horizontal direction; a gate separation spacer disposed on a first sidewall of a first nanosheet stack in the pair of nanosheet stacks, wherein the first sidewall is opposite to a second sidewall of the first nanosheet stack, and wherein the second sidewall is closer to the second nanosheet stack in the pair of nanosheet stacks than the first sidewall; a pair of gate lines, on the pair of nanosheet stacks, the pair of gate lines comprising a first metal layer, a second metal layer, and a third metal layer; as well as Gate cutting structure, including: a first gate cutting structure separating the upper nanosheet stacks of the pair of nanosheet stacks from each other in the second horizontal direction, and a second gate cutting structure, separating another pair of nanosheet stacks adjacent to the pair of nanosheet stacks from the pair of nanosheet stacks in the second horizontal direction; wherein the nanosheet partition wall separates the lower nanosheet stacks of the pair of nanosheet stacks from each other in the second horizontal direction, and The third metal layer includes a lower gate metal layer and an upper gate metal layer separated from each other by the gate separation spacer. 20 . The semiconductor device of claim 19 , wherein the nanosheet partition walls, the gate separation spacers, and the residual insulating material comprise a same material, the same material comprising SiCN, SiBCN, or a combination thereof.

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