Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The first dielectric layer is located on the substrate; the first gate layer is convexly arranged on the first dielectric layer and enables the first dielectric layer at the side part to be exposed; the second dielectric layer is positioned on the top and the side wall of the first gate layer and on the first dielectric layer at the side part of the first gate layer; the second gate layer is located on the second dielectric layer and located on the top and the side wall of the first gate layer; and the source-drain doped layer is located in the substrate at two sides of the first gate layer and the second gate layer. The second grid electrode layer is located on the first dielectric layer and the second dielectric layer, so that the thickness of the dielectric layer at the bottom of the second grid electrode layer is large, the overall voltage endurance capability of the second grid electrode layer and the first grid electrode layer is improved, correspondingly, the breakdown voltage guided by grid-induced drain electrode leakage current can be improved, and the reliability of the device is improved. And punch-through breakdown voltage between the source doping layer and the drain doping layer is reduced, so that the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In the current semiconductor industry, integrated circuit products can be primarily categorized into three main types: logic, memory, and analog circuits. Memory devices account for a significant portion of integrated circuit products. With the advancement of semiconductor technology, the wider application of memory devices requires integrating these devices with other device areas on a single chip to form an embedded semiconductor memory device. For example, if a memory device is embedded within a central processing unit (CPU), it is necessary to ensure compatibility with the CPU platform and maintain the original memory device specifications and corresponding electrical performance.

[0003] Generally, the memory device needs to be compatible with the embedded standard logic device. For embedded semiconductor devices, they are usually divided into a logic area and a storage area. The logic area usually includes logic devices, and the storage area includes memory devices. With the development of storage technology, various types of semiconductor memories have emerged, such as static random access memory (SRAM), dynamic random access memory (DRAM), one-time programmable read only memory (OTPROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash memory.

[0004] With the rapid development of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to advance towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller size, higher circuit precision and higher circuit complexity.

[0005] Currently, the performance of semiconductors still needs to be improved. Summary of the Invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0007] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate; a first dielectric layer located on the substrate; a first gate layer protruding from the first dielectric layer and exposing the first dielectric layer on the side; a second dielectric layer located on the top and sidewalls of the first gate layer and on the first dielectric layer on the side of the first gate layer; a second gate layer located on the second dielectric layer and on the top and sidewalls of the first gate layer; and a source-drain doped layer located in the substrate on both sides of the first gate layer and the second gate layer.

[0008] Accordingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first dielectric layer on the substrate; forming a protruding first gate layer on the first dielectric layer, the first gate layer exposing the first dielectric layer on its side; forming a second dielectric layer on the top and sidewalls of the first gate layer and on the first dielectric layer on the side of the first gate layer; forming a second gate layer on the second dielectric layer; and forming source-drain doping layers in the substrate on both sides of the first gate layer and the second gate layer.

[0009] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0010] The semiconductor structure provided by an embodiment of the present invention includes a first gate layer protruding from the first dielectric layer and exposing the first dielectric layer on the side, a second dielectric layer located on the top and sidewalls of the first gate layer and on the first dielectric layer on the side of the first gate layer, and a second gate layer located on the second dielectric layer and on the top and sidewalls of the first gate layer, that is, the second gate layer is located on the first dielectric layer and the second dielectric layer, and the thickness of the dielectric layer at the bottom of the second gate layer is the sum of the thicknesses of the first dielectric layer and the second dielectric layer, so that the dielectric layer thickness at the bottom of the second gate layer is larger, which is beneficial to improving the overall withstand voltage capability of the second gate layer and the first gate layer, and correspondingly also beneficial to improving the breakdown voltage (BV) dominated by gate-induced drain leakage (GIDL) current and the punch-through breakdown voltage (BV) between the source and drain doped layers, thereby improving the performance of the semiconductor structure.

[0011] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a protruding first gate layer is formed on the first dielectric layer, the first gate layer exposes the first dielectric layer on its side, a second dielectric layer is formed on the top and sidewalls of the first gate layer, and on the first dielectric layer on the side of the first gate layer, and a second gate layer is formed on the second dielectric layer, that is, the second gate layer is formed on the first dielectric layer and the second dielectric layer, and the thickness of the dielectric layer at the bottom of the second gate layer is the sum of the thicknesses of the first dielectric layer and the second dielectric layer, so that the thickness of the dielectric layer at the bottom of the second gate layer is larger, which is beneficial to improving the overall withstand voltage of the second gate layer and the first gate layer, and correspondingly also beneficial to improving the breakdown voltage dominated by the gate induced drain leakage current and the punch-through breakdown voltage between the source and drain doped layers, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a structural diagram of a semiconductor structure;

[0013] Figure 2 is a schematic structural diagram of a first embodiment of a semiconductor structure of the present invention;

[0014] Figure 3 is a schematic structural diagram of a second embodiment of a semiconductor structure of the present invention;

[0015] Figure 4 for Figure 3 A local enlarged view of area A;

[0016] Figures 5 to 16 1 is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention;

[0017] Figures 17 and 18 1 is a schematic structural diagram corresponding to each step in the second embodiment of the method for forming a semiconductor structure of the present invention;

[0018] Figure 19 It is a relationship diagram between the drain current value and the drain voltage value of an NMOS device and a PMOS device of a semiconductor structure;

[0019] Figure 20 The figure is a relationship diagram between the drain terminal current value and the drain terminal voltage value of the NMOS device and the PMOS device of the semiconductor structure of the present invention. DETAILED DESCRIPTION

[0020] Currently, the performance of semiconductor structures still needs to be improved. This article analyzes the reasons why the performance of semiconductor structures needs to be improved by combining a semiconductor structure. Figure 1 It is a schematic diagram of the structure of a semiconductor structure. Figure 19A diagram showing the relationship between the drain current and drain voltage of an NMOS device and a PMOS device of a semiconductor structure.

[0021] refer to Figure 1 The semiconductor structure includes: a substrate 10; a first dielectric layer 11 located on the substrate 10; a first gate layer 12 protruding from the first dielectric layer 11 and exposing a side portion of the first dielectric layer 11; a second dielectric layer 13 located on top of the first gate layer 12; a second gate layer 14 located on the second dielectric layer 13; and source-drain doped layers 15 located in the substrate 10 on both sides of the first gate layer 12 and the second gate layer 14.

[0022] The study found that the overall withstand voltage of the first gate layer 12 and the second gate layer 14 is limited by the thickness of the first dielectric layer 11 at the bottom of the first gate layer 12, resulting in poor overall withstand voltage of the first gate layer 12 and the second gate layer 14, which makes the breakdown voltage dominated by the gate induced drain leakage current of the semiconductor structure and the punch-through breakdown voltage between the source and drain doped layers 15 low (e.g. Figure 19 shown).

[0023] Figure 19 The curves in the figure represent the drain current, bulk current, source current, and gate current, respectively. ID represents the drain current, IB represents the bulk current, the ordinate represents the drain current value, and the abscissa represents the drain voltage value.

[0024] It should be noted that GIDL BV is usually represented by the drain voltage value when ID and IB coincide.

[0025] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate; a first dielectric layer located on the substrate; a first gate layer protruding from the first dielectric layer and exposing the first dielectric layer on the side; a second dielectric layer located on the top and sidewalls of the first gate layer and on the first dielectric layer on the side of the first gate layer; a second gate layer located on the second dielectric layer and on the top and sidewalls of the first gate layer; and a source-drain doped layer located in the substrate on both sides of the first gate layer and the second gate layer.

[0026] An embodiment of the present invention provides a semiconductor structure including a first gate layer protruding above a first dielectric layer and exposing a side portion of the first dielectric layer; a second dielectric layer located on the top and sidewalls of the first gate layer and on the first dielectric layer on the side portion of the first gate layer; and a second gate layer located on the second dielectric layer and on the top and sidewalls of the first gate layer, i.e., the second gate layer is located on the first dielectric layer and the second dielectric layer. The thickness of the dielectric layer at the bottom of the second gate layer is the sum of the thicknesses of the first dielectric layer and the second dielectric layer, so that the thickness of the dielectric layer at the bottom of the second gate layer is larger, thereby facilitating improvement in the overall withstand voltage of the second gate layer and the first gate layer, and correspondingly facilitating improvement in the breakdown voltage dominated by the gate-induced drain leakage current and the punch-through breakdown voltage between the source-drain doped layers, thereby improving the performance of the semiconductor structure.

[0027] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0028] Figure 2 is a schematic structural diagram of a first embodiment of a semiconductor structure of the present invention, Figure 20 The figure is a relationship diagram between the drain terminal current value and the drain terminal voltage value of the NMOS device and the PMOS device of the semiconductor structure of the present invention.

[0029] refer to Figure 2 In this embodiment, the semiconductor structure includes: a substrate 100; a first dielectric layer 110 located on the substrate 100; a first gate layer 120 protruding from the first dielectric layer 110 and exposing a side portion of the first dielectric layer 110; a second dielectric layer 130 located on the top and sidewalls of the first gate layer 120 and on the first dielectric layer 110 on the side portion of the first gate layer 120; a second gate layer 140 located on the second dielectric layer 130 and on the top and sidewalls of the first gate layer 120; and a source-drain doped layer 190 located in the substrate 100 on both sides of the first gate layer 120 and the second gate layer 140.

[0030] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0031] In this embodiment, the substrate 100 is used to form a planar field effect transistor. In other embodiments, the substrate can also be used to form other types of field effect transistors, such as a fin field effect transistor (FinFET), a gate all around (GAA) field effect transistor, etc.

[0032] In this embodiment, the base 100 includes a substrate (not shown), which is a silicon substrate. In other embodiments, the substrate material may be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0033] It should be noted that the substrate may be a planar substrate or a substrate having a channel protrusion.

[0034] In this embodiment, the substrate is a P-type substrate (P-sub), that is, the substrate is doped with P-type ions, and the P-type ions include B ions, Ga ions, or In ions.

[0035] In this embodiment, a shallow trench isolation (STI) structure 101 is formed in the substrate 100 .

[0036] Shallow trench isolation structures 101 are used to define active areas (not labeled) and isolation areas (not labeled). The area between the shallow trench isolation structures 101 serves as the active area, and the remaining area serves as the isolation area. Specifically, the shallow trench isolation structures 101 are made of silicon oxide. In other embodiments, the shallow trench isolation structures can also be made of other dielectric materials such as silicon nitride or silicon oxynitride.

[0037] In this embodiment, the substrate 100 includes a first region i and a second region ii.

[0038] The first region i is used to form an NMOS device, and the second region ii is used to form a PMOS device.

[0039] Specifically, the first region i and the second region ii are both peripheral regions (not labeled), and the substrate 100 further includes a storage region (not shown), where a storage device is formed.

[0040] In this embodiment, a deep N-type well region (DNW) 102 is formed in the substrate of the first region i and the second region ii; a P-type well region 103 is formed in the deep N-type well region 102 of the first region i, and an N-type well region 104 is formed in the deep N-type well region 102 of the second region ii.

[0041] The deep N-type well region 102 is used to isolate the P-type well region 103 from the P-type substrate, and is also used to isolate the N-type well region 104 from the P-type well region 103, thereby reducing substrate coupling noise.

[0042] It is understandable that the doping ions in the P-type well region 103 are P-type ions, such as B ions, Ga ions or In ions; the doping ions in the N-type well region 104 are N-type ions, such as P ions, As ions or Sb ions.

[0043] The first dielectric layer 110 located at the bottom of the first gate layer 120 serves as a gate dielectric layer for isolating the first gate layer 120 from the substrate 100. The first dielectric layer 110 in the remaining area is used to reduce the probability of damage to the substrate 100 during the semiconductor process, and is also used to improve the short channel effect during the formation of the source-drain doping layer 190, thereby further optimizing the performance of the semiconductor structure.

[0044] In this embodiment, the material of the first dielectric layer 110 is silicon oxide. In other embodiments, the material of the first dielectric layer 110 may also be other suitable dielectric materials, such as silicon oxynitride.

[0045] The first dielectric layer 110, the first gate layer 120, the second dielectric layer 130 and the second gate layer 140 at the bottom of the first gate layer 120 constitute a gate structure (not shown). The gate structure and the source-drain doped layers 190 formed on both sides of the first gate layer 120 and the second gate layer 140 constitute a field effect transistor.

[0046] In this embodiment, the material of the first gate layer 120 includes polysilicon.

[0047] Polysilicon is a commonly used material in semiconductor manufacturing and thus has the characteristic of low process cost.

[0048] It should be noted that the height h1 of the first gate layer 120 along the normal direction of the top surface of the substrate 100 should not be too small or too large. If the height h1 of the first gate layer 120 is too small, it will easily increase the difficulty of forming the first gate layer 120. If the height h1 of the first gate layer 120 is too large, it will easily make the overall height of the gate structure too large, causing the gate structure to occupy too much space, affecting the development of high-integration semiconductor structures. Alternatively, if the overall height of the gate structure remains unchanged, the height of the second gate layer 140 will be too small, thereby increasing the difficulty of forming the second gate layer 140. Therefore, in this embodiment, the height h1 of the first gate layer 120 along the normal direction of the top surface of the substrate 100 ranges from 900 angstroms to 1200 angstroms.

[0049] It should also be noted that the width w1 of the first gate layer 120, along a direction perpendicular to the sidewalls of the first gate layer 120, should not be too small or too large. If the width w1 of the first gate layer 120 is too small, it may not be effective in improving the overall voltage resistance of the second gate layer 140 and the first gate layer 120. If the width w1 of the first gate layer 120 is too large, it may increase the overall width of the gate structure, causing the gate structure to occupy too much space, thereby affecting the development of high-integration semiconductor structures. Therefore, in this embodiment, the width w1 of the first gate layer 120, along a direction perpendicular to the sidewalls of the first gate layer 120, ranges from 6000 angstroms to 8000 angstroms.

[0050] As an example, the width w1 of the first gate layer 120 is two-thirds of the width w3 of the second gate layer 140 .

[0051] The first gate layer 120 protrudes above the first dielectric layer 110, and exposes the side of the first dielectric layer 110. The second dielectric layer 130 is located on the top and sidewalls of the first gate layer 120, and on the first dielectric layer 110 on the side of the first gate layer 120. The second gate layer 140 is located on the second dielectric layer 130 and on the top and sidewalls of the first gate layer 120, that is, the second gate layer 140 is located on the first dielectric layer 110 and the second dielectric layer 130. The thickness of the dielectric layer at the bottom of the second gate layer 140 is the sum of the thicknesses of the first dielectric layer 110 and the second dielectric layer 130, so that the thickness of the dielectric layer at the bottom of the second gate layer 140 is larger, which is beneficial to improving the overall withstand voltage of the second gate layer 140 and the first gate layer 120, and correspondingly, it is also beneficial to improve the breakdown voltage dominated by the gate induced drain leakage circuit and the punch-through breakdown voltage between the source and drain doped layers, thereby improving the performance of the semiconductor structure (such as Figure 20 shown).

[0052] Figure 20 The curves in FIG represent the drain current, the bulk current, the source current, and the gate current, respectively. Curve ID represents the drain current, curve IB represents the bulk current, the ordinate represents the drain current value, and the abscissa represents the drain voltage value.

[0053] It should be noted that GIDL BV is usually represented by the drain voltage value when ID and IB coincide.

[0054] In this embodiment, the second dielectric layer 130 conformally covers the top and sidewalls of the first gate layer 120 , and the first dielectric layer 110 on the side of the first gate layer 120 .

[0055] The second dielectric layer 130 conformally covers the top and sidewalls of the first gate layer 120, as well as the first dielectric layer 110 on the side of the first gate layer 120. That is, the second dielectric layer 130 covering the top and sidewalls of the first gate layer 120, as well as the side of the first gate layer 120, is not etched. As a result, the thickness h2 of the second dielectric layer 130 is not affected by the etching process, thereby avoiding the influence of the etching process on the thickness h2 of the second dielectric layer 130. This also helps to reduce the difficulty of forming the second dielectric layer 130.

[0056] It should be noted that the thickness h2 of the second dielectric layer 130 along the normal direction of the top surface of the substrate 100 should not be too small or too large. If the thickness h2 of the second dielectric layer 130 is too small, the thickness h2 of the second dielectric layer 130 at the bottom of the second gate layer 140 may be too small, which may result in poor improvement in the overall withstand voltage of the second gate layer 140 and the first gate layer 120. If the thickness h2 of the second dielectric layer 130 is too large, the overall size of the gate structure may be too large, resulting in the gate structure occupying too much space, thereby affecting the development of high-integration semiconductor structures. Therefore, in this embodiment, the thickness h2 of the second dielectric layer 130 along the normal direction of the top surface of the substrate 100 ranges from 120 angstroms to 180 angstroms.

[0057] In this embodiment, the second dielectric layer 130 is a stacked structure and includes at least one material having a stress buffering function.

[0058] The second dielectric layer 130 has a stacked structure and includes at least one material having a stress-buffering effect. This allows the second dielectric layer 130 to be made of a material with a relatively high dielectric constant (e.g., silicon nitride, a high-K dielectric material, etc.). This increases the electrical thickness of the second dielectric layer 130 while maintaining the same physical thickness, further improving the overall withstand voltage of the second gate layer 140 and the first gate layer 120. Furthermore, the inclusion of at least one material having a stress-buffering effect in the second dielectric layer 130 improves the adhesion between the second dielectric layer 130 and other layers (e.g., the first dielectric layer 110 and the second gate layer 140), thereby reducing the effect of using a material with a relatively high dielectric constant on the adhesion between the second dielectric layer 130 and other layers.

[0059] As an example, the second dielectric layer 130 has an ONO (Oxide-Nitride-Oxide) structure, that is, the second dielectric layer 130 includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked sequentially from bottom to top. Specifically, the material of the silicon oxide layer in the ONO structure includes high temperature oxide (HTO).

[0060] In other embodiments, the second dielectric layer may also be a single-layer structure, and the second dielectric layer is a silicon oxide layer or a silicon nitride layer.

[0061] The second dielectric layer 130 is located on the top and sidewalls of the first gate layer 120 and on the first dielectric layer 110 on the side of the first gate layer 120. The second gate layer 140 is located on the second dielectric layer 130 and on the top and sidewalls of the first gate layer 120. That is, the second gate layer 140 is stacked on the first gate layer 120, which makes the process of forming the first gate layer 120, the second dielectric layer 130 and the second gate layer 140 compatible with the existing process, thereby improving process compatibility and reducing costs.

[0062] As an example, the first gate layer 120 , the second dielectric layer 130 , and the second gate layer 140 may be formed in the step of forming the floating gate structure and the control gate structure of the storage region.

[0063] In this embodiment, the peripheral region MOS device is used to provide voltage to the storage region control gate structure. It is understood that the higher the breakdown voltage of the peripheral region MOS device, the higher the corresponding operating voltage of the peripheral region MOS device. Therefore, the voltage output from the source terminal of the peripheral region MOS device to the storage region control gate structure is higher, which increases the voltage applied to the storage region control gate structure and, in turn, increases the voltage difference between the storage region control gate structure and the drain terminal thereof. This allows more electrons to enter the floating gate structure of the storage region, increasing the threshold voltage (VT) value of the erase state and, in turn, the threshold voltage value of the program state. Furthermore, since the threshold voltages of both the erase and program states gradually approach 0V as the number of cycles of the memory device increases, a larger absolute value of the initial threshold voltages of the erase and program states is beneficial for increasing the threshold voltage window, thereby increasing the number of cycles of the memory device, correspondingly increasing the service life of the memory device, and, in turn, improving the market competitiveness of the memory device.

[0064] As an example, the same voltage value is applied to the first gate layer 120 and the second gate layer 140 .

[0065] In this embodiment, the material of the second gate layer 140 includes polysilicon.

[0066] Polysilicon is a commonly used material in semiconductor manufacturing and thus has the characteristic of low process cost.

[0067] In this embodiment, the second gate layer 140 is electrically connected to the first gate layer 120 .

[0068] The second gate layer 140 is electrically connected to the first gate layer 120 , which reduces the difficulty of applying voltage to the first gate layer 120 .

[0069] It should be noted that the height h3 of the second gate layer 140 along the normal direction of the top surface of the substrate 100 should not be too small or too large. If the height h3 of the second gate layer 140 is too small, it may not be effective in improving the overall voltage resistance of the second gate layer 140 and the first gate layer 120. If the height h3 of the second gate layer 140 is too large, the overall height of the gate structure may be too large, resulting in the gate structure occupying too much space, thereby affecting the development of high-integration semiconductor structures. Therefore, in this embodiment, the height h3 of the second gate layer 140 along the normal direction of the top surface of the substrate 100 ranges from 2600 angstroms to 3100 angstroms.

[0070] It should also be noted that the width w2 of the second gate layer 140 located on the sidewall of the first gate layer 120, along a direction perpendicular to the sidewall of the first gate layer 120, should not be too small or too large. If the width w2 of the second gate layer 140 located on the sidewall of the first gate layer 120 is too small, it is likely to result in poor improvement in the overall voltage resistance of the second gate layer 140 and the first gate layer 120. If the width w2 of the second gate layer 140 located on the sidewall of the first gate layer 120 is too large, it is likely to result in an excessively large overall width of the gate structure, causing the gate structure to occupy too much space, thereby affecting the development of high-integration semiconductor structures. Therefore, in this embodiment, the width w2 of the second gate layer 140 located on the sidewall of the first gate layer 120, along a direction perpendicular to the sidewall of the first gate layer 120, ranges from 900 angstroms to 1400 angstroms.

[0071] As an example, the second gate layers 140 located on both side walls of the same first gate layer 120 have the same width w2. The same width w2 of the second gate layers 140 located on both side walls of the same first gate layer 120 facilitates interchangeability of the source and drain ends of the source-drain doped layer 190. In other embodiments, the widths of the second gate layers located on both side walls of the same first gate layer may also differ, thereby further reducing the width of the second gate layers and, accordingly, further reducing the size of the semiconductor device.

[0072] In this embodiment, a height h1 of the first gate layer 120 ranges from 900 angstroms to 1200 angstroms; correspondingly, a height h4 of the second gate layer 140 located on the sidewall of the first gate layer 120 ranges from 900 angstroms to 1300 angstroms.

[0073] In this embodiment, the semiconductor structure further includes a protection layer 150 located on top of the second gate layer 140 .

[0074] The protection layer 150 is used to isolate the material of the second gate layer 140 and the mask layer (not shown) formed on the top of the material of the second gate layer 140 during the formation of the second gate layer 140 , thereby reducing the impact of the mask layer on the material of the second gate layer 140 .

[0075] In this embodiment, the semiconductor structure further includes a spacer 170 located on the sidewalls of the second dielectric layer 130 and the second gate layer 140 .

[0076] The sidewall spacer 170 is used to protect the sidewalls of the second dielectric layer 130 and the second gate layer 140 , and is also used to define the formation position of the source / drain doped layer 190 .

[0077] In this embodiment, the semiconductor structure further includes: a lightly doped region 180 located in the substrate 100 on both sides of the first gate layer 120 and the second gate layer 140 , and the doping ion type of the lightly doped region 180 is the same as the doping ion type of the source and drain doping layer 190 .

[0078] The lightly doped region 180 is used to reduce the probability of punch-through between the source and drain doped layers 190 .

[0079] Specifically, the lightly doped region 180 includes a first lightly doped region 181 located in the first region i and a second lightly doped region 182 located in the second region ii. The first lightly doped region 181 is doped with N-type ions, and the second lightly doped region 182 is doped with P-type ions.

[0080] When the device is working, the source-drain doped layer 190 is used as a source or drain to provide a carrier source.

[0081] In this embodiment, the source-drain doped layer 190 includes a first source-drain doped layer 191 located in the first region i and a second source-drain doped layer 192 located in the second region ii.

[0082] Correspondingly, the first source-drain doping region 191 is located in the first lightly doped region 181, the second source-drain doping region 192 is located in the second lightly doped region 182, and the doping ion type of the first source-drain doping layer 191 is the same as the doping ion type of the first lightly doped region 181, and the doping ion type of the second source-drain doping layer 192 is the same as the doping ion type of the second lightly doped region 182.

[0083] In this embodiment, the semiconductor structure further includes a gate plug 125 located on top of the first gate layer 120 and penetrating the second dielectric layer 130 and the second gate layer 140 . The gate plug 125 electrically connects the first gate layer 120 and the second gate layer 140 .

[0084] The gate plug 125 is located on top of the first gate layer 120 and penetrates the second dielectric layer 130 and the second gate layer 140, which reduces the difficulty of electrically connecting the first gate layer 120 and the second gate layer 140, and is conducive to combining with existing process steps to simplify the process flow.

[0085] In this embodiment, the semiconductor structure is a BSG (bit select gate) device in the peripheral region of a floating gate memory.

[0086] Typically, the operating voltage of the storage area is controlled by the operating voltage of the BSG device in the peripheral area, that is, the voltage output from the source end of the BSG device is transmitted to the gate structure of the storage area through the metal interconnection layer.

[0087] In other embodiments, the semiconductor structure may also be other semiconductor devices having a stacked gate structure.

[0088] Figure 3 is a schematic structural diagram of a second embodiment of a semiconductor structure of the present invention, Figure 4 for Figure 3 A partial enlarged view of area A.

[0089] The second embodiment is similar to the above embodiment, and no further description is given here. The second embodiment is different from the above embodiment in that Figure 3 and Figure 4 The second dielectric layer 230 has an opening 225 exposing the first gate layer 220 ; the second gate layer 240 is also located in the opening 225 and is electrically connected to the first gate layer 220 through the opening 225 .

[0090] It should be noted that in order to clearly show the semiconductor structure, Figure 4 The second gate layer is omitted.

[0091] The second dielectric layer 230 has an opening 225 exposing the first gate layer 220 . The second gate layer 240 is also located in the opening 225 and is electrically connected to the first gate layer 220 through the opening 225 , thereby facilitating electrical connection between the first gate layer 220 and the second gate layer 240 .

[0092] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 5 to 16 1 is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention, Figure 20 The figure is a relationship diagram between the drain terminal current value and the drain terminal voltage value of the NMOS device and the PMOS device of the semiconductor structure of the present invention.

[0093] refer to Figure 5 , providing a substrate 500.

[0094] The substrate 500 is used to provide a process platform for the subsequent formation of semiconductor structures.

[0095] In this embodiment, the substrate 500 is used to form a planar field effect transistor. In other embodiments, the substrate can also be used to form other types of field effect transistors, such as a fin field effect transistor, a gate-all-around field effect transistor, and the like.

[0096] In this embodiment, the base 500 includes a substrate (not shown), which is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0097] It should be noted that the substrate may be a planar substrate or a substrate having a channel protrusion.

[0098] In this embodiment, the substrate is a P-type substrate, that is, the substrate is doped with P-type ions, and the P-type ions include B ions, Ga ions or In ions.

[0099] In this embodiment, in the step of providing the substrate 500 , a shallow trench isolation structure 501 is formed in the substrate 500 .

[0100] Shallow trench isolation structures 501 are used to define active areas (not labeled) and isolation areas (not labeled). The area between the shallow trench isolation structures 501 serves as the active area, and the remaining area serves as the isolation area. Specifically, the shallow trench isolation structures 501 are made of silicon oxide. In other embodiments, the shallow trench isolation structures can also be made of other dielectric materials such as silicon nitride or silicon oxynitride.

[0101] In this embodiment, in the step of providing the substrate 500 , the substrate 500 includes a first region I and a second region II.

[0102] The first region I is used to form an NMOS device, and the second region II is used to form a PMOS device.

[0103] Specifically, the first region I and the second region II are peripheral regions (not labeled), and the substrate 500 further includes a storage region (not shown), where a storage device is formed.

[0104] In this embodiment, in the step of providing a substrate 500, a deep N-type well region 502 is formed in the substrate of the first region I and the second region II; a P-type well region 503 is formed in the deep N-type well region 502 of the first region I, and an N-type well region 504 is formed in the deep N-type well region 502 of the second region II.

[0105] The deep N-type well region 502 is used to isolate the P-type well region 503 from the P-type substrate, and is also used to isolate the N-type well region 504 from the P-type well region 503, thereby reducing substrate coupling noise.

[0106] It is understandable that the doping ions in the P-type well region 503 are P-type ions, such as B ions, Ga ions or In ions; the doping ions in the N-type well region 504 are N-type ions, such as P ions, As ions or Sb ions.

[0107] Continue to refer Figure 5 , a first dielectric layer 510 is formed on the substrate 500 .

[0108] Subsequently, a protruding first gate layer is formed on the first dielectric layer 510. The first dielectric layer 510 located at the bottom of the first gate layer serves as a gate dielectric layer for isolating the first gate layer from the substrate 500. The first dielectric layer 510 in the remaining area reduces the probability of damage to the substrate 500 in subsequent process steps, and is also used to improve the short channel effect in the subsequent formation of the source and drain doping layers, thereby further optimizing the performance of the semiconductor structure.

[0109] In this embodiment, the material of the first dielectric layer 510 is silicon oxide. In other embodiments, the material of the first dielectric layer 510 may also be other suitable dielectric materials, such as silicon oxynitride.

[0110] refer to Figure 6 and Figure 7 A protruding first gate layer 520 is formed on the first dielectric layer 510 , and the first gate layer 520 exposes the first dielectric layer 510 at its side.

[0111] The first dielectric layer 510, the first gate layer 520, the second dielectric layer and the second gate layer at the bottom of the first gate layer constitute a gate structure (not marked), and the gate structure and the source and drain doped layers subsequently formed on both sides of the first gate layer 520 and the second gate layer constitute a field effect transistor.

[0112] In this embodiment, the material of the first gate layer 520 includes polysilicon.

[0113] Polysilicon is a commonly used material in semiconductor manufacturing and thus has the characteristic of low process cost.

[0114] It should be noted that the height H1 of the first gate layer 520 along the normal direction of the top surface of the substrate 500 should not be too small or too large. If the height H1 of the first gate layer 520 is too small, it will easily increase the difficulty of forming the first gate layer 520. If the height H1 of the first gate layer 520 is too large, it will easily make the overall height of the gate structure too large, causing the gate structure to occupy too much space, affecting the development of high-integration semiconductor structures. Alternatively, if the overall height of the gate structure remains unchanged, the height of the second gate layer will be too small, thereby increasing the difficulty of forming the second gate layer. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 500, the height H1 of the first gate layer 520 ranges from 900 angstroms to 1200 angstroms.

[0115] It should also be noted that the width W1 of the first gate layer 520, along a direction perpendicular to the sidewalls of the first gate layer 520, should not be too small or too large. If the width W1 of the first gate layer 520 is too small, it will easily increase the difficulty of forming the first gate layer 520. If the width W1 of the first gate layer 520 is too large, it will easily make the overall width of the gate structure too large, causing the gate structure to occupy too much space, affecting the development of high-integration semiconductor structures. Alternatively, if the overall width of the gate structure remains unchanged, the width of the second gate layer will be too small, thereby increasing the difficulty of subsequently forming the second gate layer. Therefore, in this embodiment, along a direction perpendicular to the sidewalls of the first gate layer 520, the width W1 of the first gate layer 520 ranges from 6000 angstroms to 8000 angstroms.

[0116] As an example, the width W1 of the first gate layer 520 is two-thirds of the width of the second gate layer to be formed subsequently.

[0117] In this embodiment, the steps of forming the first gate layer 520 include: Figure 6 As shown, a first gate material layer 521 is formed on the first dielectric layer 510; Figure 7 As shown, the first gate material layer 521 is patterned, and the remaining first gate material layer 521 serves as the first gate layer 520 .

[0118] First, the first gate material layer 521 is formed on the first dielectric layer 510 , and then the first gate material layer 521 is patterned. The remaining first gate material layer 521 serves as the first gate layer 520 , which helps to reduce the difficulty of forming the first gate layer 520 .

[0119] It should be noted that the process of forming the first gate material layer 521 on the first dielectric layer 510 includes a chemical vapor deposition process.

[0120] It should also be noted that the process of patterning the first gate material layer 521 includes a dry etching process.

[0121] The dry etching process has anisotropic etching characteristics, so the etching accuracy is high and the cross-section controllability is better, which is beneficial to improving the size accuracy, morphology accuracy and position accuracy of the first gate layer 520.

[0122] refer to Figures 8 to 12 A second dielectric layer (eg, Figure 12 shown)530.

[0123] A protruding first gate layer 520 is formed on the first dielectric layer 510, and the first gate layer 520 exposes the first dielectric layer 510 on its side. A second dielectric layer 530 is formed on the top and sidewalls of the first gate layer 520, and on the first dielectric layer 510 on the side of the first gate layer 520. Subsequently, a second gate layer is formed on the second dielectric layer 530, that is, the second gate layer is formed on the first dielectric layer 510 and the second dielectric layer 530. The thickness of the dielectric layer at the bottom of the second gate layer is the sum of the thicknesses of the first dielectric layer 510 and the second dielectric layer 530, so that the thickness of the dielectric layer at the bottom of the second gate layer is larger, which is beneficial to improving the overall withstand voltage of the second gate layer and the first gate layer 520, and correspondingly, it is also beneficial to improve the breakdown voltage dominated by the gate induced drain leakage circuit and the punch-through breakdown voltage between the source and drain doped layers, thereby improving the performance of the semiconductor structure (such as Figure 20 shown).

[0124] about Figure 20 For the various descriptions in the embodiment, please refer to the corresponding description in the aforementioned embodiment, and this embodiment will not be repeated here.

[0125] In this embodiment, the peripheral region MOS device is used to provide voltage to the storage region control gate structure. It is understood that the higher the breakdown voltage of the peripheral region MOS device, the higher the corresponding operating voltage of the peripheral region MOS device. Therefore, the voltage output from the source terminal of the peripheral region MOS device to the storage region control gate structure is higher, which increases the voltage applied to the storage region control gate structure and, in turn, increases the voltage difference between the storage region control gate structure and the drain terminal thereof. This allows more electrons to enter the floating gate structure of the storage region, increasing the threshold voltage value of the erase state and, accordingly, the threshold voltage value of the edit state. Furthermore, since the threshold voltages of both the erase state and the edit state gradually approach 0V as the number of cycles of the memory device increases, when the absolute values of the initial threshold voltages of the erase state and the edit state are relatively large, this helps to increase the threshold voltage window, thereby increasing the number of cycles of the memory device, correspondingly increasing the service life of the memory device, and thus improving the market competitiveness of the memory device.

[0126] As an example, the same voltage value is applied to the first gate layer 520 and the second gate layer 540 .

[0127] In this embodiment, in the step of forming the second dielectric layer 530 , the second dielectric layer 530 conformally covers the top and sidewalls of the first gate layer 520 and the first dielectric layer 510 on the side of the first gate layer 520 .

[0128] In the step of forming the second dielectric layer 530, the second dielectric layer 530 conformally covers the top and sidewalls of the first gate layer 520, as well as the first dielectric layer 510 on the side of the first gate layer 520. That is, the second dielectric layer 530 on the first dielectric layer 510 covering the top and sidewalls of the first gate layer 520, as well as the side of the first gate layer 520, is not etched. As a result, the thickness H2 of the second dielectric layer 530 is not affected by the etching process, thereby avoiding the influence of the etching process on the thickness H2 of the second dielectric layer 530. This correspondingly helps to reduce the difficulty of forming the second dielectric layer 530.

[0129] It should be noted that the thickness H2 of the second dielectric layer 530 along the normal direction of the top surface of the substrate 500 should not be too small or too large. If the thickness H2 of the second dielectric layer 530 is too small, the thickness H2 of the second dielectric layer 530 at the bottom of the second gate layer is likely to be too small, which in turn may result in poor improvement in the overall withstand voltage of the second gate layer and the first gate layer 520. If the thickness H2 of the second dielectric layer 530 is too large, the overall size of the gate structure is likely to be too large, resulting in the gate structure occupying too much space, thereby affecting the development of high-integration semiconductor structures. Therefore, in this embodiment, the thickness H2 of the second dielectric layer 530 along the normal direction of the top surface of the substrate 500 ranges from 120 angstroms to 180 angstroms.

[0130] In this embodiment, the second dielectric layer 530 is a stacked structure and includes at least one material having a stress buffering function.

[0131] The second dielectric layer 530 has a stacked structure and includes at least one material having a stress-buffering effect. This allows the second dielectric layer 530 to be made of a material with a relatively high dielectric constant (e.g., silicon nitride, a high-K dielectric material, etc.). This increases the electrical thickness of the second dielectric layer 130 while maintaining the same physical thickness, further improving the overall withstand voltage of the second gate layer 540 and the first gate layer 520. Furthermore, the inclusion of at least one material having a stress-buffering effect in the second dielectric layer 530 improves the adhesion between the second dielectric layer 530 and other film layers (e.g., the first dielectric layer 510 and the second gate layer 540), thereby reducing the effect of the use of a material with a relatively high dielectric constant on the adhesion between the second dielectric layer 130 and other film layers.

[0132] As an example, the second dielectric layer 530 has an ONO structure, that is, the second dielectric layer 530 includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked sequentially from bottom to top. Specifically, the silicon oxide layer in the ONO structure can be formed by rapid thermal oxidation (RTO), and the material of the silicon oxide layer in the ONO structure includes a high-temperature oxide.

[0133] In other embodiments, the second dielectric layer may also be a single-layer structure, and the second dielectric layer is a silicon oxide layer or a silicon nitride layer.

[0134] Continue to refer Figures 8 to 12 , a second gate layer 540 is formed on the second dielectric layer 530 .

[0135] A second dielectric layer 530 is formed on the top and sidewalls of the first gate layer 520 and on the first dielectric layer 510 on the side of the first gate layer 520, and a second gate layer 540 is formed on the second dielectric layer 530. That is, the second gate layer 540 is stacked on the first gate layer 520, so that the process for forming the first gate layer 520, the second dielectric layer 530 and the second gate layer 540 is compatible with the existing process, thereby improving process compatibility and reducing costs.

[0136] As an example, the first gate layer 520 , the second dielectric layer 530 , and the second gate layer 540 may be formed in the step of forming the floating gate structure and the control gate structure of the storage region.

[0137] In this embodiment, the material of the second gate layer 540 includes polysilicon.

[0138] Polysilicon is a commonly used material in semiconductor manufacturing and thus has the characteristic of low process cost.

[0139] In this embodiment, the second gate layer 540 is electrically connected to the first gate layer 520 .

[0140] The second gate layer 540 is electrically connected to the first gate layer 520 , which reduces the difficulty of applying voltage to the first gate layer 520 .

[0141] It should be noted that the height H3 of the second gate layer 540 along the normal direction of the top surface of the substrate 500 should not be too small or too large. If the height H3 of the second gate layer 540 is too small, it will easily increase the difficulty of forming the second gate layer 540. If the height H3 of the second gate layer 540 is too large, it will easily make the overall height of the gate structure too large, causing the gate structure to occupy too much space, affecting the development of high-integration semiconductor structures. Alternatively, if the overall height of the gate structure remains unchanged, the height of the first gate layer 520 will be too small, thereby increasing the difficulty of forming the first gate layer 520. Therefore, in this embodiment, the height H3 of the second gate layer 540 along the normal direction of the top surface of the substrate 500 ranges from 2600 angstroms to 3100 angstroms.

[0142] It should also be noted that the width W2 of the second gate layer 540 located on the sidewall of the first gate layer 520, along a direction perpendicular to the sidewall of the first gate layer 520, should not be too small or too large. If the width W2 of the second gate layer 540 located on the sidewall of the first gate layer 520 is too small, it will easily increase the difficulty of forming the second gate layer 540. If the width W2 of the second gate layer 540 located on the sidewall of the first gate layer 520 is too large, it will easily increase the overall width of the gate structure, causing the gate structure to occupy too much space, affecting the development of high-integration semiconductor structures. Alternatively, if the overall width of the gate structure remains unchanged, the width W1 of the first gate layer 520 will be too small, thereby increasing the difficulty of forming the first gate layer 520. Therefore, in this embodiment, the width W2 of the second gate layer 540 located on the sidewall of the first gate layer 520, along a direction perpendicular to the sidewall of the first gate layer 520, ranges from 900 angstroms to 1400 angstroms.

[0143] As an example, the second gate layers 540 located on both side walls of the same first gate layer 520 have the same width W2. The same width W2 of the second gate layers 540 located on both side walls of the same first gate layer 520 facilitates the interchangeability of the source and drain ends of the source-drain doped layers. In other embodiments, the widths of the second gate layers located on both side walls of the same first gate layer may also differ, thereby further reducing the width of the second gate layers and, accordingly, further reducing the size of the semiconductor device.

[0144] In this embodiment, a height H1 of the first gate layer 520 ranges from 900 angstroms to 1200 angstroms; correspondingly, a height H4 of the second gate layer 540 located on the sidewall of the first gate layer 520 ranges from 900 angstroms to 1300 angstroms.

[0145] In this embodiment, the steps of forming the second dielectric layer 530 and the second gate layer 540 include: Figure 8 As shown, a conformal second dielectric material layer 531 is formed on the top and sidewalls of the first gate layer 520 and on the first dielectric layer 510 at the side of the first gate layer 520; Figure 9 As shown, a second gate material layer 541 is formed covering the second dielectric material layer 531; Figure 12 As shown, part of the second gate material layer 541 on the side of the first gate layer 520 is removed, and the remaining second gate material layer 541 covering the top and sidewalls of the first gate layer 520 is retained, and the remaining second gate material layer 541 serves as the second gate layer 540; the second dielectric material layer 531 exposed by the second gate layer 540 is removed, and the remaining second dielectric material layer 531 serves as the second dielectric layer 530.

[0146] First, a conformal second dielectric material layer 531 is formed on the top and sidewalls of the first gate layer 520 and the first dielectric layer 510 on the side of the first gate layer 520, and a second gate material layer 541 is formed to cover the second dielectric material layer 531. Then, a portion of the second gate material layer 541 on the side of the first gate layer 520 is removed, and the remaining second gate material layer 541 covering the top and sidewalls of the first gate layer 520 is retained. The remaining second gate material layer 541 serves as the second gate layer 540, and the second dielectric material layer 531 exposed by the second gate layer 540 is removed. This helps to reduce the difficulty of forming the second gate layer 540 and the second dielectric layer 530, and is combined with the existing process to simplify the process flow.

[0147] It should be noted that the process of forming the second dielectric material layer 531 includes a furnace deposition process.

[0148] The furnace tube deposition process is simple and easy to operate, has a low process cost, and is conducive to forming a second dielectric material layer 531 with good quality, thereby helping to improve the quality of the second dielectric layer 530 .

[0149] It should also be noted that the steps of removing a portion of the second gate material layer 541 on the side of the first gate layer 520 and removing the second dielectric material layer 531 exposed by the second gate layer 540 include: Figure 11 A patterned mask layer 560 is formed on top of the second gate material layer 541. Along the direction perpendicular to the side wall of the first gate layer 520, the width W3 of the mask layer 560 is greater than the width W1 of the first gate layer 520. Using the mask layer 560 as a mask, the second gate material layer 541 and the second dielectric material layer 531 on the side of the mask layer 560 are removed.

[0150] First, a patterned mask layer 560 is formed on the top of the second gate material layer 541, and then the second gate material layer 541 and the second dielectric material layer 531 on the side of the mask layer 560 are removed using the mask layer 560 as a mask. This is beneficial to improving the position accuracy, size accuracy, and morphology accuracy of the formed second gate layer 540 and the second dielectric layer 530.

[0151] It should be further explained that the process of removing the second gate material layer 541 and the second dielectric material layer 531 on both sides of the first gate layer 520 includes an anisotropic etching process.

[0152] The anisotropic etching process has anisotropic etching characteristics, so the etching precision is high and the cross-section controllability is better. As an example, the anisotropic etching process includes an anisotropic dry etching process.

[0153] In this embodiment, before forming the patterned mask layer 560 on the top of the second gate material layer 541, the following steps are further included: Figure 10 , forming a protective layer 550 covering the top of the second gate material layer 541; in the step of forming the mask layer 560, a patterned mask layer 560 is formed on the top of the protective layer 550; in the step of removing the second gate material layer 541 and the second dielectric material layer 531 on the side of the mask layer 560, the protective layer 550 on the side of the mask layer 560 is also removed.

[0154] The protection layer 550 is used to isolate the second gate material layer 541 from the mask layer 560 , thereby reducing the impact of the mask layer 560 on the second gate material layer 541 .

[0155] refer to Figure 13 In this embodiment, after forming the second gate layer 540 and the second dielectric layer 530 and before forming the source-drain doped layer, it also includes: forming a lightly doped region 580 in the substrate 500 on both sides of the first gate layer 520 and the second gate layer 540, and the doping ion type of the lightly doped region 580 is the same as the doping ion type of the source-drain doped layer.

[0156] The lightly doped region 580 is used to reduce the probability of punch-through between the source and drain doped layers.

[0157] Specifically, the lightly doped region 580 includes a first lightly doped region 581 located in the first region I and a second lightly doped region 582 located in the second region II. The first lightly doped region 581 is doped with N-type ions, and the second lightly doped region 582 is doped with P-type ions.

[0158] refer to Figure 14 In this embodiment, after the second dielectric layer 530 and the second gate layer 540 are formed, sidewall spacers 570 are further formed on the sidewalls of the second dielectric layer 530 and the second gate layer 540 .

[0159] The sidewall spacer 570 is used to protect the sidewalls of the second dielectric layer 530 and the second gate layer 540 , and is also used to define the formation position of the source and drain doping layers.

[0160] As an example, after the lightly doped region 580 is formed, the sidewall spacer 570 is formed.

[0161] refer to Figure 15 A source-drain doped layer 590 is formed in the substrate 500 on both sides of the first gate layer 520 and the second gate layer 540 .

[0162] When the device is working, the source-drain doped layer 590 is used as a source or drain to provide a carrier source.

[0163] In this embodiment, the source-drain doped layer 590 includes a first source-drain doped layer 591 located in the first region I and a second source-drain doped layer 592 located in the second region II.

[0164] Accordingly, after the side wall 570 is formed, a source-drain doped layer 590 is formed; in the step of forming the source-drain doped layer 590, a first source-drain doped layer 591 is formed in the first lightly doped region 581, and a second source-drain doped layer 592 is formed in the second lightly doped region 582, and the doping ion type of the first source-drain doped layer 591 is the same as the doping ion type of the first lightly doped region 581, and the doping ion type of the second source-drain doped layer 592 is the same as the doping ion type of the second lightly doped region 582.

[0165] refer to Figure 16 After forming the second gate layer 540 , the method further includes: forming a gate plug 525 on top of the first gate layer 520 that penetrates the second dielectric layer 530 and the second gate layer 540 , wherein the gate plug 525 electrically connects the first gate layer 520 and the second gate layer 540 .

[0166] A gate plug 525 is formed on top of the first gate layer 520 to penetrate the second dielectric layer 530 and the second gate layer 540, which reduces the difficulty of electrically connecting the first gate layer 520 and the second gate layer 540, and is conducive to combining with the existing process to simplify the process flow.

[0167] In this embodiment, the semiconductor structure is a BSG device in the peripheral region of a floating gate memory.

[0168] Typically, the operating voltage of the storage area is controlled by the operating voltage of the BSG device in the peripheral area, that is, the voltage output from the source end of the BSG device is transmitted to the gate structure of the storage area through the metal interconnection layer.

[0169] In other embodiments, the semiconductor structure may also be other semiconductor devices having a stacked gate structure.

[0170] Figures 17 and 18 1 is a schematic structural diagram corresponding to each step in the second embodiment of the method for forming a semiconductor structure of the present invention.

[0171] The similarities between this embodiment and the above embodiment are not described here. Figure 17 , before forming the second gate material layer covering the second dielectric material layer, further comprising: forming an opening 625 in the second dielectric material layer 631 to expose the first gate layer 620; Figure 18 In the step of forming the second gate material layer 641 covering the second dielectric material layer 631 , the second gate material layer 641 is also located in the opening 625 and is electrically connected to the first gate layer 620 through the opening 625 .

[0172] First, an opening 625 is formed in the second dielectric material layer 631 to expose the first gate layer 620. Then, in the step of forming the second gate material layer 641 covering the second dielectric material layer 631, the second gate material layer 641 is also located in the opening 625 and is electrically connected to the first gate layer 620 through the opening 625, so as to facilitate the electrical connection between the first gate layer and the second gate layer.

[0173] It should be noted that the semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the detailed description of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0174] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; a first dielectric layer, located on the substrate; a first gate layer protruding from the first dielectric layer and exposing a side portion of the first dielectric layer; a second dielectric layer located on the top and sidewalls of the first gate layer and on the first dielectric layer at the side of the first gate layer; a second gate layer, located on the second dielectric layer and on the top and sidewalls of the first gate layer; The source-drain doped layer is located in the substrate on both sides of the first gate layer and the second gate layer.

2. The semiconductor structure according to claim 1, wherein The second dielectric layer conformally covers the top and sidewalls of the first gate layer and the first dielectric layer on the side of the first gate layer.

3. The semiconductor structure according to claim 1, wherein: The second gate layer is electrically connected to the first gate layer.

4. The semiconductor structure according to claim 1, wherein: The second dielectric layer has an opening exposing the first gate layer; the second gate layer is also located in the opening and is electrically connected to the first gate layer through the opening; Alternatively, the semiconductor structure further includes: a gate plug located on top of the first gate layer and penetrating the second dielectric layer and the second gate layer, wherein the gate plug electrically connects the first gate layer and the second gate layer.

5. The semiconductor structure according to claim 1, wherein Along a normal direction of the top surface of the substrate, a height of the second gate layer ranges from 2600 angstroms to 3100 angstroms.

6. The semiconductor structure according to claim 1, wherein Along a direction perpendicular to the sidewall of the first gate layer, a width of the second gate layer located on the sidewall of the first gate layer ranges from 900 angstroms to 1400 angstroms.

7. The semiconductor structure according to claim 1, wherein: Along a normal direction of the top surface of the substrate, a height of the first gate layer ranges from 900 angstroms to 1200 angstroms.

8. The semiconductor structure according to claim 1, wherein: Along a direction perpendicular to the sidewall of the first gate layer, the width of the first gate layer ranges from 6000 angstroms to 8000 angstroms.

9. The semiconductor structure according to claim 1, wherein: Along a normal direction of the top surface of the substrate, the thickness of the second dielectric layer ranges from 120 angstroms to 180 angstroms.

10. The semiconductor structure according to claim 1, wherein: The second dielectric layer is a stacked structure and includes at least one material having a stress buffering function.

11. The semiconductor structure according to claim 1, wherein: The semiconductor structure is a semiconductor device with a stacked gate structure.

12. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a first dielectric layer on the substrate; forming a protruding first gate layer on the first dielectric layer, wherein the first gate layer exposes the first dielectric layer at its side; forming a second dielectric layer on the top and sidewalls of the first gate layer and on the first dielectric layer at the side of the first gate layer; forming a second gate layer on the second dielectric layer; A source-drain doped layer is formed in the substrate on both sides of the first gate layer and the second gate layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The step of forming the first gate layer includes: forming a first gate material layer on the first dielectric layer; The first gate material layer is patterned, and the remaining first gate material layer serves as a first gate layer.

14. The method for forming a semiconductor structure according to claim 12, wherein: In the step of forming the second dielectric layer, the second dielectric layer conformally covers the top and sidewalls of the first gate layer and the first dielectric layer on the side of the first gate layer.

15. The method for forming a semiconductor structure according to claim 12, wherein: The steps of forming the second dielectric layer and the second gate layer include: forming a conformal second dielectric material layer on the top and sidewalls of the first gate layer and on the first dielectric layer at the side of the first gate layer; forming a second gate material layer covering the second dielectric material layer; removing a portion of the second gate material layer on the side of the first gate layer, and retaining the remaining second gate material layer covering the top and sidewalls of the first gate layer, with the remaining second gate material layer serving as the second gate layer; The second dielectric material layer exposed by the second gate layer is removed, and the remaining second dielectric material layer serves as the second dielectric layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: The steps of removing a portion of the second gate material layer on the side of the first gate layer and removing the second dielectric material layer exposed by the second gate layer include: forming a patterned mask layer on top of the second gate material layer, wherein a width of the mask layer is greater than a width of the first gate layer in a direction perpendicular to the sidewall of the first gate layer; The mask layer is used as a mask to remove the second gate material layer and the second dielectric material layer on the side of the mask layer.

17. The method for forming a semiconductor structure according to claim 16, wherein: Before forming a patterned mask layer on top of the second gate material layer, the method further includes: forming a protection layer covering the top of the second gate material layer; In the step of forming the mask layer, a patterned mask layer is formed on top of the protective layer; In the step of removing the second gate material layer and the second dielectric material layer on the side of the mask layer, the protective layer on the side of the mask layer is also removed.

18. The method for forming a semiconductor structure according to claim 15, wherein: Before forming a second gate material layer covering the second dielectric material layer, the method further includes: forming an opening in the second dielectric material layer to expose the first gate layer; In the step of forming a second gate material layer covering the second dielectric material layer, the second gate material layer is also located in the opening and is electrically connected to the first gate layer through the opening.

19. The method for forming a semiconductor structure according to claim 12, wherein: After forming the second gate layer, the method further includes: forming a gate plug penetrating the second dielectric layer and the second gate layer on top of the first gate layer, wherein the gate plug electrically connects the first gate layer and the second gate layer.

20. The method for forming a semiconductor structure according to claim 12, wherein: The semiconductor structure is a semiconductor device with a stacked gate structure.

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