Semiconductor device

Abstract

A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including a device region and an edge region surrounding the device region; an interconnection structure including a plurality of conductive pattern layers stacked on the device region in a vertical direction; a guard ring structure extending in a horizontal direction to surround the interconnect structure within the edge region; the crack blocking structure is arranged outside the protection ring structure; a pad structure disposed on the interconnect structure; and a passivation layer disposed on the pad structure, in which each of the plurality of barrier pattern layers extends to surround at least a portion of an exterior of the guard ring structure.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0019645 filed on February 8, 2024, in the Korean Intellectual Property Office, Korean Patent Application No. 10-2024-0031616 filed on March 5, 2024, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0086929 filed on July 2, 2024, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] Example embodiments relate to semiconductor devices. Background Art

[0003] As the demand for high performance, high speed, and / or multifunctionality of semiconductor devices has increased, the integration of semiconductor devices has also increased. In responding to the trend of high integration of semiconductor devices, fine patterned semiconductor devices are manufactured, and patterns with fine widths or fine distances are required. In addition, high integration of semiconductor devices mounted on semiconductor packages is required. Summary of the Invention

[0004] Generally, in some aspects, the present disclosure is directed to semiconductor devices having improved reliability.

[0005] In general, according to some aspects, a semiconductor device includes: a semiconductor substrate including a device area and an edge area surrounding the device area; an interconnect structure including a plurality of conductive pattern layers stacked on the device area in a vertical direction; a guard ring structure extending in a horizontal direction to surround the interconnect structure in the edge area; a crack barrier structure disposed outside the guard ring structure and including a plurality of barrier pattern layers stacked in a vertical direction; a pad structure disposed on the interconnect structure and electrically connected to at least a portion of the plurality of conductive pattern layers; and a passivation layer disposed on the pad structure and including an opening exposing at least a portion of the pad structure, wherein each of the plurality of barrier pattern layers extends to surround at least a portion of the outside of the guard ring structure and includes a plurality of first through holes arranged in a horizontal direction and having substantially the same planar shape.

[0006] According to some aspects of the present disclosure, a semiconductor device includes: a semiconductor substrate, including a device area and an edge area surrounding the device area; a plurality of conductive pattern layers stacked on the device area in a vertical direction; a guard ring structure extending in a horizontal direction to surround the device area; and a plurality of barrier pattern layers arranged on the edge area around the guard ring structure and stacked in the vertical direction, wherein at least a portion of the plurality of conductive pattern layers and the plurality of barrier pattern layers are adjacent to each other in the vertical direction and include mesh pattern layers each having a plurality of through holes.

[0007] According to some aspects of the present disclosure, a semiconductor device includes: a semiconductor substrate including a device area in which an integrated circuit device is disposed and an edge area surrounding the device area; a plurality of interconnect pattern layers stacked on the device area in a vertical direction and electrically connected to the integrated circuit device; a plurality of dummy pattern layers stacked on the device area in a vertical direction and electrically insulated from the plurality of interconnect pattern layers; and a plurality of crack pattern layers stacked on the edge area in a vertical direction and extending in a horizontal direction to surround the device area, wherein each of the plurality of crack pattern layers is a grid pattern including a plurality of first through holes, and at least a portion of the plurality of interconnect pattern layers is a grid pattern including a plurality of second through holes. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 is a plan view of an example semiconductor substrate including a semiconductor device according to example embodiments.

[0010] Figure 2 According to an example embodiment Figure 1 An enlarged partial view of an example of area "A".

[0011] Figure 3A It is along Figure 2 A sectional view taken along line II', and Figure 3B is a cross-sectional view illustrating an example of a portion of a semiconductor device according to example embodiments.

[0012] Figures 4A to 4C is a perspective view illustrating an example of a vertical arrangement of a mesh pattern layer according to example embodiments.

[0013] Figures 5A to 5F is a plan view illustrating an example of a plan shape of a mesh pattern according to example embodiments.

[0014] Figure 6 is a plan view of an example of a semiconductor device according to example embodiments.

[0015] Figure 7 is a plan view of an example of a semiconductor device according to example embodiments.

[0016] Figure 8 is a plan view of an example of a partial region of a semiconductor device according to example embodiments.

[0017] Figure 9 is a plan view of an example of a partial region of a semiconductor device according to example embodiments.

[0018] Figure 10 is a plan view of an example of a partial region of a semiconductor device according to example embodiments.

[0019] Figure 11 is a plan view of an example of a partial region of a semiconductor device according to example embodiments.

[0020] Figure 12A is a perspective view illustrating a guard ring structure of an example embodiment, and Figure 12B yes Figure 12A A plan view of a portion of a guard ring structure.

[0021] Figure 13 is a plan view of a semiconductor device according to example embodiments.

[0022] Figure 14 is a plan view of a semiconductor device according to example embodiments.

[0023] Figure 15 is a plan view of a semiconductor device according to example embodiments.

[0024] Figure 16 is a plan view of a semiconductor device according to example embodiments.

[0025] Figure 17 is a plan view of a semiconductor device according to example embodiments.

[0026] Figure 18 is a plan view of a semiconductor device according to example embodiments.

[0027] Figure 19A is a cross-sectional view of an example of a semiconductor package including a semiconductor device according to example embodiments, and Figure 19B According to an example embodiment Figure 19A An enlarged partial view of an example of area "B".

[0028] Figure 20 is a cross-sectional view of an example of a semiconductor package including a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0029] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. Unless otherwise specified, in this specification, terms such as "upper portion," "upper surface," "lower portion," "lower surface," "side surface," etc., are based on the accompanying drawings and may be used differently depending on the orientation of the components.

[0030] In addition, ordinal numbers (such as "first," "second," "third," etc.) can be used as labels for specific elements, steps, directions, etc. to distinguish various elements, steps, directions, etc. from each other. Terms that are not described using "first," "second," etc. in the specification may still be referred to as "first" or "second" in the claims. In addition, a term referenced by a specific ordinal number (for example, "first" in a specific claim) may be described elsewhere using a different ordinal number (for example, "second" in the specification or other claims).

[0031] Figure 1 is a plan view of an example of a semiconductor substrate including a semiconductor device according to example embodiments. Figure 2 According to an example embodiment Figure 1 An enlarged partial view of an example of area "A".

[0032] exist Figure 1 and Figure 2 In the present invention, the semiconductor substrate W may include a device region DR and a scribeline region SL between the device regions DR. The scribeline region SL may extend in a first horizontal direction D1 and a second horizontal direction D2 intersecting the first horizontal direction D1. The device regions DR may be arranged to be spaced apart from each other in the first horizontal direction D1 and the second horizontal direction D2 and may be surrounded by the scribeline region SL. The device regions DR may be separated along the scribeline region SL to form semiconductor devices through a dicing process described below. The scribeline region SL may include a cutting region CR cut by a saw or dicing machine and an edge region ER between the cutting region CR and the device regions DR. The edge regions ER may respectively surround the device regions DR.

[0033] In example embodiments, the device region DR may be provided with a volatile memory device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM) or a non-volatile memory device such as a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). In one example embodiment, a logic device such as a microprocessor, an analog device, or a digital signal processor may be provided in the device region DR.

[0034] Figure 3A is according to an example embodiment along Figure 2 A sectional view taken along line II', and Figure 3B is a cross-sectional view illustrating an example of a portion of a semiconductor device 100 according to example embodiments.

[0035] exist Figure 3A and Figure 3BIn the embodiment, the semiconductor device 100 may include a semiconductor substrate 101, a device layer 110 and an interconnection layer 120. The semiconductor substrate 101 may correspond to Figure 1 The semiconductor substrate W is shown in FIG.

[0036] The semiconductor substrate 101 may include a device region DR and a scribe line region SL between the device regions DR. The scribe line region SL may include an edge region ER and a cut region CR between the edge regions ER. The edge region ER may surround the device region DR. The cut region CR may represent a portion separated during the dicing process described below. The semiconductor substrate 101 may include a semiconductor material. For example, the semiconductor substrate 101 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, or a silicon-on-insulator (SOI) substrate. The semiconductor substrate 101 may include a semiconductor material (such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor). The semiconductor substrate 101 may include a conductive region 112 and an isolation region 102. The conductive region 112 may be, for example, a well doped with impurities or a structure doped with impurities. The isolation region 102 is a device isolation structure having a shallow trench isolation (STI) structure and may include silicon oxide.

[0037] Device layer 110 may include a lower insulating layer 111 and an integrated circuit (IC) device 113. Lower insulating layer 111 may cover semiconductor substrate 101 and IC device 113. Lower insulating layer 111 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. For example, lower insulating layer 111 may include silicon oxide. IC device 113 may be disposed in device region DR. IC device 113 may include a memory cell array including switching elements and data storage elements, and logic elements including metal oxide semiconductor field effect transistors (MOSFETs), capacitors, and resistors. The IC device 113 may include, for example, field effect transistors (FETs) such as planar FETs and fin FETs (FinFETs), memory devices such as flash memory, DRAM, SRAM, electrically erasable programmable read-only memory (EEPROM), PRAM, MRAM, FeRAM, and RRAM, logic devices such as AND, OR, NOT, etc., and various active and / or passive elements such as large-scale integration (LSI) systems, complementary metal insulator semiconductor (CIS) imaging sensors, and microelectromechanical systems (MEMS).

[0038] The interconnection layer 120 may be formed on the device layer 110. The interconnection layer 120 may include a plurality of conductive pattern layers (or referred to as a plurality of pattern layers) 125a, 125b, and 125c arranged at different levels in the vertical direction, and an interlayer insulating layer 121a and an upper insulating layer 121b covering the plurality of conductive pattern layers 125a, 125b, and 125c. The plurality of conductive pattern layers 125a, 125b, and 125c may include an interconnection pattern layer 125a and a dummy pattern layer 125b disposed in the device region DR, and a crack barrier pattern layer (or "barrier pattern layer") 125c disposed in the edge region ER. In some example embodiments, at least a portion of the barrier pattern layer 125c may also be disposed in the cutting region CR. The plurality of conductive pattern layers 125a, 125b, and 125c aligned in the vertical direction may respectively form an interconnection structure CS, a dummy interconnection structure CS', and a crack barrier structure BS, which will be described below.

[0039] The interlayer insulating layer 121a surrounds the multiple conductive pattern layers 125a, 125b, and 125c and may include a low-k material with a low dielectric constant. For example, the interlayer insulating layer 121a may include silicon oxide or an organic polymer doped with impurities. In example embodiments, the interlayer insulating layer 121a may include SiOCH, SiCN, or a combination thereof. The interlayer insulating layer 121a may include multiple insulating layers (or referred to as multiple interlayer insulating layers 121a) sequentially stacked on the lower insulating layer 111. However, depending on the process, the boundaries between the interlayer insulating layers may not be distinct. The uppermost interlayer insulating layer 121a among the interlayer insulating layers 121a (e.g., the portion covering the uppermost conductive pattern layer) may include a different material from the interlayer insulating layers 121a below the uppermost interlayer insulating layer 121a. For example, the uppermost interlayer insulating layer 121a may include silicon oxide.

[0040] The upper insulating layer 121b may include a first upper insulating layer UL1, a second upper insulating layer UL2, and a third upper insulating layer UL3. In example embodiments, a portion of the second upper insulating layer UL2 vertically overlapping the uppermost pattern layers 125a, 125b, and 125c may protrude upward. The second upper insulating layer UL2 may include a material having an etch selectivity relative to the first upper insulating layer UL1. For example, the first upper insulating layer UL1 may include a high-density plasma (HDP) oxide. The second upper insulating layer UL2 may include silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof. In one example embodiment, the third upper insulating layer UL3 may include silicon oxide. For example, the third upper insulating layer UL3 may include tetraethyl orthosilicate (TEOS).

[0041] The multiple conductive pattern layers 125a, 125b, and 125c may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), gold (Au), or a combination thereof. For example, the topmost pattern layer may include aluminum (Al), and the pattern layer below the topmost pattern layer may include copper (Cu). At least a portion of the conductive pattern layers 125a, 125b, and 125c may include multiple patterns spaced apart from each other in the horizontal direction. In this disclosure, "pattern layer" may be understood to generally refer to "patterns" arranged at the same level. A "pattern" may include interconnects extending in the horizontal direction and pads connected to the interconnects. At least a portion of the multiple conductive pattern layers 125a, 125b, and 125c may be connected vertically via vias 124.

[0042] The interconnection structure CS may include a plurality of interconnection pattern layers 125 a stacked vertically on the device region DR. The interconnection structure CS may be electrically connected to the conductive region 112 and / or at least one IC device 113 through interconnectors 123 (eg, contact plugs).

[0043] The dummy interconnection structure CS' may include a plurality of dummy pattern layers 125b stacked in a vertical direction. The dummy interconnection structure CS' may be electrically insulated from the interconnection structure CS.

[0044] The crack barrier structure BS may be disposed in the edge region ER. The crack barrier structure BS may extend in the horizontal direction to surround the outer portion of the device region DR. The crack barrier structure BS may include a plurality of barrier pattern layers 125c stacked in the vertical direction. The plurality of barrier pattern layers 125c may be electrically insulated from each other by the interlayer insulating layer 121a. According to example embodiments, the plurality of barrier pattern layers 125c may be connected to each other by vias 124. The crack barrier structure BS may be disposed outside the guard ring structure GS. The crack barrier structure BS may be formed to surround the guard ring structure GS continuously or discontinuously in a plane.

[0045] According to example embodiments, the interconnection layer 120 may further include a guard ring structure GS between the interconnection structure CS and the crack barrier structure BS. The guard ring structure GS may be formed to surround the device region DR. For example, the guard ring structure GS may extend in the horizontal direction to surround the interconnection structure CS within the edge region ER. The guard ring structure GS may include guard ring pattern layers 125d stacked in the vertical direction and / or guard ring via layers 124' connecting the guard ring pattern layers 125d. The guard ring pattern layer 125d may include the same material as the corresponding plurality of conductive pattern layers 125a, 125b, and 125c in the horizontal direction. In example embodiments, the guard ring structure GS may further include a dummy connection layer 123' connected to the upper surface of the semiconductor substrate 101. The guard ring structure GS may prevent cracks from propagating toward the interior of the device region DR or moisture from being absorbed into the interior of the device region DR.

[0046] A passivation layer 131 and an upper conductive pattern (or "pad structure") 135 may be formed on the interconnection layer 120. The upper conductive pattern 135 may be connected to the dummy interconnection structure CS' and the interconnection structure CS through conductive vias 138. The conductive vias 138 may vertically penetrate the second upper insulating layer UL2 and the third upper insulating layer UL3. The upper conductive pattern 135 and the conductive vias 138 may include the same material, but are not limited thereto.

[0047] The passivation layer 131 may include a single-layer or multi-layer insulating film. For example, the passivation layer 131 may include an oxide film and / or a nitride film. The passivation layer 131 may include an opening OP exposing at least a portion of the upper conductive pattern 135.

[0048] The upper conductive pattern 135 may include, for example, a ground pad, a power pad, an alternating current (AC) pad, a data pad, and a direct current (DC) pad. The ground pad may be a pad for providing a reference potential for circuit operation of the semiconductor device 100. The power pad may be a pad for supplying power for circuit operation. The AC pad may be a pad for supplying AC power to the semiconductor device 100 or receiving a signal for performing an AC test. The data pad may be a pad for inputting / outputting logic signals or data. The DC pad may be a pad for measuring the potential level at a specific location of the semiconductor device 100.

[0049] The semiconductor device 100 may be separated by cutting a cutting region CR in which a trench T is formed by a scribing process. The trench T may extend in a horizontal direction to surround the device region DR and the edge region ER. In some example embodiments, the trench T may not completely cut the interconnection layer 120 .

[0050] According to example embodiments, at least a portion of the pattern layers within the semiconductor device 100 (e.g., the plurality of conductive pattern layers 125a, 125b, and 125c) may include a mesh pattern. A portion of the pattern layers that respectively constitute the interconnect structure CS, the dummy interconnect structure CS', and the crack barrier structure BS may include a mesh pattern layer or a mesh pattern that is adjacent to each other in the vertical direction D3 and has a plurality of through holes. Alternatively, the plurality of through holes may include a mesh pattern. The plurality of through holes may have a circular or polygonal planar shape (see FIG. Figures 5A to 5F ).

[0051] In an example embodiment, a grid pattern or a grid structure may be applied in the layout design phase of the semiconductor device 100 without distinguishing between regular patterns and irregular patterns. Therefore, the reliability of the semiconductor device 100 may be improved by applying a grid pattern layer without distinguishing between the device region DR and the edge region ER. For example, the grid pattern layer applied to the crack barrier structure BS may grid-pattern the stress propagating from the cut region CR and prevent the occurrence and propagation of cracks. In addition, the grid pattern layer applied to the interconnect structure CS and the dummy interconnect structure CS' may disperse the stress occurring inside the device region DR and prevent the occurrence and propagation of cracks. By arranging the grid pattern layer of the example embodiment in the vertical direction, the vertical component of the stress may be effectively dispersed.

[0052] In the following, as referenced below Figures 4A to 4C and Figures 5A to 5F As described above, the mesh pattern layer may be applied to example embodiments.

[0053] Figures 4A to 4C is a perspective view illustrating an example of a vertical arrangement of mesh pattern layers ML1, ML2, ML3, and ML4 according to example embodiments. Figure 4AIn the embodiment of the present invention, semiconductor device 100a may include multiple mesh pattern layers (or "mesh patterns") ML1, ML2, ML3, and ML4 aligned in a vertical direction D3. Semiconductor device 100a may include a first mesh pattern ML1, a second mesh pattern ML2, a third mesh pattern ML3, and a fourth mesh pattern ML4. In one exemplary embodiment, a first hole H1 of the first mesh pattern ML1, a second hole H2 of the second mesh pattern ML2, a third hole H3 of the third mesh pattern ML3, and a fourth hole H4 of the fourth mesh pattern ML4 may be aligned to completely overlap in the vertical direction. The multiple mesh patterns ML1, ML2, ML3, and ML4 may extend to define the holes H1, H2, H3, and H4 in a closed loop shape, thereby effectively dissipating the horizontal component HS of stress. Furthermore, by arranging the multiple mesh patterns ML1, ML2, ML3, and ML4 in the vertical direction D3, the vertical component VS of stress may be effectively dispersed. Furthermore, the multiple mesh patterns ML1, ML2, ML3, and ML4 have curved boundaries, allowing stress transmitted from the exterior of each pattern to be more effectively released.

[0054] The plurality of mesh patterns ML1, ML2, ML3 and ML4 may be understood as being included in Figure 3A and Figure 3B The plurality of interconnect pattern layers 125a, the plurality of dummy pattern layers 125b and / or the plurality of barrier pattern layers 125c may partially or completely include the pattern layers in at least one of the interconnect structure CS, the dummy interconnect structure CS' and the crack barrier structure BS. Figure 4A and the following description Figure 4B and Figure 4C The grid pattern layers ML1, ML2, ML3 and ML4 are shown in the vertically aligned regions. Figure 4A The mesh pattern layers ML1, ML2, ML3 and ML4 shown in FIG can be understood as corresponding to Figure 3B The plurality of blocking pattern layers 125c shown in FIG. 1 may include four lower layers, but are not limited thereto. Furthermore, the plurality of mesh patterns ML1, ML2, ML3, and ML4 may not be arranged at equal intervals in the vertical direction, and in some example embodiments, a non-mesh pattern may be provided between the plurality of mesh patterns ML1, ML2, ML3, and ML4. The plurality of mesh patterns ML1, ML2, ML3, and ML4 may have different thicknesses.

[0055] exist Figure 4BIn the embodiment of the present invention, the semiconductor device 100b may include a plurality of mesh patterns ML1, ML2, ML3, and ML4 arranged to be staggered in a horizontal direction (e.g., D2). In example embodiments, the first hole H1 of the first mesh pattern ML1, the second hole H2 of the second mesh pattern ML2, the third hole H3 of the third mesh pattern ML3, and the fourth hole H4 of the fourth mesh pattern ML4 may partially overlap. For example, the second hole H2 of the second mesh pattern ML2 may partially overlap the first hole H1 and the third hole H3 adjacent to each other in the vertical direction.

[0056] exist Figure 4C In the semiconductor device 100c, a plurality of mesh patterns ML1, ML2, ML3, and ML4 having through-holes of different sizes may be included. For example, the first hole H1 of the first mesh pattern ML1, the second hole H2 of the second mesh pattern ML2, the third hole H3 of the third mesh pattern ML3, and the fourth hole H4 of the fourth mesh pattern ML4, which are located at different levels in the vertical direction, may have different sizes (e.g., planar area, width, etc.). The planar area of each of the first holes H1 may be smaller than the planar area of each of the second holes H2, the third holes H3, and the fourth holes H4. The planar area of each of the second holes H2 may be smaller than the planar area of each of the third holes H3 and the fourth holes H4. The planar area of each of the third holes H3 may be smaller than the planar area of each of the fourth holes H4. In the drawings, the sizes of the plurality of holes H1, H2, H3, and H4 are shown as decreasing sequentially toward lower levels, but are not limited thereto.

[0057] However, in example embodiments, the through holes located at the same level in the horizontal direction may have substantially the same size. For example, the first holes H1 of the first mesh pattern ML1 may have the same size. The second holes H2 of the second mesh pattern ML2 may have the same size. The third holes H3 of the third mesh pattern ML3 may have the same size. The fourth holes H4 of the fourth mesh pattern ML4 may have the same size. Here, "same" includes process errors, process margins, etc., and means that the sizes are not intentionally designed to be different.

[0058] Figures 5A to 5F is a plan view showing an example of a planar shape of a mesh pattern ML according to an example embodiment. Figure 5AIn semiconductor device 100d, mesh pattern ML may include hexagonal through-holes H. The through-holes H formed in one mesh pattern ML may have substantially the same planar shape. The through-holes H may be arranged to partially overlap with through-holes H adjacent thereto in a horizontal direction. For example, mesh pattern ML may be formed in a honeycomb structure. The mesh pattern ML may extend with a substantially uniform line width d and may define intervals between adjacent through-holes H. The interval d between adjacent through-holes H may be equal to or less than the maximum width D of each of the through-holes H. The maximum width D of each of the through-holes H may be approximately 1 micrometer (μm) or less.

[0059] exist Figure 5B In the semiconductor device 100e, the mesh pattern ML may include hexagonal through-holes H. The through-holes H may be arranged to completely overlap with horizontally adjacent through-holes H. The mesh pattern ML may include portions having different line widths. For example, the mesh pattern ML may include a first portion having a first line width d1 and a second portion having a second line width d2 greater than the first line width d1. Thus, in the mesh pattern ML used in the example embodiment, the intervals between adjacent through-holes H may not be constant.

[0060] exist Figure 5C In the semiconductor device 100f, the mesh pattern ML may include circular through-holes H. The through-holes H may be arranged to at least partially overlap with through-holes H adjacent thereto in a horizontal direction. The distances cd between the centers of adjacent circular through-holes H may be substantially equal. In some example embodiments, the spacing between adjacent through-holes H may not be constant.

[0061] exist Figure 5D In the semiconductor device 100g, the mesh pattern ML may have triangular through-holes H. The through-holes H may be arranged to at least partially overlap with through-holes H adjacent thereto in a horizontal direction.

[0062] exist Figure 5E In the semiconductor device 100h, the mesh pattern ML may have square through-holes H. The through-holes H may be arranged to at least partially overlap with through-holes H adjacent thereto in a horizontal direction. In some example embodiments, the through-holes H may have a planar shape such as a rectangle, a trapezoid, or a diamond, or a quadrilateral planar shape.

[0063] exist Figure 5F In the semiconductor device 100i, the mesh pattern ML may include pentagonal through holes H. The through holes H may have substantially the same planar shape and size (eg, planar area, width, etc.). The through holes H may be arranged to at least partially overlap with the through holes H adjacent thereto in the horizontal direction.

[0064] Figure 6 is a plan view of an example of a semiconductor device according to an example embodiment. Figure 6In the embodiment, the semiconductor device 100A may include a crack barrier structure BS, which includes a plurality of barrier patterns BS1, BS2, BS3, and BS4. The plurality of barrier patterns BS1, BS2, BS3, and BS4 may have the same structure as described above. Figures 4A to 5F The semiconductor device 100A may partially include a cutting region CR that remains from the dicing process and surrounds the outside of the crack barrier structure BS. The crack barrier structure BS may include a first barrier pattern BS1, a second barrier pattern BS2, a third barrier pattern BS3, and a fourth barrier pattern BS4 that correspond to the outer surfaces of the guard ring structure GS, respectively. The guard ring structure GS may extend in the horizontal direction to surround the device region DR. In the drawings, the guard ring structure GS is shown as a square, but is not limited thereto. In example embodiments, the guard ring structure GS may have a circular or elliptical plan shape. The plan shape of the crack barrier structure BS shown in the drawings may be understood to reflect Figure 3A and Figure 3B For example, each of the blocking pattern layers 125c may include a plurality of blocking patterns (eg, BS1, BS2, BS3, and BS4) extending on a plane to surround at least a portion of the exterior of the guard ring structure GS.

[0065] Figure 7 is a plan view of an example of a semiconductor device according to an example embodiment. Figure 7 In the embodiment, the semiconductor device 100B may include a crack barrier structure BS extending entirely on a plane. The crack barrier structure BS may be formed by a structure having the same structure as that described above. Figures 4A to 5F The crack barrier structure BS may be formed with a structure having the same or similar structure as the grid pattern described above. The crack barrier structure BS may extend in the horizontal direction to continuously surround the guard ring structure GS. The planar shape of the crack barrier structure BS shown in the drawings may be understood as reflecting Figure 3A and Figure 3B For example, each of the barrier pattern layers 125c may extend to completely surround the outside of the guard ring structure GS on a plane.

[0066] Figure 8 is a plan view of an example of a partial region of a semiconductor device according to an example embodiment. Figure 8In the embodiment of the present invention, the semiconductor device 100C may include a grid pattern disposed in the device region DR. In an example embodiment, at least a portion of the interconnection pattern layer 125a may include a rectangular interconnection pattern CP extending in a first direction D1 in a plane, and at least a portion of the dummy pattern layer 125b may include at least one dummy pattern (or referred to as at least one grid dummy pattern) DP, the at least one dummy pattern DP having a plurality of through holes H adjacent to the rectangular interconnection pattern CP in the first direction D1 in a plane and arranged in a second direction D2 perpendicular to the first direction D1. The line width d of the portion of the at least one dummy pattern DP that overlaps the rectangular interconnection pattern CP in the first direction D1 and defines the plurality of through holes H may be smaller than the length L of the corresponding rectangular interconnection pattern CP in the first direction D1.

[0067] The mesh dummy patterns DP may reduce warpage and improve reliability of the semiconductor device 100D by reducing the volume of a material (eg, metal) having a high thermal expansion coefficient in a length direction of the rectangular interconnection pattern CP.

[0068] Figure 9 is a plan view of an example of a partial region of a semiconductor device according to an example embodiment. Figure 9 In the embodiment of the present invention, the semiconductor device 100D may include a plurality of dummy patterns DP1 and DP2 disposed in the device region DR. In example embodiments, at least a portion of the interconnection pattern layer 125a may include a rectangular interconnection pattern CP extending in the first direction D1, and at least a portion of the dummy pattern layer 125b may include a first dummy pattern DP1 and a second dummy pattern DP2 adjacent to the rectangular interconnection pattern CP in the first direction D1 and spaced apart from each other in the second direction D2.

[0069] Figure 10 is a plan view of an example of a partial region of a semiconductor device according to an example embodiment. Figure 10 In the present invention, the semiconductor device 100E may include an interconnection pattern CP extending in a first direction D1 and a second direction D2 in a device region DR and at least one dummy pattern DP1 and DP2 adjacent to at least one side of the interconnection pattern CP. The dummy pattern layer 125b may include a first dummy pattern DP1 and a second dummy pattern DP2 occupying empty spaces on both sides of the interconnection pattern CP. The at least one dummy pattern DP1 and DP2 may reduce the undulation of the interlayer insulating layer 121a near the interconnection pattern CP.

[0070] Figure 11 is a plan view of an example of a portion of a semiconductor device according to an example embodiment. Figure 11In the embodiment, the semiconductor device 100F may include a mesh interconnect pattern CP and mesh dummy patterns DP1 and DP2. At least a portion of each of the interconnect pattern layer 125a and the dummy pattern layer 125b may include a mesh pattern. The through holes H of the interconnect pattern CP and the through holes H of the dummy patterns DP1 and DP2 may have substantially the same planar shape and size. According to example embodiments, only the interconnect pattern layer 125a may include a mesh pattern, and the dummy pattern layer 125b may not include a mesh pattern.

[0071] In example embodiments, the sizes of the through holes H in the device region DR may be different. For example, the size (e.g., maximum width, planar area, etc.) of the through holes formed in the interconnection pattern layer 125 a (interconnection pattern located at a relatively low level) requiring a relatively fine line width may be smaller than the size (e.g., maximum width, planar area, etc.) of the through holes formed in other interconnection pattern layers 125 a.

[0072] Additionally, the through-holes H in the device region DR (e.g., the through-holes of the interconnection pattern layer 125a) and the through-holes in the edge region ER (e.g., the through-holes of the barrier pattern layer 125c) may have different sizes. For example, the size (e.g., maximum width, planar area, etc.) of the through-holes formed in the interconnection pattern layer 125a, which requires a relatively fine line width, may be smaller than the size (e.g., maximum width, planar area, etc.) of the through-holes formed in the barrier pattern layer 125c.

[0073] Figure 12A is a perspective view showing a guard ring structure GS of an example embodiment, and Figure 12B yes Figure 12A A plan view of a portion of a guard ring structure.

[0074] Reference Figure 12A and Figure 12B The guard ring structure GS of the example embodiment may include a plurality of guard ring pattern layers 125d, a plurality of guard ring via layers 124', and a dummy connection layer 123' stacked in a vertical direction. The plurality of guard ring pattern layers 125d and the plurality of guard ring via layers 124' may be alternately stacked in the vertical direction D3. The plurality of guard ring via layers 124' may be arranged between the plurality of guard ring pattern layers 125d. The dummy connection layer 123' may be provided between the lowest guard ring pattern layer 125d among the plurality of guard ring pattern layers 125d and the semiconductor substrate.

[0075] The guard ring structure GS may define an inner space IN sealed in the horizontal directions D1 and D2. That is, the plurality of guard ring pattern layers 125d, the plurality of guard ring via layers 124', and the dummy connection layer 123' may each have a dam shape that defines at least one region of the inner space IN sealed in the horizontal directions D1 and D2. As described above with reference to Figures 4A to 5FAs described above, the guard ring pattern layers 125 d , the guard ring via layers 124 ′, and the dummy connection layer 123 ′ may be a grid pattern having a plurality of through holes H. The through holes H may pass through the guard ring pattern layers 125 d , the guard ring via layers 124 ′, and the dummy connection layer 123 ′ in the vertical direction D3 .

[0076] The height h1 of the dummy connection layer 123' and the height h2 of the plurality of guard ring via layers 124' may be different from each other. In addition, the height h2 of each of the plurality of guard ring via layers 124' may also be different from each other. The height h1 of the dummy connection layer 123' and the height h2 of the plurality of guard ring via layers 124' may correspond to the distance in the vertical direction D3 between the plurality of guard ring pattern layers 125d.

[0077] Each of the multiple guard ring pattern layers 125d may have a grid structure in which multiple first through holes Ha are repeated in the horizontal direction, and each of the multiple guard ring via layers 124' may have a grid structure in which multiple second through holes Hb are repeated in the horizontal direction. In addition, the dummy connection layer 123' may have a grid structure in which multiple third through holes (same as the second through holes "Hb") are repeated in the horizontal direction. Hereinafter, the multiple second through holes Hb may be understood to refer to both the through holes in the dummy connection layer 123' and the through holes of the multiple guard ring via layers 124'. The multiple first through holes Ha and the multiple second and third through holes Hb may overlap in the vertical direction D3. In an example embodiment, the multiple first through holes Ha of each of the multiple barrier pattern layers 125c may at least partially overlap each other in the vertical direction D3.

[0078] The plurality of guard ring pattern layers 125d may extend continuously along the perimeters of the plurality of first through holes Ha, and the plurality of guard ring via layers 124' and the dummy connection layer 123' may extend continuously along the perimeters of the plurality of second through holes Hb. The line widths of the plurality of guard ring via layers 124' and the dummy connection layer 123' may be equal to or smaller than the line width of the plurality of guard ring pattern layers 125d. For example, the gap between the second inner side surface IS2 and the second outer side surface OS2 may be equal to or smaller than the gap between the first inner side surface IS1 and the first outer side surface OS1.

[0079] According to example embodiments, the first through holes Ha in the plurality of guard ring pattern layers 125d and the second through holes Hb in the plurality of guard ring via layers 124' and the dummy connection layer 123' may have the same or different sizes. For example, the maximum width D2' of the second through holes Hb may be equal to or greater than the maximum width D1' of the first through holes Ha. The maximum width of each of the plurality of first through holes Ha and the plurality of second through holes Hb may be approximately 1 μm or less.

[0080] The plurality of guard ring pattern layers 125d may have a first inner surface IS1 defining the inner wall of the first through-hole Ha and a first outer surface OS1 opposite the first inner surface IS1. The plurality of guard ring via layers 124' and the dummy connection layer 123' may have a second inner surface IS2 defining the inner wall of the second through-hole Hb and a second outer surface OS2 opposite the second inner surface IS2. The first outer surface OS1 may have a curved shape along the boundary of the first through-hole Ha arranged at the edge among the plurality of first through-holes Ha. The second outer surface OS2 may have a curved shape along the boundary of the second through-hole Hb arranged at the edge among the plurality of second through-holes Hb.

[0081] The first inner surface IS1 and the second inner surface IS2 may not coincide with each other. In a plan view, the second inner surface IS2 may be located inside the plurality of guard ring pattern layers 125d. Additionally, the first outer surface OS1 and the second outer surface OS2 may not coincide with each other, and in a plan view, the second outer surface OS2 may be located inside the plurality of guard ring pattern layers 125d. In some example embodiments, the first inner surface IS1 and the second inner surface IS2 may be coplanar with each other, and the first outer surface OS1 and the second outer surface OS2 may be coplanar with each other. In this case, the maximum width D1' of the first through hole Ha and the maximum width D2' of the second through hole Hb may be substantially the same.

[0082] Figure 13 is a plan view of a semiconductor device 100G according to example embodiments.

[0083] Reference Figure 13 , the semiconductor device 100G of the example embodiment may include a guard ring structure GS configured in a grid pattern. The guard ring structure GS may be formed to completely surround the device region DR on a plane. The guard ring structure GS may be a structure stacked on the edge region ER in the vertical direction D3 to surround the device region DR. The guard ring structure GS may have the same structure as that described above with reference to FIG. Figure 12A and Figure 12B The same or similar structure as described above (which may be referred to as a "grid structure"). That is, the device region DR may be arranged in the above reference Figure 12A and Figure 12B The guard ring structure GS is configured to seal the device region DR in the horizontal directions D1 and D2. In the drawings, the guard ring structure GS is shown as a square, but is not limited thereto. In some example embodiments, the guard ring structure GS may have a circular or elliptical planar shape.

[0084] The crack barrier structure BS may include a plurality of barrier pattern layers 125c arranged outside the guard ring structure GS. The plurality of barrier pattern layers 125c may be arranged to be staggered relative to each other in the horizontal directions D1 and D2. The semiconductor device 100H may include a portion of a cutting region CR that is retained in the dicing process and surrounds the periphery of the crack barrier structure BS. For example, Figure 3A and Figure 3B The barrier pattern layers 125 c shown in FIG. 1 may each include a rectangular pattern extending from the outside of the guard ring structure GS.

[0085] Figure 14 is a plan view of a semiconductor device 100H according to an example embodiment. Figure 14 The semiconductor device 100H of example embodiments may have the same structure as that described above with reference to FIG. 1 , except that the semiconductor device 100H includes both the guard ring structure GS formed of a mesh pattern and the crack barrier structure BS formed of a mesh pattern. Figure 13 The plurality of barrier patterns BS1, BS2, BS3 and BS4 constituting the crack barrier structure BS may have the same or similar characteristics as those described above. Figures 4A to 5F The crack barrier structure BS may include a first barrier pattern BS1, a second barrier pattern BS2, a third barrier pattern BS3, and a fourth barrier pattern BS4 corresponding to the outer side surfaces of the guard ring structure GS, respectively. The planar shape of the crack barrier structure BS shown in the drawings may be understood as reflecting Figure 3A and Figure 3B For example, each of the blocking pattern layers 125c may include a plurality of blocking patterns (eg, BS1, BS2, BS3, and BS4) extending to surround at least a portion of the outer side of the guard ring structure GS in a plan view.

[0086] The guard ring structure GS may include an inner side facing the device region DR and an outer side opposite the inner side of the guard ring structure GS, and may have a first width W1 between the inner and outer sides. The crack barrier structure BS may include an inner side facing the guard ring structure GS and an outer side opposite the inner side, and may have a second width W2 between the inner and outer sides. In an example embodiment, the first width W1 of the guard ring structure GS may be smaller than the second width W2 of the crack barrier structure BS.

[0087] Figure 15 is a plan view of a semiconductor device 100I according to example embodiments.

[0088] Reference Figure 15 , except that the semiconductor device 100I includes a guard ring structure GS including a mesh pattern portion MP and at least one line connection portion LP, the semiconductor device 100I of the example embodiment may have the same structure as that described above with reference to FIG. Figure 13 and Figure 14 The mesh pattern portion MP may have the same or similar characteristics as those described above. Figures 4A to 5F The grid pattern described above may have the same or similar structure. The line connection portion LP may be provided between the grid pattern portions MP that are spaced apart from each other. The line connection portion LP may extend in at least one direction between the grid pattern portions MP. In order to maximize the crack blocking, moisture absorption prevention, and other effects of the guard ring structure GS, the guard ring structure GS may be designed to minimize the length of the line connection portion LP. For example, at least one line connection portion LP may extend a first length d3 in the first horizontal direction and a second length d4 in the second horizontal direction between the grid pattern portions MP. Here, the first length d3 and the second length d4 may each be in the range of about 5 μm or less (for example, about 0.1 μm to about 5 μm, about 1 μm to about 5 μm, about 2 μm to about 5 μm, etc.).

[0089] Since the line connection portion LP is provided between the mesh pattern portions MP where it is difficult to form a regular mesh pattern, the line connection portion LP can improve the design freedom of the mesh pattern portion MP. For example, the line connection portion LP can be provided at the corner portion of the quadrilateral guard ring structure GS, but is not limited thereto.

[0090] Figure 16 is a plan view of a semiconductor device 100J according to example embodiments.

[0091] Reference Figure 16 The semiconductor device 100J of example embodiments may have the same structure as described above with reference to FIG. 1 , except that the semiconductor device 100J includes a dam structure (eg, a mesh dam structure) DS in which a guard ring structure GS and a crack barrier structure BS are integrated. Figures 13 to 15 The characteristics described above are the same or similar characteristics. For example, the dam structure DS may be understood as a structure in which the mesh guard ring structure GS and the crack barrier structure BS are connected to each other in the horizontal direction. The dam structure DS may include a structure in which Figure 3A and Figure 3B The barrier pattern layer 125c and the guard ring pattern layer 125d shown in FIG are wide pattern layers integrated in the horizontal directions D1 and D2. In addition, the dam structure DS may further include Figure 3A and Figure 3B The dummy connection layer 123 ′ and / or the guard ring via layer 124 ′ shown in FIG. 1 extends to the wide via layer of the barrier pattern layer 125 c in the horizontal directions D1 and D2 .

[0092] Figure 17 is a plan view of a semiconductor device 100K according to example embodiments.

[0093] Reference Figure 17, except that the semiconductor device 100K includes the alignment key area KZ, the semiconductor device 100K of the example embodiment may have the same Figures 13 to 16 The alignment key region KZ may be a region where alignment patterns for vertical alignment are formed. The alignment key region KZ may be disposed in an outer region of the device adjacent to the cutting region CR (i.e., outside the guard ring structure GS). The alignment key region KZ may overlap at least a portion of the crack barrier structure BS. A pattern for blocking cracks (e.g., a barrier pattern layer) may not be formed within the alignment key region KZ. For example, the crack barrier structure BS may include mesh barrier patterns BS1, BS2, BS3, and BS4, respectively corresponding to the outer surface of the guard ring structure GS. The alignment key region KZ may remove a portion of at least one barrier pattern (e.g., the first barrier pattern BS1).

[0094] Figure 18 is a plan view of a semiconductor device 100L according to example embodiments.

[0095] The semiconductor device 100L of example embodiments may have the same structure as described above with reference to FIG. 1 , except that the semiconductor device 100L includes the mesh dam structure DS and the alignment key region KZ. Figures 13 to 17 The dam structure DS may include a mesh-wide pattern layer in which the guard ring structure GS and the crack barrier structure BS are integrated. In one example embodiment, the alignment key region KZ may partially overlap with the wide pattern layer of the dam structure DS. The dam structure DS may be formed to surround at least a portion of the alignment key region KZ. The dam structure DS may block the space between the alignment key region KZ and the device region DR. According to example embodiments, the alignment key region KZ may extend to a region overlapping with the guard ring structure GS.

[0096] Figure 19A is a cross-sectional view of an example of a semiconductor package including a semiconductor device according to example embodiments, and Figure 19B According to an example embodiment Figure 19A An enlarged partial view of an example of area "B". Figure 19A and Figure 19B In the embodiment of the present invention, semiconductor package 1000 may be a high bandwidth memory (HBM) package. Semiconductor package 1000 may include a package substrate PS, an interposer IP mounted on the package substrate PS, a memory package 800 mounted on the interposer IP, and a processor chip 900. The interposer IP may electrically connect the memory package 800 to the processor chip 900.

[0097] The memory package 800 may include a buffer chip 805, a first semiconductor device 810, a second semiconductor device 820, a third semiconductor device 830, and a fourth semiconductor device 840 stacked sequentially. The buffer chip 805 and the first to fourth semiconductor devices 810, 820, 830, and 840 may have the same structure as described above. Figures 1 to 18 The structure of the described semiconductor device 100 is the same or similar structure, and may include, for example, mesh pattern layers stacked in the device region DR and the edge region ER in a vertical direction.

[0098] The memory package 800 may further include bumps 855 between the second semiconductor device 820 and the third semiconductor device 830 and between the third semiconductor device 830 and the fourth semiconductor device 840. The first to fourth semiconductor devices 810, 820, 830, and 840 may further include connection pads 195 connected to the upper conductive pattern 150. The connection pads 195 may be filled with Figure 3B 1 and may contact the upper conductive pattern 135. The connection pad 195 may pass through the passivation layer 131. The bump 855 may connect the via pad 190 and the connection pad 195 between the adjacent semiconductor devices 820, 830, and 840. The adhesive layer 850 may cover the sides of the via pad 190, the connection pad 195, and the bump 855. In an example embodiment, the bump 855 may be omitted, and the via pad 190 and the connection pad 195 may directly contact each other.

[0099] In an example embodiment, the buffer chip 805 may be a semiconductor chip of a different type than the first to fourth semiconductor devices 810, 820, 830, and 840. For example, the buffer chip 805 may be a logic chip, and the first to fourth semiconductor devices 810, 820, 830, and 840 may be memory chips. The logic chip may include a microprocessor, an analog element, or a digital signal processor. The memory chip may include a volatile memory chip (such as DRAM or SRAM) or a non-volatile memory chip (such as PRAM, MRAM, FeRAM, or RRAM).

[0100] Memory package 800 may further include an adhesive layer 850 and an encapsulant 860. Adhesive layer 850 may be provided between buffer chip 805 and first semiconductor device 810, and between first through fourth semiconductor devices 810, 820, 830, and 840. Adhesive layer 850 may be a non-conductive film (NCF) or non-conductive paste (NCP). Encapsulant 860 may be a resin including epoxy or polyimide. For example, the resin may include bisphenol epoxy resin, polycyclic aromatic epoxy resin, o-cresol novolac epoxy resin, biphenyl epoxy resin, or naphthalene epoxy resin.

[0101] The processor chip 900 may be a central processing unit (CPU), a graphics processing unit (GPU), a mobile application, or a digital signal processor (DSP) chip.

[0102] Figure 20 is a cross-sectional view of an example of a semiconductor package including a semiconductor device according to example embodiments. Figure 20 In the embodiment, the semiconductor package 1100 may include a substrate 2, an adhesive member 10, bonding wires 20, and an encapsulant 30. The semiconductor package 1100 may further include a semiconductor device 100 on the substrate 2.

[0103] The substrate 2 may include an upper pad 3, a lower pad 5, an internal interconnect 6, and an external connection terminal 7. In an exemplary embodiment, the substrate 2 may be a printed circuit board and may include an insulating material (such as phenolic resin, epoxy resin, or prepreg). In another exemplary embodiment, the substrate 2 may be a redistribution layer in which insulating and conductive materials are stacked. The upper pad 3 and the lower pad 5 may be formed by forming a metal layer on the base of the substrate 2 and then patterning the metal layer.

[0104] Upper pads 3 may be disposed on the upper surface of substrate 2 and may be electrically connected to semiconductor device 100. Lower pads 5 may be disposed on the lower surface of substrate 2, and upper pads 3 may be electrically connected to corresponding lower pads 5 via internal interconnects 6. External connection terminals 7 may be disposed below lower pads 5. Lower pads 5, upper pads 3, and internal interconnects 6 may include metal (e.g., copper (Cu)). External connection terminals 7 may be, for example, solder bumps.

[0105] The semiconductor device 100 may be understood to have the same Figures 1 to 18 The characteristics of the semiconductor device 100 described above are the same as or similar to those of the semiconductor device 100 . The passivation layer 131 can protect the upper conductive pattern 135 from external physical impact. The upper conductive pattern 135 can be connected to the upper pad 3 through the bonding wire 20 .

[0106] The adhesive member 10 may be disposed between the substrate 2 and the semiconductor device 100 . The adhesive member 10 may secure the semiconductor device 100 to the substrate 2 . The adhesive member 10 may be, but is not limited to, a die attach film (DAF). The encapsulant 30 may cover the substrate 2 , the semiconductor device 100 , and the bonding wires 20 .

[0107] According to example embodiments, a semiconductor device having improved reliability and a semiconductor package including the semiconductor device may be provided by introducing a mesh pattern into a conductive pattern layer in the semiconductor device.

[0108] Although the present disclosure contains many specific embodiment details, these should not be interpreted as limiting the scope of the protection that can be claimed. Specific features described in the context of separate embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described above as working in a specific combination, in some cases one or more features from a combination may be cut out from the combination, and a combination may refer to a sub-combination or a variation of a sub-combination.

Claims

1. A semiconductor device comprising: a semiconductor substrate comprising a device region and an edge region surrounding the device region; An interconnect structure comprising a plurality of conductive pattern layers stacked vertically on a device region; a guard ring structure, located in the edge region, extending in a horizontal direction and surrounding the interconnect structure; a crack blocking structure disposed outside the guard ring structure and comprising a plurality of blocking pattern layers stacked in a vertical direction; a pad structure disposed on the interconnect structure and electrically connected to at least a portion of the plurality of conductive pattern layers; as well as a passivation layer disposed on the pad structure and including an opening exposing at least a portion of the pad structure, wherein each of the plurality of barrier pattern layers extends to surround at least a portion of an outer portion of the guard ring structure, and Each of the plurality of barrier pattern layers includes a plurality of first through holes, and the plurality of first through holes are arranged in a horizontal direction and have the same planar shape.

2. The semiconductor device according to claim 1, wherein The plurality of first through holes of each of the plurality of barrier pattern layers at least partially overlap one another in a vertical direction.

3. The semiconductor device according to claim 1, wherein The planar shape of the plurality of first through holes includes a circle or a polygon.

4. The semiconductor device according to claim 1, wherein An interval between the plurality of first through-holes adjacent to each other is equal to or smaller than a maximum width of each of the plurality of first through-holes.

5. The semiconductor device according to claim 4, wherein A maximum width of each of the plurality of first through holes is 1 micrometer or less. The semiconductor device according to claim 1 , wherein: The plurality of barrier pattern layers include at least one barrier pattern having the plurality of first via holes and surrounding an outside of the guard ring structure in a plan view.

7. The semiconductor device according to any one of claims 1 to 6, in, The plurality of conductive pattern layers include an interconnection pattern layer and a dummy pattern layer electrically insulated from the interconnection pattern layer, the interconnection pattern layer being electrically connected to an integrated circuit device arranged on an active surface of the semiconductor substrate, wherein at least a portion of the interconnection pattern layer and at least a portion of the dummy pattern layer include a plurality of second through holes arranged in a horizontal direction, and Wherein, the plurality of second through holes have the same planar shape.

8. The semiconductor device according to claim 7, in, In a plan view, at least a portion of the interconnection pattern layer includes a rectangular interconnection pattern extending in a first direction, wherein at least a portion of the dummy pattern layer includes at least one dummy pattern adjacent to the rectangular interconnection pattern in the first direction, and Wherein, in a plan view, the at least a portion of the dummy pattern layer has the plurality of second through holes arranged in a second direction perpendicular to the first direction.

9. The semiconductor device according to claim 8, wherein A line width of a portion of the at least one dummy pattern defining the plurality of second vias is smaller than a length of a corresponding rectangular interconnection pattern in the first direction.

10. The semiconductor device according to claim 7, in, In a plan view, at least a portion of the interconnection pattern layer includes interconnection patterns extending in a first direction and a second direction, wherein at least a portion of the dummy pattern layer includes at least one dummy pattern adjacent to at least one side of the interconnection pattern, and Wherein, the at least a portion of the dummy pattern layer has the plurality of second through holes.

11. The semiconductor device according to claim 7, wherein The at least a portion of the interconnection pattern layer and the at least a portion of the dummy pattern layer each include a mesh pattern having the plurality of second through holes.

12. A semiconductor device comprising: a semiconductor substrate comprising a device region and an edge region surrounding the device region; A plurality of conductive pattern layers are stacked on the device area in a vertical direction; a guard ring structure extending in a horizontal direction and surrounding the device area; as well as A plurality of barrier pattern layers are stacked in a vertical direction and arranged on an edge region around the guard ring structure. wherein at least a portion of the plurality of conductive pattern layers and at least a portion of the plurality of barrier pattern layers are adjacent to each other in a vertical direction, Wherein, the at least a portion of the plurality of conductive pattern layers includes a plurality of mesh pattern layers, and each of the plurality of mesh pattern layers has a plurality of through holes.

13. The semiconductor device according to claim 12, in, The plurality of conductive pattern layers include an interconnection pattern layer and a dummy pattern layer electrically insulated from the interconnection pattern layer, the interconnection pattern layer being electrically connected to the integrated circuit device disposed on the device region, and Wherein, at least a portion of each of the interconnection pattern layer and the dummy pattern layer includes the plurality of mesh pattern layers.

14. A semiconductor device comprising: a semiconductor substrate comprising a device region and an edge region surrounding the device region; An interconnect structure comprising a plurality of conductive pattern layers stacked vertically on a device region; A guard ring structure comprising a plurality of guard ring pattern layers and a plurality of guard ring via layers alternately stacked in a vertical direction on an edge region and surrounding a device region; as well as a pad structure disposed on the interconnect structure and electrically connected to at least a portion of the plurality of conductive pattern layers, wherein each of the plurality of guard ring pattern layers has a grid structure in which a plurality of first through holes are repeated in a horizontal direction, Each of the plurality of guard ring via layers has a grid structure in which a plurality of second through holes are repeated in a horizontal direction, and The plurality of first through holes and the plurality of second through holes are stacked in a vertical direction.

15. The semiconductor device according to claim 14, wherein The guard ring structure further includes a dummy connection layer disposed between a lowermost guard ring pattern layer among the plurality of guard ring pattern layers and the semiconductor substrate, and the dummy connection layer has a grid structure in which a plurality of third through holes are repeated in a horizontal direction.

16. The semiconductor device according to claim 15, wherein The plurality of third through holes overlap the plurality of first through holes and the plurality of second through holes in a vertical direction.

17. The semiconductor device according to claim 14, wherein The plurality of guard ring pattern layers include a first inner side surface defining inner walls of the plurality of first through holes and a first outer side surface curved along boundaries of first through holes arranged at edges among the plurality of first through holes, and The plurality of guard ring via layers include a second inner surface and a second outer surface, the second inner surface defines the inner wall of the plurality of second through holes, and the second outer surface curves along the boundary of the second through holes arranged at the edge among the plurality of second through holes.

18. The semiconductor device according to claim 17, wherein A gap between the second inner surface and the second outer surface is equal to or smaller than a gap between the first inner surface and the first outer surface.

19. The semiconductor device according to claim 14, wherein The plurality of guard ring pattern layers continuously extend along perimeters of the plurality of first through-holes, and the plurality of guard ring via layers continuously extend along perimeters of the plurality of second through-holes.

20. The semiconductor device according to any one of claims 14 to 19, wherein The plurality of guard ring pattern layers include a plurality of mesh pattern portions including the plurality of first vias and at least one wire connection portion connecting the plurality of mesh pattern portions to each other.

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