Heterojunction solar cell

Abstract

A heterojunction solar cell comprises a monocrystalline silicon substrate, the monocrystalline silicon substrate is provided with a first main surface and a second main surface which are oppositely arranged, and a side surface connecting the first main surface and the second main surface, and the second main surface comprises a middle area and an edge area surrounding the periphery of the middle area; the first intrinsic amorphous layer, the first doped amorphous layer, the first transparent conductive film layer and the first collector electrode are sequentially arranged on the first main surface, and the first intrinsic amorphous layer covers the first main surface and the side surface and extends to the edge area of the second main surface; the second intrinsic amorphous layer, the second doped amorphous layer, the second transparent conductive film layer and the second collector electrode are sequentially arranged on the second main face, and the second doped amorphous layer and the second transparent conductive film layer are only located in the middle area. According to the invention, the side surface and the edge area of the monocrystalline silicon substrate are wrapped by the first intrinsic amorphous layer, so that the passivation effect of the surface of the monocrystalline silicon substrate can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic manufacturing, and in particular to a heterojunction solar cell. Background Art

[0002] Heterojunction solar cells are currently a relatively efficient crystalline silicon solar cell. They combine the characteristics of crystalline silicon cells and silicon-based thin-film cells, and have the advantages of short manufacturing process, low process temperature, high conversion efficiency and high power generation. Figure 1 The figure shows a schematic structural diagram of a heterojunction solar cell involved in the prior art, which includes, from top to bottom, a first collector 51', a first transparent conductive film layer 41', a first doped amorphous layer 31', a first intrinsic amorphous layer 21', a single crystal silicon substrate 10', a second intrinsic amorphous layer 22', a second doped amorphous layer 32', a second transparent conductive film layer 42', and a second collector 52'.

[0003] In the specific production process of heterojunction solar cells in the prior art, the PECVD process is usually first used to complete the production of four amorphous silicon layers, namely the first intrinsic amorphous layer 21', the second intrinsic amorphous layer 22', the first doped amorphous layer 31', and the second doped amorphous layer 32' on both surfaces of the single-crystal silicon substrate 10'; then the PVD process is used to produce the first transparent conductive film layer 41' and the second transparent conductive film layer 42'; finally, the first collector 51' and the second collector 52' are produced through the screen printing process.

[0004] Among them, the specific production of the four amorphous silicon layers requires the use of Figure 2 The carrier 600' of the illustrated structure has a groove matching the size of the single-crystal silicon substrate 10'. Specifically, to fabricate the four amorphous silicon layers, the single-crystal silicon substrate 10' is placed within the groove of the carrier 600'. A first intrinsic amorphous layer 21' and a first doped amorphous layer 31' are sequentially deposited on one surface of the single-crystal silicon substrate 10' using PECVD. The single-crystal silicon substrate 10' is then flipped over using a robot, and a second intrinsic amorphous layer 22' and a second doped amorphous layer 32' are sequentially deposited on the other surface of the single-crystal silicon substrate 10' using PECVD, completing the fabrication of the four amorphous silicon layers.

[0005] However, the heterojunction solar cells and their manufacturing methods involved in the existing technology have the following problems: the edge area of the single-crystalline silicon substrate 10' is not sufficiently passivated; the single-crystalline silicon substrate 10' needs to be turned over during the production of the four-layer amorphous silicon layer, which will introduce contamination and cause the battery's electrical performance to deteriorate, and will also extend the battery production cycle; when the first doped amorphous layer 31' is produced, the drift of free radicals in the PECVD chamber can easily cause the edge of the undeposited surface of the single-crystalline silicon substrate 10' to be contaminated by doped atoms, thereby reducing the passivation performance of the interface between the single-crystalline silicon substrate 10' and the second intrinsic amorphous layer 22'.

[0006] In view of this, it is necessary to provide an improved technical solution to solve the above problems. Summary of the Invention

[0007] The present invention aims to solve at least one of the technical problems existing in the prior art. To achieve the above-mentioned purpose, the present invention provides a heterojunction solar cell, the specific design of which is as follows.

[0008] A heterojunction solar cell comprises: a single-crystal silicon substrate having a first main surface and a second main surface arranged opposite to each other, and side surfaces connecting the first main surface and the second main surface, the second main surface comprising a middle region and an edge region surrounding the middle region; a first intrinsic amorphous layer, a first doped amorphous layer, a first transparent conductive film layer, and a first collector arranged in sequence on the first main surface, the first intrinsic amorphous layer covering the first main surface and the side surfaces and extending to the edge region of the second main surface; a second intrinsic amorphous layer, a second doped amorphous layer, a second transparent conductive film layer, and a second collector arranged in sequence on the second main surface, the second doped amorphous layer and the second transparent conductive film layer being located only in the middle region.

[0009] In some embodiments, the first doped amorphous layer and the first transparent conductive film layer both extend to the second main surface and only cover part of the edge region of the second main surface; and / or, the second intrinsic amorphous layer is only located in the middle region of the second main surface, the edges of the second doped amorphous layer and the second transparent conductive film layer are both connected to the second main surface of the single crystal silicon substrate, and the first transparent conductive film layer and the second transparent conductive film layer are spaced apart in the width direction of the edge region.

[0010] In some embodiments, the width of the edge region is 0.1-1.0 mm; or the width of the edge region is 0.2-0.8 mm; or the width of the edge region is 0.3-0.5 mm.

[0011] In some embodiments, the first main surface is the light-receiving surface, and the second main surface is the backlight surface; in the direction from the backlight surface to the light-receiving surface, the first doped amorphous layer sequentially includes a first doped amorphous silicon film and a fifth doped amorphous silicon film located on the surface of the first doped amorphous silicon film, and the fifth doped amorphous silicon film is a doped amorphous silicon oxide film, or a doped amorphous silicon carbide film, or a composite film of doped amorphous silicon carbide and doped amorphous silicon oxide.

[0012] In some embodiments, the carrier concentration of the first doped amorphous silicon film is 5E19-5E21 / cm 3 .

[0013] In some embodiments, the thickness of the first doped amorphous silicon film is 1-5 nm, and / or the thickness of the fifth doped amorphous silicon film is 2-10 nm.

[0014] In some embodiments, the first doped amorphous layer further includes a second doped amorphous silicon film located on the surface of the fifth doped amorphous silicon film, and the carrier concentration of the second doped amorphous silicon film is 5E19-5E21 / cm 3 .

[0015] In some embodiments, the first doped amorphous layer also includes a second doped amorphous silicon film located on the surface of the fifth doped amorphous silicon film, the thickness of the first doped amorphous silicon film is 1-4 nm, and / or the thickness of the fifth doped amorphous silicon film is 1-7 nm, and / or the thickness of the second doped amorphous silicon film is 1-4 nm.

[0016] In some embodiments, the first main surface is a light-receiving surface; in a direction from the light-receiving surface to the backlight surface, the second doped amorphous layer sequentially includes a third doped amorphous silicon film and a fourth doped amorphous silicon film located on the surface of the third doped amorphous silicon film, and the carrier concentration of the third doped amorphous silicon film is 5E18-5E19 / cm 3 , and / or the carrier concentration of the fourth doped amorphous silicon film is 5E19-5E21 / cm 3 .

[0017] In some embodiments, the first main surface is the light-receiving surface; in the direction from the light-receiving surface to the backlight surface, the second doped amorphous layer sequentially includes a third doped amorphous silicon film and a fourth doped amorphous silicon film located on the surface of the third doped amorphous silicon film, the thickness of the third doped amorphous silicon film is 1-5nm, and / or the thickness of the fourth doped amorphous silicon film is 2-15nm.

[0018] In some embodiments, the first main surface is a light-receiving surface, the second main surface is a backlight surface, the first conductive film layer has a thickness of 60-90 nm, and / or the second conductive film layer has a thickness of 80-120 nm.

[0019] In some embodiments, the first main surface is the light-receiving surface; the second main surface is the backlight surface, the sum of the thicknesses of the first intrinsic amorphous layer and the first doped amorphous layer is 6-21 nm, and / or the sum of the thicknesses of the second intrinsic amorphous layer and the second doped amorphous layer is 7-30 nm; and / or the thickness of the first intrinsic amorphous layer located on the first main surface is 3-6 nm, and / or the thickness of the second intrinsic amorphous layer is 4-10 nm; and / or the thickness of the first doped amorphous layer located on the first main surface is 3-15 nm, and / or the thickness of the second doped amorphous layer is 3-20 nm.

[0020] In some embodiments, the first main surface is a light-receiving surface, the second main surface is a backlight surface, the single crystal silicon substrate is n-type single crystal silicon, the first doped amorphous layer is n-type doped amorphous silicon, and the second doped amorphous layer is p-type doped amorphous silicon.

[0021] In some embodiments, the first intrinsic amorphous layer and the second intrinsic amorphous layer respectively include at least two stacked intrinsic films, each of which is composed of one of an intrinsic amorphous silicon film, an intrinsic amorphous silicon oxide film, and an intrinsic amorphous silicon carbide film; the intrinsic film farthest from the single crystal silicon substrate in the first intrinsic amorphous layer and / or the second intrinsic amorphous layer is an intrinsic amorphous silicon oxide film.

[0022] In some embodiments, the first intrinsic amorphous layer and the second intrinsic amorphous layer each include three stacked intrinsic films, and in a direction away from the single crystal silicon substrate, the hydrogen content of the three intrinsic films of the first intrinsic amorphous layer and the second intrinsic amorphous layer ranges from 20% to 40%, 10% to 25%, and 8% to 20%, respectively; and / or the average concentration of hydrogen atoms in the first intrinsic amorphous layer and the second intrinsic amorphous layer is 1e22-5e22 / cm 3 ; and / or, the proportion of bonded hydrogen atoms in the first intrinsic amorphous layer and the second intrinsic amorphous layer to the total hydrogen atoms is 15%-25%; and / or, in the direction away from the single crystal silicon substrate, the thicknesses of the three intrinsic film layers located on the light-receiving surface are 1-3nm, 2-4nm, and 1-3nm, respectively; the thicknesses of the three intrinsic film layers located on the backlight surface are 1-5nm, 3-10nm, and 0-5nm, respectively.

[0023] The beneficial effect of the present invention is that in the heterojunction solar cell structure provided by the present invention, the side surfaces of the single crystal silicon substrate and the edge areas of the second main surface are wrapped by the first intrinsic amorphous layer, which can effectively improve the passivation effect of the surface of the single crystal silicon substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0025] Figure 1 The figure shows a schematic structural diagram of a heterojunction solar cell in the prior art;

[0026] Figure 2 The figure shows a schematic diagram of the state of manufacturing four amorphous silicon layers of a heterojunction solar cell using the prior art;

[0027] Figure 3 Shown is a schematic diagram of the first embodiment of the heterojunction solar cell of the present invention;

[0028] Figure 4 Shown is a schematic diagram of a second embodiment of the heterojunction solar cell of the present invention;

[0029] Figure 5 FIG2 is a schematic diagram showing a third embodiment of the heterojunction solar cell structure of the present invention;

[0030] Figure 6 FIG2 is a schematic diagram showing the structure of a fourth embodiment of a heterojunction solar cell according to the present invention;

[0031] Figure 7 A schematic diagram of a partial structure of a heterojunction solar cell according to the present invention is shown;

[0032] Figure 8 Another partial structural schematic diagram of the heterojunction solar cell of the present invention is shown;

[0033] Figure 9 The figure shows another partial structural diagram of the heterojunction solar cell of the present invention;

[0034] Figure 10 Shown is a schematic diagram of the manufacturing process of the heterojunction solar cell of the present invention.

[0035] In the figure, 10 is a single crystal silicon substrate, 21 is a first intrinsic amorphous layer, 31 is a first doped amorphous layer, 41 is a first conductive film layer, 51 is a first collector, 22 is a second intrinsic amorphous layer, 32 is a second doped amorphous layer, 42 is a second conductive film layer, 52 is a second collector, 201 is a first side passivation portion, 202 is a second side passivation portion, 210 is an intrinsic side portion, 211 is a first intrinsic film, 212 is a second intrinsic film, 2 13 is the third intrinsic film, 221 is the fourth intrinsic film, 222 is the fifth intrinsic film, 223 is the sixth intrinsic film, 310 is the doped side portion, 301 is the first doped amorphous silicon film, 302 is the fifth doped amorphous silicon film, 303 is the second doped amorphous silicon film, 304 is the third doped amorphous silicon film, 305 is the fourth doped amorphous silicon film, 410 is the side portion of the conductive layer, 60 is the through hole, 61 is the supporting portion, and 600 is the first carrier. DETAILED DESCRIPTION

[0036] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0037] refer to Figure 3 As shown, the heterojunction solar cell involved in the present invention includes a single crystal silicon substrate 10, a first intrinsic amorphous layer 21, a first doped amorphous layer 31, a first transparent conductive film layer 41, a first collector 51, a second intrinsic amorphous layer 22, a second doped amorphous layer 32, a second transparent conductive film layer 42, and a second collector 52.

[0038] Specifically, the single crystal silicon substrate 10 has a first main surface and a second main surface that are disposed opposite to each other (i.e., opposite to each other), and a side surface connecting the first main surface and the second main surface. The second main surface includes a middle area and an edge area surrounding the middle area. The thickness of the single crystal silicon substrate 10 is generally 120-180 μm, and the resistivity is generally 0.7 to 3.5 Ω.cm. Figure 3 As shown, the first main surface refers to the upper surface of the single crystal silicon substrate 10 , and the second main surface refers to the lower surface of the single crystal silicon substrate 10 .

[0039] The first intrinsic amorphous layer 21 in the present invention covers the first main surface and the side surface of the single-crystalline silicon substrate 10; the first doped amorphous layer 31 is located on the side surface of the first intrinsic amorphous layer 21 facing away from the single-crystalline silicon substrate 10 and covers the first intrinsic amorphous layer 21; the first transparent conductive film layer 41 is located on the side surface of the first doped amorphous layer 31 facing away from the first intrinsic amorphous layer 21 and covers the first doped amorphous layer 31; the first collector 51 is located on the side surface of the first transparent conductive film layer 41 facing away from the first doped amorphous layer 31.

[0040] refer to Figure 3 As shown in FIG, the portion of the first intrinsic amorphous layer 21 located on the side of the single crystal silicon substrate 10 is the intrinsic layer side portion 210. It can be understood that in the present invention, the first doped amorphous layer 31 covers the first intrinsic amorphous layer 21 and the first transparent conductive film layer 41 covers the first doped amorphous layer 31, which means that both the first doped amorphous layer 31 and the first transparent conductive film layer 41 have portions located outside the side of the single crystal silicon substrate 10 and corresponding to the intrinsic layer side portion 210. Figure 3 As shown in , the first doped amorphous layer 31 has a doped layer side portion 310 covering the outer side of the intrinsic layer side portion 210 , and the first transparent conductive film layer 41 has a conductive layer side portion 410 covering the outer side of the doped layer side portion 310 .

[0041] The second intrinsic amorphous layer 22 in the present invention is located in the middle area of the second main surface of the single crystal silicon substrate 10; the second doped amorphous layer 32 is located on the side surface of the second intrinsic amorphous layer 22 facing away from the single crystal silicon substrate 10; the second transparent conductive film layer 42 is located on the side surface of the second doped amorphous layer 32 facing away from the second intrinsic amorphous layer 22; the second collector 52 is located on the side surface of the second transparent conductive film layer 42 facing away from the second doped amorphous layer 32.

[0042] In the present invention, the doping type of the second doped amorphous layer 32 is opposite to the doping type of the first doped amorphous layer 31. In a specific implementation, the first doped amorphous layer 31 is one of an N-type doped amorphous layer and a P-type doped amorphous layer, and the second doped amorphous layer 32 is the other of the N-type doped amorphous layer and the P-type doped amorphous layer. Specifically, the N-type doped amorphous layer is doped with phosphorus, and the P-type doped amorphous layer is doped with boron.

[0043] In the heterojunction solar cell structure provided by the present invention, the side surfaces of the single crystal silicon substrate 10 are wrapped by the first intrinsic amorphous layer 21 , which can effectively improve the passivation effect of the surface of the single crystal silicon substrate 10 .

[0044] The present invention also provides a method for manufacturing a heterojunction solar cell, which is used to manufacture the above heterojunction solar cell, Figure 10 As shown, it includes:

[0045] A single crystal silicon substrate 10 is provided and placed on a first carrier 600 with its first main surface facing upward. The first carrier 600 includes a body and a through hole 60 defined in the body. The through hole 60 includes a supporting portion 61 for supporting the single crystal silicon substrate 10 and shielding the edge of the second main surface of the single crystal silicon substrate 10. The side length of the through hole 60 located above the supporting portion 61 is greater than the corresponding side length of the single crystal silicon substrate 10.

[0046] Fabricating an amorphous silicon layer: depositing a first intrinsic amorphous layer 21 and a first doped amorphous layer 31 on the first main surface of the single crystal silicon substrate 10 in sequence; and depositing a second intrinsic amorphous layer 22 and a second doped amorphous layer 32 on the second main surface of the single crystal silicon substrate 10 in sequence;

[0047] To fabricate the transparent conductive film layer, a single crystal silicon substrate 10 having an amorphous silicon layer is placed with its first main surface facing upward on a second carrier 700. A first transparent conductive film layer 41 and a second transparent conductive film layer 42 are deposited from the upper and lower sides of the second carrier 700, respectively. It is understood that the second carrier 700 has the same structure as the first carrier 600.

[0048] A collector electrode (not shown) is formed. A first collector electrode 51 is formed on the surface of the first transparent conductive film layer 41 facing away from the first doped amorphous layer 31 . A second collector electrode 52 is formed on the surface of the second transparent conductive film layer 42 facing away from the second doped amorphous layer 32 .

[0049] In the present invention, since the size of the through hole 60 located in the upper area of the supporting portion 61 is larger than the size of the single crystal silicon substrate 10, the first intrinsic amorphous layer 21 and the first doped amorphous layer 31 will extend toward one side of the single crystal silicon substrate 10 during the formation process, thereby forming an intrinsic layer side portion 210 and a doped layer side portion 310 respectively; correspondingly, since the second carrier 700 has the same structure as the first carrier 600, the first transparent conductive film layer 41 will also extend toward one side of the single crystal silicon substrate 10 to form a conductive layer side portion 410.

[0050] It can be understood that the area of the second main surface of the single-crystalline silicon substrate 10 that is blocked by the supporting portion 61 constitutes the edge area of the second main surface. Since the supporting portion 61 blocks the edge area of the second main surface of the single-crystalline silicon substrate 10, the second intrinsic amorphous layer 22 and the second doped amorphous layer 32 can be confined to the middle area of the second main surface; accordingly, the second carrier 700 can also confine the second transparent conductive film layer 42 to the middle area of the second main surface.

[0051] In practice, the four amorphous silicon layers involved in the present invention—the first intrinsic amorphous layer 21, the second intrinsic amorphous layer 22, the first doped amorphous layer 31, and the second doped amorphous layer 32—are all formed using PECVD deposition. The order in which the four amorphous silicon layers are formed can be adjusted as needed. The first transparent conductive film layer 41 and the second transparent conductive film layer 42 involved in the present invention are formed using PVD deposition. The first collector electrode 51 and the second collector electrode 52 involved in the present invention are formed using screen printing.

[0052] Precisely because the molding processes of the four amorphous silicon layers and the first transparent conductive film layer 41 and the second transparent conductive film layer 42 are different, in the specific implementation, the first carrier 600 used to make the four amorphous silicon layers and the second carrier 700 used to make the first transparent conductive film layer 41 and the second transparent conductive film layer 42 are different carriers.

[0053] Based on the structure of the heterojunction solar cell, when the four-layer amorphous silicon layer is specifically manufactured, the flipping action can be avoided by selecting the first carrier 600 having the structure involved in this embodiment. This can avoid the problem of degradation of battery electrical performance caused by pollution introduced by the flipping action in the prior art, and can also shorten the production cycle of the heterojunction solar cell.

[0054] When manufacturing a heterojunction solar cell, preferably, during the amorphous silicon layer formation step, the deposition of the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22 precedes the deposition of the first doped amorphous layer 31 and the second doped amorphous layer 32. This ensures that the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22 have an optimal passivation effect on both sides of the single-crystalline silicon substrate 10, thus avoiding the problem of contamination of one side of the single-crystalline silicon substrate surface by dopant atoms due to process flow limitations in the prior art.

[0055] In some specific embodiments of the present invention, the first intrinsic amorphous layer 21, the first doped amorphous layer 31 and the first transparent conductive film layer 41 all extend to the second main surface of the single crystal silicon substrate 10 and block (or cover) a portion of the edge region of the second main surface. Figure 4 As shown, the first intrinsic amorphous layer 21 has a first intrinsic wrap-around portion 210a that extends to the second main surface of the single-crystalline silicon substrate 10 and blocks a portion of the edge region. The first doped amorphous layer 31 and the first transparent conductive film layer 41 respectively have a first doped wrap-around portion 310a and a first conductive wrap-around portion 410a that correspond to the first intrinsic wrap-around portion 210a. In this embodiment, the first intrinsic amorphous layer 21, the first doped amorphous layer 31, and the first transparent conductive film layer 41 block only a portion of the edge region to prevent electrical conduction between the first transparent conductive film layer 41 and the second transparent conductive film layer 42.

[0056] Specifically for Figure 4 For the embodiment shown, the reason for the formation of the heterojunction cell with this structure is that the edge of the supporting portion of the carrier (for example, the supporting portion 61 of the first carrier 600) is tightly matched with the second main surface of the single crystal silicon substrate 10, and the edge of the single crystal silicon substrate 10 is warped due to gravity. A certain gap will be formed between the edge of the single crystal silicon substrate 10 and the carrier (including the first carrier 600 and the second carrier 700). When the first intrinsic amorphous layer 21, the first doped amorphous layer 31 and the first transparent conductive film layer 41 are formed, they will be plated from the gap to the edge area of the second main surface of the single crystal silicon substrate 10, thereby forming the first intrinsic plating portion 210a, the first doped plating portion 310a and the first conductive plating portion 410a respectively.

[0057] In some other embodiments of the present invention, the edges of the second doped amorphous layer 32 and the second transparent conductive film layer 42 are both connected to the second main surface of the single crystal silicon substrate 10. Figure 5 As shown, the second doped amorphous layer 32 has a second doped bypass portion 320 that bypasses the edge of the second intrinsic amorphous layer 22 and is connected to the second main surface of the single crystal silicon substrate 10, and the second transparent conductive film layer 42 has a second conductive bypass portion 420 that bypasses the edge of the second intrinsic amorphous layer 22 and is connected to the second main surface of the single crystal silicon substrate 10.

[0058] Specifically for Figure 5For the embodiment shown, the reason for the formation of the heterojunction cell with this structure is that the edge of the single crystal silicon substrate 10 and the supporting part of the carrier (for example, the supporting part 61 of the first carrier 600) fit tightly together. When the first intrinsic amorphous layer 21, the first doped amorphous layer 31 and the first transparent conductive film layer 41 are formed on the single crystal silicon substrate 10, the tension of each layer causes the single crystal silicon substrate 10 to deform in the normal direction of its first main surface (arch upward), thereby causing a certain gap to be generated between the edge of the supporting part of the carrier (for example, the supporting part 61 of the first carrier 600) and the single crystal silicon substrate 10. When the second doped amorphous layer 32 and the second transparent conductive film layer 42 are produced, the second doped wrap-around portion 320 and the second conductive wrap-around portion 420 connected to the second main surface of the single crystal silicon substrate 10 are respectively formed through the gap.

[0059] Of course, it is understood that in some embodiments of the present invention, there may be Figure 6 The heterojunction solar cell with the structure shown, i.e., the first intrinsic amorphous layer 21, the first doped amorphous layer 31, and the first transparent conductive film layer 41, all extend to the second main surface of the single-crystalline silicon substrate 10 and block (cover) part of the edge region of the second main surface. The edges of the second doped amorphous layer 32 and the second transparent conductive film layer 42 are also connected to the second main surface of the single-crystalline silicon substrate 10. The reason for the formation of such a heterojunction solar cell structure is that the matching relationship between the single-crystalline silicon substrate 10 and the supporting portion of the carrier (e.g., the supporting portion 61 of the first carrier 600) is affected by both gravity and film tension. Specifically, the relationship between the first intrinsic amorphous layer 21, the first doped amorphous layer 31, and the first transparent conductive film layer 41 all extend to the second main surface of the single-crystalline silicon substrate 10 and block (cover) part of the edge region of the second main surface. The edges of the second doped amorphous layer 32 and the second transparent conductive film layer 42 are also connected to the second main surface of the single-crystalline silicon substrate 10. Figure 4 、 Figure 5 The description of the implementation structure will not be repeated here.

[0060] In the present invention, combined with Figure 3 As shown, the width d of the edge region of the second main surface of the single crystal silicon substrate 10 is 0.1-1.0 mm. Preferably, the width d of the edge region is 0.2-0.8 mm. Furthermore, the width d of the edge region is 0.3-0.5 mm.

[0061] As a preferred embodiment of the present invention, the first main surface of the single crystal silicon substrate 10 is the light-receiving surface, and the second main surface is the backlight surface.

[0062] Although the single crystal silicon substrate 10 can be a p-type single crystal silicon substrate or an n-type single crystal silicon substrate, as a preferred embodiment of the present invention, the single crystal silicon substrate 10 is an n-type single crystal silicon substrate. Further preferably, the first doped amorphous layer 31 is n-type doped amorphous silicon, and the second doped amorphous layer 32 is p-type doped amorphous silicon.

[0063] In some embodiments of the present invention, the sum of the thicknesses of the first intrinsic amorphous layer 21 and the first doped amorphous layer 31 on the first main surface is less than or equal to the sum of the thicknesses of the second intrinsic amorphous layer 22 and the second doped amorphous layer 32. Preferably, the sum of the thicknesses of the first intrinsic amorphous layer 21 and the first doped amorphous layer 31 on the first main surface is less than the sum of the thicknesses of the second intrinsic amorphous layer 22 and the second doped amorphous layer 32.

[0064] For heterojunction solar cells, the light absorption effect of the light-receiving surface has a much greater impact on the photoelectric conversion efficiency of the cell than the light absorption effect of the backlight surface. Since the sum of the thicknesses of the first intrinsic amorphous layer 21 and the first doped amorphous layer 31 located on the first main surface is less than or equal to the sum of the thicknesses of the second intrinsic amorphous layer 22 and the second doped amorphous layer 32, the loss of sunlight when entering the light-receiving surface can be effectively reduced, the short-circuit current of the heterojunction solar cell can be increased, and the heterojunction solar cell has better photoelectric conversion efficiency.

[0065] More specifically, the sum of the thicknesses of the first intrinsic amorphous layer 21 and the first doped amorphous layer 31 is 6-21 nm, and the sum of the thicknesses of the second intrinsic amorphous layer 22 and the second doped amorphous layer 32 is 7-30 nm.

[0066] In some other embodiments of the present invention, the thickness of the first intrinsic amorphous layer 21 on the first main surface is less than or equal to the thickness of the second intrinsic amorphous layer 22. Preferably, the thickness of the first intrinsic amorphous layer 21 on the first main surface is less than the thickness of the second intrinsic amorphous layer 22. In a specific implementation, the thickness of the first intrinsic amorphous layer 21 on the first main surface is 3-6 nm, and the thickness of the second intrinsic amorphous layer 22 is 4-10 nm.

[0067] Furthermore, in the present invention, the thickness of the first doped amorphous layer 31 on the first main surface is less than or equal to the thickness of the second doped amorphous layer 32. Preferably, the thickness of the first doped amorphous layer 31 is less than the thickness of the second doped amorphous layer 32. In a specific implementation, the thickness of the first doped amorphous layer 31 is 3-15 nm, and the thickness of the second doped amorphous layer 32 is 3-20 nm.

[0068] Preferably, the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22 involved in the present invention respectively include at least two stacked intrinsic films, and each intrinsic film layer is composed of one of an intrinsic amorphous silicon film, an intrinsic amorphous silicon oxide film, and an intrinsic amorphous silicon carbide film.

[0069] refer to Figure 7As shown, the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22 involved in this specific embodiment each include three stacked intrinsic films. Specifically, in the direction away from the single-crystalline silicon substrate 10, the first intrinsic amorphous layer 21 includes, in sequence, a first intrinsic film 211, a second intrinsic film 212, and a third intrinsic film 213, and the second intrinsic amorphous layer 22 includes, in sequence, a fourth intrinsic film 221, a fifth intrinsic film 222, and a sixth intrinsic film 223. It will be understood that in other embodiments of the present invention, the number of film layers in the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22 is not limited to a three-layer structure.

[0070] In the present invention, since the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22 both include at least two stacked intrinsic films, in the specific implementation process, it is convenient to control the characteristics of each film layer to form the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22 with better comprehensive performance.

[0071] As a preferred embodiment of the present invention, in a specific implementation process, the intrinsic film layer farthest from the single crystal silicon substrate 10 in the first intrinsic amorphous layer 21 is set to be an intrinsic amorphous silicon oxide film. Figure 7 As shown, in this embodiment, the third intrinsic film 213 is the intrinsic film layer in the first intrinsic amorphous layer 21 that is farthest from the single crystal silicon substrate 10. In this embodiment, the third intrinsic film 213 is preferably an intrinsic amorphous silicon oxide film. It will be understood that in other embodiments of the present invention, the intrinsic film layer in the second intrinsic amorphous layer 22 that is farthest from the single crystal silicon substrate 10 may also be an intrinsic amorphous silicon oxide film. That is, the sixth intrinsic film 223 that is farthest from the single crystal silicon substrate 10 in this embodiment may be an intrinsic amorphous silicon oxide film.

[0072] The passivation effect of the intrinsic amorphous silicon oxide film is worse than that of the intrinsic amorphous silicon film and the intrinsic amorphous silicon carbide film, but it has better light transmittance than the intrinsic amorphous silicon film and the intrinsic amorphous silicon carbide film. In the heterojunction solar cell, the intrinsic film farthest from the single crystal silicon substrate 10 in the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22 has limited passivation effect on the single crystal silicon substrate 10 due to the distance. Setting it as the intrinsic amorphous silicon oxide film with the best light transmittance can optimize the photoelectric conversion efficiency of the heterojunction solar cell to a certain extent.

[0073] As a further preference of the present invention, in the present invention, the hydrogen content of the intrinsic film close to the single crystal silicon substrate 10 in the first intrinsic amorphous layer 21 is higher than the hydrogen content of the intrinsic film far away from the single crystal silicon substrate, and the hydrogen content of the intrinsic film close to the single crystal silicon substrate 10 in the second intrinsic amorphous layer 22 is higher than the hydrogen content of the intrinsic film far away from the single crystal silicon substrate.

[0074] refer to Figure 7As shown, in this embodiment, the hydrogen contents of the first intrinsic film 211, the second intrinsic film 212, and the third intrinsic film 213 in the first intrinsic amorphous layer 21 decrease in sequence, and the hydrogen contents of the fourth intrinsic film 221, the fifth intrinsic film 222, and the sixth intrinsic film 223 in the second intrinsic amorphous layer 22 also decrease in sequence. It is easy to understand that the closer the intrinsic film is to the single-crystalline silicon substrate 10 in the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22, the more significant its passivation effect on the single-crystalline silicon substrate 10. The first intrinsic film 211 and the fourth intrinsic film 221 are both directly attached to the single-crystalline silicon substrate 10 and have the highest hydrogen content, which enables the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22 to have the best passivation effect on the single-crystalline silicon substrate 10.

[0075] As a preferred embodiment of the present invention, when the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22 each include three stacked intrinsic films, the hydrogen content of the three intrinsic films of the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22 is in the range of 20%-40%, 10%-25%, and 8%-20% in the direction away from the single crystal silicon substrate 10. That is, the hydrogen content of the first intrinsic film 211 and the fourth intrinsic film 221 is in the range of 20%-40%, the hydrogen content of the second intrinsic film 212 and the fifth intrinsic film 222 is in the range of 10%-25%, and the hydrogen content of the third intrinsic film 213 and the sixth intrinsic film 223 is in the range of 8%-20%.

[0076] More preferably, Figure 7 In the embodiment, the hydrogen content of the first intrinsic film 211 and the fourth intrinsic film 221 ranges from 24% to 30%, the hydrogen content of the second intrinsic film 212 and the fifth intrinsic film 222 ranges from 12% to 18%, and the hydrogen content of the third intrinsic film 213 and the sixth intrinsic film 223 ranges from 10% to 15%.

[0077] As the present invention Figure 7 It is further preferred that, when the first main surface of the single crystal silicon substrate 10 is the light-receiving surface, the thickness ranges of the first intrinsic film 211, the second intrinsic film 212 and the third intrinsic film 213 in the first intrinsic amorphous layer 21 are 1-3nm, 2-4nm and 1-3nm respectively, and the thickness ranges of the fourth intrinsic film 221, the fifth intrinsic film 222 and the sixth intrinsic film 223 in the second intrinsic amorphous layer 22 are 1-5nm, 3-10nm and 0-5nm respectively.

[0078] Correspondingly, it can be understood that when the first main surface of the single-crystal silicon substrate 10 is the backlight surface, the thickness ranges of the fourth intrinsic film 221, the fifth intrinsic film 222 and the sixth intrinsic film 223 in the second intrinsic amorphous layer 22 are 1-3nm, 2-4nm, and 1-3nm, respectively, and the thickness ranges of the first intrinsic film 211, the second intrinsic film 212 and the third intrinsic film 213 in the first intrinsic amorphous layer 21 are 1-5nm, 3-10nm, and 0-5nm, respectively.

[0079] As a further preferred embodiment, the proportion of bonded hydrogen atoms in the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22 involved in the present invention is 15%-25% of the total hydrogen atoms. Bonded hydrogen atoms play a decisive role in the specific passivation effect. In the prior art, the proportion of bonded hydrogen atoms in the intrinsic amorphous layer is typically around 10%. By increasing the proportion of bonded hydrogen atoms in the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22, the present invention can also improve the passivation effect of the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22 on the surface of the single-crystalline silicon substrate 10, thereby further increasing the open-circuit voltage of the corresponding heterojunction solar cell.

[0080] In some other embodiments of the present invention, the average concentration of hydrogen atoms in the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22 is 1e22-5e22 / cm 3 ; preferably 2.5e22-5e22 / cm 3 The concentration of hydrogen atoms in the intrinsic amorphous silicon layer of heterojunction solar cells in the prior art is usually less than 1e22 atoms / cm 3 The low concentration of hydrogen atoms results in a poor passivation effect on the intrinsic amorphous silicon layer. In the present invention, by increasing the hydrogen atom concentration in the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22, the passivation effect of the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22 on the surface of the single-crystalline silicon substrate 10 can be effectively improved, thereby increasing the open-circuit voltage of the corresponding heterojunction solar cell.

[0081] As a further specific embodiment of the present invention, refer to Figure 8 As shown, in the direction from the backlight surface to the light-receiving surface, the first doped amorphous layer 31 includes a first doped amorphous silicon film 301 located on the surface of the first intrinsic amorphous layer 21 and a fifth doped amorphous silicon film 302 located on the surface of the first doped amorphous silicon film 301. The fifth doped amorphous silicon film 302 is one of a doped amorphous silicon oxide film, a doped amorphous silicon carbide film, or a doped amorphous silicon carbide / doped amorphous silicon oxide composite film. It is relatively easy to understand that the doped amorphous silicon carbide / doped amorphous silicon oxide composite film refers to a film layer composed of a doped amorphous silicon oxide film and a doped amorphous silicon carbide film.

[0082] Doped amorphous silicon oxide and doped amorphous silicon carbide have superior light transmittance compared to doped amorphous silicon. The first doped amorphous layer 31' in the prior art is typically a single-layer doped amorphous silicon film structure; in this embodiment, the first doped amorphous layer 31 utilizes a double-layer design. The first doped amorphous silicon film 301 ensures good contact between the first doped amorphous layer 31 and the first intrinsic amorphous layer 21, while the fifth doped amorphous silicon film 302 replaces the partially doped amorphous silicon in the prior art with highly transmittant doped amorphous silicon oxide or doped amorphous silicon carbide. This improves the overall light transmittance of the first doped amorphous layer 31. The combination of the first doped amorphous silicon film 301 and the fifth doped amorphous silicon film 302 results in a heterojunction solar cell with even better performance.

[0083] exist Figure 8 In the illustrated embodiment, preferably, the thickness of the first doped amorphous silicon film 301 is generally less than the thickness of the fifth doped amorphous silicon film 302. This ensures good contact between the first doped amorphous layer 31 and the first intrinsic amorphous layer 21 while also greatly enhancing the light transmittance of the first doped amorphous layer 31.

[0084] In a specific implementation process, the thickness of the fifth doped amorphous silicon film 302 is 2-10 nm, and correspondingly, the thickness of the first doped amorphous silicon film 301 is 1-5 nm.

[0085] To ensure good contact between the first doped amorphous layer 31 and the first intrinsic amorphous layer 21, the first doped amorphous silicon film 301 is a highly doped film with a carrier concentration of 5E19-5E21 / cm 3 .

[0086] In other embodiments of the present invention, reference Figure 9 As shown, the first doped amorphous layer 31 further includes a second doped amorphous silicon film 303 located on the surface of the fifth doped amorphous silicon film 302. Doped amorphous silicon generally has relatively good electrical conductivity. Figure 9 The second doped amorphous silicon film 303 in the embodiment shown can provide better contact between the first doped amorphous layer 31 and the first transparent conductive film layer 41. Figure 8 The illustrated embodiment can reduce contact resistance, thereby enabling a higher fill factor for heterojunction solar cells.

[0087] exist Figure 9In the illustrated embodiment, the thickness of the second doped amorphous silicon film 303 is also typically less than the thickness of the fifth doped amorphous silicon film 302, thereby ensuring that the first doped amorphous layer 31 has good light transmittance. In a specific implementation, the thickness of the first doped amorphous silicon film 301 is 1-4 nm, the thickness of the fifth doped amorphous silicon film 302 is 1-7 nm, and the thickness of the second doped amorphous silicon film 303 is 1-4 nm.

[0088] To ensure good contact between the first doped amorphous layer 31 and the first transparent conductive film layer 41, the second doped amorphous silicon film 303 is also a highly doped film with a carrier concentration of 5E19-5E21 / cm 3 .

[0089] refer to Figure 8 、 Figure 9 As shown, in some further embodiments of the present invention, the second doped amorphous layer 32 includes a third doped amorphous silicon film 304 located on the surface of the second intrinsic amorphous layer 22 and a fourth doped amorphous silicon film 305 located on the surface of the third doped amorphous silicon film 304 and having a doping concentration greater than that of the third doped amorphous silicon film 304.

[0090] Preferably, the carrier concentration of the third doped amorphous silicon film 304 is 5E18-5E19 / cm 3 The carrier concentration of the fourth doped amorphous silicon film 305 is 5E19-5E21 / cm 3 .

[0091] exist Figure 8 、 Figure 9 In the illustrated embodiment, the third doped amorphous silicon film 304, due to its relatively low doping concentration, can reduce the impact on the second intrinsic amorphous layer 22, reduce the lattice distortion of the second intrinsic amorphous layer 22, and effectively ensure the passivation effect of the backlight surface of the heterojunction solar cell; the fourth doped amorphous silicon film 305, due to its relatively high doping concentration, can improve the contact between the second doped amorphous layer 32 and the second transparent conductive film, reduce the contact resistance between the two, and improve the cell fill factor.

[0092] Preferably, the thickness of the third doped amorphous silicon film 304 is generally smaller than that of the fourth doped amorphous silicon film 305. In a specific implementation, the thickness of the third doped amorphous silicon film 304 is 1-5 nm, and the thickness of the fourth doped amorphous silicon film 305 is 2-15 nm.

[0093] In the present invention, the thickness of the first conductive film layer 41 is generally less than or equal to the thickness of the second conductive film layer 42. In a specific implementation, the thickness of the first conductive film layer 41 is 60-90 nm, and the thickness of the second conductive film layer 42 is 80-120 nm. In addition, both the first conductive film layer 41 and the second conductive film layer 42 can be made of tin-doped indium oxide film (ITO) or tungsten-doped indium oxide film (IWO).

[0094] In the present invention, the more detailed design structures of the first collector 51 and the second collector 52 can be referred to the prior art and will not be described in detail here.

[0095] To better understand the present invention, the following also illustrates a specific method for fabricating four amorphous silicon layers in a heterojunction solar cell: pure SiH4 is first introduced into the side facing the first main surface of the single-crystalline silicon substrate 10, followed by SiH4 diluted with H2, to grow a first intrinsic amorphous layer 21 under the action of a 13.56 MHz radio frequency power supply; then, pure SiH4 is first introduced into the side facing the second main surface of the single-crystalline silicon substrate 10, followed by SiH4 diluted with H2, to grow a second intrinsic amorphous layer 22 under the action of a 13.56 MHz radio frequency power supply; then, PH3, SiH4, and H2 are introduced into the side facing the first main surface of the single-crystalline silicon substrate 10 to fabricate a first doped amorphous layer 31; finally, B2H6, SiH4, and H2 are introduced into the side facing the second main surface of the single-crystalline silicon substrate 10 to fabricate a second doped amorphous layer 32.

[0096] It can be understood that the first intrinsic amorphous layer 21, the second intrinsic amorphous layer 22, the first doped amorphous layer 31 and the second doped amorphous layer 32 are respectively produced and formed in different coating chambers; in addition, during the four-layer amorphous film coating process, the single crystal silicon substrate 10 is loaded on the first carrier 600 in the same state, and there is no need to flip the single crystal silicon substrate 10 during the process, which can effectively avoid the problem of contamination introduced by the flipping action in the conventional amorphous silicon layer coating process.

[0097] In addition, during the deposition of the four amorphous silicon layers, the temperature and pressure of the deposition chambers involved need to reach predetermined values before the deposition of the corresponding amorphous silicon layers. Typically, the temperature is 180°C, and the pressure is controlled at 30-200 Pa.

[0098] In order to optimize the passivation effect of the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22 on the single crystal silicon substrate 10, during the specific production process of the first intrinsic amorphous layer 21 and the second intrinsic amorphous layer 22, when SiH4 diluted with H2 is introduced, the dilution ratio of H2 / SiH4 can be adjusted, thereby adjusting the preparation of a multi-layer morphology film, for example, 2-6 layers. Typically, the dilution ratio of H2 / SiH4 ranges from 5 to 250.

[0099] When forming the first doped amorphous layer 31 and the second doped amorphous layer 32 , CO 2 or CH 4 may be introduced into the corresponding coating chamber, thereby making the first doped amorphous layer 31 and the second doped amorphous layer 32 formed of amorphous silicon oxide or amorphous silicon carbide.

[0100] It should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation method can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

[0101] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A heterojunction solar cell, characterized in that: include: a single crystal silicon substrate having a first main surface and a second main surface disposed opposite to each other, and a side surface connecting the first main surface and the second main surface, wherein the second main surface includes a middle region and an edge region surrounding the middle region; A first intrinsic amorphous layer, a first doped amorphous layer, a first transparent conductive film layer, and a first collector electrode are sequentially arranged on the first main surface, wherein the first intrinsic amorphous layer covers the first main surface and the side surface and extends to the edge region of the second main surface; A second intrinsic amorphous layer, a second doped amorphous layer, a second transparent conductive film layer and a second collector are sequentially arranged on the second main surface, and the second doped amorphous layer and the second transparent conductive film layer are only located in the middle area.

2. The heterojunction solar cell according to claim 1, wherein: The first doped amorphous layer and the first transparent conductive film layer both extend to the second main surface and only cover a portion of the edge region of the second main surface; And / or, the second intrinsic amorphous layer is only located in the middle area of the second main surface, the edges of the second doped amorphous layer and the second transparent conductive film layer are both connected to the second main surface of the single crystal silicon substrate, and the first transparent conductive film layer and the second transparent conductive film layer are spaced apart in the width direction of the edge area.

3. The heterojunction solar cell according to claim 1, wherein: The width of the edge region is 0.1-1.0 mm; or the width of the edge region is 0.2-0.8 mm; or the width of the edge region is 0.3-0.5 mm.

4. The heterojunction solar cell according to claim 1, wherein: The first main surface is the light-receiving surface, and the second main surface is the backlight surface; in the direction from the backlight surface to the light-receiving surface, the first doped amorphous layer sequentially includes a first doped amorphous silicon film and a fifth doped amorphous silicon film located on the surface of the first doped amorphous silicon film, and the fifth doped amorphous silicon film is a doped amorphous silicon oxide film, or a doped amorphous silicon carbide film, or a composite film of doped amorphous silicon carbide and doped amorphous silicon oxide.

5. The heterojunction solar cell according to claim 4, characterized in that: The carrier concentration of the first doped amorphous silicon film is 5E19-5E21 / cm 3 .

6. The heterojunction solar cell according to claim 4, characterized in that: The thickness of the first doped amorphous silicon film is 1-5 nm, and / or the thickness of the fifth doped amorphous silicon film is 2-10 nm.

7. The heterojunction solar cell according to claim 4, characterized in that: The first doped amorphous layer further includes a second doped amorphous silicon film located on the surface of the fifth doped amorphous silicon film, and the carrier concentration of the second doped amorphous silicon film is 5E19-5E21 / cm 3 .

8. The heterojunction solar cell according to claim 4, characterized in that: The first doped amorphous layer also includes a second doped amorphous silicon film located on the surface of the fifth doped amorphous silicon film, the thickness of the first doped amorphous silicon film is 1-4nm, and / or the thickness of the fifth doped amorphous silicon film is 1-7nm, and / or the thickness of the second doped amorphous silicon film is 1-4nm.

9. The heterojunction solar cell according to claim 1, characterized in that: The first main surface is a light-receiving surface; in the direction from the light-receiving surface to the backlight surface, the second doped amorphous layer includes a third doped amorphous silicon film and a fourth doped amorphous silicon film located on the surface of the third doped amorphous silicon film, and the carrier concentration of the third doped amorphous silicon film is 5E18-5E19 / cm 3 , and / or the carrier concentration of the fourth doped amorphous silicon film is 5E19-5E21 / cm 3 .

10. The heterojunction solar cell according to claim 1, characterized in that: The first main surface is the light-receiving surface; in the direction from the light-receiving surface to the backlight surface, the second doped amorphous layer sequentially includes a third doped amorphous silicon film and a fourth doped amorphous silicon film located on the surface of the third doped amorphous silicon film, the thickness of the third doped amorphous silicon film is 1-5nm, and / or the thickness of the fourth doped amorphous silicon film is 2-15nm.

11. The heterojunction solar cell according to claim 1, characterized in that: The first main surface is a light-receiving surface, the second main surface is a backlight surface, the thickness of the first conductive film layer is 60-90 nm, and / or the thickness of the second conductive film layer is 80-120 nm.

12. The heterojunction solar cell according to claim 1, wherein: The first main surface is a light-receiving surface; the second main surface is a backlight surface; the sum of the thicknesses of the first intrinsic amorphous layer and the first doped amorphous layer is 6-21 nm, and / or the sum of the thicknesses of the second intrinsic amorphous layer and the second doped amorphous layer is 7-30 nm; and / or the thickness of the first intrinsic amorphous layer on the first main surface is 3-6 nm, and / or the thickness of the second intrinsic amorphous layer is 4-10 nm; And / or, the thickness of the first doped amorphous layer on the first main surface is 3-15 nm, and / or the thickness of the second doped amorphous layer is 3-20 nm.

13. The heterojunction solar cell according to any one of claims 1 to 12, characterized in that: The first main surface is a light-receiving surface, the second main surface is a backlight surface, the single crystal silicon substrate is n-type single crystal silicon, the first doped amorphous layer is n-type doped amorphous silicon, and the second doped amorphous layer is p-type doped amorphous silicon.

14. The heterojunction solar cell according to any one of claims 1 to 12, characterized in that: The first intrinsic amorphous layer and the second intrinsic amorphous layer respectively include at least two stacked intrinsic films, each of which is composed of one of an intrinsic amorphous silicon film, an intrinsic amorphous silicon oxide film, and an intrinsic amorphous silicon carbide film; the intrinsic film farthest from the single crystal silicon substrate in the first intrinsic amorphous layer and / or the second intrinsic amorphous layer is an intrinsic amorphous silicon oxide film.

15. The heterojunction solar cell according to any one of claims 1 to 12, characterized in that: The first intrinsic amorphous layer and the second intrinsic amorphous layer each include three stacked intrinsic films, and in a direction away from the single crystal silicon substrate, the hydrogen content of the three intrinsic films of the first intrinsic amorphous layer and the second intrinsic amorphous layer are in the range of 20%-40%, 10%-25%, and 8%-20% respectively; And / or, the average concentration of hydrogen atoms in the first intrinsic amorphous layer and the second intrinsic amorphous layer is 1e22-5e22 / cm 3 ; and / or, the proportion of bonded hydrogen atoms in the first intrinsic amorphous layer and the second intrinsic amorphous layer to the total hydrogen atoms is 15%-25%; And / or, in the direction away from the single crystal silicon substrate, the thicknesses of the three intrinsic films on the light-receiving surface are 1-3nm, 2-4nm, and 1-3nm respectively; the thicknesses of the three intrinsic films on the backlight surface are 1-5nm, 3-10nm, and 0-5nm respectively.

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