Flip LED chip and manufacturing method thereof

Abstract

The invention provides a flip LED chip and a manufacturing method thereof. According to the method, a traditional slender flip LED chip is designed and optimized to be of a wide and short structure, the layout of slender strip-shaped P / N electrode bonding pads is adopted, and the distance between the two electrode bonding pads is controlled to be 50-250 micrometers. The specific process comprises the steps of growing an LED epitaxial structure on a patterned substrate, forming an MESA, determining the size of a chip, sequentially preparing a transparent conductive layer, a medium reflecting layer and a metal reflecting layer, and improving the light emitting efficiency; and then depositing a double-layer insulating passivation layer and windowing, and manufacturing a two-stage metal electrode to form a P / N bonding pad. Through the design, the stress distribution of the chip is more uniform, the crystal breaking risk caused by stress concentration in the solid crystal packaging process is greatly reduced, meanwhile, the tin connection short circuit is avoided through the moderate bonding pad distance, and the reliability and the product yield of the LED chip are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor light-emitting devices, and in particular to a flip-chip LED chip and a manufacturing method thereof. Background Art

[0002] With the continuous advancement of display and lighting technologies, the demand for high-efficiency, compact light sources in edge-lit backlights is increasing. Flip-chip LED chips, as an innovative form of LED packaging, have demonstrated significant advantages in the backlighting field. Compared to traditional upright LED chips, flip-chip LEDs eliminate gold wire bonding. Light is emitted directly from the bottom of the chip and refracted upward by a reflective layer. This results in higher light extraction efficiency and more uniform light distribution. It also simplifies the packaging process and enhances heat dissipation, thereby extending the device's lifespan. However, existing flip-chip LED chip designs mostly follow the structural principles of upright chips, resulting in an elongated chip shape (with a high aspect ratio, such as 1:2 or greater). For example, a conventional flip-chip LED chip measures approximately 220 × 1145 μm and is shaped like a long, narrow strip. During the die bonding and subsequent packaging processes, such an elongated chip structure is prone to stress concentration under external forces, particularly in the central region of the chip where the pads are spaced apart, which can easily lead to wafer fracture (crystal breakage). Crystal breakage not only leads to chip failure and reduced product yield, but also seriously affects the reliability and service life of the LED module. In addition, in order to reduce the risk of breakage, reducing the distance between the P / N pads is an intuitive idea, but too small a distance between the pads will create the hidden danger of tin short circuit during reflow soldering.

[0003] Therefore, how to optimize the structural design of flip-chip LED chips to alleviate stress concentration and avoid crystal breakage while taking into account the safe spacing of solder pad layout has become a technical problem that needs to be solved urgently in this field. Summary of the Invention

[0004] In response to the aforementioned issues with wafer breakage and pad placement in flip-chip LED chips, the present invention aims to provide an improved flip-chip LED chip fabrication method and structural design. By optimizing the chip shape and electrode pad layout, this method achieves uniform force distribution, reducing mechanical stress concentration during chip packaging, significantly reducing the incidence of wafer breakage while ensuring reliable electrode pad soldering.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] In one aspect, the present invention provides a method for fabricating a flip-chip LED chip. This method sequentially fabricates each functional layer on a patterned substrate, specifically optimizing the chip's geometry and electrode layout. The method includes, but is not limited to, the following steps:

[0007] Epitaxial Growth: The LED structure is grown epitaxially on a patterned sapphire substrate, sequentially forming an N-type GaN layer, multiple quantum well active light-emitting layers, and a P-type GaN layer. This epitaxial structure forms the base layer of the LED chip.

[0008] MESA etching: The epitaxial layer is subjected to photolithography and MESA etching, and a ring or isolation groove is etched in the P-type region to expose the local N-type GaN layer as the N-electrode contact area, and the final size and shape of the chip are defined by the etched area. Unlike the traditional design, the chip layout is designed as a wide and short structure in this step, that is, the chip length is shortened and the width is increased relative to the existing slender design. For example, the traditional chip layout with a size of approximately 220×1145μm can be adjusted to approximately 1145×220μm. This change in geometric structure helps to improve the mechanical strength of the chip itself and reduce the bending stress of the chip when it is subjected to force.

[0009] Insulation isolation (ISO): Deep etching is performed in the chip's cut area (street area), partially penetrating the substrate or etching to a certain depth to form an insulation isolation structure. This step helps reduce stress concentration in the chip edge area and provides a stress buffer area for subsequent chip separation.

[0010] Transparent conductive layer fabrication: A transparent conductive layer is deposited on the P-type GaN surface to serve as the ohmic contact layer for the P-electrode. This transparent conductive layer can be a continuous film or a patterned grid / island distribution to maximize the transmission of outgoing light while ensuring uniform carrier injection. Preferably, the transparent conductive layer material is a transparent conductive oxide such as ITO (indium tin oxide) or zinc oxide, with a thickness of approximately 5–200 nm. This transparent electrode layer forms an electrical connection with the subsequent metal reflective electrode and reduces the P-type GaN contact resistance.

[0011] Reflective layer fabrication: A reflective layer is formed on the transparent conductive layer to improve the chip's upward light extraction efficiency. The reflective layer is preferably a stacked structure consisting of a non-metallic dielectric reflective layer and a metal reflective layer. First, a dielectric reflective layer is deposited on the transparent conductive layer. This can be a low-refractive-index dielectric thin film (e.g., 50–5000 nm thick) such as SiO2, MgF2, or Al2O3, or a distributed Bragg reflector (DBR) multilayer film (≥3 film pairs) formed by alternating deposition of high- and low-refractive-index materials. This dielectric reflective layer is used to reflect light in areas where it does not affect electrical conductivity and acts as an insulating layer to isolate subsequent metal layers from direct contact with the P-type layer. Next, a metallic conductive reflective layer is deposited on the dielectric reflective layer through pre-patterned openings. This metal conductive reflective layer connects to the underlying transparent conductive layer through the openings, thereby electrically connecting to the P-type GaN. The metal reflective layer is preferably made of highly reflective silver (Ag) or aluminum (Al), with a thickness greater than 80 nm to ensure sufficient reflectivity and conductivity. To improve the adhesion and stability of the metal reflective layer, a thin layer (<10nm) of adhesion metal (such as Cr, Ti or Ni) can be sputtered before depositing Ag / Al, and a protective film (such as Ni, TiW, Pt, etc.) can be covered on the Ag / Al to prevent the reflective layer from being oxidized or damaged in subsequent processes.

[0012] Deposition of the first passivation layer: After the reflective layer structure is completed, a dielectric insulating passivation layer (the first passivation layer) is deposited across the entire chip surface. This passivation layer can be made of one or more of Al2O3, SiO2, or Si3N4, with a deposition temperature of approximately 150–300°C and a thickness of 200–2000nm. The passivation layer covers the entire chip surface, including the metal reflective layer and the exposed edge of the N-type contact area. Subsequently, windows (vias) are created in the first passivation layer through photolithography and etching. One window exposes the metal reflective layer or a portion of its protective layer in the P-type region, serving as a P-electrode connection hole; another window exposes the N-type GaN contact region (the N-region mesa formed by MESA etching), serving as an N-electrode connection hole. If necessary, the passivation layer can also utilize a multilayer dielectric film (such as a DBR structure) to achieve both insulation and light reflection functions. The number of layers should be ≥3, with a thickness of 100nm–6000nm.

[0013] Preparation of the first metal electrode layer: A metal layer is deposited on the surface of the first passivation layer by sputtering or electroplating, and is contacted with the P and N electrode connection areas through the aforementioned through-holes to form the first layer of metal electrodes. This first electrode layer realizes the lead-out of the P-type and N-type regions inside the chip. The material can be selected from single-layer or multi-layer metal stacks such as Cr, Al, Ti, Pt, Ni, Au, etc. The total thickness can be 50nm to 5000nm (the thickness can be appropriately increased to reduce resistance according to design requirements). Among them, a part of the metal fills and contacts the P-region through-hole, connects to the metal reflective layer, and is thereby electrically connected to the P-type semiconductor layer; the other part of the metal fills the N-region through-hole and directly contacts the N-type GaN layer table. The pattern of the first electrode layer can be designed to cover most of the area above the P and N regions, providing a good bottom connection for the next layer of electrodes.

[0014] Second passivation layer deposition: A dielectric insulating passivation layer (second passivation layer) is deposited on top of the first metal electrode layer. The material can be SiO2 or Si3N4, with a thickness of approximately 200–2000 nm. This second passivation layer covers and protects the first electrode layer and smoothes the chip surface. Subsequently, pad windows are created in the second passivation layer through photolithography, exposing the locations of the corresponding P and N electrodes in the first electrode layer. The shape and size of these windows will determine the final shape of the external pads. This passivation layer can also use the same DBR structure as the first passivation layer. Second metal electrode layer (pad) fabrication: A thicker metal layer is deposited on the windowed second passivation layer to form the flip-chip's external pads (i.e., the P and N electrode pads). The metal in this second electrode layer can include Cr, Ni, Au, etc., and a Sn or AuSn alloy layer can be introduced to facilitate eutectic bonding to the package substrate. Typically, the second metal electrode layer is at least 1–5 μm thick to provide sufficient mechanical strength and solder wettability. If necessary, an appropriate amount of Au-Sn solder or prefabricated solder balls (thickness / diameter, for example, 1–100 μm) can be prepared on its surface to enable flip-chip bonding of the chip. Patterning of the second metal electrode layer ultimately forms two independent electrode pads: a P-electrode pad and an N-electrode pad.

[0015] In the above manufacturing method, the key improvement of the present invention lies in the chip layout design and electrode pad layout. By making the chip into a wide and short size during the MESA etching stage, and designing the flip-chip pads into a long strip shape and controlling their spacing during the electrode metallization stage, the chip's stress structure is optimized. Figure 2As shown, in the top-down structure of the flip-chip LED chip of the present invention, the chip is a wide and short rectangle, and two long strip-shaped pads (P pad 21 and N pad 22) are roughly parallel to each other on both sides of the chip surface, separated by a narrow spacer 23 in the middle. Each pad extends along the long side of the chip, occupying a considerable proportion of the area of the chip, so that only a narrow spacer is left in the center of the chip. This layout allows the stress to be more evenly transferred to the packaging substrate through the pads when the chip is subjected to stress from the package, reducing the possibility of all stress being concentrated in the center of the chip, and effectively avoiding the chip from breaking in the middle. The present invention preferably controls the distance between the edges of the two pads (pad spacing) within the range of 50-300μm. Such a setting can ensure that there is sufficient insulation distance between the pads to prevent soldering during soldering, and prevent the spacer from being too wide to become a stress weak point. In contrast, Figure 1 In the top view of a conventional flip-chip LED chip, the chip is an elongated strip. P pads 11 and N pads 12 are typically located at the far ends of the chip, leaving a large unsupported area 13 in the middle. This large area is prone to bending and breaking when subjected to mechanical stress, which is why crystal breakage is so common in traditional structures.

[0016] On the other hand, the present invention also provides a flip-chip LED chip structure prepared by the above method. Figure 3 As shown, the chip contains various functional layers formed from bottom to top: Figure 3 Figure 1 represents the sapphire substrate; above the substrate are, in order, the N-type GaN layer 2, the light-emitting quantum well layer 3, and the P-type GaN layer 4, which together form the LED's light-emitting epitaxial structure. A transparent conductive layer 5 (such as an ITO layer) is deposited tightly atop the P-type GaN layer 4, providing electrical contact and transmitting light. A dielectric reflective layer 6 covers the transparent conductive layer 5, improving light extraction efficiency and insulating subsequent metal layers. A metal reflective layer 7 (such as an Ag reflective layer) is deposited through openings in dielectric layer 6. This layer not only connects to the transparent conductive layer 5 to electrically connect to the P-type region but also acts as a reflector, reflecting downward-emitted light upward. A protective metal layer (not separately numbered, but indicated in Figure 7) is further deposited on the surface of the metal reflective layer 7 to prevent oxidation. Subsequently, a first insulating passivation layer 8 covers the top surface of the chip, with only one through-hole in each of the P and N regions exposing the underlying P-side metal and N-type GaN to form electrode connections. A first metal electrode 9 is deposited, filling the through-holes and contacting the P and N regions, forming internal leads. The second insulating passivation layer 10 is then covered with a window only at the location of the P electrode and the N electrode. Finally, the deposited second metal electrode 11 forms the external P electrode pad and N electrode pad through the window area. These two pads correspond to the contact surface of the flip chip for soldering to the package substrate. In this embodiment, their shape is designed as an elongated rectangular strip, located on both sides of the chip (corresponding to Figure 2The chip's P-type region is located at the position shown in the figure, with a spacing band 13 remaining between the pads. This stacked structure design allows the chip's P-type region current to be evenly distributed by the transparent and reflective electrodes. Light emitted from the quantum well layer passes downward through the transparent electrode 5, is reflected by the dielectric / metal reflective layers 6 and 7, and then exits the chip upward, improving light extraction efficiency. Furthermore, the upper and lower electrodes are isolated by a double-layer passivation, preventing short circuits between the PN electrodes and forming stable, solderable external pads.

[0017] In summary, the present invention effectively improves the mechanical properties and packaging reliability of the flip-chip LED chip by changing it from a slender type to a wide and short type and adopting a slender pad layout. Specifically:

[0018] Reduced stress concentration, preventing chip breakage: The wide, short chip structure reduces the chip's long span, expanding the stressed cross-section. Combined with the chip's support provided by the large, slender pads, this more evenly distributes package stress, significantly reducing the risk of chip breakage due to stress concentration in the center. Experiments have shown that chips using this design experience no die breakage under standard die-bonding pressure testing, significantly improving product yield.

[0019] Optimizing pad spacing for reliable soldering: The P / N pad spacing is controlled within a moderate range of 50–300μm. This avoids stress-weakened areas caused by pads being too far apart, while also ensuring that solder flow during reflow soldering prevents short circuits between the two terminals. Compared to traditional designs where pad spacing is too large or too small, resulting in failure modes, this design achieves a balance between mechanical reliability and electrical safety.

[0020] Maintaining excellent optoelectronic performance: The transparent conductive layer + dielectric / metal reflective layer combination employed in this invention ensures that the light extraction efficiency of the flip-chip LED chip is not affected by changes in chip shape. While the wide, short chip geometry changes, this layered structure still achieves efficient light extraction and reflection, resulting in chip brightness and luminous efficiency comparable to or even better than existing slender structures. Furthermore, the flip-chip structure eliminates light shading losses associated with gold wires, resulting in more uniform and reliable light emission.

[0021] Process Compatibility: The method is based on conventional flip-chip LED manufacturing processes, requiring only optimized layout design and several process parameters, making it easily adaptable to existing production lines. The entire process, including transparent electrode deposition, reflective layer lamination, double-layer passivation, and electrode plating, is a mature process with high feasibility and stability.

[0022] In summary, the flip-chip LED chip manufacturing method and structural design provided by the present invention significantly improve the mechanical reliability and service life of the edge-type backlight LED chip, reduce the scrap caused by broken crystals, and have significant practical application value and economic benefits. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 : A top view of a conventional flip-chip LED chip. The chip is in the shape of a long and thin strip, with the P electrode pad 11 and the N electrode pad 12 located at both ends of the chip, with a larger spacing area 13 in the middle.

[0024] Figure 2 : A top view of the flip-chip LED chip of the present invention. The chip is designed as a wide and short rectangle. The P electrode pad 21 and the N electrode pad 22 are slender strips and are distributed parallel to each other on both sides of the chip. The pad spacing area 23 in the middle is narrow and uniform.

[0025] Figure 3 Schematic diagram of the cross-sectional structure of a flip-chip LED chip of the present invention (not drawn to scale). 1 - substrate, 2 - N-type semiconductor layer, 3 - quantum well layer, 4 - P-type semiconductor layer, 5 - transparent conductive layer, 6 - dielectric reflective layer, 7 - metal reflective layer, 8 - first passivation layer, 9 - first metal electrode layer, 10 - second passivation layer, 011 - second metal electrode layer. DETAILED DESCRIPTION

[0026] The following detailed description of the flip-chip LED chip fabrication method and structure of the present invention is provided in conjunction with the accompanying drawings and specific embodiments. It should be understood that these embodiments are intended to illustrate the technical principles of the present invention and do not limit the scope of protection of the present invention. Those skilled in the art may adjust and modify the specific process parameters and structural form without departing from the spirit of the present invention, and the present invention covers all such adjustments and modifications.

[0027] Example 1:

[0028] This embodiment provides a specific production process of a flip-chip LED chip. Figure 2 and Figure 3 shown.

[0029] First, a patterned sapphire substrate 1 is provided, its surface pre-prepared with a regular pattern (such as an array of micron-scale bumps) to improve epitaxial growth quality and light extraction efficiency. Next, multiple gallium nitride-based semiconductor layers are epitaxially grown on substrate 1 using metal-organic chemical vapor deposition (MOCVD) to form an LED epitaxial structure: First, an N-type semiconductor layer 2 is deposited, specifically N-type GaN (doped with Si and several microns thick) in this embodiment. Then, a quantum well active layer 3 consisting of several periods of InGaN / GaN (e.g., 3-5 pairs, emitting light of the desired wavelength) is grown. Finally, a P-type semiconductor layer 4 is grown, specifically a P-type GaN layer (doped with Mg and tens to hundreds of nanometers thick) in this embodiment. After the epitaxial growth is completed, the P-type GaN is annealed to activate the doping.

[0030] Next, the epitaxial wafer is subjected to MESA pattern lithography and dry etching. Etching is performed through the P-type semiconductor layer 4, the quantum well layer 3 and into the N-type semiconductor layer 2 at the location where the chip boundary needs to be formed, thereby defining the area of a single chip and the peripheral insulation trench. Etching continues to the surface of the N-type GaN layer in a corner or edge area of the chip, exposing the N-type GaN as the N-electrode contact area. After MESA etching, the shape of each chip is defined as a wide and short rectangular layout.

[0031] After completing the MESA etch, a deep etch (ISO process) can be performed in the middle of the chip dicing streets to remove or thin the substrate directly below the streets, forming isolation trenches. This step is not required, but it helps reduce debris during subsequent chip separation and can alleviate stress at the chip edge to a certain extent.

[0032] Then, a layer of transparent conductive oxide is deposited on the entire surface of the wafer as the P-side transparent conductive layer 5. Preferably, an ITO film is deposited by sputtering with a thickness of about 100 nm to cover the P-type GaN surface of all chips. This ITO layer forms a good ohmic contact with the P-type GaN, expands the current injection area, and ensures that most visible light can pass through. In order to optimize the current distribution, the ITO layer can be selectively photoetched into a grid pattern, that is, part of the ITO is removed in the pad area or the edge of the chip to reduce resistance while reducing light absorption. In this embodiment, the ITO is retained as a large-area continuous film.

[0033] Next, the reflective layer structure is formed. A SiO2 dielectric reflective layer 6, approximately 300 nm thick, is first deposited on the transparent conductive layer 5 by vacuum evaporation. This dielectric layer covers the entire chip surface. Subsequently, a through-hole array with diameters of several tens of microns is created in the dielectric layer 6 by photolithography. Multiple small holes are opened in the center of each chip's P-type region, exposing the surface of the transparent conductive layer 5 below. The dielectric layer above the N-type region (the exposed N-GaN region) remains completely covered (to prevent direct metal contact with the N-region to prevent short circuits). Then, Ag is thermally evaporated to a thickness of approximately 120 nm across the entire surface to form a metal reflective layer 7. Because through-holes were previously opened in the dielectric layer 6, the deposited Ag directly fills these holes and contacts the underlying ITO layer, thus electrically connecting the Ag layer to the P-type GaN. Simultaneously, the Ag forms a continuous reflective film on the dielectric layer surface, covering most of the area except for the through-holes. To enhance the stability of the Ag film, a layer of approximately 10 nm of Ni is sputtered on the Ag layer as a protective layer. The composite reflective layer obtained in this way can serve as an extension of the P electrode and also play the role of efficiently reflecting light.

[0034] Next, a layer of Si3N4 is deposited on the chip surface using plasma enhanced chemical vapor deposition (PECVD) as the first passivation layer 8 with a thickness of about 500nm. This passivation layer covers the Ag reflective layer and the exposed N-type contact area. Through photolithography and dry etching, a rectangular window is etched at the position corresponding to the P electrode of each chip to expose part of the Ag / Ni layer below (i.e., the P electrode connection area); a window is also etched at the position where the N electrode is located to expose the N-type GaN contact surface (N electrode connection area). After etching is completed, the chip is cleaned to remove residual dielectrics.

[0035] Subsequently, the first metal electrode layer 9 is deposited using electron beam evaporation. First, a 20nm layer of Cr is deposited across the entire wafer as an adhesion layer, followed by 200nm of Al as the main conductive layer, and finally Ni (50nm) to prevent aluminum oxidation. This multilayer metal layer is patterned using a lift-off process (mask-mask etching), leaving only the previously opened holes covered and slightly enlarged to form lead-out plates for the P and N electrodes. Specifically, a metal region is formed around the P-region through-hole and its periphery, firmly contacting the underlying Ag / Ni layer. This metal region serves as the P-electrode lead-out plate. A metal region is also formed above the N-region through-hole, directly contacting the N-GaN and serving as the N-electrode lead-out plate. The areas of both regions can be designed as needed, but generally, the P-electrode metal covers most of the central area of the chip, while the N-electrode metal is located above the N-contact area at the edge of the chip. This first electrode layer serves to lead the P and N regions to the chip surface, respectively. The P and N metals on the same layer are insulated from each other (separated by a dielectric layer) to prevent short circuits.

[0036] After the internal electrodes are connected, a second passivation layer 10 of approximately 500 nm thick Si3N4 is deposited using PECVD, covering the first electrode layer 9. A bonding pad window is created in the center of each chip's P-electrode metal region using photolithography, exposing a portion of the underlying P-electrode metal surface. A correspondingly smaller window is also created in the N-electrode metal region, exposing the N-electrode metal surface. In this way, each P- and N-region forms a window area for external soldering.

[0037] Finally, make the external pad (second metal electrode layer 011). This embodiment uses electroplating to fill thick copper in the pad window, and then forms a raised pad by tin plating: first, a seed layer of metal (such as Ti / Au double layer) is sputtered on the entire surface of the wafer, and then photolithography is used to define the plating area, leaving only the photolithography holes at the P pad window and the N pad window. Subsequently, copper is electroplated in this area to a thickness of about 5μm, filling the window and slightly above the surface, and then a layer of Au with a thickness of about 0.5μm is electroplated. The photoresist is then removed and the unplated portion of the seed layer is etched away. In this way, thick gold-plated pads are formed in the P region and N region of each chip. In order to improve solderability, an appropriate amount of low-melting-point solder (such as Sn-Bi or Au-Sn alloy) can be placed on these pads before the subsequent reflow soldering assembly. At this point, the manufacture of the flip-chip LED chip is completed. By cutting, an independent LED chip finished product is obtained.

[0038] Structural features of embodiment 1:

[0039] like Figure 2 and Figure 3 As shown in the figure: the finished chip is a wide and short rectangle with a size of about 1448μm×608μm. There are two rectangular pads at the bottom of the chip: the P-electrode pad 21 is on the left, and the N-electrode pad 22 is on the right (seen from a top-down perspective). Each pad is approximately 1368μm×164μm in size and extends in the horizontal direction (the direction of the long side of the chip). The interval 23 between the two pads is approximately 200μm and is located slightly below the center of the chip. The two pads are connected to the P-type region and N-type region of the chip through their respective internal metal layers: the P-electrode pad 21 contacts the P-type semiconductor layer 4 through the first metal electrode layer 9 (conducted through the transparent conductive layer 5 and the metal reflective layer 7), and the N-electrode pad 22 directly contacts the N-type semiconductor layer 2 through the first metal electrode layer 9. When the chip is operating, current enters the N pad 22 from the substrate solder point, is injected into the N-type semiconductor layer 2 along the internal metal lead, passes upward through the quantum well layer 3, generates photons, then enters the P-side transparent conductive layer 5 and metal reflective layer 7 through the P-type semiconductor layer 4, and finally converges at the P pad 21 and flows out of the chip. Due to the use of a large-area transparent electrode and reflective layer structure, the current distribution is uniform and the light extraction efficiency is high. Most of the light generated by the chip is emitted upward, and the side-emitted light is also reflected by the metal reflective layer 7 below and directed upward, effectively reducing light loss.

[0040] In terms of mechanical reliability, the short, wide chip shape and slender dual pads provide excellent fracture resistance. When the chip is subjected to mechanical loads generated by the packaging process (such as pressure applied during die bonding or thermal stress caused by temperature cycling), the stress is transferred through the larger pads and distributed more evenly within the chip, rather than being concentrated in the narrow, central region. As a result, the chip of this invention exhibited no fractures even under rigorous thermal shock or vibration tests, demonstrating far superior reliability compared to traditional, slender chips.

[0041] It should be noted that the dimensions, materials, and process parameters described in the above embodiments are preferred embodiments of the present invention, but the present invention is not limited thereto. For example, the specific length and width of the chip can be adjusted within a range of several hundred microns to several millimeters based on application requirements; the transparent conductive layer material can also be AZO (aluminum-doped zinc oxide) or other transparent electrodes; the dielectric reflective layer can also adopt a multi-layer Ta2O5 / SiO2 DBR structure to enhance reflection in specific wavelength bands; the metal reflective layer can also be made of Al or its alloys with excellent reflective properties in addition to Ag; the pad metal can adopt different multi-layer metal solutions, and the pad shape can also be designed to be circular, elliptical, etc. based on bonding requirements. As long as the overall shape is slender and the spacing is appropriate, it falls within the scope of protection of the present invention.

[0042] Example 2:

[0043] In another variation, the two electrode pads of the flip-chip LED chip can be designed asymmetrically. For example, for chips that require specific polarity identification, the P-electrode pad can be designed to be slightly larger than the N-electrode pad, or a small protrusion can be drawn on one side of the P-electrode pad as an identification mark (i.e., a "notch" or additional pattern is made on the pad). Such an asymmetric detail design is conducive to quickly identifying the positive and negative directions of the chip when packaging the chip. This variation still maintains the pad in the shape of a slender strip and the total spacing within a safe range, but the shape is slightly different. This change does not affect the force optimization effect of the chip and also achieves the purpose of reducing the risk of crystal breakage. Furthermore, in some high-power flip-chip LED applications, it can be considered to connect three or more small pads in parallel instead of a single long pad to further distribute stress and current. For example, the P-electrode pad is divided into two parallel slender strips spaced apart from each other, and the N-electrode is arranged in a similar manner. This is a further improvement to the shape of the pad and also falls within the scope of the present invention.

[0044] In summary, this invention overcomes the shortcomings of existing flip-chip LED chips in terms of mechanical strength and packaging reliability through its innovative chip shape and electrode layout design. Without sacrificing optoelectronic performance, it significantly reduces the probability of chip fracture and failure. The above-described embodiments and variations demonstrate the effectiveness of this invention, but the scope of protection of this invention is not limited thereto. Any improvements resulting from equivalent substitutions or simple modifications are also covered by this patent.

Claims

1. A method for fabricating a flip-chip LED chip, comprising the following steps: epitaxially growing an LED structure comprising an N-type semiconductor layer, a quantum well layer, and a P-type semiconductor layer on a substrate; etching to form a MESA to expose the N-type semiconductor layer and determine the chip size; and forming a transparent conductive layer on the surface of the P-type semiconductor layer to form a P-electrode contact. Depositing a dielectric reflective layer on the transparent conductive layer and opening a hole, and then depositing a metal reflective layer and electrically connecting it to the transparent conductive layer through the opening to form a reflective electrode; An insulating passivation layer is deposited and through holes are opened to expose the electrode connection area of the P-type semiconductor layer and the electrode connection area of the N-type semiconductor layer respectively; a first metal electrode layer is deposited and electrically connected to the P-type semiconductor layer and the N-type semiconductor layer respectively through the through holes; a second insulating passivation layer is deposited and a window is opened to form a pad window; and a second metal electrode layer is deposited in the pad window to form a P-electrode pad and an N-electrode pad; characterized in that: the LED chip is designed to be a wide and short structure, and the P-electrode pad and the N-electrode pad are designed to be slender strips and are arranged in parallel, with a spacing of 50-250μm between the two, so that the force distribution of the chip is more uniform, reducing the risk of crystal breakage of the flip chip during the crystal bonding process.

2. The production method according to claim 1, characterized in that: The chip shape is made into a wide and short type through the MESA etching step, and the ratio of the long side to the short side of the chip is less than 1:2, so as to adjust the size of the traditional slender chip to a wide and short type, thereby improving the bending strength of the chip structure.

3. The production method according to claim 1, characterized in that: When forming the second metal electrode layer, the P-electrode pad and the N-electrode pad are patterned into elongated rectangular or strip electrodes, the length of which extends along the long side of the chip to increase the pad coverage area and avoid force concentration caused by the pad being too wide.

4. The production method according to claim 1, wherein: When forming the second metal electrode layer, the spacing between the P-electrode pad and the N-electrode pad is controlled to be 50-250 μm to ensure that no solder short circuit occurs between the pads while reducing the unsupported span in the central area of the chip and reducing the risk of breakage.

5. A flip-chip LED chip comprising a substrate, an LED epitaxial structure (comprising an N-type semiconductor layer, a quantum well layer, and a P-type semiconductor layer) disposed on the substrate, a transparent conductive layer disposed on the P-type semiconductor layer, a reflective layer disposed on the transparent conductive layer, an insulating passivation layer covering the reflective layer and edges of the N-type semiconductor layer, and a metal electrode layer disposed on the insulating passivation layer; characterized in that: The flip-chip LED chip has a wide and short chip structure. The metal electrode layer includes a P-electrode pad and an N-electrode pad separated from each other. The P-electrode pad and the N-electrode pad are in the shape of slender strips and are arranged at intervals. The center distance between the two is 50-250 μm.

6. The flip-chip LED chip according to claim 5, wherein: The transparent conductive layer is formed of indium tin oxide (ITO) or zinc oxide (ZnO) material with a thickness of 5-200nm, and forms an ohmic contact with the P-type semiconductor layer; the reflective layer includes a dielectric reflective layer and a metal reflective layer, the dielectric reflective layer is an insulating dielectric film or a distributed Bragg reflector (DBR) multilayer film covering the transparent conductive layer, and the metal reflective layer is a silver (Ag) or aluminum (Al) film with a thickness greater than 80nm, and is electrically connected to the transparent conductive layer through the hollow openings in the dielectric reflective layer; the insulating passivation layer includes a first passivation layer and a second passivation layer stacked in sequence, the first passivation layer covers the metal The reflective layer has through holes exposing the P-electrode connection area and the N-electrode connection area respectively, and the second passivation layer covers the first metal electrode layer and has an opening exposing the P-electrode pad area and the N-electrode pad area; the metal electrode layer includes a first metal electrode layer and a second metal electrode layer, the first metal electrode layer is composed of one or more of Cr, Al, Ti, Pt, Ni, and Au, and is used to connect the P-type semiconductor layer and the N-type semiconductor layer through the through holes, and the second metal electrode layer is composed of one of Cr, Al, Ti, Pt, Ni, Au, and Sn or an alloy thereof, and is used to form the slender strip-shaped P-electrode pad and N-electrode pad.

7. The flip-chip LED chip according to claim 6, wherein: The dielectric reflective layer is made of one of SiO2, MgF2, Al2O3 or Si3N4 dielectric materials, with a thickness of 50-5000nm; or the dielectric reflective layer is a multilayer structure in which high-refractive index and low-refractive index films are alternately stacked; the dielectric material in the first passivation layer and the second passivation layer is one or more of SiO2 or Si3N4, with a thickness of 200-2000nm.

8. The flip-chip LED chip according to claim 5, wherein: The P-electrode pad and the N-electrode pad are symmetrically distributed on both sides and have approximately equal areas; or the P-electrode pad and the N-electrode pad are asymmetrically distributed, and a notch structure is provided on one or both pads to further optimize the pad stress and welding reliability.

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