LATCH CROSS-COUPLING FOR STACKED AND STEP FETs

Abstract

A semiconductor structure is disclosed having a first field effect transistor (FET) including a first device layer; a second FET including a second device layer, wherein the first device layer has a stepped portion with respect to the second device layer; and an electrical connection between a gate of the first FET and a gate of the second FET at the step portion of the first device layer. The first FET is stacked on the second FET. The second device layer is larger than the first device layer. A gate of the first FET is over the first device layer having the step portion.

Description

Background Art

[0001] The present invention relates generally to semiconductor devices and, more particularly, to constructing latch cross-coupling for stacked and laddered field effect transistors (FETs).

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and layers of semiconductor material onto a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This increase in integration density has largely come from shrinking semiconductor process nodes. As the demand for miniaturization, higher speed, greater bandwidth, lower power consumption, and lower latency increases, chip layouts are becoming increasingly complex and difficult to implement in the production of semiconductor die.

[0004] The device structure of a field effect transistor (FET) generally includes a source, a drain, and a gate electrode, which is configured to switch the flow of carriers in a channel formed between the source and drain electrodes in the semiconductor body. When a control voltage exceeding a specified threshold voltage is applied to the gate electrode, the flow of carriers in the channel between the source and drain generates the device output current.

[0005] The body region and channel of a planar FET are arranged below the top surface of a substrate that supports a gate electrode. A fin field-effect transistor (FinFET) is a non-planar device structure of a FET that can be more densely packed in an integrated circuit than a planar FET. A FinFET comprises a fin, heavily doped source / drain regions, and a gate electrode surrounding the fin. During operation, a channel for carrier flow is formed in the fin between the source / drain regions. The arrangement between the gate structure and the fin improves control of the channel and reduces leakage current when the FinFET is in its "off" state compared to a planar FET. This in turn lowers the threshold voltage compared to a planar FET and results in improved performance and reduced power consumption.

[0006] Nanosheet FETs have been developed as an advanced type of FinFET that can allow for further increases in packaging density in integrated circuits (ICs). The body region of a nanosheet FET includes multiple nanosheet channel layers stacked vertically in a three-dimensional array. Segments of the gate stack can surround all sides of each nanosheet channel layer in a gate-all-around arrangement. The nanosheet channel layer is initially arranged in a layer stack having a sacrificial layer composed of a material (e.g., silicon germanium) that can be selectively etched to the material (e.g., silicon) that constitutes the nanosheet channel layer. The sacrificial layer is etched and removed to release the nanosheet channel layer and provide space for the formation of the gate stack.

[0007] To improve drive current and electrostatics and to allow device scaling, increased device density, and reduced area consumption, all-around gate field-effect transistors (GAAFETs) (e.g., nanowire-type GAAFETs or nanosheet-type GAAFETs) have been developed. A GAAFET includes longitudinal nanoshapes (e.g., nanowires or nanosheets) extending laterally between source / drain regions, and a surrounding gate structure surrounding the nanoshapes so that the nanoshapes serve as channel regions.

[0008] Recently, in order to further increase the on-chip device density and reduce area consumption, complementary field effect transistors (CFETs) have been developed. A CFET typically includes a pair of N-type and P-type GAAFETs that are stacked on each other and have a common gate structure, rather than being positioned side by side and having separate gate structures. Specifically, a CFET includes an N-type GAAFET on one level, a P-type GAAFET on an adjacent level (e.g., above or below), and a common gate that vertically spans and surrounds the stacked channel region of the N-type and P-type GAAFETs. Typically, the source / drain region of the lower level GAAFET will be electrically isolated from the source / drain region of the higher level GAAFET by one or more isolation layers. For example, such a CFET can be incorporated into a six-transistor (6T) static random access memory (SRAM) cell, with one CFET for each pair of pull-down and pull-up field effect transistors. While using CFETs can increase on-chip device density and reduce area consumption, providing signal connections to the source / drain regions of the lower-level GAAFETs (e.g., to implement cross-coupling connections in SRAM cells) can be very complex. Summary of the Invention

[0009] According to one embodiment, a semiconductor structure is provided, comprising: a first field effect transistor (FET) including a first device layer; a second FET including a second device layer, wherein the first device layer has a stepped portion relative to the second device layer; and an electrical connection between a gate of the first FET and a gate of the second FET at the stepped portion of the first device layer.

[0010] According to another embodiment, a semiconductor structure is provided that includes: a first field effect transistor (FET) including a first device layer; a second FET including a second device layer; and an electrical connection between a gate of the first FET and a gate of the second FET at a stepped portion of the first device layer.

[0011] According to yet another embodiment, a semiconductor structure is provided, comprising: a first field effect transistor (FET) including a first device layer; a second FET including a second device layer, wherein the second device layer is larger than the first device layer; and an electrical connection between a gate of the first FET and a gate of the second FET at a stepped portion of the first device layer.

[0012] In a preferred aspect, the first FET is stacked on top of the second FET.

[0013] In another preferred aspect, the second device layer is larger than the first device layer.

[0014] In yet another preferred aspect, the first FET is a p-type FET and the second FET is an n-type FET.

[0015] In a preferred aspect, the gate of the first FET is located above the first device layer having the stepped portion.

[0016] In another preferred aspect, the gate of the first FET is located above both the first device layer and the second device layer.

[0017] In yet another preferred aspect, the second FET includes a floating gate.

[0018] In yet another preferred aspect, the floating gate is vertically aligned with the stepped portion of the first device layer.

[0019] In a preferred aspect, the first device layer is centered relative to the second device layer.

[0020] In another preferred aspect, the first device layer is positioned adjacent to the second device layer such that a surface of the first device layer is horizontally aligned with a surface of the second device layer.

[0021] In yet another preferred aspect, the first device layer substantially overlaps the second device layer.

[0022] In yet another preferred aspect, the gate of the first FET is located above the first device layer having a double staircase configuration.

[0023] In yet another preferred aspect, the gate of the first FET is located above both the first device layer and the second device layer.

[0024] Advantages of the present invention include producing transistors that consume less power, have better performance, occupy a smaller area on the wafer and reduce costs in semiconductor manufacturing. Advantages of the present invention also include improving the latch cross-coupling configuration or connection used in the circuit. In conventional non-stacked transistors, the latch cross-coupling connects the PC or gate layer of the NFET to the PC or gate layer of the PFET, so that a cross or "X" connection is established between them. However, this "X" connection between the PC or gate layers of the PFET and NFET can be challenging. However, stacked FETs as presented herein, for example, a PFET stacked on top of an NFET, can advantageously alleviate this implementation challenge. In addition to the PFETs and NFETs being stacked, they can also be advantageously stepped. The term "staircase" refers to a stair-like structure in which one nanosheet (or FET) is wider than the other nanosheet (or FET) to advantageously create steps or terraces. For example, the first nanosheet stack (or FET) is advantageously wider than the second nanosheet stack (or FET), such that a stepped region or mesa is advantageously formed at the intersection of the first nanosheet stack (or FET) and the second nanosheet stack (or FET).

[0025] It should be noted that the exemplary embodiments are described with reference to different subject matters. In particular, some embodiments are described with reference to method-type claims, while other embodiments are described with reference to apparatus-type claims. However, a person skilled in the art will appreciate from the above and following descriptions that, unless otherwise indicated, any combination of features relating to different subject matters, in addition to any combination of features belonging to one type of subject matter, and in particular, combinations of features from method-type claims and features from apparatus-type claims, are considered to be described in this document.

[0026] These and other features and advantages will become apparent from the following detailed description of exemplary embodiments, which description should be taken in conjunction with the accompanying Figure 1 Read together. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The present invention will be described in detail in the following description of preferred embodiments with reference to the following drawings, in which:

[0028] Figure 1 is a circuit diagram of a stacked field effect transistor (FET) according to an embodiment of the present invention;

[0029] Figure 2is a top view of a semiconductor structure according to an embodiment of the present invention, showing stacked and stepped FET configurations;

[0030] Figure 3 According to an embodiment of the present invention Figure 2 A cross-sectional view of a semiconductor structure depicting a first FET and a second FET in a stacked and stepped FET configuration;

[0031] Figure 4 is a circuit diagram of a stacked FET according to an embodiment of the present invention;

[0032] Figure 5 is a top view of a semiconductor structure according to an embodiment of the present invention, wherein a top FET of a stacked and stepped FET configuration includes a floating gate;

[0033] Figure 6 According to an embodiment of the present invention Figure 5 A cross-sectional view of a semiconductor structure depicting the floating gate of the top FET;

[0034] Figure 7 is a circuit diagram of a stacked FET according to an embodiment of the present invention;

[0035] Figure 8 is a top view of a semiconductor structure according to an embodiment of the present invention, wherein the stacked and stepped FET configuration includes a double stepped stacked FET;

[0036] Figure 9 According to an embodiment of the present invention Figure 8 A cross-sectional view of a semiconductor structure depicting a first FET and a second FET in a stacked and stepped FET configuration;

[0037] Figure 10 is a circuit diagram of a stacked FET according to an embodiment of the present invention;

[0038] Figure 11 is a top view of a semiconductor structure according to an embodiment of the present invention, wherein the stacked and laddered FET configuration includes a double laddered stacked FET with a smaller bottom transistor;

[0039] Figure 12 According to an embodiment of the present invention Figure 11 A cross-sectional view of a semiconductor structure depicting a first FET and a second FET in a stacked and stepped FET configuration with a smaller bottom FET;

[0040] Figure 13 is a circuit diagram of a stacked FET according to an embodiment of the present invention;

[0041] Figure 14is a top view of a semiconductor structure according to an embodiment of the present invention, wherein the stacked and laddered FET configuration includes a double laddered stacked FET with a larger bottom transistor; and

[0042] Figure 15 According to an embodiment of the present invention Figure 14 A cross-sectional view of a semiconductor structure depicting first and second FETs in a stacked and stepped FET configuration with a larger bottom FET.

[0043] Throughout the drawings, the same or similar reference numerals refer to the same or similar elements. DETAILED DESCRIPTION

[0044] According to an embodiment of the present invention, a method and apparatus for constructing a latch cross-coupling of a stacked and stepped field effect transistor (FET) is provided. The stacked FET includes a first device layer and a second device layer, wherein one device layer is advantageously shifted or tapered or stepped relative to the other device layer. The shifted or tapered device layer is advantageously shifted or tapered between device gates or "PCs." An electrical connection is advantageously formed from the bottom gate to the top gate at the shifted or tapered device layer. A floating gate may also be deployed on the shifted or tapered device layer. In other embodiments, a double-staircase stacked FET is advantageously deployed. In addition, one of the device layers advantageously has a larger size or larger than the other device layer.

[0045] Examples of semiconductor materials that can be used to form such a structure include silicon (Si), germanium (Ge), silicon-germanium alloys (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), III-V compound semiconductors, and / or II-VI compound semiconductors. III-V compound semiconductors are materials that include at least one element from Group III of the periodic table and at least one element from Group V of the periodic table. II-VI compound semiconductors are materials that include at least one element from Group II of the periodic table and at least one element from Group VI of the periodic table.

[0046] It should be understood that the present invention will be described with reference to a given exemplary architecture; however, other architectures, structures, substrate materials, and process features and steps may be varied within the scope of the present invention.

[0047] Block. It should be noted that for the sake of clarity, some features may not be shown in all drawings. This is not intended to be interpreted as a limitation on any particular embodiment, diagram, or the scope of the claims.

[0048] Figure 1 is a circuit diagram of stacked field effect transistors (FETs) according to an embodiment of the present invention.

[0049] Circuit 5 depicts an NFET circuit portion, including a first NFET 20 (N1), a second NFET 22 (N2), a third NFET 24 (N3), and a fourth NFET 26 (N4). Circuit 5 also depicts a PFET circuit portion, including a first PFET 10 (P1), a second PFET 12 (P2), a third PFET 14 (P3), and a fourth PFET 16 (P4). The PFET portion is stacked on the NFET portion. The PFET portion can be in a stepped or tapered relationship relative to the NFET portion.

[0050] Figure 2 is a top view of a semiconductor structure according to an embodiment of the present invention, showing stacked and stepped FET configurations.

[0051] The top view depicts a top device layer 30T (Top Rx) and a bottom device layer 40 (Bot Rx) having a plurality of segments 30, 32, 34. The top device layer 30T may be referred to as a first device layer, and the bottom device layer 40 may be referred to as a second device layer. The plurality of segments 30, 32, 34 of the top device layer 30T may advantageously be displaced and / or tapered and / or offset from one another.

[0052] P-type transistors are shown stacked on top of n-type transistors. For example, first PFET 10 (P1) is stacked on first NFET 20 (N1), second PFET 12 (P2) is stacked on second NFET 22 (N2), third NFET 24 (N3) is stacked on third PFET 14 (P3), and fourth NFET 26 (N4) is stacked on fourth PFET 16 (P4). Device gates "top PC" and "bottom PC" are also shown. The shifted or tapered device layers are advantageously shifted or tapered between the device gates or "PCs." An electrical connection is advantageously made from the bottom gate to the top gate at the shifted or tapered device layers.

[0053] The letters "A" and "B" represent circuit input pins, while the letter "Z" represents a circuit output pin. Circuit input pin 50 is represented as "S," and circuit input pin 52 is represented as "SB." "S" stands for "Select," and "SB" stands for "Select Bar." Vias 60, 62 are shown connecting circuit input pin 50 to second NFET 22 (N2) and third PFET 14 (P3).

[0054] As used herein, PC means shorter (<40 nm) gate lithography layer, CB means longer (>40 nm) gate lithography layer, CT means PC cut lithography layer, CA and CC mean source / drain open lithography layer.

[0055] Thus, a first FET comprising a first device layer and a second FET comprising a second device layer are presented, wherein the first device layer has a stepped portion (or a shifted or tapered configuration) relative to the second device layer. At the stepped portion of the first device layer, an electrical connection is formed between the gate of the first FET and the gate of the second FET. The first FET is stacked on top of the second FET. The second device layer is larger than the first device layer. The first FET is a p-type FET and the second FET is an n-type FET. In one embodiment, the gate of the first FET is located above the first device layer having the stepped portion. In other embodiments, the gate of the first FET is located above both the first device layer and the second device layer.

[0056] Figure 3 According to an embodiment of the present invention Figure 2 A cross-sectional view of a semiconductor structure depicting a first FET and a second FET in a stacked and stepped FET configuration.

[0057] Figure 3 1 is a cross-sectional view along axis "X" depicting third PFET 14 (P3) and fourth PFET 16 (P4), as well as first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). Top device layer 30T extends over third PFET 14 (P3) and fourth PFET 16 (P4). In particular, section 34 of top device layer 30T extends over third PFET 14 (P3) and fourth PFET 16 (P4). Bottom device layer 40 extends over first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). Via 60 extends from circuit input pin 50 ("S") to second NFET 22 (N2), and via 62 extends from circuit input pin 50 ("S") to third PFET 14 (P3).

[0058] Figure 4 is a circuit diagram of stacked FETs according to an embodiment of the present invention.

[0059] Circuit 5 depicts an NFET circuit portion including a first NFET 20 (N1), a second NFET 22 (N2), a third NFET 24 (N3), and a fourth NFET 26 (N4). Circuit 5 also depicts a PFET circuit portion including a first PFET 10 (P1), a second PFET 12 (P2), a third PFET 14 (P3), and a fourth PFET 16 (P4). The PFET portion is stacked on the NFET portion. The PFET portion can be in a stepped or tapered relationship with the NFET portion.

[0060] Figure 5 is a top view of a semiconductor structure in which a top FET of a stacked and stepped FET configuration includes a floating gate in accordance with an embodiment of the present invention.

[0061] The top view depicts a top device layer 30T and a bottom device layer 42 having a plurality of segments 30, 32, 35. The top device layer 30T may be referred to as a first device layer, and the bottom device layer 42 may be referred to as a second device layer. The plurality of segments 30, 32, 35 of the top device layer 30T may advantageously be displaced and / or tapered and / or offset from one another. The segments 35 of the top device layer 30T may be larger or take up more space than the segments 30, 32. In addition, the bottom device layer 42 is enlarged to accommodate the first NFET 20 (N1), the second NFET 22 (N2), the third NFET 24 (N3), and the fourth NFET 26 (N4), as well as the floating gate 70. Thus, Figure 5 The bottom device layer 42 is larger than Figure 2 The bottom device layer 40 is larger or occupies more space. The floating gate 70 is advantageously vertically aligned with the stepped portion of the top device layer 30T.

[0062] P-type transistors are shown stacked on top of n-type transistors. For example, first PFET 10 (P1) is stacked on first NFET 20 (N1), second PFET 12 (P2) is stacked on second NFET 22 (N2), third NFET 24 (N3) is stacked on third PFET 14 (P3), and fourth NFET 26 (N4) is stacked on fourth PFET 16 (P4). Device gates "top PC" and "bottom PC" are also shown. The shifted or tapered device layer is advantageously shifted or tapered between the device gates or "PCs." An electrical connection is advantageously made from the bottom gate to the top gate at the shifted or tapered device layer. Floating gates 70 are located between the PFETs and NFETs. In one example, floating gates 70 are shown between second NFET 22 (N2) and third NFET 24 (N3), and between second PFET 12 (P2) and third PFET 14 (P3).

[0063] The letters “A” and “B” represent circuit input pins, while the letter “Z” represents a circuit output pin. The circuit output pin “Z” is located above the floating gate 70 .

[0064] Circuit input pin 50 is designated "S," and circuit input pin 52 is designated "SB." "S" stands for "select," and "SB" stands for "select bar." Circuit input pin 50 extends over floating gate 70. Vias 60, 62 are shown connecting circuit input pin 50 to second NFET 22 (N2) and third PFET 14 (P3).

[0065] Figure 6 According to an embodiment of the present invention Figure 5 A cross-sectional view of a semiconductor structure depicting the floating gate of the top FET.

[0066] Figure 6 1 is a cross-sectional view along axis “X” depicting third PFET 14 (P3) and fourth PFET 16 (P4), as well as first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4).

[0067] 14 (P3) and fourth PFET 16 (P4). Specifically, section 35 of top device layer 30T extends over third PFET 14 (P3) and fourth PFET 16 (P4). Bottom device layer 42 extends over first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). Via 60 extends from circuit input pin 50 ("S") to second NFET 22 (N2), and via 62 extends from circuit input pin 50 ("S") to third PFET 14 (P3).

[0068] The section 35 of the top device layer 30T extends to the floating gate 70 positioned between the second NFET 22 (N2) and the third NFET 24 (N3). Thus, the section 35 is elongated or enlarged to extend to the floating gate 70.

[0069] Figure 7 is a circuit diagram of stacked FETs according to an embodiment of the present invention.

[0070] Circuit 5 depicts an NFET circuit portion including a first NFET 20 (N1), a second NFET 22 (N2), a third NFET 24 (N3), and a fourth NFET 26 (N4). Circuit 5 also depicts a PFET circuit portion including a first PFET 10 (P1), a second PFET 12 (P2), a third PFET 14 (P3), and a fourth PFET 16 (P4). The PFET portion is stacked on the NFET portion. The PFET portion can be in a stepped or tapered relationship relative to the NFET portion.

[0071] Figure 8 is a top view of a semiconductor structure according to an embodiment of the present invention, wherein the stacked and stepped FET configuration includes a double stepped stacked FET.

[0072] The top view depicts a top device layer 30T and a bottom device layer 42 having a plurality of segments 30, 32, 35. The top device layer 30T may be referred to as a first device layer, and the bottom device layer 42 may be referred to as a second device layer. The plurality of segments 30, 32, 35 of the top device layer 30T may be aligned with each other (with respect to the device layer 30T). Figure 2 and Figure 5 This may be referred to as a double ladder stacked FET configuration. The top device layer 30T is substantially or approximately centered relative to the bottom device layer 42.

[0073] P-type transistors are shown stacked on top of n-type transistors. For example, first PFET 10 (P1) is stacked on first NFET 20 (N1), second PFET 12 (P2) is stacked on second NFET 22 (N2), third NFET 24 (N3) is stacked on third PFET 14 (P3), and fourth NFET 26 (N4) is stacked on fourth PFET 16 (P4). Device gates "top PC" and "bottom PC" are also shown.

[0074] The letters "A" and "B" represent circuit input pins, while the letter "Z" represents a circuit output pin. Circuit input pin 50 is designated "S," and circuit input pin 52 is designated "SB." "S" stands for "select," and "SB" stands for "select bar." Vias 60, 62 are shown connecting circuit input pin 50 to second NFET 22 (N2) and third PFET 14 (P3).

[0075] Also shown is a cross-sectional view along the Y-axis depicting the connection of circuit input pin 50 to third PFET 14 ( P3 ) through via 62 and the connection of circuit input pin 52 to third NFET 24 ( N3 ) through via 64 .

[0076] Figure 9 According to an embodiment of the present invention Figure 8 A cross-sectional view of a semiconductor structure depicting a first FET and a second FET in a stacked and ladder FET configuration.

[0077] Figure 9is a cross-sectional view along axis “X” depicting third PFET 14 (P3) and fourth PFET 16 (P4), as well as first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). Bottom device layer 42 extends over first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). Via 60 extends from circuit input pin 50 (“S”) to second NFET 22 (N2), and via 62 extends from circuit input pin 50 (“S”) to third PFET 14 (P3). Figure 3 and Figure 6 In contrast, the top device layer 30T is not visible.

[0078] Figure 10 is a circuit diagram of stacked FETs according to an embodiment of the present invention.

[0079] Circuit 5 depicts an NFET circuit portion including a first NFET 20 (N1), a second NFET 22 (N2), a third NFET 24 (N3), and a fourth NFET 26 (N4). Circuit 5 also depicts a PFET circuit portion including a first PFET 10 (P1), a second PFET 12 (P2), a third PFET 14 (P3), and a fourth PFET 16 (P4). The PFET portion is stacked on the NFET portion. The PFET portion can be in a stepped or tapered relationship relative to the NFET portion.

[0080] Figure 11 is a top view of a semiconductor structure in accordance with an embodiment of the present invention wherein the stacked and laddered FET configuration includes a double laddered stacked FET with a smaller bottom transistor.

[0081] The top view depicts a top device layer 30T having a plurality of segments 30, 32, 35 and a bottom device layer 44. The top device layer 30T may be referred to as a first device layer, and the bottom device layer 44 may be referred to as a second device layer. The plurality of segments 30, 32, 35 of the top device layer 30T may be aligned with each other (with respect to the device layer 30T). Figure 2 and Figure 5 This can be referred to as a double ladder stack FET configuration. Figure 2 and Figure 3 The bottom device layer 42 is thin. The top device layer 30T almost completely overlaps the bottom device layer 44.

[0082] P-type transistors are shown stacked on top of n-type transistors. For example, first PFET 10 (P1) is stacked on first NFET 20 (N1), second PFET 12 (P2) is stacked on second NFET 22 (N2), third NFET 24 (N3) is stacked on third PFET 14 (P3), and fourth NFET 26 (N4) is stacked on fourth PFET 16 (P4). Device gates "top PC" and "bottom PC" are also shown.

[0083] The letters "A" and "B" represent circuit input pins, while the letter "Z" represents a circuit output pin. Circuit input pin 50 is represented as "S," and circuit input pin 52 is represented as "SB." S stands for "select," and SB stands for "select bar." Vias 60, 62 are shown connecting circuit input pin 50 to second NFET 22 (N2) and third PFET 14 (P3).

[0084] Also shown is a cross-sectional view along the Y-axis, which depicts the circuit input pin 50 connected to the third PFET 14 (P3) through the via 62 and the circuit input pin 52 connected to the third NFET 24 (N3) through the via 64. Figure 8 The difference is that the bottom device layer 44 is smaller, so that a larger portion of the first NFET 20 (N1), the second NFET 22 (N2), the third NFET 24 (N3), and the fourth NFET 26 (N4) are exposed. In addition, a larger portion of the third PFET 14 (P3) and the fourth PFET 16 (P4) are exposed.

[0085] Figure 12 According to an embodiment of the present invention Figure 11 1. A cross-sectional view of a semiconductor structure depicting first and second FETs in a stacked and ladder FET configuration with a smaller bottom FET.

[0086] Figure 12 is a cross-sectional view along axis “X” depicting third PFET 14 (P3) and fourth PFET 16 (P4), as well as first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). Bottom device layer 44 extends over first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). Via 60 extends from circuit input pin 50 (“S”) to second NFET 22 (N2), and via 62 extends from circuit input pin 50 (“S”) to third PFET 14 (P3). Figure 3 and Figure 6In contrast, the top device layer 30T is not visible.

[0087] Figure 13 is a circuit diagram of stacked FETs according to an embodiment of the present invention.

[0088] Circuit 5 depicts an NFET circuit portion including a first NFET 20 (N1), a second NFET 22 (N2), a third NFET 24 (N3), and a fourth NFET 26 (N4). Circuit 5 also depicts a PFET circuit portion including a first PFET 10 (P1), a second PFET 12 (P2), a third PFET 14 (P3), and a fourth PFET 16 (P4). The PFET portion is stacked on the NFET portion. The PFET portion can advantageously be stepped or tapered relative to the NFET portion.

[0089] Figure 14 is a top view of a semiconductor structure according to an embodiment of the present invention, wherein the stacked and laddered FET configuration includes a double laddered stacked FET with a larger bottom transistor.

[0090] The top view depicts a top device layer 30T having a plurality of segments 30, 32, 35 and a bottom device layer 46. The top device layer 30T may be referred to as a first device layer, and the bottom device layer 46 may be referred to as a second device layer. The plurality of segments 30, 32, 35 of the top device layer 30T may be aligned with each other (with respect to the device layer 30T). Figure 2 and Figure 5 ). This can be referred to as a double-staircase stacked FET configuration. In addition, bottom device layer 46 extends along direction "A", which causes top device layer 30T to be non-centered relative to bottom device layer 46. Therefore, the first device layer is positioned adjacent to the second device layer such that the surface of the first device layer is horizontally aligned with the surface of the second device layer.

[0091] P-type transistors are shown stacked on top of n-type transistors. For example, first PFET 10 (P1) is stacked on first NFET 20 (N1), second PFET 12 (P2) is stacked on second NFET 22 (N2), third NFET 24 (N3) is stacked on third PFET 14 (P3), and fourth NFET 26 (N4) is stacked on fourth PFET 16 (P4). Device gates "top PC" and "bottom PC" are also shown.

[0092] The letters "A" and "B" represent circuit input pins, while the letter "Z" represents a circuit output pin. Circuit input pin 50 is represented as "S," and circuit input pin 52 is represented as "SB." S stands for "select," and SB stands for "select bar." Vias 60, 62 are shown connecting circuit input pin 50 to second NFET 22 (N2) and third PFET 14 (P3).

[0093] Also shown is a cross-sectional view along the Y-axis, which depicts the circuit input pin 50 connected to the third PFET 14 (P3) through the via 62 and the circuit input pin 52 connected to the third NFET 24 (N3) through the via 64. Figure 11 4. The difference is that bottom device layer 46 is advantageously larger than bottom device layer 44 and is off-center from top device layer 30T.

[0094] Figure 15 According to an embodiment of the present invention Figure 14 1. A cross-sectional view of a semiconductor structure depicting first and second FETs in a stacked and stepped FET configuration with a larger bottom FET.

[0095] Figure 15 is a cross-sectional view along axis “X” depicting third PFET 14 (P3) and fourth PFET 16 (P4), as well as first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). Bottom device layer 46 extends over first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). Via 60 extends from circuit input pin 50 (“S”) to second NFET 22 (N2), and via 62 extends from circuit input pin 50 (“S”) to third PFET 14 (P3). Figure 3 and Figure 6 In contrast, the top device layer 30T is not visible.

[0096] In summary, exemplary embodiments of the present invention provide methods and apparatus for constructing a latch cross-coupling of a stacked ladder FET. The stacked FET includes a first device layer and a second device layer, wherein one of the device layers is advantageously shifted or tapered or stepped relative to the other device layer. The shifted or tapered device layer is advantageously shifted or tapered between device gates or "PCs." An electrical connection is advantageously made from the bottom gate to the top gate at the shifted or tapered device layer. A floating gate may also be deployed on the shifted or tapered device layer. In other embodiments, a double ladder stacked FET is advantageously deployed. Moreover, one of the device layers advantageously has a larger size or is larger than the other device layer.

[0097] about Figure 1-15 , deposition is any process of growing, coating or otherwise transferring a material onto a wafer. Available techniques include, but are not limited to, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). As used herein, "deposition" may include any now known or later developed technique suitable for the material to be deposited, including, but not limited to, for example, chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction process CVD (LRPCVD), metal organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin coating methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.

[0098] The term "processing" as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, stripping, implantation, doping, stressing, lamination, and / or removal of material or photoresist, as necessary in forming the described structures.

[0099] It will be understood that the present invention will be described with reference to a given illustrative architecture; however, other architectures, structures, substrate materials, and process features and steps / blocks may be varied within the scope of the present invention.

[0100] It will also be understood that when an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it can be directly on the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "over" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0101] This embodiment may include a design for an integrated circuit chip, which design may be created in a graphical computer programming language and stored in a computer storage medium such as a disk, tape, physical hard drive, or virtual hard drive (such as in a storage access network). If the designer does not manufacture the chip or the photolithographic masks used to manufacture the chip, the designer may transmit the resulting design directly or indirectly to such an entity by a physical mechanism (e.g., by providing a copy of the storage medium on which the design is stored) or electronically (e.g., via the Internet). The stored design is then converted to an appropriate format (e.g., GDSII) for use in manufacturing photolithographic masks, which typically include multiple copies of the chip design in question to be formed on a wafer. The photolithographic masks are used to define areas of the wafer (and / or the layers thereon) to be etched or otherwise processed.

[0102] The method described herein can be used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier with leads fixed to a motherboard or other higher-level carrier) or in a multi-chip package (such as a ceramic carrier with one or both of surface interconnects or buried interconnects). In any case, the chip is integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0103] It should also be understood that material compounds will be described with reference to listed elements, such as SiGe. These compounds include different ratios of elements within the compound, for example, SiGe includes Si x Ge 1-x , where x is less than or equal to 1, etc. In addition, other elements can be included in the compound and still function according to the present embodiment. Compounds with additional elements are referred to herein as alloys.

[0104] References in the specification to "one embodiment" or "an embodiment" of the present invention, and variations thereof, mean that a particular feature, structure, characteristic, etc. described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment," and any other variations thereof, in various places throughout the specification are not necessarily all referring to the same embodiment.

[0105] It should be appreciated that the use of any of " / ," "and / or," and "at least one of" below, such as in the case of "A / B," "A and / or B," and "at least one of A and B," is intended to encompass the selection of selecting only the first-listed option (A), only the second-listed option (B), or both options (A and B). As a further example, in the case of "A, B, and / or C" and "at least one of A, B, and C," such language is intended to encompass the selection of selecting only the first-listed option (A), only the second-listed option (B), only the third-listed option (C), only the first and second-listed options (A and B), only the first and third-listed options (A and C), only the second and third-listed options (B and C), or all three options (A, B, and C). This can be extended to any number of items listed, as readily appreciated by those of ordinary skill in this and related arts.

[0106] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the exemplary embodiments. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when used herein, the terms "comprises," "comprising," "includes," and / or "comprising" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0107] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It will be understood that, in addition to the orientations shown in the figures, spatially relative terms are intended to also include different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as being "below" or "below" other elements or features will be oriented as being "above" the other elements or features. Thus, the term "below" can include both above and below orientations. The device can also be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intermediate layers can also be present.

[0108] It will be understood that although the terms first, second, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, the first element discussed below can be called the second element without departing from the scope of this concept.

[0109] Having described preferred embodiments of methods and structures for constructing latch cross-coupling for stacked and stepped FETs (which are intended to be illustrative and not limiting), it should be noted that modifications and variations may be made by those skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made to the specific embodiments described within the scope of the invention as outlined in the appended claims. Having therefore described aspects of the invention with the detail and particularity required by the patent laws, what is claimed and desired to be protected by Letters Patent is set forth in the appended claims.

Claims

1. A semiconductor structure comprising: a first field effect transistor (FET) comprising a first device layer; a second FET comprising a second device layer, wherein the first device layer has a stepped portion relative to the second device layer; as well as An electrical connection between the gate of the first FET and the gate of the second FET at the stepped portion of the first device layer. 2 . The semiconductor structure of claim 1 , wherein the first FET is stacked on the second FET. The semiconductor structure of claim 1 , wherein the second device layer is larger than the first device layer.

4. The semiconductor structure of claim 1, wherein the first FET is a p-type FET and the second FET is an n-type FET. 5 . The semiconductor structure of claim 1 , wherein the gate of the first FET is located above the first device layer having the stepped portion. 6 . The semiconductor structure of claim 1 , wherein the gate of the first FET is located above both the first device layer and the second device layer. The semiconductor structure of claim 1 , wherein the second FET comprises a floating gate.

8. The semiconductor structure of claim 7, wherein the floating gate is vertically aligned with the stepped portion of the first device layer.

9. A semiconductor structure comprising: a first field effect transistor (FET) comprising a first device layer; a second FET comprising a second device layer; as well as An electrical connection between the gate of the first FET and the gate of the second FET at the stepped portion of the first device layer.

10. The semiconductor structure of claim 9, wherein the first FET is stacked on the second FET. The semiconductor structure of claim 9 , wherein the second device layer is larger than the first device layer. 12 . The semiconductor structure of claim 11 , wherein the first device layer is centered relative to the second device layer.

13. The semiconductor structure of claim 11, wherein the first device layer is positioned adjacent to the second device layer such that a surface of the first device layer is horizontally aligned with a surface of the second device layer. The semiconductor structure of claim 9 , wherein the first device layer substantially overlaps the second device layer.

15. The semiconductor structure of claim 9, wherein the gate of the first FET is located above the first device layer in a double staircase configuration.

16. The semiconductor structure of claim 9, wherein the gate of the first FET is located above both the first device layer and the second device layer.

17. A semiconductor structure comprising: a first field effect transistor (FET) comprising a first device layer; a second FET comprising a second device layer, wherein the second device layer is larger than the first device layer; as well as An electrical connection between the gate of the first FET and the gate of the second FET at the stepped portion of the first device layer. 18 . The semiconductor structure according to claim 17 , wherein the first device layer has a stepped portion with respect to the second device layer. The semiconductor structure of claim 17 , wherein the first FET is stacked on the second FET.

20. The semiconductor structure of claim 17, wherein the gate of the first FET is located above the first device layer having a stepped portion.

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