Method of manufacturing wafer comprising two regions having wettability contrast greater than 90 DEG and wafer manufactured thereby

Abstract

The invention mainly relates to the technical field of microelectronic 3D (three-dimensional) interconnection, but is also suitable for any application requiring micron-sized high wettability contrast. The proposed method can produce a wafer (1) comprising a main surface (10) having a solid region (101) and a micro-or nanostructured region (102), the wettability contrast between which is greater than 90 DEG, preferably greater than 120 DEG, each structured region (102) extending around the solid region (101). The wafer comprises a substrate (11), the substrate (11) comprising a first layer (111) based on a semiconductor material and a second layer (112) based on a dielectric material, a solid region and each structural region being formed in the second layer of the substrate, each structural region having a plurality of terminals (131) based on a dielectric material, the wafer having the terminals having facet ends.

Description

Technical Field

[0001] The present invention primarily relates to the field of microelectronic 3D interconnect technology, but can also be used in any application scenario requiring high wettability contrast at the micrometer scale.

[0002] More specifically, the present invention relates to chip-to-wafer (DTW) hybrid bonding chip self-assembly technology.

[0003] The present invention is particularly suitable for the three-dimensional integrated self-assembly of microelectronic components. In the case of self-assembly, the present invention can also involve the self-assembly of various chips other than microelectronic chips, in particular the self-assembly of microsystems, biochips, fluidic devices, optical devices, etc. Background Art

[0004] The development of 3D interconnect technologies aims to increase the number of functions per surface unit. Chip-to-wafer (DTW) type transfer technologies are particularly interesting for heterogeneous 3D integration, which has the advantage of assembling different technologies on the same receiving circuit, or equivalently on the same functionalized receiving wafer.

[0005] Current DTW methods are divided into two categories: a. Pick-and-Place transfer method: A robot picks up the chips and aligns them one by one on a receiving wafer (hereinafter referred to as the "target wafer"). However, in these methods, the alignment accuracy is inversely proportional to the transfer speed; and b. Self-assembly transfer method: The chip is transferred to the receiving wafer by pick-and-place equipment and roughly pre-aligned. The final alignment is achieved by liquid capillary force at the interface between the chip and the transfer area where the chip is transferred to the receiving wafer.

[0006] More specifically, self-assembly involves depositing a water droplet onto the transfer area of a hydrophilic chip and then bringing it closer to the chip. With the water droplet on both sides, capillary forces between the two surfaces allow for self-alignment. This technique improves alignment accuracy and transfer speed. Chips can be transferred individually or collectively.

[0007] Therefore, self-assembly requires adjustments to the usual chip-to-wafer (DTW) bonding integration, specifically defining hydrophilic and hydrophobic areas on the target wafer, preferably with a high surface energy contrast between the two.

[0008] In this context, it is important to note that the hydrophilicity, hydrophobicity and superhydrophobicity characteristics of a surface are characterized by its contact angle value: a hydrophilic surface has a contact angle less than 90°, a hydrophobic surface has a contact angle between 90 and 120°, and a superhydrophobic surface has a contact angle greater than 120°.

[0009] like Figure 1As shown, one way to create this wettability contrast (the difference between the contact angle α of the transferred area 101 of the chip and the contact angle β of the area 102 surrounding the transferred area 101) is: a. forming a boss (mesa in French) 15, which is typically several microns thick, on the surface 10 of the receiving wafer 1, so that the upper surface of the boss 15 constitutes a receiving area 101 for the chip; and / or b. Producing a boss typically several microns thick on the surface of each chip to be transferred; and / or c. forming a chemical contrast between each receiving area 101 on the surface of the receiving wafer 1 and the inter-chip area 102 surrounding each receiving area 101, and even between the receiving area 101 on the surface of the receiving wafer 1 and other parts of the surface of the receiving wafer 1, by providing a hydrophilic layer 1000 on the upper surface of each boss, and / or d. A chemical contrast is formed between the receiving area 101 and the inter-chip area 102 on the surface of the receiving wafer 1 by the hydrophobic layer 1001 . The hydrophobic layer 1001 covers at least the inter-chip area 102 and, if necessary, also covers the periphery of each boss 15 .

[0010] Therefore, a wettability contrast of approximately 90° can be obtained.

[0011] To create a wettability contrast between the receiving areas of the receiving wafer where the chips are to be transferred and the surrounding areas, a microstructured or nanostructured surface (i.e., a surface with micro-nano roughness) can be formed at least in the area surrounding the receiving areas, particularly to create conditions for observing a lotus-like effect. When this surface structure is combined with a chemically hydrophobic coating, it is possible to achieve a wettability contrast greater than 120°. This achieves superhydrophobicity, thereby improving alignment accuracy.

[0012] In their article “Surface Tension-Driven Self-Alignment of Microchips Based on Black-Silicon Hybrid Templates in Ambient Air,” published in the Journal of Microelectromechanical Systems (Volume 22, Issue 3, June 2013, page 739), Ali Shah et al. describe a method for fabricating hydrophilic receptor sites surrounded by a superhydrophobic surface by dry etching of silicon using deep reactive ion etching (DRIE). This method yields black silicon (i.e., a highly rough silicon surface composed of tiny needle-like structures).

[0013] However, reproducibly creating such superhydrophobic surfaces using deep reactive ion etching is not easy. Furthermore, black silicon produces a large amount of silicon fragments that fall off the surface in the form of particles, as the resulting microneedles are highly irregular and fragile in places. This is a significant disadvantage for hybrid bonding techniques, which require a surface that is as clean and particle-free as possible.

[0014] Furthermore, the methods described in the aforementioned documents require access to the substrate silicon in the inter-die region, which may require removing all materials deposited on the target wafer during circuit fabrication. Depending on the complexity of the material stack, this can become difficult and costly, especially when the upper layers of the receiving wafer are typically already functionalized and serve as interconnect layers between the target wafer and the chips.

[0015] Therefore, the object of the present invention is to propose a method for manufacturing a wafer comprising a main surface having at least one solid area and one microstructured or nanostructured area, with a wettability contrast between the two being greater than 90° (preferably greater than 120°), each microstructured or nanostructured area extending around the solid area, which makes it possible to overcome at least one disadvantage of the prior art.

[0016] More specifically, the present invention aims to provide a method for manufacturing a wafer suitable for chip self-assembly via a chip-to-wafer (DTW) hybrid bonding process.

[0017] Other purposes, features and advantages of the present invention will become apparent after the following description and the accompanying drawings. It should be understood that the present invention also has other advantages. Summary of the Invention

[0018] To achieve this goal, according to one embodiment, a method for manufacturing a wafer is provided, the wafer comprising a main surface, the main surface having at least one solid area and one microstructured or nanostructured area, the wettability contrast between them being greater than 90°, preferably greater than 120°, each microstructured or nanostructured area extending around the solid area, the method comprising the following steps: a. Providing a substrate comprising a first layer based on a semiconductor material and a second layer based on a dielectric material, the second layer extending over the first layer; b. forming a sacrificial material layer based on a sacrificial material (such as a resin) on the exposed surface of the second layer of the provided substrate, the layer having at least one first region and a second region, a solid layer based on the sacrificial material extending on the first region, and a structured surface formed by a plurality of micro-scale or nano-scale terminals based on the sacrificial material in the second region, each of the first regions being surrounded by the second region, and the surface extending from each first region being at least one order of magnitude larger than the micro-scale or nano-scale surface extending from each terminal based on the sacrificial material; and then c. etching a portion of the previously formed layer based on the sacrificial material and a portion of the second layer of the substrate, In the second layer of the substrate, at least one solid region is formed at each first region, and each microstructure or nanostructure region is formed at each second region, each microstructure or nanostructure region having a plurality of terminals based on dielectric material corresponding to a plurality of terminals based on sacrificial material.

[0019] The manufacturing method described above has the following advantages: a. The shape, size and density of the terminals made of dielectric material are fully controllable and adjustable because they are determined by the pattern drawn by the sacrificial material layer. Similarly, the distance between the solid area and the microstructure or nanostructure area is also fully controllable and adjustable because it is also determined by the pattern drawn by the sacrificial material layer; and / or b. This avoids the creation of solid areas (plateaus) of excessive thickness on the wafer surface, while still ensuring a high wettability contrast between the solid areas (or plateaus) and the microstructured or nanostructured areas.

[0020] Optionally, the first aspect of the present invention may further have at least any one of the following features, which may be used alone or in combination: According to one example, after etching, over-etching may be performed until the terminals based on the sacrificial material are completely removed. Based on each solid layer of the sacrificial material and based on the size difference (order of magnitude) between each terminal based on the sacrificial material, the sacrificial material constituting the terminals based on the sacrificial material is consumed faster during the etching process than the sacrificial material constituting each first region. This is due to the "facet effect," whereby the sacrificial material is consumed laterally in addition to being consumed from the top. Thus, a terminal based on a dielectric material having a facet end (such as a needle shape) can be obtained. Compared to the contact angle obtained with a flat-head terminal (which is substantially equal to 130°), the facet end of the terminal obtained after over-etching can increase the contact angle to substantially equal to 160°, thereby achieving a better hydrophobic effect.

[0021] According to another example, the formation of the sacrificial material-based layer can include a photolithography step. Thus, a single photolithography step on the provided substrate is sufficient to obtain a wafer having at least two regions with a wettability contrast between them greater than 90°, preferably greater than 120°. Furthermore, the etching step enables the generation of microroughness, thus belonging to a standard and fully controlled microelectronics technique, without generating defects or particles. It can be easily integrated into the manufacturing method of a receiving wafer for transferring wafers via hybrid wafer bonding, using the same type of equipment as the provided substrate manufacturing technology.

[0022] According to another example, etching can be stopped before the layer based on the sacrificial material on the right side of each first region is completely peeled off, and the thickness of the layer based on the sacrificial material remaining on the right side of each first region is preferably between 100 nm and 5 μm. Preferably, etching includes exposure to etching plasma or ion etching.

[0023] According to another example, the manufacturing method according to the first aspect of the present invention may further include, after etching, depositing (preferably conformally depositing) a layer based on a hydrophobic material (hereinafter referred to as the "hydrophobic layer"). For example, the hydrophobic material constituting the hydrophobic layer is preferably based on at least one polymer. For example, a 0.1% by weight fluorosilane polymer in a hydrofluoroether carrier solvent may be included. For example, the deposition of the hydrophobic layer may include a spin coating step or a plasma deposition step.

[0024] According to another example, the manufacturing method according to the first aspect of the present invention may further include a step of removing a portion of the sacrificial material-based layer remaining on the right side of the first region after etching so as to expose the surface of the second layer of the substrate located on the right side of each first region.

[0025] According to an example related to the two previous examples, deposition of the hydrophobic layer can be performed before the portion of the sacrificial material layer remaining to the right of the first region after etching is completely stripped. In this way, after the sacrificial material layer remaining to the right of the first region is stripped, the hydrophobic material layer to the right of the solid region is also stripped. Subsequently, because the material constituting the second substrate layer is hydrophilic, the wettability contrast between the solid region (or protrusion) and the microstructured or nanostructured region is significantly enhanced.

[0026] According to another example, the wafer can constitute a receiving wafer for transferring microelectronic components (such as microelectronic chips) by hybrid bonding, each solid area is used to receive a microelectronic component, and each micro- or nanostructured area is used to constitute at least a portion of the area between the microelectronic components.

[0027] According to the above example, the second layer of the substrate includes at least one electrical interconnect layer that extends at least to the right of each solid region and, if necessary, from the solid region to the adjacent microstructured or nanostructured region. Etching can be stopped before reaching the at least one electrical interconnect layer. Therefore, this method can maintain the integrity of insulating and metallic materials, which can be abundant in inter-chip regions and difficult to remove by etching due to their variety.

[0028] A second aspect of the present invention relates to a wafer comprising a main surface having at least one solid area and one microstructure or nanostructure area, the wettability contrast between the two being greater than 90°, preferably greater than 120°, each microstructure or nanostructure area extending around the solid area, the wafer comprising a substrate comprising a first layer based on semiconductor material and a second layer based on dielectric material, the second layer extending on the first layer, the at least one solid area and each microstructure or nanostructure area being formed in the second layer of the substrate, each microstructure or nanostructure area having a plurality of terminals based on the dielectric material, the wafer being mainly characterized in that the terminals based on the dielectric material have faceted ends.

[0029] The wafer according to the second aspect of the present invention can achieve a higher wettability contrast compared to a wafer supporting columnar terminals having a substantially constant cross-section from bottom to top.

[0030] A third aspect of the present invention relates to a method for wafer self-assembly of microelectronic components according to the second aspect of the present invention. For example, multiple microelectronic components (such as microelectronic chips) are self-assembled on a wafer by chip-to-wafer hybrid bonding.

[0031] A fourth aspect of the present invention relates to an assembly comprising the wafer according to the second aspect of the present invention and a plurality of microelectronic components (such as microelectronic chips) assembled on the wafer by hybrid bonding. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The objects, goals, features and advantages of the present invention will be better presented by the detailed description of an embodiment thereof, which is illustrated in the following drawings, in which: FIG1 schematically shows a partial cross-sectional view of an embodiment of a receiving wafer in the prior art; Figure 2 Schematically shows a partial cross-sectional view of an embodiment of a receiver wafer according to the invention and a microelectronic chip arranged opposite a surface of the receiver wafer, via which surface the microelectronic chip is intended to be assembled onto the receiver wafer by hybrid bonding; Figures 3A to 3E Schematically shows Figure 2 The steps of the embodiment of the receiving wafer manufacturing method shown in ; Figure 4A schematically illustrates a top view of one embodiment of a receiver wafer according to the present invention; Figure 4B Shown Figure 4A An enlarged view of four terminals made of dielectric material of an embodiment of a receiver wafer of the present invention is shown; Figure 5A and Figure 5BPerspective photographs of terminals without overetching and with overetching, respectively, made of dielectric material, obtained by implementing one embodiment of the manufacturing method according to the first aspect of the present invention; Figure 6A a perspective photograph showing a portion of a receiving wafer according to the present invention, the wafer comprising terminals made of a dielectric material and a cover layer made of a hydrophobic material, the terminals and the cover layer being obtained by implementing an embodiment of the manufacturing method according to the first aspect of the present invention; Figure 6B a perspective photograph showing a portion of a receiving wafer according to the present invention, the wafer comprising a receiving boss obtained by implementing one embodiment of the manufacturing method according to the first aspect of the present invention, a hydrophobic layer covering the side surfaces of the boss and the bottom of the main surface of the substrate but not covering the upper surface of the boss; Figure 7 A partial cross-sectional view of an embodiment of a receiver wafer according to the present invention is schematically shown, together with a microelectronic chip arranged opposite a surface of the receiver wafer, via which the microelectronic chip is assembled by hybrid bonding with the receiver wafer. Figure 7 and Figure 2 Basically corresponding, only the electrical interconnection layers of the receiving wafer and the microelectronic chip are further shown.

[0033] The accompanying drawings are provided for illustrative purposes only and are not intended to limit the present invention. They are schematic diagrams intended to facilitate understanding of the present invention and are not necessarily to scale in actual applications. In particular, the thicknesses of the various layers shown in the drawings do not necessarily represent actual conditions. DETAILED DESCRIPTION

[0034] Before starting to describe the embodiments of the present invention in detail, the following describes optional functions that can be used in combination or in an alternative manner: According to one example, the dielectric material constituting the second layer of the provided substrate is an oxide of the material constituting the first layer of the substrate.

[0035] Alternatively, or in addition to the above examples, the material constituting the first layer of the substrate and / or the second layer of the substrate may be selected from the following materials: silicon, germanium, sapphire, and the like.

[0036] According to an example of the first aspect of the present invention, the photolithography step includes the following sub-steps: a. solid-state deposition of a sacrificial material-based layer (eg, a photosensitive resin-based layer) on the exposed surface of the second layer of the substrate provided; b. exposing the sacrificial material layer to light radiation through a structured photolithography mask to determine a negative or positive pattern based on the microstructure of the sacrificial material layer; and then c. Chemically etching the layer based on the sacrificial material, thereby obtaining the microstructure of the layer based on the sacrificial material.

[0037] As an alternative to the above examples, the formation of the layer based on the sacrificial material comprises a screen printing step or an electron beam lithography step.

[0038] According to another example of the first aspect of the present invention, the deposition of the hydrophobic layer can be configured so that the hydrophobic layer covers each terminal based on the dielectric material, and covers each gap between the same group of terminals based on the dielectric material, and even covers the side edges of each solid area when necessary.

[0039] According to another example of the first aspect of the present invention, the layer based on sacrificial material can be formed so that its thickness is substantially constant between 200 nm and 5 µm, preferably between 500 nm and 1.5 µm, more preferably substantially equal to 800 nm.

[0040] According to another example of the first aspect of the present invention, the layer based on sacrificial material can be such that each solid area has at least one lateral dimension between 100µm and 20000µm, preferably between 500µm and 5000µm, and more preferably substantially equal to 2000µm.

[0041] According to another example of the first aspect of the present invention, the layer based on sacrificial material can be formed in such a way that the spacing between two adjacent terminals in the same group of multiple terminals is between 100nm and 1µm, preferably between 200nm and 800nm, and more preferably substantially equal to 500nm.

[0042] According to another example of the first aspect of the present invention, the etching is configured in such a way that the height of each terminal based on the dielectric material is between 100 nm and 5 µm, preferably between 400 nm and 2.5 µm, and more preferably substantially equal to 1 µm.

[0043] In one example, multiple terminals based on dielectric materials can be distributed in the microstructure or nanostructure area in a matrix manner, and / or can have an octagonal cross-section with a characteristic size substantially equal to 500nm, and / or a minimum spacing between each other substantially between 300nm and 1µm.

[0044] According to an example of the second aspect of the present invention, the wafer may further include a hydrophobic layer covering each terminal based on a dielectric material, covering each gap between the same group of multiple terminals based on a dielectric material, and even covering the side edges of each solid area if necessary, without covering the at least one solid area.

[0045] According to another example of the second aspect of the present invention: a. The height of each terminal based on the dielectric material is between 100nm and 5µm, preferably between 400nm and 2.5µm, more preferably substantially equal to 1µm, and / or b. Each terminal based on a dielectric material has at least one lateral dimension between 100 nm and 2 µm, preferably between 200 nm and 1 µm, more preferably substantially equal to 500 nm, and / or c. The distance between two adjacent terminals in the same group of multiple terminals based on dielectric material is between 100 nm and 1 μm, preferably between 200 nm and 800 nm, and more preferably substantially equal to 500 nm.

[0046] According to another example of the second aspect of the present invention, the wafer can constitute a receiving wafer for transferring microelectronic components (such as microelectronic chips) by hybrid bonding, each solid area is used to receive a microelectronic component, and each microstructure or nanostructure area is used to constitute at least a part of the area between the microelectronic components.

[0047] According to another example of the second aspect of the present invention, the second layer of the substrate may include at least one electrical interconnection layer, which extends at least to the right side of each solid area and, if necessary, extends from the solid area to the adjacent microstructure or nanostructure area. The electrical interconnection layer starts from the exposed surface of each solid area and is flush with the second layer of the substrate, and extends from each solid area at least to the adjacent microstructure or nanostructure area, more specifically, extends to below a plurality of terminals based on dielectric material of the adjacent microstructure or nanostructure area, and is encapsulated in the dielectric material constituting the second layer of the substrate.

[0048] Hybrid bonding refers to bonding between hybrid surfaces—that is, surfaces composed of multiple materials. In the case of 3D interconnects, these materials can be copper (for electrical contact) and SiO2 (for insulating the contacts). Hybrid bonding can be performed in wafer-to-wafer or chip-to-wafer mode.

[0049] A terminal with a faceted end (un plot présentant une extrémité facettée in French) means that the cross-section of the terminal decreases from its base, or from a non-zero distance from the base, to the end opposite the base. For example, a terminal may have a bullet-nose or needle-pointed end.

[0050] The so-called "microstructured or nanostructured region" refers to a region having a microstructure, that is, an element whose characteristic size is in the micrometer or nanometer range. Here, it mainly refers to a region having a microstructured or nanostructured surface.

[0051] The so-called "solid region" refers to the region opposite the microstructured or nanostructured region, such as a smooth (or flat) surface region, whose roughness is much smaller (for example, at least one order of magnitude smaller) than the surface microstructure roughness of the microstructured or nanostructured region. For example, the surface roughness of the solid region is less than 0.3 nm.

[0052] The so-called "film based on material A" refers to a film containing material A and other materials.

[0053] When a parameter is "basically equal to / greater than / less than" a given value, it means that the parameter is equal to / greater than / less than the given value, plus or minus 20% or even 10% of the given value. When a parameter is "basically between" two given values, it means that the minimum value of the parameter is equal to the lowest given value, plus or minus 20% or even 10% of the given value, and the maximum value of the parameter is equal to the maximum given value, plus or minus 20% or even 10% of the given value.

[0054] In its broadest sense, with reference to FIG. 2 , a first aspect of the present invention relates to a method for manufacturing a wafer 1 comprising a main surface 10 having at least one solid region 101 and one microstructured or nanostructured region 102 (hereinafter referred to as "structured region 102"). These regions exhibit a wettability contrast, defined as the difference between the contact angle α associated with the solid region 101 and the contact angle β associated with the structured region 102, which is greater than 90°, preferably greater than 120°. Furthermore, each structured region 102 extends around the solid region 101.

[0055] This definition allows the wafer and the method for its manufacture to be used not only for receiving a microelectronic component 2 (such as a microelectronic chip) by transfer for hybrid bonding onto the wafer, but also for any other type of application, in particular any type of application requiring a high wettability contrast on a micrometer scale.

[0056] Therefore, although the present invention is described below as its main application scenario (ie, the application of self-assembly of microelectronic components 2 on a wafer 1 by chip-to-wafer hybrid bonding), the present invention is not limited to this application.

[0057] An embodiment of the manufacturing method according to the first aspect of the present invention will be described below with reference to FIG. 3A to FIG. 3E .

[0058] The method first begins by providing a substrate 11 comprising a first layer 111 based on a semiconductor material and a second layer 112 based on a dielectric material, with the second layer 112 extending onto the first layer 111 and having an exposed surface 1121. In the illustrated example, the semiconductor material constituting the first layer 111 is silicon, and the dielectric material constituting the second layer 112 is silicon oxide. However, the dielectric material constituting the second layer of the provided substrate is not necessarily an oxide of the material constituting the first layer of the substrate. Furthermore, semiconductor materials other than silicon are contemplated, for example, as long as they can be structured using the photolithography and dry etching techniques that may be involved in implementing the method according to the first aspect of the present invention; germanium, sapphire, and the like are typical examples of such materials. In this context, it is important to note that the thickness e of the second layer 112 of the substrate 11 is less than 10µm; this thickness e will be further greater than the height of the dielectric-based terminals 131 that can be fabricated on the surface of the substrate 11 using this method; if necessary, it will even be greater than the height of the terminals 131 and the height of the electrical interconnect layer 110 embedded in the dielectric material of the second layer 112 (see FIG. 7 ). In practice, the dielectric terminal 131 may be formed on an upper layer of the second layer 112 of the substrate 11 that has no electrical interconnections at all, so that its formation maintains the integrity of electrical interconnections, if any.

[0059] Reference Figure 3B , the method according to the first aspect of the present invention further includes forming a layer 12 based on a sacrificial material on the exposed surface 1121 of the second layer 112 of the substrate 11, hereinafter referred to as the "sacrificial layer 12". The sacrificial material can be a resin, more specifically, a photosensitive resin, a thermosetting resin or an electrosensitive resin (in the case of electronic lithography). The sacrificial layer 12 is formed to have a first region 1201 and a second region 1202, on which a solid layer 121 based on the sacrificial material extends; on the second region, a plurality of micrometer-scale or nanometer-scale terminals 122 based on the sacrificial material extend, hereinafter referred to as the "sacrificial terminals 122". In Figure 3B In FIG. 1 , the second region 1202 is shown as being located on both sides of the first region 1201, but Figure 3B What is shown is a cross-sectional view, and in reality each first region 1201 is surrounded by a second region 1202 .

[0060] Figure 4AA top view of an embodiment of a wafer 1 according to the second aspect of the present invention is provided. As can be seen from the figure, each solid region 101 is effectively surrounded by structured regions 102, requiring a corresponding distribution of each first region 1201 and its surrounding second regions 1202. In this context, FIG4A also illustrates that the receiving surface of the microelectronic component 2 need not necessarily be circular or square, but can have various shapes. However, it is understood that the greater the aspect ratio of the receiving surface, the greater the risk of inaccurate alignment of the microelectronic component 2 on the receiving surface.

[0061] In addition, the surface area of each first region 1201 is larger than the micrometer or nanometer surface area of each sacrificial terminal 122. Preferably, the surface area of each first region 1201 is at least one order of magnitude larger than the surface area of each sacrificial terminal 122. Figure 3B In the schematic diagram provided, all sacrificial terminals 122 are of equal size and regularly spaced, but any variation of this matrix arrangement is contemplated, as long as the wafer 1 can be manufactured according to the second aspect of the present invention. In particular, it is contemplated that the sacrificial layer 12 follows a design that ultimately makes it possible to form a density gradient of dielectric terminals 131 on the surface of the structured region 102, thereby making it possible to form a wettability gradient between the bonding surfaces.

[0062] As will be described below, the surface over which each first region 1201 extends is intended to form a receiving surface for a microelectronic element 2; therefore, its dimensions are primarily limited by the dimensions of said microelectronic element 2, or by the dimensions of the protrusions formed on the surface of the microelectronic element 2 and defining the transfer surface of said element on the wafer 1. In this sense, the sacrificial layer 12 can be formed so that each solid region 1201 has at least one lateral dimension between 100 µm and 20,000 µm, preferably between 500 µm and 5,000 µm, and more preferably substantially equal to 2,000 µm.

[0063] The dimensions of sacrificial terminals 122 are inherently limited by the desired goal, namely, the wettability contrast between solid areas 101 and structured areas 102 of main surface 10 of wafer 1. Indeed, the dimensions of sacrificial terminals 122 predetermine the dimensions of the terminals made of dielectric material 131 (hereinafter referred to as "dielectric terminals 131"), as well as the dimensions of the gaps separating these dielectric terminals 131; these dimensions determine the contact angle β on the microstructured surface created by dielectric terminals 131, and therefore influence the wettability contrast of the resulting wafer 1.

[0064] The dimensions of the dielectric terminals 131 and the separation gaps between these terminals preferably satisfy the following conditions: a. Each sacrificial terminal 122 has at least one lateral dimension between 100 nm and 2 µm, preferably between 200 nm and 1 µm, more preferably substantially equal to 500 nm, and / or b. The distance between two adjacent sacrificial terminals 122 in the same group of multiple sacrificial terminals 122 is between 100 nm and 1 μm, preferably between 200 nm and 800 nm, and more preferably substantially equal to 500 nm.

[0065] Furthermore, the sacrificial layer 12 is preferably formed to have a substantially constant thickness between 200 nm and 5 µm, preferably between 500 nm and 1.5 µm, and more preferably approximately 800 nm. As described below, the thickness of the sacrificial layer 12, along with its material properties and the etching method employed, determines the height of the dielectric terminals 131 and, therefore, affects the resulting wettability contrast.

[0066] Although the sacrificial layer 12 preferably has a substantially constant thickness between different solid regions 101 or structured regions 102, the manufacturing method of the first aspect of the present invention is not limited thereto. For example, the sacrificial layer 12 may be formed such that the thickness of the sacrificial layer 12 on each solid region 101 is greater than the height of the sacrificial terminal 122, so that, for example, etching can be further advanced during the overetching process described below without consuming all of the sacrificial material present on each solid region 101 before the overetching.

[0067] According to a preferred embodiment of the manufacturing method of the first aspect of the present invention, the formation of the sacrificial layer 12 includes a photolithography step, which is a standard microelectronics step that is controllable and can be adjusted over a wide range. Also, it should be noted that this photolithography step can include the following sub-steps: a. depositing a solid layer based on the sacrificial material on the exposed surface 1121 of the second layer 112 of the provided substrate 11, b. exposing the layer based on the sacrificial material to light radiation through a structured photolithographic mask to define a negative or positive pattern of the desired microstructure of the layer based on the sacrificial material, and then c. Chemically etching the layer based on the sacrificial material to obtain the desired microstructure.

[0068] Alternatively, the formation of the layer based on the sacrificial material comprises at least one screen printing step.

[0069] Reference Figure 3C, the method according to the first aspect of the present invention further includes etching a portion of the previously formed sacrificial layer 12 and a portion of the second layer 112 of the substrate 11. More specifically, the etching is such that, in the second layer 112 of the substrate 12, a solid region 100 is formed on each first region 1201, and a structure region 102 is formed on each second region 1202, each structure region 102 having a plurality of dielectric terminals 131, as described above, these dielectric terminals 131 correspond to the plurality of sacrificial terminals 122, and each dielectric terminal 131 has a cross-section whose size and shape correspond to the size and shape of the sacrificial terminal 122. For example, referring to Figure 4A and Figure 4B If the sacrificial terminal 122 has an octagonal cross-section, a characteristic dimension A between two opposing edges of 500 nm, and a minimum separation distance B between 300 nm and 1 µm, then the corresponding dielectric terminal 131 will have the same octagonal cross-section and the same minimum separation distance. Other shapes are naturally possible (circular, square, etc.).

[0070] The multiple dielectric terminals 131 extending from each structural region 102 create a lotus effect observation condition, making the exposed surface of the structural region 102 superhydrophobic. However, the degree of superhydrophobicity imparted by the multiple dielectric terminals to the exposed surface of each structural region 102 varies depending on the etching method.

[0071] In the field of microelectronics, the standard implementation of this etching involves exposure to plasma or ion etching in order to form Figure 5A The cross-section of these pillars is substantially constant from the base to the apex, and can be identified at the dielectric terminals 131. However, in order to increase the wettability contrast between the solid area 101 and the structured area 102 surrounding the solid area 101, it is preferred that the cross-section of the dielectric terminals 131 gradually decreases from their base (or a non-zero distance from their base) to their apex. For example, Figure 5B As shown, each dielectric terminal 131 preferably has a bullet-shaped or needle-pointed end. To achieve this advantageous shape for the dielectric terminals 131, etching can simply be continued beyond the standard etching method until the sacrificial terminals 122 are completely removed; thus, as described above, this can be referred to as overetching. Therefore, by pushing the etching step far enough, more specifically, beyond the standard etching method (which only consumes a portion of the sacrificial material), so that the sacrificial material constituting the sacrificial terminals 122 is completely consumed by a single etching step, it is possible to obtain dielectric terminals 131 with pointed ends, as shown in FIG. Figure 5B As shown, the structured region 102 has super hydrophobic properties, with a contact angle substantially equal to 160°, compared to the structured region 102 having a flat dielectric terminal (such as Figure 5A The contact angle was significantly increased.

[0072] The difference between the lateral dimensions of the solid layer 121 and each sacrificial terminal 122 is at least one order of magnitude, which makes the above situation possible. In fact, during the etching process, the sacrificial material is consumed faster in the narrow pattern formed by the sacrificial terminals 122 than in the larger pattern forming the solid layer 121. Therefore, due to over-etching, a solid layer 121' with a thickness less than the original solid layer 121 will remain on the right side of the solid area 101, as shown in FIG. Figure 3C This phenomenon can be explained as a "facet effect". This effect indicates that during the etching process, in addition to the sacrificial material and the dielectric material forming the basis of the second layer 112 of the substrate 11 being consumed from the top, these materials are also consumed from the lateral direction; however, when the same etching is performed on patterns of different sizes, the lateral consumption of small-sized patterns is more significant than that of large-sized patterns. Note that in Figure 3C , the effect of faceting on the shape of the resulting dielectric terminals 131 is roughly illustrated by illustrating each terminal in a tapered cross-section.

[0073] However, there is preferably an upper limit to the degree of etching beyond the standard for at least two reasons.

[0074] The first of these two reasons is that it is indeed advantageous to stop etching before the sacrificial material on the right side of each first region 1201 is stripped off. In this way, at the end of etching, more specifically, at the end of overetching, there is still a certain thickness of sacrificial material on the right side of each first region 1201, and the thickness is preferably between 100 nm and 5 μm.

[0075] The second of the two reasons for not extending the etching is that after the sacrificial material 12 on the right side of each second region 1202 is removed, the size of the dielectric terminal 131 is reduced, especially the height is reduced; however, the etching is preferably configured so that the height of each dielectric terminal 131 is between 100nm and 5µm, preferably between 400nm and 2.5µm, and more preferably substantially equal to 1µm.

[0076] Reference Figure 3DThe method according to the first aspect of the present invention may further comprise, after etching, depositing a layer 14 based on a hydrophobic material (preferably conformally deposited), hereinafter referred to as "hydrophobic layer 14". For example, the hydrophobic material constituting the hydrophobic layer 14 is preferably at least one polymer. For example, it comprises a 0.1% by weight fluorosilane polymer in a hydrofluoroether carrier solvent. For example, this may be a coating with the trade name 3M™ Novec™ 1720 Electronic Grade Ultra Fine. In the context of the present invention, any material known to have hydrophobic properties may be considered, and the above examples are not intended to limit the present invention. For example, the deposition of the hydrophobic layer comprises a spin coating step or a plasma deposition step. Of course, the hydrophobic layer 14 is beneficial in improving the wettability contrast between the solid area 101 and the structured area 102.

[0077] Preferably, if Figure 6A and Figure 6B As shown, the deposition configuration of the hydrophobic layer 14 is such that the hydrophobic layer 14 covers each dielectric terminal 131 and each gap 132 between the dielectric terminals 131 or between the dielectric terminals and the solid area, and even covers the side edges 1011 of the protrusions 15 when necessary. It should be noted that in this case, if the etching is advanced to consume all the sacrificial material on the right side of the second area 1202 to obtain the faceted dielectric terminals 131, the advantage of this over-etching is that the hydrophobic layer 14 can be deposited on the dielectric terminals 131 and in the gaps therein without the need to remove the sacrificial material remaining on the right side of the second area 1202. In addition, since it is preferred that the etching does not completely consume all the sacrificial material formed on the right side of the first area 1201, in this case, the deposition of the hydrophobic layer 14 will also result in covering the sacrificial material remaining on the right side of the first area 1201 (at least covering its upper surface and possibly also covering its side surfaces). This situation is shown in FIG. Figure 3D shown.

[0078] Reference Figure 3E The method according to the first aspect of the present invention may further include, preferably after the hydrophobic layer 14 is deposited, removing any remaining portion of the sacrificial layer 12 (particularly the portion of the sacrificial layer 12 remaining to the right of the first region 1201 after etching). After removing this portion of the sacrificial layer, the surface 1000 of the second layer 112 of the substrate 11 located to the right of each first region 1201 is exposed. In this case, Figure 2 and Figure 7 This surface 1000 is also shown in FIG. Figure 3D and Figure 3EAs can be seen in the figure, depositing the hydrophobic layer 14 before removing the remaining portions of the sacrificial layer 12 after etching simultaneously removes the hydrophobic layer 14 covering the remaining portions of the sacrificial layer 12, particularly in the etched solid areas 101. Subsequently, as long as the material constituting the second layer 112 of the substrate 11 (particularly silicon oxide) is hydrophilic, the wettability contrast between the solid areas 101 and the structured areas 102 is significantly increased. Notably, the contact angle α of water on such hydrophilic silicon oxide-based surfaces is typically less than 10°.

[0079] It is worth noting that Figure 3E The wafer shown is Figure 2 In other words, from Figure 3E At the end of the steps of the method shown, a wafer 1 has been produced which is suitable for self-assembly of microelectronic components 2 on the wafer 1 by hybrid bonding of the chip-to-wafer type.

[0080] Figure 7 As an example (but not exclusive of the above), a more specific scenario is illustrated in which the second layer 112 of the substrate 11 includes at least one electrical interconnect layer 110 extending from the solid region 101 to the structured region 102. More specifically, the electrical interconnect layer is buried in, or equivalently encapsulated within, the dielectric material comprising the second layer 112 of the substrate 11. Starting from the exposed surface 1000 of each solid region 101, the electrical interconnect is flush with the second layer 112 of the substrate 11, facilitating electrical reconnection with the microelectronic component 2 to be removed from the solid region 101. Conversely, within each structured region 102, the electrical interconnect layer is buried in, or equivalently encapsulated within, the dielectric material comprising the second layer 112 of the substrate 11. The depth of these buried electrical interconnect layers determines the thickness of the second layer 112 of the substrate 11 that can be used to form the dielectric terminals 131, ensuring that etching does not alter the integrity of the buried interconnect layer. It can be seen that the manufacturing method according to the first aspect of the present invention is compatible with the self-assembly method, so that the microelectronic components transferred by the receiving wafer 1 are functionally electrically connected, and the electrical interconnection layer can extend from the solid area 101 to the adjacent structural area 102, or even further. In order to maintain the integrity of the electrical interconnection layer, it is necessary to stop etching before the etching reaches the electrical interconnection layer. Therefore, in the process of manufacturing the substrate 11, a sufficiently thick dielectric material can be covered on the electrical interconnection layer where the structural area 102 is intended to be formed, so that the dielectric terminal 131 of the desired geometric shape can be etched on this layer of material without etching the electrical interconnection layer. In addition, it should be noted that the height of the dielectric terminal 131 obtained by implementing the method of the first aspect of the present invention is substantially equal to the height of the boss 15 obtained by the same implementation method. With respect to the receiving wafer known in the prior art, for example, with respect to Figure 1In the wafer of the example, the height of the protrusion 15 obtained by implementing the method of the first aspect of the present invention is reduced. Although this reduction does not increase the wettability contrast between the solid area 100 and the surrounding structured area 102, its advantages are: a. facilitate industrial integration according to the method of the first aspect of the present invention, and b. The micro-roughness imparted to the structured region 102 by the microstructure obtained by implementing the method of the first aspect of the present invention can largely compensate for the potential degradation of the self-alignment performance.

[0081] Therefore, the manufacturing method according to the first aspect of the present invention can manufacture a wafer 1 according to the second aspect of the present invention, more specifically, a receiving wafer 1 for transferring microelectronic components 2 by hybrid bonding, each solid area 101 is used to receive a microelectronic component 2, and each structured area 102 is used to constitute at least a part of the area between the microelectronic components 2.

[0082] More specifically, such a wafer 1 mainly includes a main surface 10, the main surface 10 has at least one solid area 101 and a structured area 102, the wettability contrast between the two is greater than 90°, preferably greater than 120°, each microstructure or nanostructured area 102 extends around the solid area 101, the wafer includes a substrate 11, the substrate 11 includes a first layer 111 based on a semiconductor material and a second layer 112 based on a dielectric material, the second layer 112 extends onto the first layer 111, the at least one solid area 101 and each structured area 102 are formed in the second layer 112 of the substrate 11, and each microstructure or nanostructured area 102 has a plurality of terminals 131 based on a dielectric material.

[0083] Moreover, when the etching is over-etching, all sacrificial materials formed on the right side of each second region 1202 are consumed. For example, the dielectric terminal 131 of the wafer 1 has a dielectric layer 132 of the same thickness as shown in FIG. Figure 5B The facet ends 1311 are shown to further increase the wettability contrast and can easily be made greater than 120°, or even greater than 140°.

[0084] More specifically, according to the second aspect of the present invention, the wafer 1 may satisfy the following conditions: a. The height of each dielectric terminal 131 is between 100 nm and μm, preferably between 400 nm and 2.5 μm, more preferably substantially equal to 1 μm, and / or b. Each dielectric terminal 131 has at least one lateral dimension between 100 nm and 2 μm, preferably between 200 nm and 1 μm, more preferably substantially equal to 500 nm, and / or c. The spacing between two adjacent dielectric terminals 131 in the same group of multiple dielectric terminals is between 100nm and 1µm, preferably between 200nm and 800nm, and more preferably substantially equal to 500nm, Regardless of whether the dielectric terminals 131 and the gaps 132 between these terminals are covered by the hydrophobic coating 14 , this dimensioning enables the surface of the structured region 102 to have superhydrophobicity.

[0085] According to a third aspect, the present invention also relates to a self-assembly method of a receiving wafer 1 implemented according to the second aspect of the present invention, and an assembly 0 obtained by implementing the self-assembly method according to the third aspect of the present invention.

[0086] It should be understood that the present invention has the following advantages: a. Simply adding a single photolithography layer on the substrate 11 to make it more suitable for self-assembly; and / or b. The etching step that makes it possible to generate the micro-roughness is a standard, fully controlled microelectronics step that does not generate defects or particles. It can be easily integrated into the chip production process and uses the same type of equipment as the previous steps of the production process; and / or c. The shape, size, and density of the resulting dielectric terminals 131 are fully controllable, as they correspond to the pattern drawn on the added photoresist layer. Similarly, the distance between the receiving area (hydrophilic area) of the chip 2 and the receiving area between the chips (superhydrophobic area) is also adjustable, as this is determined by the design of the sacrificial layer 12, which is not the case with the black silicon available in the scientific literature mentioned in the background art; and / or d. without removing all insulating and metallic materials that constitute the electrical interconnect layer 110, which may be very abundant in the inter-chip region and difficult to remove by etching due to their wide variety; and / or e. This can avoid the generation of very large protrusions 15 on the surface of the chip and the receiving wafer 1. Similarly, the acquisition of this protrusion also helps to achieve a higher wettability contrast between the solid area 101 and the structured area 102.

[0087] The present invention is not limited to the embodiments described above, but extends to all embodiments covered by the claims.

Claims

1. A method for manufacturing a wafer (1), said wafer (1) comprising a main surface (10), said main surface (10) having at least one solid area (101) and one microstructured or nanostructured area (102), the wettability contrast between the two being greater than 90°, preferably greater than 120°, each microstructured or nanostructured area (102) extending around said solid area (101), said method comprising the following steps: • providing a substrate (11) comprising a first layer (111) based on a semiconductor material and a second layer (112) based on a dielectric material, said second layer (112) extending onto said first layer (111); • forming a sacrificial material layer (12) based on, for example, a resin, on the exposed surface (1121) of the second layer (112) of the provided substrate (11), the sacrificial material layer having at least one first region (1201) and a second region (1202), a solid layer (121) based on the sacrificial material extending on the first region, a plurality of micrometer- or nanometer-scale sacrificial terminals (122) based on the sacrificial material extending on the second region, each first region (1201) being surrounded by the second region (1202), and each first region (1201) extending onto a surface that is at least one order of magnitude larger than the micrometer- or nanometer-scale surface to which each sacrificial terminal (122) extends; • etching a portion of the previously formed sacrificial material layer (12) and a portion of the second layer (112) of the substrate (11), In the second layer (112) of the substrate (12), the at least one solid region (101) is formed at each first region (1201) and each microstructure or nanostructure region (102) is formed at each second region (1202), each microstructure or nanostructure region (102) having a plurality of dielectric material-based dielectric terminals (131) corresponding to a plurality of sacrificial terminals (122).

2. The method according to the preceding claim, wherein the etching comprises overetching the sacrificial terminal (122) so as to cause lift-off of the sacrificial terminal (122).

3. A method according to any one of the preceding claims, wherein forming the sacrificial material layer (12) comprises a photolithographic step.

4. A method according to any one of the preceding claims, wherein Etching is stopped before stripping of the sacrificial material layer (12) on the right side of each first region (1201) is achieved, and the remaining thickness of the sacrificial material layer (12) on the right side of each first region (1201) is preferably between 100 nm and 5 μm.

5. The method according to any of the preceding claims, further comprising, after etching, depositing, preferably conformally depositing, a hydrophobic layer (14) based on a hydrophobic material.

6. The method according to the preceding claim, wherein the deposition configuration of the hydrophobic layer (14) is such that the hydrophobic layer (14) covers each dielectric terminal (131) and each gap (132) between the same group of multiple dielectric terminals (131), and even covers the side edges (1011) of each solid area (101) when necessary.

7. The method according to any one of the preceding claims, further comprising the step of removing the portion of the sacrificial material layer (12) remaining on the right side of the first region (1201) after etching, so as to expose the surface (1000) of the second layer (112) of the substrate (11) located on the right side of each first region (1201).

8. The method according to any one of claims 5 and 6 and claim 7, wherein the deposition of the hydrophobic layer (14) is performed before stripping the portion of the sacrificial material layer (12) remaining on the right side of the first area (1201) after etching.

9. The method according to claim 1 , wherein the wafer ( 1 ) constitutes a receiving wafer for transferring microelectronic components ( 2 ), such as microelectronic chips, by hybrid bonding, each solid region ( 101 ) being intended to receive a microelectronic component ( 2 ) and each microstructured or nanostructured region ( 102 ) being intended to constitute at least a portion of the region between the microelectronic components ( 2 ).

10. The method according to any of the preceding claims, wherein the sacrificial material layer (12) is formed such that the sacrificial terminal (122) and the dielectric terminal (131) have at least one lateral dimension between 100 nm and 2 µm, preferably between 200 nm and 1 µm, more preferably substantially equal to 500 nm.

11. The method according to any one of the preceding claims, wherein the sacrificial material layer (12) is formed so that the spacing between two adjacent terminals (122, 131) in the same group of multiple terminals is between 100nm and 1µm, preferably between 200nm and 800nm, and more preferably substantially equal to 500nm.

12. The method according to any of the preceding claims, wherein the etching is configured such that the height of each dielectric terminal (131) is between 100 nm and 5 µm, preferably between 400 nm and 2.5 µm, more preferably substantially equal to 1 µm.

13. A wafer (1) comprising a main surface (10), the main surface (10) having at least one solid area (101) and one microstructured or nanostructured area (102), the wettability contrast between the two being greater than 90°, preferably greater than 120°, each microstructured or nanostructured area (102) extending around the solid area (101), the wafer comprising a substrate (11), the substrate (11) comprising a first layer (111) based on a semiconductor material and a second layer (112) based on a dielectric material, the second layer (112) extending on the first layer (111), the at least one solid area (101) and each microstructured or nanostructured area (102) being formed in the second layer (112) of the substrate (11), each microstructured or nanostructured area (102) having a plurality of dielectric terminals (131) based on a dielectric material, the wafer being characterized in that the dielectric terminals (131) have faceted ends (1311).

14. The wafer (1) according to the preceding claim further comprises a hydrophobic layer (14) covering each of the dielectric terminals (131) and each gap (132) between the same group of multiple dielectric terminals (131), and even covering the side edges (1011) of each solid area (1201) when necessary, but not covering the at least one solid area (1201).

15. The wafer (1) according to any one of claims 13 to 14, wherein • the height of each of said dielectric terminals (131) is between 100 nm and 5 µm, preferably between 400 nm and 2.5 µm, more preferably substantially equal to 1 µm, and / or • each of said dielectric terminals (131) has at least one lateral dimension between 100 nm and 2 µm, preferably between 200 nm and 1 µm, more preferably substantially equal to 500 nm, and / or • The distance between two adjacent dielectric terminals (131) in the same group of multiple dielectric terminals is between 100 nm and 1 µm, preferably between 200 nm and 800 nm, and more preferably substantially equal to 500 nm.

16. Wafer (1) according to any one of claims 13 to 15, constituting a receiving wafer for transferring microelectronic components (2), such as microelectronic chips, by hybrid bonding, each solid area (101) being intended to receive a microelectronic component (2), and each microstructured or nanostructured area (102) being intended to constitute at least a part of an area between the microelectronic components (2).

17. Wafer (1) according to the preceding claim, wherein the second layer (112) of the substrate (11) comprises at least one electrical interconnection layer (110), which extends at least to the right of each solid area (101) and, if necessary, from the solid area (101) to the adjacent microstructure or nanostructure area (102), starting from the exposed surface (1000) of each solid area (101), the electrical interconnection layer (100) is flush with the second layer (112) of the substrate (11) and extends from each solid area (101) at least to the adjacent microstructure or nanostructure area (102), more specifically to below a plurality of dielectric terminals (131) of the adjacent microstructure or nanostructure area (102) encapsulated in the dielectric material constituting the second layer (112) of the substrate (11).

18. A method for self-assembly of microelectronic components of a wafer (1) according to any one of claims 13 to 17.

19. The self-assembly method according to the preceding claim, wherein a plurality of microelectronic components (2), such as microelectronic chips, are self-assembled on the wafer (1) by chip-to-wafer type hybrid bonding.

20. An assembly (0) comprising a wafer (1) according to any one of claims 13 to 17 and a plurality of microelectronic elements (2), such as microelectronic chips, assembled on the wafer (1) by hybrid bonding.

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