A backside illumination image sensor failure analysis layer-by-layer delayering method

Abstract

The present application relates to a kind of back-illuminated image sensor failure analysis layer-by-layer delamination method, belong to back-illuminated image sensor technical field.The back-illuminated image sensor failure analysis layer-by-layer delamination method described in the present application includes the following steps: first, the packaging of back-illuminated image sensor is removed, then the obtained back-illuminated image sensor chip is inverted and fixed in the chip accommodating groove opened in a wafer by glue, then plane thinning substrate layer, etching, grinding, chemical etching etc. Layer-by-layer delamination technology is carried out to delaminate layer by layer.The back-illuminated image sensor failure analysis layer-by-layer delamination method of the present application can prevent the damage of each layer structure in the back-illuminated image sensor chip caused by uneven stress and other factors in each delamination technology, ensure that the key circuit structure is not damaged while delaminating, so as to meet the subsequent monitoring observation, failure analysis.

Description

Technical Field

[0001] This invention relates to the field of back-illuminated image sensor technology, and in particular to a layer-by-layer method for failure analysis of back-illuminated image sensors. Background Technology

[0002] Back-illuminated (BSI) image sensors are widely used in smartphones, autonomous driving, medical imaging, and other fields. As consumers' demands for the quality and reliability of BSI image sensors continue to increase, failure analysis of these sensors is becoming increasingly important. Failure analysis of BSI image sensors requires removing the package and de-layering the chip to facilitate failure analysis of its internal structure (primarily the metal interconnect structure within the dielectric layer).

[0003] However, the multi-layered stacked structure of back-illuminated image sensor chips (such as microlenses, photosensitive layers, photodiodes, and metal interconnects in the dielectric layer) faces significant challenges in failure analysis. Traditional delamination techniques (such as mechanical polishing and dry etching) are prone to damaging sensitive structures due to uneven stress or thermal damage during the delamination process, leading to the loss of failure points and difficulty in accurately locating defects. This makes it impossible to determine the failure mechanism based on the failure phenomena. For example, mechanical polishing relies on physical grinding for delamination, which is prone to causing the microlenses, photosensitive layers, photodiodes, and metal interconnects in the dielectric layer of back-illuminated image sensor chips to break due to uneven stress. Furthermore, it cannot ensure that critical circuit structures are not damaged during delamination, affecting failure analysis. In addition, plasma focused ion beam (P-FIB) can also be used for delamination in existing technologies. P-FIB offers high precision in layer-by-layer milling but is inefficient, costly, and unsuitable for large-area failure analysis. Summary of the Invention

[0004] Based on this, the purpose of the present invention is to provide a layer-by-layer delamination method for failure analysis of back-illuminated image sensors, which has the advantages of non-destructive layer-by-layer delamination, selective delamination, and prevention of damage to critical structures, and is applicable to failure analysis of back-illuminated image sensors.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] This invention provides a layer-by-layer removal method for failure analysis of back-illuminated image sensors, comprising the following steps:

[0007] (1) Remove the packaging of the back-illuminated image sensor to obtain the back-illuminated image sensor chip.

[0008] (2) Take a wafer with a chip receiving groove (the chip receiving groove is used to receive the image sensor chip); fill the chip receiving groove with glue, and invert the back-illuminated image sensor chip and place it in the chip receiving groove, bake and cure to obtain a sample;

[0009] (3) The sample is thinned by grinding, so that the substrate layer of the back-illuminated image sensor chip and the wafer are thinned together, and the upper surface of the thinned wafer and the upper surface of the thinned substrate layer are located on the same plane.

[0010] (4) The sample after step (3) is etched by reactive ion etching to remove the substrate layer and expose a metal layer of the back-illuminated image sensor chip. The upper surface of the etched wafer and the upper surface of the metal layer are located on the same plane.

[0011] (5) The metal layer is removed by chemical etching and the interconnect layer of the back-illuminated image sensor chip is exposed by grinding, and the upper surface of the wafer after grinding is located on the same plane as the upper surface of the interconnect layer; the interconnect layer is removed by chemical etching and the next metal layer is exposed by grinding, and the upper surface of the wafer after grinding is located on the same plane as the upper surface of the next metal layer.

[0012] (6) Repeat step (5) to remove the next metal layer and interconnect layer one by one until the last interconnect layer is exposed by grinding, and the upper surface of the ground wafer is on the same plane as the upper surface of the last interconnect layer.

[0013] The back-illuminated image sensor failure analysis layer-by-layer delamination method of the present invention first removes the packaging of the back-illuminated image sensor, then inverts the obtained back-illuminated image sensor chip and fixes it in the chip receiving groove of the wafer with adhesive, and then performs subsequent layer-by-layer delamination work. The back-illuminated image sensor failure analysis layer-by-layer delamination method of the present invention, by fixing the back-illuminated image sensor chip in the chip receiving groove, and simultaneously ensuring that the upper surface of the wafer after etching, grinding, and other delamination techniques is always on the same plane as the upper surface of the back-illuminated image sensor chip during subsequent layer-by-layer delamination work, can effectively protect the undelamination layers in the back-illuminated image sensor chip. It can prevent the edges of the layers in the back-illuminated image sensor chip from being easily damaged or misaligned due to factors such as inconsistent material hardness and height differences between the layers in the back-illuminated image sensor chip, and uneven stress during etching, grinding, and other delamination techniques, thus preventing failure analysis and subsequent monitoring.

[0014] The layer-by-layer delamination method for failure analysis of back-illuminated image sensors described in this invention can avoid damage to microlenses, photosensitive layers, photodiodes, and metal interconnect structures in dielectric layers caused by uneven stress or thermal damage in traditional delamination techniques. It achieves non-destructive layer-by-layer delamination and provides different delamination techniques for different back-illuminated image sensor chip materials to achieve selective delamination. The delamination effect is good, and it can also prevent damage to critical structures, significantly improving the efficiency and accuracy of failure location. It is applicable to defect analysis (failure analysis) in the field of semiconductor manufacturing and packaging processes.

[0015] Further, in step (1), a mixed acid is used to remove the encapsulation of the back-illuminated image sensor, wherein the mixed acid includes concentrated sulfuric acid and fuming nitric acid. As a preferred embodiment, the mixed acid is placed in a container (e.g., a beaker) and heated to 90-110°C (preferably 100°C). The back-illuminated image sensor is then placed in the container and etched for 4-6 minutes (preferably 5 minutes) to remove the outer encapsulation, thus obtaining the back-illuminated image sensor chip. The mixed acid comprises concentrated sulfuric acid and fuming nitric acid; the mass fraction of the concentrated sulfuric acid is 96-98%, and the mass fraction of the fuming nitric acid is 98%; the volume ratio of concentrated sulfuric acid to fuming nitric acid in the mixed acid is 0.8-1.2:0.8-1.2 (preferably 1:1). This mixed acid is beneficial for removing the encapsulation of the back-illuminated image sensor. Of course, those skilled in the art can selectively adjust the concentration and volume ratio of the concentrated sulfuric acid and fuming nitric acid in the mixed acid, as well as the temperature and time, according to actual conditions, as long as the encapsulation of the back-illuminated image sensor can be removed.

[0016] Further, in step (1), the structure of the back-illuminated image sensor chip includes a microlens, a photosensitive layer, a photodiode, a dielectric layer, and a substrate layer arranged sequentially from top to bottom; wherein, a metal interconnect structure is formed in the dielectric layer, and the metal interconnect structure includes several groups of interconnect layers and metal layers connected from top to bottom. That is, in step (2), the inverted back-illuminated image sensor chip includes a substrate layer, a dielectric layer, a photodiode, a photosensitive layer, and a microlens arranged sequentially from top to bottom; wherein, a metal interconnect structure is formed in the dielectric layer, and the metal interconnect structure includes several groups of interconnect layers and metal layers connected from top to bottom. When performing failure analysis on a back-illuminated image sensor chip, the main focus is on the failure analysis of the metal layers and interconnect layers in the metal interconnect structure. The layer-by-layer delamination method for failure analysis of the back-illuminated image sensor described in this invention can effectively protect the metal layers and interconnect layers in the metal interconnect structure. It can prevent damage to the metal layers and interconnect layers in the metal interconnect structure of the back-illuminated image sensor chip due to factors such as uneven stress during delamination techniques such as etching and polishing. This ensures that critical circuit structures are not damaged during delamination, so as to meet the requirements of subsequent monitoring, observation, failure analysis, etc.

[0017] Furthermore, in step (2), the area of ​​the wafer is more than two-thirds larger than the area of ​​the back-illuminated image sensor chip, and the thickness of the wafer is greater than the thickness of the back-illuminated image sensor chip. Therefore, a wafer can be pre-cut using a diamond pen, and the area and thickness of the wafer are larger than those of the back-illuminated image sensor chip, respectively, to facilitate subsequent slotting and accommodating of the back-illuminated image sensor chip.

[0018] Further, in step (2), an infrared laser (preferably with a wavelength of 1064 nm) is used to groove the wafer to obtain the chip accommodating groove; the area of ​​the chip accommodating groove is more than one-third larger than the area of ​​the back-illuminated image sensor chip, and the depth of the chip accommodating groove is greater than or equal to the thickness of the back-illuminated image sensor chip. Grooving the wafer with an infrared laser enables high-precision size and shape control of the chip accommodating groove, ensuring the accuracy of grooving. The grooving speed is fast, which can significantly improve production efficiency. The grooved cutting edge is neat, without burrs or material deformation.

[0019] By designing the wafer area to be more than two-thirds larger than the back-illuminated image sensor chip area, the wafer thickness to be greater than the back-illuminated image sensor chip thickness, the chip accommodating groove area to be more than one-third larger than the back-illuminated image sensor chip area, and the chip accommodating groove thickness to be greater than or equal to the back-illuminated image sensor chip thickness, the back-illuminated image sensor chip can be housed within the chip accommodating groove. Simultaneously, during subsequent etching, polishing, and other delamination processes, the wafer and the back-illuminated image sensor chip can effectively avoid the influence of factors such as uneven stress, thereby preventing damage to the critical circuit structures in the back-illuminated image sensor chip and thus avoiding impacts on subsequent monitoring, observation, and failure analysis.

[0020] Further, in step (2), the adhesive is AB glue, and the baking conditions are: 70-90℃ (preferably 80℃) for 110-130 minutes (preferably 120 minutes) to cure the AB glue and fix the back-illuminated image sensor chip in the chip receiving groove. Curing at a suitable temperature allows the AB glue to react fully, forming stronger adhesion and improving the bonding quality, thereby enhancing the adhesion of the back-illuminated image sensor chip in the chip receiving groove; in addition, controlling the curing time can prevent insufficient or excessive curing, avoid defects such as bubbles and internal stress, and ensure the bonding effect.

[0021] Further, in step (3), the sample is first ground with 2500-grit sandpaper to thin the substrate layer of the back-illuminated image sensor chip and the wafer together until the silicon of the substrate layer is exposed, and the upper surface of the thinned wafer and the upper surface of the thinned substrate layer are on the same plane; then, the grinding scratches are removed with 4000-grit sandpaper; finally, the sample is polished with alumina powder polishing slurry. In this invention, the sample is first ground with 2500-grit sandpaper to thin the substrate layer of the back-illuminated image sensor chip. The thickness of the thinning is selected by those skilled in the art according to actual needs, until the silicon of the substrate layer is exposed, so as to facilitate subsequent reactive ion etching. The grinding scratches are removed with 4000-grit sandpaper to further optimize the silicon surface of the substrate layer and the surface of the wafer, so as to facilitate subsequent reactive ion etching. Finally, the silicon surface of the thinned substrate and the wafer surface are polished together using alumina powder polishing slurry to obtain a smooth surface, which also facilitates the subsequent reactive ion etching.

[0022] Further, in step (4), the etching gas used in reactive ion etching (RIE) includes sulfur hexafluoride (SF6) and oxygen (O2), with a gas flow ratio of sulfur hexafluoride (SF6): oxygen (O2) = 190-210: 10-30 sccm (preferably 200 / 20 sccm). Preferably, the process parameters for reactive ion etching include: power 250W, pressure 50mTorr, etching rate approximately 55nm / min, and etching time 15 minutes. Reaction principle: Sulfur hexafluoride (SF6) is ionized or dissociated in a plasma environment, producing fluorine atoms and (F) and sulfofluorine groups (SFx). Fluorine atoms react with silicon (Si) to generate the volatile product silicon tetrafluoride (SiF4), thereby achieving silicon etching. The addition of oxygen (O2) allows oxygen to react with fluorocarbons, releasing more fluorine atoms while consuming some carbon, changing the ratio of fluorine to carbon atoms, which helps to improve the etching rate and selectivity.

[0023] Furthermore, in steps (4), (5), and (6), the metal layer is either copper or aluminum. In step (5), phosphoric acid (H3PO4) or nitric acid (HNO3) is used to etch and remove the metal layer.

[0024] Further, in steps (5) and (6), the interconnect layers are all tungsten vias (Via, interconnecting vias made of tungsten material); in step (5), an etchant is used to remove the interconnect layers. The etchant includes ammonium hydroxide and hydrogen peroxide, and the volume ratio of ammonium hydroxide to hydrogen peroxide (H2O2) in the etchant is 0.8-1.2:0.8-1.2 (preferably 1:1). Preferably, the etchant is a mixture of ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2), and the etchant is obtained by mixing ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2) at a volume ratio of 1:1 at room temperature. The ammonium hydroxide (NH4OH) is preferably 25-28% by mass, and the hydrogen peroxide (H2O2) is preferably 35% by mass. The reaction principle is: the etchant reacts with tungsten to generate ammonium paratungstate ((NH4)6W7O). 24 The reaction equation is: ·6H2O)

[0025] 7W + 21H₂O₂ + 6NH₄OH → (NH₄)₆W₇O 24 ·6H2O+18H2O

[0026] In steps (4), (5), and (6), the polishing method is as follows: polishing with a velvet polishing cloth and a silicon dioxide polishing slurry. By adopting the above method, the dielectric layer portion and wafer portion located outside the same plane layer as the corresponding metal layer or interconnect layer can be effectively removed, and the upper surface of the polished wafer and the polished back-illuminated image sensor chip are located on the same plane. It can also avoid the influence of uneven stress on the key circuit structure.

[0027] Furthermore, in steps (4), (5), and (6), optical microscopes (OM) and / or scanning electron microscopes (SEM) are used to perform real-time monitoring and inspection and failure analysis on the exposed metal layers or interconnect layers. For example: in step (4), after exposing the metal layer of the back-illuminated image sensor chip, the metal layer is further monitored and inspected in real time and subjected to failure analysis using an optical microscope (OM) and / or a scanning electron microscope (SEM); in step (5), after exposing the interconnect layer of the back-illuminated image sensor chip, the interconnect layer is monitored and inspected in real time and subjected to failure analysis using an optical microscope (OM) and / or a scanning electron microscope (SEM); in step (5), after exposing the next metal layer of the back-illuminated image sensor chip, the metal layer is monitored and inspected in real time and subjected to failure analysis using an optical microscope (OM) and / or a scanning electron microscope (SEM); in step (6), after exposing the last interconnect layer, the next metal layer, and so on of the back-illuminated image sensor chip, the metal layer is monitored and inspected in real time and subjected to failure analysis using an optical microscope (OM) and / or a scanning electron microscope (SEM). After exposing the metal layer or interconnect layer, the process also includes real-time monitoring and failure analysis of the metal layer or interconnect layer using an optical microscope (OM) and / or a scanning electron microscope (SEM).

[0028] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0029] (1) Achieve non-destructive layer-by-layer delamination: avoid damage to the metal interconnect structure in the microlens, photosensitive layer, photodiode and dielectric layer caused by the uneven mechanical stress or thermal damage of traditional delamination technology, especially avoid damage to the metal interconnect structure (critical circuit structure).

[0030] (2) Selective delamination of multilayer heterogeneous materials (such as SiO, Cu, Al, tungsten pores, etc.) in back-illuminated image sensors (or chips) is beneficial for achieving precise control of delamination.

[0031] (3) Real-time monitoring is performed during the delamination process using optical microscopy (OM) and / or scanning electron microscopy (SEM), which significantly improves the efficiency and accuracy of failure location and prevents the loss of key information due to over-etching. It is suitable for defect analysis (failure analysis) in semiconductor manufacturing and packaging processes. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of a back-illuminated image sensor chip (upright orientation).

[0033] Figure 2 A schematic diagram of the operation of laser grooving to form chip receiving grooves on a wafer, wherein (a) is a top view of the wafer; (b) is a top view of the wafer after laser grooving to form chip receiving grooves; and (c) is a cross-sectional view of the wafer being laser-grooved to form chip receiving grooves.

[0034] Figure 3 A schematic cross-sectional view illustrating the process of filling the chip housing groove of a wafer with AB adhesive;

[0035] Figure 4 The diagram shows a back-illuminated image sensor chip inverted and cured with AB glue in a chip receiving groove, where (a) is a top view and (b) is a cross-sectional view.

[0036] Figure 5 This is a schematic cross-sectional view of the sample after planar thinning.

[0037] Figure 6 for Figure 5 A schematic cross-sectional view after reactive ion etching;

[0038] Figure 7 for Figure 5 A schematic cross-sectional view of the structure after reactive ion etching;

[0039] Figure 8 for Figure 7 A schematic cross-sectional view of the structure after the second metal layer has been removed by chemical etching;

[0040] Figure 9 for Figure 8 A schematic cross-sectional view of the structure after grinding to expose the second interconnect layer;

[0041] Figure 10 for Figure 9 A schematic cross-sectional view of the structure after the second interconnect layer has been removed by chemical etching;

[0042] Figure 11 for Figure 10 A schematic cross-sectional view of the structure after grinding to expose the first metal layer;

[0043] Figure 12for Figure 11 A schematic cross-sectional view of the structure after the first metal layer has been removed by chemical etching;

[0044] Figure 13 for Figure 12 A schematic cross-sectional view of the structure after grinding to expose the first interconnect layer;

[0045] In the figure: 1. Microlens; 2. Photosensitive layer; 3. Photodiode; 4. Dielectric layer; 41. First interconnect layer; 42. First metal layer; 43. Second interconnect layer; 44. Second metal layer; 5. Substrate layer; 6. Wafer; 61. Chip receiving slot. Detailed Implementation

[0046] The embodiments and examples of the present invention will be described in detail below with reference to the implementation methods and examples. However, those skilled in the art will understand that the following implementation methods and examples are only for illustrating the present invention and should not be regarded as limiting the scope of the present invention. Unless otherwise specified, conventional conditions or conditions recommended by the manufacturer shall be followed. Unless otherwise specified, the reagents or instruments used are all conventional products that can be purchased commercially.

[0047] In the description of this invention, it should be noted that the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed when in use. They are only used to facilitate the description of this invention and to simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0048] Example 1

[0049] This embodiment provides a layer-by-layer method for failure analysis of back-illuminated image sensors, including the following steps:

[0050] (1) Removal of encapsulation:

[0051] The back-illuminated image sensor chip is obtained by removing its package. Specifically:

[0052] (11) First, concentrated sulfuric acid and fuming nitric acid are mixed in a volume ratio of 1:1 to obtain a mixed acid, wherein the mass fraction of concentrated sulfuric acid is 98% and the mass fraction of fuming nitric acid is 98%.

[0053] (12) Place the mixed acid in a beaker and heat it to 100°C. Place the back-illuminated image sensor in the beaker and etch it for 5 minutes. Remove the outer packaging to obtain the back-illuminated image sensor chip.

[0054] The amount of mixed acid relative to the back-illuminated image sensor is not specifically limited, as long as it ensures that the back-illuminated image sensor is completely immersed in the mixed acid. The basic structure of a back-illuminated image sensor is well known in the art. To facilitate understanding of the back-illuminated image sensor chip structure and the method of this invention, a brief description of the back-illuminated image sensor chip structure is provided here. Please refer to... Figure 1 The back-illuminated image sensor chip structure includes, from top to bottom, a microlens 1, a photosensitive layer 2, a photodiode 3, a dielectric layer 4, and a substrate layer 5; wherein, a metal interconnect structure is formed in the dielectric layer 4, and the metal interconnect structure includes two sets of interconnect layers and metal layers connected from top to bottom. For details, please refer to... Figure 1 The dielectric layer 4 has a first interconnect layer 41, a first metal layer 42, a second interconnect layer 43, and a second metal layer 44 formed from top to bottom; the first interconnect layer 41 and the second interconnect layer 43 are both tungsten vias (Via, interconnecting vias made of tungsten); the first metal layer 42 and the second metal layer 44 are aluminum (Al).

[0055] (2) Sample preparation:

[0056] Please see Figure 2 Take a wafer 6, on which a chip receiving slot 61 is formed. The chip receiving slot 61 is used to receive an image sensor chip; please refer to Figure 3 and Figure 4 The chip receiving groove 61 is filled with adhesive (AB glue), and the back-illuminated image sensor chip is inverted and placed into the chip receiving groove 61, then baked and cured to obtain the sample. Specifically:

[0057] (21) Please refer to Figure 2 (a) Use a diamond pen to cut out a wafer 6. Please refer to [link / reference]. Figure 2 (b) Figure 2 (c) and Figure 3 The area and thickness of wafer 6 are larger than those of the back-illuminated image sensor chip, respectively; in particular, the area of ​​wafer 6 is two-thirds larger than that of the back-illuminated image sensor chip.

[0058] (22) Please refer to Figure 2 (c) A laser is used to create a groove on the wafer using an infrared laser (wavelength 1064nm) to obtain a chip accommodating groove; wherein the area of ​​the chip accommodating groove is one-third larger than the area of ​​the back-illuminated image sensor chip, and the depth of the chip accommodating groove is slightly greater than (or equal to) the thickness of the back-illuminated image sensor chip.

[0059] (23) Please refer to Figure 3 Fill the chip receiving slot 61 with AB glue, please refer to [link / reference]. Figure 4 (a) and Figure 4 (b) The back-illuminated image sensor chip is placed in the chip receiving groove with the microlens 1 facing down and the substrate 5 facing up, and the upper surface of the substrate 5 does not extend beyond the upper surface of the chip receiving groove 61.

[0060] (24) Heat the wafer from step (23) using a heating stage, maintaining the temperature at 80°C, and bake for 120 minutes until the AB adhesive is cured to obtain the sample, such as... Figure 4 (a) and Figure 4 As shown in (b).

[0061] (3) Planar thinning:

[0062] The sample was gradually thinned from top to bottom in a planar manner using a grinding method. Please refer to [link to relevant documentation]. Figure 5 This thins the substrate layer 5 of the back-illuminated image sensor chip, ensuring that the upper surface of the thinned wafer 6 is on the same plane as the upper surface of the substrate layer 5 of the thinned back-illuminated image sensor chip. Specifically:

[0063] (31) The sample is gradually ground from top to bottom using 2500 grit sandpaper, so that the substrate layer 5 and the wafer 6 of the back-illuminated image sensor chip are thinned together. The grinding is thinned until all the silicon (surface silicon) in the substrate layer 5 is exposed, and the upper surface of the thinned wafer 6 and the upper surface of the thinned substrate layer 5 are on the same plane.

[0064] (32) Continue grinding with 4000 grit sandpaper to reduce the grinding scratches on the surface of substrate 5 and wafer 6.

[0065] (33) Finally, the substrate layer 5 and the wafer 6 are polished with alumina powder polishing slurry to obtain a smooth and flat surface.

[0066] (4) Reactive ion etching:

[0067] Please see Figure 6 and Figure 7 The sample after step (3) is etched using reactive ion etching to remove the substrate layer 4 of the back-illuminated image sensor chip and expose the second metal layer 44 of the back-illuminated image sensor chip. The upper surface of the etched wafer 6 and the upper surface of the second metal layer 44 of the etched back-illuminated image sensor chip are located on the same plane. The first metal layer 44 is monitored, inspected, and analyzed for failure using an optical microscope and / or a scanning electron microscope. Wherein:

[0068] Reactive ion etching was performed using a reactive ion etching apparatus under the following conditions:

[0069] ① The etching gas includes sulfur hexafluoride (SF6) and oxygen (O2), and the gas flow ratio is sulfur hexafluoride (SF6): oxygen (O2) = 200 / 20 sccm.

[0070] ② Power: 250W.

[0071] ③ Pressure: 50mTorr.

[0072] ④ Rate: Approximately 55 nm / min.

[0073] ⑤ Etching time: 15 minutes.

[0074] The reaction principle is as follows: Sulfur hexafluoride (SF6) is ionized or dissociated in a plasma environment, producing fluorine atoms (F) and sulfofluorine groups (SFx). The fluorine atoms react with silicon (Si) to generate the volatile product silicon tetrafluoride (SiF4), thus achieving silicon etching. The addition of oxygen (O2) causes it to react with fluorocarbons, releasing more fluorine atoms while consuming some carbon, thus altering the fluorine-carbon atom ratio and contributing to improved etching rate and selectivity.

[0075] Please see Figure 6 and Figure 7 After reactive ion etching, the second metal layer 44 of the back-illuminated image sensor chip is exposed, and the upper surface of the wafer 6 after reactive ion etching and the upper surface of the second metal layer 44 of the back-illuminated image sensor chip after etching are located in the same plane (that is, reactive ion etching also acts on the wafer 6, and the upper surface of the wafer 6 after etching and the upper surface of the back-illuminated image sensor chip after etching are always located in the same plane); the second metal layer 44 is monitored and inspected in real time and its failure is analyzed using an optical microscope (OM) and / or a scanning electron microscope (SEM).

[0076] (5) Removal of the first metal layer and the first interconnect layer:

[0077] Please see Figure 8 The second metal layer 44 was removed using chemical etching. Please refer to [link / reference]. Figure 9 The second interconnect layer 43 is exposed by grinding, and the upper surface of the ground wafer 6 is at the same height plane as the upper surface of the second interconnect layer 43 of the back-illuminated image sensor chip; the second interconnect layer 43 is monitored, inspected and analyzed for failure using an optical microscope and / or a scanning electron microscope.

[0078] Please see Figure 10 and Figure 11The second interconnect layer 43 is removed by chemical etching, and the first metal layer 42 is exposed by grinding. The upper surface of the ground wafer 6 is on the same plane as the upper surface of the first metal layer 42 of the back-illuminated image sensor chip. The first metal layer 42 is monitored, inspected and analyzed for failure using an optical microscope and / or a scanning electron microscope.

[0079] Specifically:

[0080] (51) Please refer to Figure 8 and Figure 9 The second metal layer 44 is removed using phosphoric acid (H3PO4), and the dielectric layer 4 and wafer 6 located on the same layer as the second metal layer 44 are removed by polishing with a velvet cloth and silicon dioxide polishing slurry, so that the second interconnect layer 43 is exposed. The upper surface of the polished wafer 6 is at the same height plane as the upper surface of the second interconnect layer 43 of the back-illuminated image sensor chip. The second interconnect layer 43 is monitored, inspected and analyzed for failure using an optical microscope and / or a scanning electron microscope.

[0081] (52) Please refer to Figure 10 and Figure 11 The second interconnect layer 43 is removed using an etchant, which is prepared by mixing 25% ammonium hydroxide (NH4OH) and 35% hydrogen peroxide (H2O2) at a volume ratio of 1:1 at room temperature. The reaction principle is as follows: the etchant reacts with tungsten to generate ammonium paratungstate ((NH4)6W7O). 24 The reaction equation is: ·6H2O)

[0082] 7W + 21H₂O₂ + 6NH₄OH → (NH₄)₆W₇O 24 ·6H2O+18H2O

[0083] Then, the dielectric layer 4 and wafer 6 located in the same layer as the second interconnect layer 43 are removed by polishing with a velvet polishing cloth and silicon dioxide polishing slurry, so that the first metal layer 43 is exposed. The upper surface of the polished wafer 6 is on the same plane as the upper surface of the first metal layer 42 of the back-illuminated image sensor chip. The first metal layer 42 is monitored, inspected and analyzed for failure using an optical microscope and / or a scanning electron microscope.

[0084] (6) Repeat the process of removing layers one by one:

[0085] Please see Figure 12 and Figure 13Repeat step (5) to remove the first metal layer 42 until the last interconnect layer (i.e., the first interconnect layer 41) is exposed by grinding, and the upper surface of the ground wafer 6 is at the same height plane as the upper surface of the last interconnect layer (i.e., the first interconnect layer 41) of the back-illuminated image sensor chip. Specifically:

[0086] (71) The first metal layer 42 is removed using phosphoric acid (H3PO4), and the dielectric layer 4 and wafer 6 located in the same layer as the first metal layer 42 are removed by polishing with a velvet cloth and silicon dioxide polishing slurry, so that the first interconnect layer 41 is exposed, and the upper surface of the polished wafer is on the same plane as the upper surface of the first interconnect layer 41 of the back-illuminated image sensor chip; the first interconnect layer 41 is monitored, inspected and analyzed for failure using an optical microscope and / or a scanning electron microscope.

[0087] Furthermore, the applicant would like to emphasize that when there are multiple sets of metal layers and interconnect layers in the metal interconnect structure of dielectric layer 4, the method of step (5) can be repeated for removal until the last interconnect layer is exposed by polishing. This embodiment only illustrates two sets of metal layers and interconnect layers. Those skilled in the art can select the appropriate steps for layer removal according to the actual situation of the metal interconnect structure in the dielectric layer.

[0088] Since the failure analysis focuses on the critical circuit structure (i.e., the metal interconnect structure), the layer-by-layer delamination method for failure analysis of the back-illuminated image sensor in this embodiment is now complete. Of course, those skilled in the art can also, according to actual needs and conventional methods in the field, choose whether to perform corresponding delamination or other operations on the photodiode, photosensitive layer, microlens, etc.

[0089] The layer-by-layer delamination method for failure analysis of back-illuminated image sensors in this embodiment avoids the damage to the metal interconnect structures in the microlens, photosensitive layer, photodiode, and dielectric layer caused by uneven mechanical stress or thermal damage in traditional delamination techniques. In particular, it avoids damage to the metal interconnect structures (critical circuit structures), achieving non-destructive layer-by-layer delamination. It also enables selective delamination of the multilayer heterogeneous materials of back-illuminated image sensors (or chips). During the delamination process, optical microscopy (OM) and / or scanning electron microscopy (SEM) are used for real-time monitoring, significantly improving the efficiency and accuracy of failure location.

[0090] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and the present invention also intends to include these modifications and variations.

Claims

1. A layer-by-layer failure analysis method for back-illuminated image sensors, characterized in that: Includes the following steps: (1) Remove the packaging of the back-illuminated image sensor to obtain the back-illuminated image sensor chip. (2) Take a wafer with a chip receiving groove formed on it; fill the chip receiving groove with glue, and invert the back-illuminated image sensor chip and place it in the chip receiving groove, bake and cure it to obtain a sample; (3) The sample is thinned by grinding, so that the substrate layer of the back-illuminated image sensor chip and the wafer are thinned together, and the upper surface of the thinned wafer and the upper surface of the thinned substrate layer are located on the same plane. (4) The sample after step (3) is etched by reactive ion etching to remove the substrate layer and expose a metal layer of the back-illuminated image sensor chip. The upper surface of the etched wafer and the upper surface of the metal layer are located on the same plane. (5) The metal layer is removed by chemical etching and the interconnect layer of the back-illuminated image sensor chip is exposed by grinding, and the upper surface of the wafer after grinding is on the same plane as the upper surface of the interconnect layer. The interconnect layer is removed by chemical etching, and the next metal layer is exposed by grinding. The upper surface of the wafer after grinding is on the same plane as the upper surface of the next metal layer. (6) Repeat step (5) to remove the next metal layer and interconnect layer one by one until the last interconnect layer is exposed by grinding, and the upper surface of the ground wafer is on the same plane as the upper surface of the last interconnect layer.

2. The layer-by-layer failure analysis method for back-illuminated image sensors according to claim 1, characterized in that: In step (1), a mixed acid is used to remove the encapsulation of the back-illuminated image sensor, wherein the mixed acid includes concentrated sulfuric acid and fuming nitric acid.

3. The layer-by-layer failure analysis method for back-illuminated image sensors according to claim 1, characterized in that: In step (1), the structure of the back-illuminated image sensor chip includes a microlens, a photosensitive layer, a photodiode, a dielectric layer and a substrate layer arranged sequentially from top to bottom; wherein, a metal interconnect structure is formed in the dielectric layer, and the metal interconnect structure includes several groups of interconnect layers and metal layers connected from top to bottom.

4. The layer-by-layer failure analysis method for back-illuminated image sensors according to claim 1, characterized in that: In step (2), the area of ​​the wafer is more than two-thirds larger than the area of ​​the back-illuminated image sensor chip, and the thickness of the wafer is greater than the thickness of the back-illuminated image sensor chip; the wafer is slotted using an infrared laser to obtain the chip receiving slot; the area of ​​the chip receiving slot is more than one-third larger than the area of ​​the back-illuminated image sensor chip, and the depth of the chip receiving slot is greater than or equal to the thickness of the back-illuminated image sensor chip.

5. The layer-by-layer failure analysis method for back-illuminated image sensors according to claim 1, characterized in that: In step (2), the adhesive is AB glue, and the baking conditions are: baking at 70-90℃ for 110-130 minutes to cure the AB glue and fix the back-illuminated image sensor chip in the chip receiving slot.

6. The layer-by-layer failure analysis method for back-illuminated image sensors according to claim 1, characterized in that: In step (3), the sample is first polished with 2500-grit sandpaper to thin the substrate layer of the back-illuminated image sensor chip and the wafer together until the silicon of the substrate layer is exposed, and the upper surface of the thinned wafer and the upper surface of the thinned substrate layer are on the same plane; then the polishing scratches are removed with 4000-grit sandpaper. Finally, polishing is performed using an alumina powder polishing slurry.

7. The layer-by-layer failure analysis method for back-illuminated image sensors according to claim 1, characterized in that: In step (4), the etching gases used in reactive ion etching include sulfur hexafluoride and oxygen, and the gas flow ratio is sulfur hexafluoride: oxygen = 190-210: 10-30 sccm.

8. The layer-by-layer failure analysis method for back-illuminated image sensors according to claim 1, characterized in that: In steps (4), (5), and (6), the metal layer is either copper or aluminum; In step (5), phosphoric acid or nitric acid is used to remove the metal layer; In steps (5) and (6), the interconnect layers are all tungsten vias; In step (5), an etchant is used to remove the interconnect layer, the etchant comprising ammonium hydroxide and hydrogen peroxide, wherein the volume ratio of ammonium hydroxide to hydrogen peroxide in the etchant is 0.8-1.2:0.8-1.

2.

9. The layer-by-layer failure analysis method for back-illuminated image sensors according to claim 1, characterized in that: In steps (4), (5), and (6), the grinding method is as follows: grinding with a velvet polishing cloth and a silica polishing liquid.

10. The layer-by-layer failure analysis method for back-illuminated image sensors according to claim 1, characterized in that: In steps (4), (5), and (6), optical microscopes and / or scanning electron microscopes are used to monitor and inspect the exposed metal layers or interconnect layers in real time and perform failure analysis.

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