A pull-up resistor detection circuit and sensor chip

Abstract

This invention discloses a pull-up resistor detection circuit and sensor chip, relating to the fields of electronic engineering and digital circuit technology, to solve the problem in existing technologies that cannot effectively measure the pull-up resistor at a low active interrupt pin. The circuit includes at least: a voltage shifting circuit, a voltage comparison circuit, and a voltage generation circuit; wherein, the voltage shifting circuit is used to shift the change in the target node voltage to the target low active interrupt pin; the voltage comparison circuit is used to compare the target node voltage with the ground voltage, and adjust the target node voltage according to the comparison result, keeping the loop voltage of the pull-up resistor detection circuit stable after adjustment; the voltage generation circuit is used to generate the detection voltage of the pull-up resistor and transmit the detection voltage to the analog-to-digital converter in the sensor chip; thus achieving effective measurement of the pull-up resistor at a low active interrupt pin.

Description

Technical Field

[0001] This invention relates to the fields of electronic engineering and digital circuit technology, and in particular to a pull-up resistor detection circuit and sensor chip. Background Technology

[0002] In chip application scenarios, support for low active interrupts is required. Different pull-up resistors RP of varying values ​​are connected to the pins to achieve different chip configurations, such as configuring the chip to different communication addresses, and configuring the active low-level pins as appropriate. Different threshold values ​​can be configured on the pins. This can reduce the hardware and software costs of the chip to some extent. Taking the two usage scenarios mentioned above as examples, when different communication addresses are configured using different pull-up resistors, the number of address pins on the chip can be reduced; when different pull-up resistors are configured... Using different threshold values ​​for pins can reduce software communication between the chip and the device to achieve the same purpose. However, existing technologies lack a means to measure the pull-up resistance at active low interrupt pins, preventing sensor chips from effectively measuring this resistance and hindering rapid chip development. Therefore, there is an urgent need to design a more efficient measurement method to address the problem of the inability to effectively measure the pull-up resistance at active low interrupt pins in existing technologies. Summary of the Invention

[0003] The purpose of this invention is to provide a pull-up resistor detection circuit and sensor chip, which can detect low active interrupt pins (…). The pull-up resistor RP at the pin is converted into the voltage VRP to be measured. Since sensor chips usually integrate a high-precision ADC, after obtaining VRP, it can be quantized by the ADC, converting the resistance value of RP into a digital signal for subsequent chip processing. This solves the problem in existing technologies that cannot effectively measure the pull-up resistor at the low active interrupt pin, and promotes the rapid development of chips.

[0004] In order to achieve the above object, the present invention provides the following technical solutions:

[0005] In a first aspect, the present invention provides a pull-up resistor detection circuit, which may include at least:

[0006] Voltage shifting circuit, voltage comparison circuit, and voltage generation circuit;

[0007] The first terminal of the voltage shifting circuit is connected to the target active low interrupt pin, and the second terminal of the voltage shifting circuit is connected to the first terminal of the voltage comparator circuit; the second terminal of the voltage comparator circuit is connected to the first terminal of the voltage generation circuit, and the second terminal of the voltage generation circuit is connected to the target active low interrupt pin; wherein, the target active low interrupt pin is connected to the first terminal of the pull-up resistor, and the second terminal of the pull-up resistor is connected to the first power supply terminal;

[0008] The voltage shifting circuit is used to shift the change in the target node voltage to the target low active interrupt pin;

[0009] The voltage comparison circuit is used to compare the target node voltage with the ground voltage, and adjust the target node voltage according to the comparison result. The loop voltage of the pull-up resistor detection circuit remains stable after adjustment.

[0010] The voltage generation circuit is used to generate the detection voltage of the pull-up resistor and transmit the detection voltage to the analog-to-digital converter in the sensor chip.

[0011] Preferably, the voltage shifting circuit may include a first capacitor, a first NMOS transistor, and a second NMOS transistor;

[0012] The first terminal of the first capacitor is connected to the target active low interrupt pin, and the second terminal of the first capacitor is connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is connected to the first terminal, and the gate of the first NMOS transistor is connected to the third enable signal control terminal. The drain of the second NMOS transistor is connected to the first terminal, the gate of the second NMOS transistor is connected to the first enable signal control terminal, and the source of the second NMOS transistor is grounded. The voltage corresponding to the first terminal is the target node voltage.

[0013] Preferably, the voltage comparison circuit may include a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, an eighth NMOS transistor, a first resistor, a third resistor, and a fourth resistor;

[0014] The source of the first PMOS transistor is connected to the first end of the first resistor, the second end of the first resistor is connected to the first node, the gate of the first PMOS transistor is connected to the first terminal, and the drain of the first PMOS transistor is connected to the second node; the source of the second PMOS transistor is connected to the first node, the gate of the second PMOS transistor is grounded, and the drain of the second PMOS transistor is connected to the third node.

[0015] The source of the third PMOS transistor is connected to the second power supply terminal, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor, and the gate of the third PMOS transistor is connected to the third power supply terminal; the drain of the fourth PMOS transistor is connected to the first node, and the gate of the fourth PMOS transistor is connected to the second enable signal control terminal; the source of the fifth PMOS transistor is connected to the second power supply terminal, the drain of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor, and the gate of the fifth PMOS transistor is connected to the third power supply terminal; the drain of the sixth PMOS transistor is connected to the drain of the third NMOS transistor, and the gate of the sixth PMOS transistor is connected to the second enable signal control terminal; the source of the seventh PMOS transistor is connected to the second power supply terminal, the drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor, and the gate of the seventh PMOS transistor is connected to the third power supply terminal; the drain of the eighth PMOS transistor is connected to the fourth node, and the gate of the eighth PMOS transistor is connected to the second enable signal control terminal;

[0016] The source of the third NMOS transistor is connected to the second node, the gate of the third NMOS transistor is connected to the drain of the third NMOS transistor, and the gate of the third NMOS transistor is connected to the drain of the fifth NMOS transistor; the drain of the fifth NMOS transistor is grounded, and the gate of the fifth NMOS transistor is connected to the second enable signal control terminal; the drain of the fourth NMOS transistor is connected to the fourth node, the gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor, and the source of the fourth NMOS transistor is connected to the third node; the drain of the eighth NMOS transistor is connected to the fourth node, the source of the eighth NMOS transistor is grounded, and the gate of the eighth NMOS transistor is connected to the first enable signal control terminal;

[0017] The first end of the fourth resistor is connected to the second node, and the second end of the fourth resistor is grounded; the first end of the third resistor is connected to the third node, and the second end of the third resistor is grounded.

[0018] Preferably, the first PMOS transistor and the second PMOS transistor are equivalent transistors.

[0019] Preferably, the voltage generation circuit may include a first switch, a sixth NMOS transistor, a seventh NMOS transistor, and a second resistor;

[0020] The first terminal of the first switch is connected to the fourth node, the second terminal of the first switch is connected to the gate of the sixth NMOS transistor, and the third terminal of the first switch is connected to the third enable signal control terminal.

[0021] The drain of the seventh NMOS transistor is connected to the gate of the sixth NMOS transistor, the source of the seventh NMOS transistor is grounded, and the gate of the seventh NMOS transistor is connected to the second enable signal control terminal; the drain of the sixth NMOS transistor is connected to the target active low interrupt pin, and the source of the sixth NMOS transistor is connected to the second terminal; the first end of the second resistor is connected to the second terminal, and the second end of the second resistor is grounded.

[0022] Preferably, the pull-up resistor detection circuit is turned off when the first enable signal control terminal is high, the second enable signal control terminal is high, and the third enable signal control terminal is low.

[0023] Preferably, when the first enable signal control terminal is high, the second enable signal control terminal is low, and the third enable signal control terminal is high, the first NMOS transistor, the second NMOS transistor, and the eighth NMOS transistor are turned on, the first switch is turned on, the voltage of the fourth node is low, and the voltage at the target low active interrupt pin is the voltage of the first power supply terminal.

[0024] Preferably, when the first enable signal control terminal is low, the second enable signal control terminal is low, and the third enable signal control terminal is high, the current flowing through the first PMOS transistor and the second PMOS transistor is equal.

[0025] Preferably, when the sixth NMOS transistor is turned on, the current flowing through the pull-up resistor is IREF*R1 / RP, and the detection voltage of the pull-up resistor is IREF*R1 / RP*R2.

[0026] In a second aspect, the present invention provides a sensor chip, which may include at least a pull-up resistor detection circuit, a pull-up resistor, an analog-to-digital converter, and a ninth NMOS transistor; the pull-up resistor detection circuit is the detection circuit described in the first aspect.

[0027] The first end of the pull-up resistor is connected to the first power supply terminal, and the second end of the pull-up resistor is connected to the target active low interrupt pin of the sensor chip; the first end of the pull-up resistor detection circuit is connected to the target active low interrupt pin, and the second end of the pull-up resistor detection circuit is connected to the analog-to-digital converter; the drain of the ninth NMOS transistor is connected to the target active low interrupt pin, the source of the ninth NMOS transistor is grounded, and the gate of the ninth NMOS transistor is connected to the analog-to-digital converter.

[0028] The pull-up resistor detection circuit is used to detect the pull-up resistor and convert the resistance value of the pull-up resistor into a target voltage value, which is then transmitted to the analog-to-digital converter.

[0029] The analog-to-digital converter is used to convert the target voltage into a digital signal output.

[0030] Compared with the prior art, the pull-up resistor detection circuit provided by the present invention, by at least setting a voltage shifting circuit, a voltage comparison circuit, and a voltage generation circuit; connecting the first terminal of the voltage shifting circuit to the target low active interrupt pin, and the second terminal of the voltage shifting circuit to the first terminal of the voltage comparison circuit; connecting the second terminal of the voltage comparison circuit to the first terminal of the voltage generation circuit, and the second terminal of the voltage generation circuit to the target low active interrupt pin, forming a negative feedback circuit; wherein, the target low active interrupt pin is connected to the first terminal of the pull-up resistor, and the second terminal of the pull-up resistor is connected to the first power supply terminal; thereby, the voltage shifting circuit can be used to shift the change of the target node voltage to the target low active interrupt pin, and the voltage comparison circuit can be used to... The target node voltage is compared with the ground voltage, and the voltage of the target node is adjusted according to the comparison result. The loop voltage of the pull-up resistor detection circuit remains stable after adjustment, thus ensuring that the detection process will not erroneously activate the target low active interrupt pin and can resist changes in power supply voltage. When the same pull-up resistor is used under different power supply voltages, the detection result is the same. Finally, the detection voltage of the pull-up resistor is generated by the voltage generation circuit and transmitted to the analog-to-digital converter in the sensor chip. The resistance value of the pull-up resistor can be converted into a digital signal for subsequent processing by the chip. This realizes the effective measurement of the pull-up resistor at the low active interrupt pin and solves the problem that the pull-up resistor at the low active interrupt pin cannot be effectively measured in the existing technology. Attached Figure Description

[0031] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0032] Figure 1 For existing sensor chips, the low active interrupt pin ( A schematic diagram of the circuit structure (pins);

[0033] Figure 2 A schematic diagram of the circuit structure of a pull-up resistor detection circuit provided by the present invention;

[0034] Figure 3 This is a schematic diagram combining the circuit structure and partial signal timing diagram of a pull-up resistor detection circuit provided by the present invention.

[0035] Figure reference numerals: 200 - Pull-up resistor detection circuit, 210 - Voltage shifting circuit, 220 - Voltage comparator circuit, 230 - Voltage generation circuit, VDD1 - First power supply terminal, VDD2 - Second power supply terminal, Vbais - Third power supply terminal, ENN1 - First enable signal control terminal, ENN2 - Second enable signal control terminal, ENP2 - Third enable signal control terminal, VFB - First terminal, VRP - Second terminal, X1 - First node, X2 - Second node, X3 - Third node, X4 - Fourth node, RP - Pull-up resistor. - Target low active interrupt pin, S1 - first switch, C1 - first capacitor. Detailed Implementation

[0036] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different.

[0037] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0038] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding related objects have an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0039] Most sensor chips in the current technology have a low active interrupt pin ( (Pin), please refer to Figure 1 , Figure 1This is a schematic diagram of the circuit structure of the low active interrupt pin in existing sensor chips; Figure 1 In this circuit, the active low interrupt pin has an internal open-drain structure and requires an external pull-up resistor RP to connect to the power supply voltage VDD. When the gate voltage VG of the internal NMOS transistor is at a logic low level, the NMOS transistor is turned off, and the active low interrupt pin ( When the voltage of the active low interrupt pin is raised to VDD by the pull-up resistor RP, that pin becomes inactive. When the gate voltage VG of the internal NMOS transistor is at a logic high level, the NMOS transistor is turned on, and the voltage of the active low interrupt pin is pulled down to near 0 by the NMOS transistor, making that pin active. Therefore, by controlling the level of the gate voltage VG of the NMOS transistor in the open-drain structure, corresponding information can be transmitted through the active low interrupt pin. This active low interrupt pin is typically used in sensor chips to indicate whether the measured physical quantity has exceeded a threshold value. It should be noted that... Figure 1 The thick black box in the image represents the outer frame of the sensor chip, and the small square box above the thick black box represents the active low interrupt pin.

[0040] The lack of existing technology for measuring the pull-up resistance at the low active interrupt pin has hindered the rapid development of the chip, as sensor chips cannot effectively measure the pull-up resistance at the low active interrupt pin.

[0041] In view of this, the present invention provides a pull-up resistor detection circuit and a sensor chip. This circuit can convert the resistance value of the pull-up resistor RP at the active low interrupt pin into a voltage to be measured. Since a high-precision ADC is usually integrated inside the sensor chip, after obtaining the voltage to be measured, it can be quantized by the ADC, converting the resistance value of RP into a digital signal for subsequent processing by the chip; thus, effective measurement of the pull-up resistor is achieved, solving the problem in the prior art that the pull-up resistor at the active low interrupt pin cannot be effectively measured.

[0042] It should be noted that, for the sake of simplicity, in the mathematical formulas of this specification and the accompanying drawings, V1 represents the voltage of the first node X1, R1 represents the resistance value of the first resistor R1, R2 represents the resistance value of the second resistor R2, VFB represents the voltage of the first terminal VFB, GND represents the voltage of the ground terminal, RP represents the resistance value of the pull-up resistor RP, and VRP represents the voltage of the second terminal VRP.

[0043] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings:

[0044] Please see Figure 2 , Figure 2 This is a schematic diagram of a pull-up resistor detection circuit provided by the present invention. It should be noted that... Figure 2 A schematic diagram of a pull-up resistor detection circuit is provided as an example. The pull-up resistor detection circuit is set in the sensor chip, which can quickly and effectively measure the resistance value of the pull-up resistor connected to the low active interrupt pin of the sensor chip and convert it into a digital signal. Of course, the detection circuit can also be set outside the sensor, which can also achieve effective measurement of the pull-up resistor connected to the low active interrupt pin of the sensor chip. Figure 2 The thick black box around the center represents the outer frame of the sensor chip, and the small square box on the thick black box represents the active low interrupt pin.

[0045] exist Figure 2 In the circuit, the pull-up resistor detection circuit 200 may include at least:

[0046] Voltage shifting circuit 210, voltage comparison circuit 220, and voltage generation circuit 230.

[0047] Specifically, the first terminal of the voltage shifting circuit 210 can be connected to the target active low interrupt pin. The second terminal of the voltage shifting circuit 210 is connected to the first terminal of the voltage comparator circuit 220; the second terminal of the voltage comparator circuit 220 is connected to the first terminal of the voltage generation circuit 230; and the second terminal of the voltage generation circuit 230 is connected to the target active low interrupt pin. Connection; where the target active low interrupt pin The first terminal of the pull-up resistor RP is connected, and the second terminal of the pull-up resistor RP is connected to the first power supply terminal VDD1. This allows the voltage shifting circuit to shift changes in the target node voltage to the target low active interrupt pin; the voltage comparison circuit compares the target node voltage with the ground voltage, and adjusts the target node voltage based on the comparison result. The adjusted pull-up resistor detection circuit maintains a stable loop voltage, i.e., the negative feedback loop voltage remains stable; and the voltage generation circuit generates the detection voltage of the pull-up resistor and transmits the detection voltage to the analog-to-digital converter in the sensor chip. Here, the target node voltage represents the voltage corresponding to the first terminal VFB.

[0048] Based on this, the pull-up resistor detection circuit provided by the present invention, through the negative feedback circuit formed by the voltage shifting circuit, the voltage comparison circuit, and the voltage generation circuit, can use the voltage shifting circuit to shift the change of the target node voltage to the target low active interrupt pin, use the voltage comparison circuit to compare the target node voltage with the ground voltage, and adjust the target node voltage according to the comparison result. The loop voltage of the pull-up resistor detection circuit remains stable after adjustment, thereby ensuring that the target low active interrupt pin is not mistakenly activated during the detection process, and can resist changes in power supply voltage, so that the detection result is the same when the same pull-up resistor is under different power supply voltages. Finally, the voltage generation circuit generates the detection voltage of the pull-up resistor and transmits the detection voltage to the analog-to-digital converter in the sensor chip, which can convert the resistance value of the pull-up resistor into a digital signal for subsequent processing by the chip. This realizes the effective measurement of the pull-up resistor at the low active interrupt pin, and solves the problem that the pull-up resistor at the low active interrupt pin cannot be effectively measured in the prior art.

[0049] It should be noted that, based on the above design, the pull-up resistor detection circuit provided by this invention has the following characteristics:

[0050] 1) Because the pull-up resistor RP to be tested is connected to the target active low interrupt pin. When the voltage at the pin is less than 0.7 times the voltage corresponding to the first power supply terminal VDD1, the target low active interrupt pin will be activated. However, the pull-up resistor detection circuit provided by this invention maintains a stable loop voltage throughout the detection process because the detection circuit adjusts the voltage of the target node. Therefore, it will not excessively pull down the voltage of the target low active interrupt pin, avoiding false activation. The issue is with the pins.

[0051] 2) The pull-up resistor detection circuit provided by this invention can resist changes in power supply voltage (first power supply terminal VDD1) (e.g., 1.7~5.5V), thereby achieving the same detection result for the same pull-up resistor RP under different power supply voltages.

[0052] In one alternative embodiment, the voltage shifting circuit 210 may include a first capacitor, a first NMOS transistor, and a second NMOS transistor.

[0053] Specifically, the first terminal of the first capacitor can be connected to the target active low interrupt pin. The connection is as follows: the second terminal of the first capacitor is connected to the drain of the first NMOS transistor; the source of the first NMOS transistor is connected to the first terminal VFB, and the gate of the first NMOS transistor is connected to the third enable signal control terminal ENP2; the drain of the second NMOS transistor is connected to the first terminal VFB, the gate of the second NMOS transistor is connected to the first enable signal control terminal ENN1, and the source of the second NMOS transistor is grounded; wherein, the voltage corresponding to the first terminal VFB is the target node voltage, and the target ground effective interrupt pin can be any pin on the sensor chip.

[0054] Based on this, the voltage shifting circuit 210 in the pull-up resistor detection circuit provided by the present invention can be obtained, thereby shifting the change in voltage VFB to the target low active interrupt pin based on the first capacitor C1 in the voltage shifting circuit 210. .

[0055] In one alternative embodiment, the voltage comparator circuit 220 may include a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, an eighth NMOS transistor, a first resistor, a third resistor, and a fourth resistor.

[0056] The source of the first PMOS transistor is connected to the first terminal of the first resistor, the second terminal of the first resistor is connected to the first node X1, the gate of the first PMOS transistor is connected to the first terminal VFB, and the drain of the first PMOS transistor is connected to the second node X2; the source of the second PMOS transistor is connected to the first node X1, the gate of the second PMOS transistor is grounded, and the drain of the second PMOS transistor is connected to the third node X3.

[0057] Specifically, the source of the third PMOS transistor can be connected to the second power supply terminal VDD2, the drain of the third PMOS transistor can be connected to the source of the fourth PMOS transistor, and the gate of the third PMOS transistor can be connected to the third power supply terminal Vbais; the drain of the fourth PMOS transistor can be connected to the first node X1, and the gate of the fourth PMOS transistor can be connected to the second enable signal control terminal ENN2; the source of the fifth PMOS transistor can be connected to the second power supply terminal VDD2, the drain of the fifth PMOS transistor can be connected to the source of the sixth PMOS transistor, and the gate of the fifth PMOS transistor can be connected to the third power supply terminal Vbais; the drain of the sixth PMOS transistor can be connected to the drain of the third NMOS transistor, and the gate of the sixth PMOS transistor can be connected to the second enable signal control terminal ENN2; the seventh PMOS transistor can be connected to the second enable signal control terminal ENN2; the drain of the seventh PMOS transistor can be connected to the second enable signal control terminal ENN2; the drain of the seventh PMOS transistor can be connected to the second enable signal control terminal ENN2; the drain of the seventh PMOS transistor can be connected to the second enable signal control terminal ENN2; the drain of the fifth ... The source of the seventh PMOS transistor is connected to the second power supply terminal VDD2, the drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor, and the gate of the seventh PMOS transistor is connected to the third power supply terminal Vbais. The drain of the eighth PMOS transistor is connected to the fourth node X4, and the gate of the eighth PMOS transistor is connected to the second enable signal control terminal ENN2. The second power supply terminal VDD2 is powered by the VDDLA (1.5V) output of the LDO integrated in the sensor chip. The current flowing through the third and fourth PMOS transistors is twice IREF, the current flowing through the fifth and sixth PMOS transistors is IREF, and the current flowing through the seventh and eighth PMOS transistors is IREF. IREF represents the reference current generated in the sensor chip.

[0058] Furthermore, the source of the third NMOS transistor is connected to the second node X2, the gate of the third NMOS transistor is connected to the drain of the third NMOS transistor, and the gate of the third NMOS transistor is connected to the drain of the fifth NMOS transistor; the drain of the fifth NMOS transistor is grounded, and the gate of the fifth NMOS transistor is connected to the second enable signal control terminal ENN2; the drain of the fourth NMOS transistor is connected to the fourth node X4, the gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor, and the source of the fourth NMOS transistor is connected to the third node X3; the drain of the eighth NMOS transistor is connected to the fourth node X4, the source of the eighth NMOS transistor is grounded, and the gate of the eighth NMOS transistor is connected to the first enable signal control terminal ENN1.

[0059] Finally, connect the first end of the fourth resistor to the second node X2, and ground the second end of the fourth resistor; connect the first end of the third resistor to the third node X3, and ground the second end of the third resistor.

[0060] Based on this, the voltage comparison circuit 220 of the pull-up resistor detection circuit provided by the present invention can be obtained. The main structure of the voltage comparison circuit 220 is an operational amplifier with an input offset (R1). This part of the circuit continuously compares the VFB voltage and the GND voltage through the characteristics of the operational amplifier, and adjusts the node voltage of the fourth node X4 through a negative feedback loop, so that the entire pull-up resistor detection loop reaches stability, thereby avoiding the influence on the voltage at the target low active interrupt pin, avoiding the false activation of the target low active interrupt pin, and resisting the change of the power supply voltage of the first power supply terminal VDD1. Among them, the detection loop (negative feedback loop) is: first terminal VFB → fourth node X4 → sixth NMOS transistor → target low active interrupt pin. →First capacitor C1→First NMOS transistor→First terminal VFB.

[0061] In one alternative embodiment, the voltage generation circuit 230 may include a first switch, a sixth NMOS transistor, a seventh NMOS transistor, and a second resistor.

[0062] Specifically, the first terminal of the first switch S1 can be connected to the fourth node X4, the second terminal of the first switch S1 can be connected to the gate of the sixth NMOS transistor, and the third terminal of the first switch S1 can be connected to the third enable signal control terminal ENP2; the drain of the seventh NMOS transistor can be connected to the gate of the sixth NMOS transistor, the source of the seventh NMOS transistor can be grounded, and the gate of the seventh NMOS transistor can be connected to the second enable signal control terminal ENN2; the drain of the sixth NMOS transistor can be connected to the target active low interrupt pin, and the source of the sixth NMOS transistor can be connected to the second terminal VRP; the first terminal of the second resistor can be connected to the second terminal VRP, and the second terminal of the second resistor can be grounded. When ENP2 is high, switch S1 is open; when ENP2 is low, switch S1 is closed.

[0063] Based on this, the voltage generation circuit 230 can be used to connect the target active low interrupt pin through the sixth NMOS transistor after the detection loop stabilizes. The current is generated through the second resistor R2 to produce a corresponding voltage, which is output from the second terminal VRP to the analog-to-digital converter in the sensor chip, so as to convert the resistance value of RP into a digital signal for subsequent processing by the chip.

[0064] Furthermore, to illustrate the working principle and technical effects of the pull-up resistor detection circuit provided by this invention, please refer to [link to relevant documentation]. Figure 3 , Figure 3 This is a schematic diagram combining the circuit structure and partial signal timing diagram of a pull-up resistor detection circuit provided by the present invention.

[0065] exist Figure 3When the first enable signal control terminal ENN1 and the second enable signal control terminal ENN2 are both 1, and the third enable signal control terminal ENP2 is 0, the pull-up resistor detection circuit is turned off and does not perform the detection function.

[0066] When the first enable signal control terminal ENN1 is high, the second enable signal control terminal ENN2 is low, and the third enable signal control terminal ENP2 is high, the first NMOS transistor, the second NMOS transistor, and the eighth NMOS transistor are turned on, and the first switch S1 is turned on; at this time, the voltage of the fourth node X4 is low, and the target low active interrupt pin is active. The voltage at the first power supply terminal VDD1 is the voltage at the first terminal VFB. The voltage at the first terminal VFB is 0, and the voltages of the upper and lower plates of the first capacitor C1 are the voltage at the first power supply terminal VDD1 and 0, respectively. At this time, VDD will charge the first capacitor C1.

[0067] Preferably, the first PMOS transistor and the second PMOS transistor are equivalent transistors. This ensures that when the first enable signal control terminal ENN1 is low, the second enable signal control terminal ENN2 is low, and the third enable signal control terminal ENP2 is high, for the path containing the first and second PMOS transistors, since they are equivalent transistors, due to amplifier characteristics, the current flowing through the first and second PMOS transistors is equal. That is, the gate-source voltages of the two transistors are equal. At this time, we can obtain: V1 - GND = V1 - 0.5 * 2IREF * R1 - VFB, VFB = -IREF * R1. From the above formula, we can see that VFB drops from 0 to a negative voltage of -IREF * R1. The first capacitor C1 needs to ensure charge conservation, and the upper plate... The voltage drops from VDD to =VDD-IREF*R1. Because... The voltage drop at the pins should not be too large; it should be... Since IREF*R1 ≤ 0.3*1.7V = 510mV, the specific values ​​of IREF and R1 on the chip can be determined.

[0068] Furthermore, after the circuit is operating normally, the voltage at node X3 gradually increases, causing the sixth NMOS transistor to turn on. =VDD-IREF*R1, therefore the voltage drop across the pull-up resistor is VDD- =IREF*R1, the current flowing through the pull-up resistor is IREF*R1 / RP. Since at this time... The only current path for the pins is NM6, therefore the current flowing through NM6 and R2 is IREF*R1 / RP, i.e., VRP=IREF*R1 / RP*R2. That is, when the sixth NMOS transistor is turned on, the current flowing through the pull-up resistor is IREF*R1 / RP, and the detection voltage of the pull-up resistor is IREF*R1 / RP*R2. Based on this, it can be concluded without a doubt that when IREF, R1, and R2 are all constant values, the value of VRP is determined only by the value of the pull-up resistor RP, and the two have a linear relationship. Thus, the detection of the pull-up resistor RP can be completed. It can be noted that the formula VRP=IREF*R1 / RP*R2 does not contain a VDD term, meaning that this detection method is independent of the power supply voltage, and VRP and RP have a linear relationship. Therefore, the pull-up resistor detection circuit provided by this invention can resist changes in power supply voltage (e.g., 1.7~5.5V), achieving the same detection result under different power supply voltages for the same pull-up resistor.

[0069] Furthermore, the VRP voltage can be quantized using an on-chip integrated high-precision ADC, thereby converting the value of the pull-up resistor RP into a digital signal for subsequent processing; this enables effective measurement of the pull-up resistor at the low active interrupt pin, solving the problem in the prior art that the pull-up resistor at the low active interrupt pin cannot be effectively measured.

[0070] Secondly, this invention provides a sensor chip, please refer to [reference needed]. Figure 2 The sensor chip may include at least a pull-up resistor detection circuit 200, a pull-up resistor RP, an analog-to-digital converter, and a ninth NMOS transistor; the pull-up resistor detection circuit is the detection circuit described in the first aspect.

[0071] Specifically, the first terminal of the pull-up resistor RP can be connected to the first power supply terminal VDD1, and the second terminal of the pull-up resistor RP can be connected to the target active low interrupt pin of the sensor chip. Connection; the first terminal of the pull-up resistor detection circuit 200 is connected to the target active low interrupt pin. The second terminal of the pull-up resistor detection circuit 200 is connected to the analog-to-digital converter; the drain of the ninth NMOS transistor is connected to the target active low interrupt pin, the source of the ninth NMOS transistor is grounded, and the gate of the ninth NMOS transistor is connected to the analog-to-digital converter.

[0072] Based on this, a pull-up resistor detection circuit can be used to detect the pull-up resistor, convert the resistance value of the pull-up resistor into a target voltage value and transmit it to the analog-to-digital converter; the analog-to-digital converter then converts the target voltage value into a digital signal for output; this achieves effective measurement of the pull-up resistor at the low active interrupt pin, solving the problem in the prior art that the pull-up resistor at the low active interrupt pin cannot be effectively measured.

[0073] It should be noted that the technical means and effects of the pull-up resistor detection circuit 200 in the sensor chip provided by the second aspect of the present invention are the same as those of the pull-up resistor detection circuit described in the first aspect, and will not be repeated here.

[0074] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0075] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A pull-up resistor detection circuit, characterized in that, At least including: Voltage shifting circuit, voltage comparison circuit, and voltage generation circuit; The first terminal of the voltage shifting circuit is connected to the target active low interrupt pin, and the second terminal of the voltage shifting circuit is connected to the first terminal of the voltage comparator circuit; the second terminal of the voltage comparator circuit is connected to the first terminal of the voltage generation circuit, and the second terminal of the voltage generation circuit is connected to the target active low interrupt pin; wherein, the target active low interrupt pin is connected to the first terminal of the pull-up resistor, and the second terminal of the pull-up resistor is connected to the first power supply terminal; The voltage shifting circuit includes a first capacitor, a first NMOS transistor, and a second NMOS transistor; the voltage shifting circuit is used to shift the change in the target node voltage to the target active low interrupt pin; The voltage comparison circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, an eighth NMOS transistor, a first resistor, a third resistor, and a fourth resistor. The voltage comparison circuit is used to compare the target node voltage with the ground voltage, and adjust the target node voltage according to the comparison result. The loop voltage of the pull-up resistor detection circuit remains stable after adjustment. The voltage generation circuit includes a first switch, a sixth NMOS transistor, a seventh NMOS transistor, and a second resistor; the voltage generation circuit is used to generate the detection voltage of the pull-up resistor and transmit the detection voltage to the analog-to-digital converter in the sensor chip.

2. The pull-up resistor detection circuit as described in claim 1, characterized in that, In the voltage shifting circuit, the first terminal of the first capacitor is connected to the target active low interrupt pin, and the second terminal of the first capacitor is connected to the drain of the first NMOS transistor; the source of the first NMOS transistor is connected to the first terminal, and the gate of the first NMOS transistor is connected to the third enable signal control terminal; the drain of the second NMOS transistor is connected to the first terminal, the gate of the second NMOS transistor is connected to the first enable signal control terminal, and the source of the second NMOS transistor is grounded; wherein, the voltage corresponding to the first terminal is the target node voltage.

3. The pull-up resistor detection circuit as described in claim 1, characterized in that, In the voltage comparison circuit, the source of the first PMOS transistor is connected to the first end of the first resistor, the second end of the first resistor is connected to the first node, the gate of the first PMOS transistor is connected to the first terminal, and the drain of the first PMOS transistor is connected to the second node; the source of the second PMOS transistor is connected to the first node, the gate of the second PMOS transistor is grounded, and the drain of the second PMOS transistor is connected to the third node. The source of the third PMOS transistor is connected to the second power supply terminal, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor, and the gate of the third PMOS transistor is connected to the third power supply terminal; the drain of the fourth PMOS transistor is connected to the first node, and the gate of the fourth PMOS transistor is connected to the second enable signal control terminal; the source of the fifth PMOS transistor is connected to the second power supply terminal, the drain of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor, and the gate of the fifth PMOS transistor is connected to the third power supply terminal; the drain of the sixth PMOS transistor is connected to the drain of the third NMOS transistor, and the gate of the sixth PMOS transistor is connected to the second enable signal control terminal; the source of the seventh PMOS transistor is connected to the second power supply terminal, the drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor, and the gate of the seventh PMOS transistor is connected to the third power supply terminal; the drain of the eighth PMOS transistor is connected to the fourth node, and the gate of the eighth PMOS transistor is connected to the second enable signal control terminal; The source of the third NMOS transistor is connected to the second node, the gate of the third NMOS transistor is connected to the drain of the third NMOS transistor, and the gate of the third NMOS transistor is connected to the drain of the fifth NMOS transistor; the drain of the fifth NMOS transistor is grounded, and the gate of the fifth NMOS transistor is connected to the second enable signal control terminal; the drain of the fourth NMOS transistor is connected to the fourth node, the gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor, and the source of the fourth NMOS transistor is connected to the third node; the drain of the eighth NMOS transistor is connected to the fourth node, the source of the eighth NMOS transistor is grounded, and the gate of the eighth NMOS transistor is connected to the first enable signal control terminal; The first end of the fourth resistor is connected to the second node, and the second end of the fourth resistor is grounded; the first end of the third resistor is connected to the third node, and the second end of the third resistor is grounded.

4. The pull-up resistor detection circuit as described in claim 3, characterized in that, The first PMOS transistor and the second PMOS transistor are equivalent transistors.

5. The pull-up resistor detection circuit as described in claim 1, characterized in that, In the voltage generation circuit, the first terminal of the first switch is connected to the fourth node, the second terminal of the first switch is connected to the gate of the sixth NMOS transistor, and the third terminal of the first switch is connected to the third enable signal control terminal. The drain of the seventh NMOS transistor is connected to the gate of the sixth NMOS transistor, the source of the seventh NMOS transistor is grounded, and the gate of the seventh NMOS transistor is connected to the second enable signal control terminal; the drain of the sixth NMOS transistor is connected to the target active low interrupt pin, and the source of the sixth NMOS transistor is connected to the second terminal; the first end of the second resistor is connected to the second terminal, and the second end of the second resistor is grounded.

6. The pull-up resistor detection circuit as described in claim 1, characterized in that, When the first enable signal control terminal is high, the second enable signal control terminal is high, and the third enable signal control terminal is low, the pull-up resistor detection circuit is turned off.

7. The pull-up resistor detection circuit as described in claim 1, characterized in that, When the first enable signal control terminal is high, the second enable signal control terminal is low, and the third enable signal control terminal is high, the first NMOS transistor, the second NMOS transistor, and the eighth NMOS transistor are turned on, the first switch is turned on, the voltage of the fourth node is low, and the voltage at the target low active interrupt pin is the voltage of the first power supply terminal.

8. The pull-up resistor detection circuit as described in claim 7, characterized in that, When the first enable signal control terminal is low, the second enable signal control terminal is low, and the third enable signal control terminal is high, the current flowing through the first PMOS transistor and the second PMOS transistor is equal.

9. The pull-up resistor detection circuit as described in claim 8, characterized in that, When the sixth NMOS transistor is turned on, the current flowing through the pull-up resistor is The detection voltage of the pull-up resistor is .

10. A sensor chip, characterized in that, It includes at least a pull-up resistor detection circuit, a pull-up resistor, an analog-to-digital converter, and a ninth NMOS transistor; the pull-up resistor detection circuit is the detection circuit described in any one of claims 1 to 9; The first end of the pull-up resistor is connected to the first power supply terminal, and the second end of the pull-up resistor is connected to the target active low interrupt pin of the sensor chip; the first end of the pull-up resistor detection circuit is connected to the target active low interrupt pin, and the second end of the pull-up resistor detection circuit is connected to the analog-to-digital converter; the drain of the ninth NMOS transistor is connected to the target active low interrupt pin, the source of the ninth NMOS transistor is grounded, and the gate of the ninth NMOS transistor is connected to the analog-to-digital converter. The pull-up resistor detection circuit is used to detect the pull-up resistor and convert the resistance value of the pull-up resistor into a target voltage value, which is then transmitted to the analog-to-digital converter. The analog-to-digital converter is used to convert the target voltage into a digital signal output.

Images