Test structure and test method for semiconductor device

Abstract

The embodiment of the invention discloses a test structure and a test method for a semiconductor device, the semiconductor device comprises a substrate, a plurality of grid electrodes and a plurality of contact structures, the test structure comprises a plurality of first conductive structures, and the substrate comprises a plurality of first active regions arranged at intervals; the plurality of grids are arranged on the substrate, and the projection of each grid on the surface of the substrate is overlapped with the corresponding first active region; the plurality of contact structures are respectively connected to the corresponding first active regions through the through holes, and the plurality of contact structures comprise a plurality of first contact structures located between two adjacent grids; the plurality of first contact structures are electrically connected between the first measurement structure and the second measurement structure through the plurality of first conductive structures and the corresponding first active regions, so that a resistance value between the first measurement structure and the second measurement structure represents an electrical property detection result of the plurality of first contact structures. According to the embodiment of the invention, the test accuracy of the process defect of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a testing structure and testing method for semiconductor devices. Background Art

[0002] In complementary metal oxide semiconductor (CMOS) manufacturing processes, non-volatile memory cells (embedded non-volatile memory, eNVM) are often integrated. This integration approach enables efficient information storage while effectively reducing the area and cost of circuit board modules. In the layout design of eNVM, the high-density memory array area typically occupies a large proportion. To improve memory speed, power consumption, and area efficiency, the periodic memory cell structure is arranged as densely as possible and compressed to the minimum size while meeting process and performance requirements. In various types of eNVM arrays, densely packed long gate strips and highly densely distributed contact structures are common. When the pattern pitch in the layout is too small, the pattern density is too high, or the pattern length is too long, it may exceed the process tolerance, thus exceeding the process window and increasing manufacturing risks. This can easily lead to defects such as short circuits, open circuits, and transistor performance degradation during the manufacturing process. If a single or a few memory cells fail due to these defects, it could cause malfunction across the entire chip, leading to a decrease in chip yield. Therefore, test structures such as contact resistance chains (RC chains) are currently commonly used to test the electrical properties of semiconductor device contact structures and monitor process defects. However, conventional test structures often fail to fully account for the unique structural characteristics of semiconductor devices. Summary of the Invention

[0003] In view of the above problems, the purpose of this application is to provide a test structure and test method for semiconductor devices. By designing a test structure for the first contact structure at the gap position between two adjacent gates densely arranged in the semiconductor device, the test accuracy of the process defects of the semiconductor device is improved, thereby improving the performance and yield of the semiconductor device.

[0004] According to a first aspect of an embodiment of the present application, a test structure for a semiconductor device is provided, wherein the semiconductor device includes a substrate, a plurality of gates, and a plurality of contact structures, and the test structure includes a plurality of first conductive structures, wherein: The substrate includes a plurality of first active regions spaced apart from each other; The plurality of gates are disposed on the substrate, and a projection of each gate on the surface of the substrate overlaps with the corresponding first active region; The plurality of contact structures are respectively connected to the corresponding first active regions via through holes, and the plurality of contact structures include a plurality of first contact structures located between two adjacent gates; The multiple first contact structures are electrically connected between the first measurement structure and the second measurement structure through the multiple first conductive structures and the corresponding first active areas, so that the resistance value between the first measurement structure and the second measurement structure represents the electrical detection results of the multiple first contact structures.

[0005] Optionally, the first contact structure is located on both sides of the first active region, a first end of the first contact structure is connected to the corresponding first conductive structure, and a second end of the first contact structure is connected to the corresponding first active region.

[0006] Optionally, the multiple first contact structures include the 1st to nth first contact structures, and the 1st to nth first contact structures are arranged in sequence along a direction parallel to the extension of the two adjacent gates. The first first contact structure is connected to the first measurement structure, the i-th first contact structure is connected to the i+1-th first contact structure through the corresponding first conductive structure, the j-th first contact structure is connected to the j+1-th first contact structure through the corresponding first active area, and the n-th first conductive structure is connected to the second measurement structure, where n is a positive integer greater than 1, i is an even number greater than or equal to 2, and j is an odd number greater than or equal to 1.

[0007] Optionally, the distance between the two adjacent gates is greater than a first preset threshold and less than a second preset threshold, the first preset threshold is greater than or equal to the size of the first contact structure, and the second preset threshold is less than or equal to the size of the two first contact structures.

[0008] Optionally, the length of the two adjacent gates along the first direction is greater than a third preset threshold, and the first ends of the two adjacent gates are both electrically connected to a third measurement structure.

[0009] Optionally, a width of the first conductive structure along the second direction is greater than a distance between two adjacent gates.

[0010] Optionally, the substrate further includes a second active region, the second active region being spaced apart from the plurality of first active regions, a well region being provided in the substrate within the second active region, a plurality of second contact structures being provided on the well region, and first ends of the plurality of second contact structures being respectively connected to the well region via through holes; The test structure also includes: The second conductive structure, the second ends of the plurality of second contact structures are respectively connected to the second conductive structure through through holes, and the well region is electrically connected to the fourth measurement structure through the second conductive structure and the plurality of second contact structures.

[0011] Optionally, the first measurement structure is used to provide a first test voltage, the second measurement structure is used to provide a second test voltage, the third measurement structure is used to provide a gate voltage to the two adjacent gates to shut down the channel current of the device, and the fourth measurement structure is used to provide a reverse bias voltage to the well region to reduce the leakage current of the device.

[0012] Optionally, the resistance value between the first measuring structure and the second measuring structure is calculated according to the voltage difference between the first test voltage and the second test voltage and the current value flowing through the first measuring structure and the second measuring structure.

[0013] According to a second aspect of an embodiment of the present application, a testing method for a semiconductor device is provided, which is used for the test structure described above, comprising: providing a gate voltage to two adjacent gates through a third measurement structure to shut down a channel current of the device; providing a reverse bias voltage to the well region in the substrate through the fourth measurement structure to reduce leakage current of the device; providing a first test voltage to the plurality of first contact structures located between the two adjacent gates through a first measurement structure, and providing a second test voltage to the plurality of first contact structures located between the two adjacent gates through a second measurement structure; Testing current values flowing through the first measurement structure and the second measurement structure; A resistance value between the first measurement structure and the second measurement structure, which represents an electrical property detection result of the plurality of first contact structures, is calculated based on a voltage difference between the first test voltage and the second test voltage and the current value.

[0014] The unexpected technical effects of this application are: In a semiconductor device, a substrate includes a plurality of first active regions spaced apart, a plurality of gates are disposed on the substrate, and the projection of each gate on the substrate surface overlaps with the corresponding first active region. The first contact structure at the gap position between two densely arranged adjacent gates is extremely sensitive to process defects. The plurality of first contact structures are electrically connected between a first measurement structure and a second measurement structure via a plurality of first conductive structures and the corresponding first active regions, so that the resistance value between the first measurement structure and the second measurement structure represents the electrical test results of the plurality of first contact structures. By measuring the resistance value between the first measurement structure and the second measurement structure, the electrical test results of the first contact structure at the gap position between two densely arranged adjacent gates can be accurately measured, thereby effectively monitoring and evaluating the process defects of the first contact structure at the gap position between two densely arranged adjacent gates in the semiconductor device, solving problems such as abnormal film layer stacking morphology, etching residue or poor contact, improving the test accuracy of process defects of the semiconductor device, and thereby improving the performance and yield of the semiconductor device.

[0015] In addition, in an embodiment of the present application, a gate voltage is provided to two adjacent gates through a third measurement structure to shut down the channel current of the device, a reverse bias voltage is provided to the well region in the substrate through a fourth measurement structure to reduce the leakage current of the device, a first test voltage is provided through the first measurement structure, and a second test voltage is provided through the second measurement structure to test the current value flowing through the first measurement structure and the second measurement structure. Based on the voltage difference and the current value between the first test voltage and the second test voltage, a resistance value between the first measurement structure and the second measurement structure is calculated to characterize the electrical detection results of multiple first contact structures. Through precise voltage and current control, the interference of channel current and leakage current on the electrical detection results during the test process is reduced, thereby improving the test accuracy and reliability of process defects of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which: Figure 1 Shown is a schematic diagram of a layout of a semiconductor device in the related art; Figure 2A FIG2 is a schematic diagram of a layout of a test structure for a semiconductor device in the related art; Figure 2B Shown Figure 2A Cross-sectional view of the film along line AA; Figure 3A FIG. 1 is a schematic diagram of a layout of another test structure for a semiconductor device in the related art; Figure 3B Shown Figure 3ACross-sectional view of the film along line BB; Figure 4A FIG2 is a schematic diagram of a layout of an exemplary test structure for a semiconductor device according to an embodiment of the present application; Figure 4B Shown Figure 4A Cross-sectional view of the film along CC line; Figure 4C Shown Figure 4A Cross-sectional view of the film along line DD; Figure 5 FIG2 is a flow chart of an exemplary method for testing a semiconductor device according to an embodiment of the present application.

[0017] Explanation of the reference numerals: 10 - active area; 110 - shallow trench isolation (STI); 120 - first active area; 130 - second active area; 20 - gate; 30 - contact structure; 310 - first contact structure; 320 - second contact structure; 40 - conductive structure; 410 - first conductive structure; 420 - second conductive structure. DETAILED DESCRIPTION

[0018] The present application will be described in more detail below with reference to the accompanying drawings. In each of the drawings, identical elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0019] This application may be embodied in various forms, some examples of which are described below.

[0020] It should be noted that for ease of illustration, some film layers are omitted in the drawings of this application. The spacing and line widths in the drawings are used to illustrate the relative positional relationships between corresponding components and components. The actual spacing and line width shall be based on the process rules.

[0021] Figure 1 The figure shows a schematic diagram of a semiconductor device layout in the related art. Figure 1As shown, a semiconductor device (e.g., an embedded non-volatile memory) includes a substrate, multiple gates 20, and multiple contact structures 30. The substrate serves as a reference surface and mechanical support and includes multiple spaced active areas 10, which are isolated from each other by shallow trench isolation (STI). Active areas 10 refer to regions on a semiconductor substrate used to form transistors (e.g., NMOS devices, PMOS devices) or other active devices. These regions are typically doped to form well, source, drain, and channel regions. STI is an isolation technology used to isolate different active areas. It achieves electrical isolation between the different active areas by etching shallow trenches in the substrate and filling the trenches with an insulating material (e.g., silicon dioxide). Multiple gates 20 are disposed on the substrate, with the projection of each gate 20 on the substrate surface overlapping the corresponding active area 10. The gate 20 can be made of polysilicon (Poly) or metal. The gate 20 controls the formation of the channel and controls the flow of carriers between the source region and the drain region by applying a gate voltage on the gate 20. An array of contact structures 30 are provided on the active area 10, and a contact structure 30 is also provided in the gate 20. The contact structure 30 is a channel connecting the front-end transistor and the back-end metal wiring. It is connected to the gate as well as the source region and the drain region. The quality of etching of the contact structure 30 directly affects the characteristics of the semiconductor device and the yield of the product. The spacing between the gates 20 is related to the type and number of cell devices in the active area 10. For example Figure 1 As shown, in some cases, the gates 20 are densely arranged long strip gates. Specifically, it can be understood that the spacing between the gates 20 along the Y-axis direction is less than a preset threshold so that only one contact structure 30 can be set between the gates 20, and the length of the gates 20 along the X-axis direction is greater than the preset threshold. In densely arranged long strip gates, especially when the spacing between the gates 20 is very small and the contact structures 30 are highly densely distributed, the contact structures located in the gaps between adjacent gates 20 are extremely sensitive to process defects. For example, abnormal film layer stacking morphology or etching residue problems between the gates 20 may lead to poor formation of silicon-metal compounds and poor morphology at the bottom of the via. These problems not only increase the resistance of the contact structure, but may also further affect the performance of the semiconductor device, resulting in a decrease in the yield of the semiconductor device. Therefore, effective electrical testing of the contact structures at these key structural positions is an important means to improve the reliability and yield of semiconductor devices.

[0022] Figure 2A FIG. 1 is a schematic diagram of a layout of a test structure for a semiconductor device in the related art. Figure 2B Shown Figure 2A The cross-sectional view of the film along line AA. Figure 2A and Figure 2B As shown, the semiconductor device in the related art includes a plurality of active areas 10 arranged at intervals, and the active areas 10 are isolated by shallow trench isolation regions 110. Contact structures 30 are provided at both ends of the active areas 10. The test structure includes a conductive structure 40, and the plurality of active areas 10 and the conductive structure 40 are connected end to end through the contact structure 30 to form a contact resistance chain (Rc chain). The contact structure 30 of the active area 10 located at the head end and the contact structure 30 of the active area 10 located at the tail end are both connected to the measurement structure. By applying a test voltage to the measurement structure, the current flowing through the connected path of the contact resistance chain is measured, and the resistance value representing the electrical test result of the contact structure 30 can be calculated according to Ohm's law. The resistance value can directly reflect the process defects of the contact structure 30 on the active area 10 in a large area.

[0023] Figure 3A FIG. 1 is a schematic diagram of a layout of a test structure of another semiconductor device in the related art. Figure 3B Shown Figure 3A The cross-sectional view of the film along line BB. Figure 3A and Figure 3B As shown, the semiconductor device in the related art includes a plurality of gates 20 spaced apart on an active area 10, and contact structures 30 are provided at both ends of the gates 20. The test structure includes a conductive structure 40, and the plurality of gates 20 and the conductive structure 40 are connected end to end through the contact structure 30 to form a contact resistance chain (Rc chain). The contact structure 30 of the gate 20 at the head end and the contact structure 30 of the gate 20 at the tail end are both connected to the measurement structure. By applying a test voltage to the measurement structure, the current flowing through the connected path of the contact resistance chain is measured, and the resistance value representing the electrical test result of the contact structure 30 can be calculated according to Ohm's law. The resistance value can directly reflect the process defects of the contact structure 30 located on the gate 20.

[0024] Understandably, the test structures in the related art primarily focus on contact structures 30 on active regions 10 with larger areas or on gates 20, but fail to effectively monitor contact structures located between closely spaced gates 20 in semiconductor devices. Consequently, when applied to high-density memory arrays, the test structures in the related art suffer from a process defect that prevents them from effectively monitoring contact structures at critical locations in semiconductor devices, thereby impacting the performance and yield of the semiconductor devices.

[0025] Based on this, the embodiments of the present application propose a new test structure and test method for semiconductor devices. By designing a test structure of the first contact structure at the gap position between two adjacent gates densely arranged in the semiconductor device, the process defects of the semiconductor device can be accurately tested to improve the performance and yield of the semiconductor device.

[0026] Figure 4A FIG. 1 is a schematic diagram of a layout of an exemplary test structure for a semiconductor device according to an embodiment of the present application. Figure 4B Shown Figure 4A The cross-sectional view of the film along the CC line is shown in 4C. Figure 4A The cross-sectional view of the film along the DD line. Figures 4A to 4C As shown, the semiconductor device of the embodiment of the present application includes a substrate, multiple gates 20, multiple contact structures 30 and multiple second contact structures 320. The multiple contact structures 30 include multiple first contact structures 310. The test structure includes multiple first conductive structures 410 and multiple second conductive structures 420. The substrate serves as a reference surface and mechanical support, and includes multiple first active areas 120 spaced apart. The first active areas 120 are isolated by shallow trench isolation regions 110. It should be noted that Figure 4A Only three first active regions 120 are shown, spaced apart from each other. The semiconductor device may also include other numbers of first active regions 120, which is not limited in this embodiment of the present application. The multiple first active regions 120 may also be arranged in an array, for example, in two rows and three columns.

[0027] In some embodiments, the substrate further includes a second active region 130, which is spaced apart from the plurality of first active regions 120. A well region is provided in the substrate within the second active region 130. The well region can be formed in the substrate within the second active region 130 using processes such as ion implantation. In high-density memory arrays, it is often necessary to integrate NMOS and PMOS devices on the same substrate to implement CMOS logic circuits. To integrate NMOS and PMOS devices on the same P-type substrate, an N-type well region (N-well) is formed in the P-type substrate to fabricate the PMOS device, while the NMOS device is fabricated directly in the P-type substrate. To integrate NMOS and PMOS devices on an N-type substrate, a P-type well region (P-well) is formed in the N-type substrate to fabricate the NMOS device, while the PMOS device is fabricated directly in the N-type substrate. In some embodiments, to fabricate the NMOS device, a highly N-type doped source and drain region can be formed in the P-type substrate or P-well region using processes such as ion implantation. For manufacturing PMOS devices, a source and drain region with a high concentration of P-type doping can be formed in an N-type substrate or N-type well region through processes such as ion implantation. In some embodiments, a plurality of second contact structures 320 are provided on a well region provided in the substrate within the second active region 130. The first ends of the plurality of second contact structures 320 are respectively connected to the well region via through-holes. The second ends of the plurality of second contact structures 320 are respectively connected to the second conductive structure 420 via through-holes. The well region is electrically connected to the fourth measurement structure via the second conductive structure 420 and the plurality of second contact structures 320.

[0028] In some embodiments, a plurality of gates 20 are provided on the substrate, and the projection of each gate 20 on the substrate surface overlaps with the corresponding first active region 120. The gate 20 can be made of polysilicon (Poly) or metal, is located between the source region and the drain region, and is covered on the gate oxide layer (Gate Oxide). The formation of the channel between the source region and the drain region is controlled by applying a gate voltage to the gate 20. When the gate voltage reaches a certain threshold, a conductive channel is induced on the surface of the substrate, thereby allowing current to flow from the source region to the drain region (or from the drain region to the source region). In some embodiments, a plurality of contact structures 30 arranged in an array are provided on the first active region 120. It should be noted that, Figure 4AThis illustrates only one exemplary arrangement of the contact structures 30 in the first active area 120. The first active area 120 of a semiconductor device may also include other numbers and arrangements of contact structures 30, and this is not limited in the present embodiments. The contact structures 30 serve as pathways connecting front-end transistors and back-end metal wiring, connecting both the gate and the source and drain regions. The quality of their etching directly impacts the characteristics of the semiconductor device and the product yield. The spacing between adjacent gates 20 refers to the distance between two adjacent gates 20 along the Y-axis. This directly affects transistor size and density. A smaller gate spacing allows for more transistors to be accommodated within the same chip area, thereby increasing the density of the cell device. In some embodiments, the contact structures 30 include multiple first contact structures 310 located between two adjacent gates 20. The spacing between two adjacent gates 20 is greater than a first preset threshold and less than a second preset threshold. The first preset threshold is greater than or equal to the size of the first contact structure 310, while the second preset threshold is less than or equal to the size of both first contact structures 310. In some embodiments, the length of two adjacent gates 20 along the X-axis is greater than a third predetermined threshold, and the first ends of the two adjacent gates 20 are both connected to the third measurement structure 3. In some embodiments, the width of the first conductive structure 410 along the Y-axis is greater than the spacing between the two adjacent gates 20.

[0029] In some embodiments, the plurality of first contact structures 310 are electrically connected between the first measurement structure 1 and the second measurement structure 2 via the plurality of first conductive structures 410 and the corresponding first active regions 120, such that the resistance value between the first measurement structure 1 and the second measurement structure 2 represents the electrical test results of the plurality of first contact structures 310. In some embodiments, the first contact structures 310 are located on both sides of the first active region 120, with the first ends of the first contact structures 310 connected to the corresponding first conductive structures 410, and the second ends of the first contact structures 310 connected to the corresponding first active regions 120. In some embodiments, the plurality of first contact structures 310 include the 1st to nth first contact structures 310, and the 1st to nth first contact structures 310 are arranged sequentially along a direction parallel to the extension of two adjacent gates 20, the first first contact structure 310 is connected to the first measurement structure 1, the i-th first contact structure 310 is connected to the i+1-th first contact structure 310 through the corresponding first conductive structure 410, the j-th first contact structure 310 is connected to the j+1-th first contact structure 310 through the corresponding first active region 120, and the n-th first conductive structure 410 is connected to the second measurement structure 2, where n is a positive integer greater than 1, i is an even number greater than or equal to 2, and j is an odd number greater than or equal to 1.

[0030] In some embodiments, the first measurement structure 1 is used to provide a first test voltage, and the second measurement structure 2 is used to provide a second test voltage. The third measurement structure 3 is used to provide a gate voltage to two adjacent gates 20 to shut off the device's channel current. The fourth measurement structure is used to provide a reverse bias voltage to the well region to reduce device leakage current. In some embodiments, when the well region is a P-type well region of an NMOS device, the reverse bias voltage is ground voltage GND. When the well region is an N-type well region of a PMOS device, the reverse bias voltage is supply voltage VDD. The gate voltage is ground voltage GND. In some embodiments, by measuring the current flowing through the first measurement structure 1 and the second measurement structure 2, and based on the voltage difference between the first and second test voltages and the measured current value, the resistance value between the first measurement structure 1 and the second measurement structure 2 can be calculated according to Ohm's law to represent the electrical properties of the multiple first contact structures 310. This resistance value can directly reflect the process defects of the first contact structure 310 in the gap between two adjacent gates 20. When the resistance value is greater than a certain threshold, it can be determined that the first contact structure 310 at that location has a defect, such as an abnormal film buildup morphology, etching residue, or poor contact. This testing method can accurately measure the electrical properties of the first contact structure located in the gap between two closely spaced adjacent gates, thereby effectively monitoring and evaluating process defects in the first contact structure located in the gap between two closely spaced adjacent gates in a semiconductor device. This solves problems such as abnormal film buildup morphology, etching residue, or poor contact, improves the accuracy of testing process defects in semiconductor devices, and thereby improves the performance and yield of semiconductor devices.

[0031] Figure 5 The figure shows a flow chart of an exemplary method for testing a semiconductor device according to an embodiment of the present application. The testing method of the embodiment of the present application is used as follows: Figures 4A to 4C The test structure shown in Figure 5 As shown, the testing method of the embodiment of the present application includes: In step S510 , a gate voltage is provided to two adjacent gates via a third measurement structure to shut down the channel current of the device.

[0032] In step S520 , a reverse bias voltage is provided to the well region in the substrate via a fourth measurement structure to reduce leakage current of the device.

[0033] In step S530 , a first test voltage is provided to the plurality of first contact structures located between the two adjacent gates via a first measurement structure, and a second test voltage is provided to the plurality of first contact structures located between the two adjacent gates via a second measurement structure.

[0034] In step S540 , current values flowing through the first measurement structure and the second measurement structure are tested.

[0035] In step S550 , a resistance value representing an electrical detection result of the plurality of first contact structures is calculated between the first measurement structure and the second measurement structure according to a voltage difference between the first test voltage and the second test voltage and the current value.

[0036] Since the process of testing the process defects of the contact structure located at the gap position between densely arranged long strip gates using the testing method of the embodiment of the present application has been described in detail above, it will not be repeated here.

[0037] Finally, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The embodiments of the present application are described above, and these embodiments do not describe all details in detail, nor do they limit the application to only the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A test structure for a semiconductor device, the semiconductor device comprising a substrate, a plurality of gates, and a plurality of contact structures, the test structure comprising a plurality of first conductive structures, wherein: The substrate includes a plurality of first active regions spaced apart from each other; The plurality of gates are disposed on the substrate, and a projection of each gate on the surface of the substrate overlaps with the corresponding first active region; The plurality of contact structures are respectively connected to the corresponding first active regions via through holes, and the plurality of contact structures include a plurality of first contact structures located between two adjacent gates; The multiple first contact structures are electrically connected between the first measurement structure and the second measurement structure through the multiple first conductive structures and the corresponding first active areas, so that the resistance value between the first measurement structure and the second measurement structure represents the electrical detection results of the multiple first contact structures.

2. The test structure according to claim 1, wherein: The first contact structure is located on both sides of the first active region, a first end of the first contact structure is connected to the corresponding first conductive structure, and a second end of the first contact structure is connected to the corresponding first active region.

3. The test structure according to claim 2, wherein: The multiple first contact structures include the 1st to nth first contact structures, and the 1st to nth first contact structures are arranged in sequence along a direction parallel to the extension of the two adjacent gates. The first first contact structure is connected to the first measurement structure, the i-th first contact structure is connected to the i+1-th first contact structure through the corresponding first conductive structure, the j-th first contact structure is connected to the j+1-th first contact structure through the corresponding first active area, and the n-th first conductive structure is connected to the second measurement structure, where n is a positive integer greater than 1, i is an even number greater than or equal to 2, and j is an odd number greater than or equal to 1.

4. The test structure according to claim 1, wherein: The distance between the two adjacent gates is greater than a first preset threshold and less than a second preset threshold, the first preset threshold is greater than or equal to the size of the first contact structure, and the second preset threshold is less than or equal to the size of the two first contact structures.

5. The test structure according to claim 1, wherein: The length of the two adjacent gates along the first direction is greater than a third preset threshold, and the first ends of the two adjacent gates are both electrically connected to the third measurement structure. The test structure according to claim 1 , wherein: The width of the first conductive structure along the second direction is greater than the distance between the two adjacent gates.

7. The test structure according to claim 5, wherein: The substrate further includes a second active region, the second active region being spaced apart from the plurality of first active regions, a well region being provided in the substrate within the second active region, a plurality of second contact structures being provided on the well region, and first ends of the plurality of second contact structures being connected to the well region via through holes, respectively; The test structure also includes: The second conductive structure, the second ends of the plurality of second contact structures are respectively connected to the second conductive structure through through holes, and the well region is electrically connected to the fourth measurement structure through the second conductive structure and the plurality of second contact structures.

8. The test structure according to claim 7, wherein: The first measurement structure is used to provide a first test voltage, the second measurement structure is used to provide a second test voltage, the third measurement structure is used to provide a gate voltage for the two adjacent gates to shut down the channel current of the device, and the fourth measurement structure is used to provide a reverse bias voltage for the well region to reduce the leakage current of the device.

9. The test structure according to claim 8, wherein: The resistance value between the first measuring structure and the second measuring structure is calculated according to the voltage difference between the first test voltage and the second test voltage and the current value flowing through the first measuring structure and the second measuring structure.

10. A method for testing a semiconductor device, used in the test structure according to any one of claims 1 to 9, comprising: providing a gate voltage to two adjacent gates through a third measurement structure to shut down a channel current of the device; providing a reverse bias voltage to the well region in the substrate through the fourth measurement structure to reduce leakage current of the device; providing a first test voltage to the plurality of first contact structures located between the two adjacent gates through a first measurement structure, and providing a second test voltage to the plurality of first contact structures located between the two adjacent gates through a second measurement structure; Testing current values flowing through the first measurement structure and the second measurement structure; A resistance value between the first measurement structure and the second measurement structure, which represents an electrical property detection result of the plurality of first contact structures, is calculated based on a voltage difference between the first test voltage and the second test voltage and the current value.

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