Dynamic register management system and method for vector processor

Abstract

The invention relates to the technical field of computer system structures, and discloses a dynamic register management system and method for a vector processor. The system comprises an instruction fetching unit, an instruction decoding unit and an execution unit. The instruction fetching unit is used for acquiring a vector operation instruction and sending the vector operation instruction to the instruction decoding unit; the instruction decoding unit receives the vector operation instruction sent by the instruction receiving unit, decodes the vector operation instruction, analyzes vector operation to be executed and an input vector register and an output vector register corresponding to the vector operation, judges whether the input vector register and the output vector register are in a compact VRF or not, and if yes, executes the vector operation. If yes, the value of the input vector register and the value of the output vector register are transmitted to an execution unit, if not, the value of the missing vector register is read from the special memory space of the vector register, and the execution unit is used for executing vector operation. By dynamically managing the vector register, the space of a register file can be saved, and the hardware cost is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of computer architecture, for example, to a dynamic register management system and method for a vector processor. Background Art

[0002] The current RISC-V Vector Extension (RVV) specification requires 32 vector registers, resulting in traditional vector register files occupying over 60% of the VPU area in low-cost processors. Existing solutions all have certain drawbacks. For full-size register file solutions, ML applications only use an average of 4-8 active registers, resulting in wasted area due to the fixed 32-register configuration. For narrow vector solutions, reducing vector length sacrifices data-level parallelism. For solutions without register files, direct memory access leads to a sharp performance degradation.

[0003] Patent application CN116521229A discloses a low-hardware-overhead vector processor architecture based on the RISC-V vector instruction extension, belonging to the field of electronic digital data processing. This architecture includes a vector instruction queue, a scalar register cache, a decoding and dispatch module, a register status table, an instruction status table, a scoreboard issue queue, a vector addition unit, a vector multiplication unit, a vector load / store unit, and a vector register set. Vector instructions are fed into the vector instruction queue from the scalar side and dispatched to the corresponding vector unit based on the different operation types obtained by decoding. They are then executed and written back, employing a sequential dispatch strategy, with sequential issuance of identical microinstructions. The scoreboard and issue queue are combined to control dynamic scheduling of instructions, taking advantage of the microcoded nature of vector instructions, in conjunction with the register status table and instruction status table. This invention achieves the orderly and efficient execution of vector instructions within a vector processor with low hardware overhead. This invention uses a scoreboard to record certain features, such as the current register state and current register index, and tightly couples this design with a vector issue queue. Combined with the microcoded nature of vector instructions, this approach achieves pipelined execution of vector instructions while also minimizing hardware overhead and significantly reducing register usage. However, this invention still uses a fixed number of registers, making dynamic register management impossible.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to ordinary technicians in this field. Summary of the Invention

[0005] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0006] The embodiments of the present disclosure provide a dynamic register management system and method for a vector processor to solve the technical problem of the inability to balance the hardware cost and read and write performance of existing vector register files.

[0007] In some embodiments, the system includes: an instruction fetch unit, an instruction decode unit, and an execution unit;

[0008] The instruction fetch unit is used to fetch vector operation instructions and send the vector operation instructions to the instruction decoding unit;

[0009] The instruction decoding unit is connected to the instruction fetch unit, and is used to receive the vector operation instructions sent by the instruction fetch unit and decode the vector operation instructions, parse the vector operation to be executed and the input vector register and output vector register corresponding to the vector operation, and then determine whether the parsed input vector register and output vector register are both in the compact VRF. If so, the labels of the input vector register and output vector register are transferred to the compact VRF. If not, a signal is sent to the execution unit to make it read the value of the missing vector register and its label from the vector register dedicated memory space into the compact VRF. The vector register dedicated memory space is set in the memory subsystem and is used to store information of all vector registers.

[0010] The execution unit is connected to the instruction decoding unit. A compact VRF is provided in the execution unit. The compact VRF stores the values of the most recently accessed vector registers and their labels. The number of vector registers stored is less than the total number of vector registers defined by the general RISC-V architecture. When executing a vector operation instruction, the execution unit reads the value of the input vector register from the compact VRF, and stores the output data in the output vector register after executing the vector operation.

[0011] As a further optimization, the instruction fetch unit includes an instruction cache, an instruction memory interface and a program counter. The instruction memory interface is connected between the external module and the instruction cache, and the program counter is connected to the instruction cache. When fetching instructions, the vector operation instructions adjacent to the instruction pointed to by the current program counter are first stored in the instruction cache through the instruction memory interface, and then the vector operation instruction pointed to by the current program counter in the instruction cache is taken out and sent to the instruction decoding unit.

[0012] As a further optimization, the instruction decoding unit includes a vector operation decoding unit, a compact VRF label queue and a register dispersion control module. The vector operation decoding unit is connected to the instruction fetch unit and is used to receive vector operation instructions from the instruction fetch unit, parse the vector operation to be executed and send it to the execution unit, and parse the input vector register and output vector register corresponding to the vector operation and send them to the register dispersion control module. The compact VRF label queue stores the vector register labels in the current compact VRF. The register dispersion control module determines whether the input vector register and output vector register corresponding to the vector operation are both in the compact VRF according to the vector register labels in the compact VRF label queue. If so, the register dispersion control module transmits the labels of the input vector register and the output vector register to the compact VRF. If not, the register dispersion control module sends a signal to the execution unit to read the missing vector register value and its label from the vector register dedicated memory space into the compact VRF, and update the value of the compact VRF label queue at the same time.

[0013] As a further optimization, the execution unit also includes a vector access unit and a vector processing unit. The compact VRF is connected between the register distribution control module and the vector processing unit. The vector processing unit is also connected to the vector operation decoding unit. The vector access unit is connected to the register distribution control module and the vector register dedicated memory space. During the execution of the vector operation instruction, the instruction of the register distribution control module is received. If the input vector register and the output vector register are both in the compact VRF, the value of the input vector register is transferred to the vector processing unit for calculation, and the calculation result is output to the output vector register. If the input vector register and the output vector register are not both in the compact VRF, the missing vector register is read from the vector register dedicated memory space through the vector access unit and placed in the compact VRF. The vector processing unit receives the input vector register in the compact VRF, performs operations according to the operation code parsed by the vector operation decoding unit, and stores the operation result in the output vector register in the compact VRF.

[0014] As a further optimization, the compact VRF adopts a circular FIFO queue organization form. The head pointer of the circular FIFO queue always points to the register with the longest residence time in the compact VRF, and the tail pointer points to the next free vector register slot. When reading a missing vector register from the vector register dedicated memory space through the vector access unit, if the circular FIFO queue is not full, the read vector register is stored in the free vector register slot pointed to by the tail pointer, and the tail pointer is moved to the next register slot position. If the circular FIFO queue is full, the read vector register replaces the register with the longest residence time pointed to by the head pointer with the read vector register, and the head pointer is moved to the next register slot position.

[0015] As a further optimization, an instruction fetch / decode buffer is also included, and the instruction fetch unit and the instruction decode unit are connected through the instruction fetch / decode buffer.

[0016] As a further optimization, a decoding / execution buffer is also included, and the instruction decoding unit and the execution unit are connected through the decoding / execution buffer.

[0017] As a further optimization, the instruction cache includes ICACHE and instruction prefetch buffer.

[0018] In some embodiments, the method comprises:

[0019] Step S01: fetch a vector operation instruction and decode it by a vector operation decoding unit to parse out the vector operation to be executed and the input vector register and output vector register corresponding to the vector operation;

[0020] Step S02: Determine whether the parsed input vector register and output vector register are both in the compact VRF. If so, transfer the labels of the input vector register and output vector register to the compact VRF. The vector processing unit reads the value of the input vector register from the compact VRF, performs calculations, and stores the output data in the output vector register.

[0021] Step S03: If both the input vector register and the output vector register are not in the compact VRF, the values and labels of the missing vector registers are read from the vector register dedicated memory space into the compact VRF. The execution unit reads the values of the input vector registers from the compact VRF, performs the vector operation, and stores the output data into the output vector register.

[0022] As a further optimization, when executing step S03, first determine whether the compact VRF is full. If it is full, read the missing vector operands from the vector register dedicated memory space to the slot pointed to by the head pointer, and then move the head pointer to the next register slot position; if it is not full, read the missing vector operands from the vector register dedicated memory space to the free slot pointed to by the tail pointer.

[0023] The dynamic register management system and method for a vector processor provided by the embodiments of the present disclosure can achieve the following technical effects: the present invention sets a compact VRF and a vector register-specific memory space, the registers that are frequently accessed recently are placed in the compact VRF, and the vector register-specific memory space is set in the memory subsystem to store information of all vector registers. By dynamically managing the architecture vector registers, it is ensured that the recently accessed registers can be quickly used by the vector processing unit (VPU), while the unused or recently unused registers are stored in the memory subsystem (such as cache or main memory). Since the number of vector registers in the compact VRF is significantly smaller than the number of vector registers in the general RISC-V architecture, the space of the register file can be greatly saved and the hardware cost can be reduced. The present invention executes vector operation instructions and preferentially accesses the compact VRF located in the RISC-V architecture, with fast access speed, thereby being able to balance the VPU area and reasoning performance.

[0024] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments are exemplarily described by corresponding drawings. These exemplary descriptions and drawings do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation. In addition,

[0026] Figure 1 is a functional block diagram of the system described in Example 1;

[0027] Figure 2 Flowchart of the method described in Example 2. DETAILED DESCRIPTION

[0028] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The accompanying drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the sake of convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0029] The terms "first," "second," and the like in the embodiments of the present disclosure are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate to facilitate the description of the embodiments of the present disclosure herein. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0030] Unless otherwise stated, the term "plurality" means two or more.

[0031] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B means: A or B.

[0032] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0033] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0034] Example 1

[0035] This embodiment discloses a dynamic register management system for a vector processor, such as Figure 1 As shown, it includes instruction fetch (IF) unit, instruction decode (ID) unit, execution (EX) unit, instruction fetch / decode buffer ( Figure 1 IF / ID in the decode / execute buffer ( Figure 1 The instruction fetch unit is connected to the instruction decode unit through the instruction fetch / decode buffer, and the instruction decode unit is connected to the execution unit through the decode / execute buffer.

[0036] The instruction fetch unit is used to obtain vector operation instructions and send them to the instruction decoding unit. Specifically, the instruction fetch unit includes an instruction cache, an instruction memory interface, and a program counter ( Figure 1 (denoted by PC in the instruction cache), the instruction memory interface is connected between the external module and the instruction cache, and the program counter PC is connected to the instruction cache. The instruction cache includes ICACHE and an instruction prefetch buffer. When fetching an instruction, the vector operation instruction adjacent to the instruction pointed to by the current program counter is first stored in the instruction cache through the instruction memory interface, and then the vector operation instruction pointed to by the current program counter in the instruction cache is retrieved and sent to the instruction fetch / decode buffer. In this embodiment, the instruction fetch unit adopts a prefetch method, that is, the vector operation instruction needed next time is first fetched into the instruction cache. When the corresponding vector operation instruction is to be executed, it is directly sent from the instruction cache to the instruction fetch / decode buffer, which takes less time and saves operation time.

[0037] The instruction decoding unit is connected to the instruction fetch unit, and is used to receive the vector operation instructions sent by the instruction fetch unit and decode the vector operation instructions, parse the vector operation to be executed and the input vector registers (vs1, vs2) and output vector registers (vd) corresponding to the vector operation, and then determine whether the parsed input vector registers and output vector registers are both in the compact VRF. If so, the labels of the input vector registers and output vector registers are transferred to the compact VRF. If not, a signal is sent to the execution unit to read the missing vector register values and their labels from the vector register dedicated memory space into the compact VRF. The vector register dedicated memory space is set in the memory subsystem and is used to store information of all vector registers.

[0038] In this embodiment, the instruction decoding unit includes a vector operation decoding unit, a compact VRF label queue, and a register distribution control module. The vector operation decoding unit is connected to the instruction fetch / decode buffer and is used to read vector operation instructions from the instruction fetch / decode buffer, parse the vector operation to be executed, and send it to the execution unit. The vector operation is also parsed to obtain the input vector registers (vs1, vs2) and output vector register (vd) corresponding to the vector operation and send them to the register distribution control module. The compact VRF label queue stores the vector register labels in the current compact VRF. The register distribution control module determines whether the input vector registers and output vector registers corresponding to the vector operation are both in the compact VRF based on the vector register labels in the compact VRF label queue. If so, the register distribution control module transmits the labels of the input vector registers and output vector registers to the compact VRF. If not, the register distribution control module sends a signal to the execution unit to read the missing vector register values and their labels from the vector register-specific memory space into the compact VRF and update the value of the compact VRF label queue.

[0039] The execution unit is connected to the instruction decode unit and contains a compact VRF. This VRF stores the values and tags of recently accessed vector registers. The number of vector registers stored in the compact VRF is smaller than the total number of vector registers defined by the general RISC-V architecture. A fixed portion of RAM is allocated for all vector registers in the general RISC-V architecture, storing information about all vector registers. This memory space is called the vector register-specific memory space. When executing a vector operation instruction, the execution unit reads the value of the input vector register from the compact VRF and, after performing the vector operation, stores the output data in the output vector register.

[0040] The execution unit also includes a vector access unit and a vector processing unit. The compact VRF is connected between the register distribution control module and the vector processing unit. The vector processing unit is also connected to the vector operation decoding unit. The vector access unit is connected to the register distribution control module and the vector register dedicated memory space. During the execution of the vector operation instruction, according to the instruction of the register distribution control module, if the input vector register and the output vector register are both in the compact VRF, the value of the input vector register is transferred to the vector processing unit for calculation (the specific operation is determined by the operation code decoded by the vector operation decoding unit), and the calculation result is output to the output vector register. If the input vector register and the output vector register are not both in the compact VRF, the missing vector register is read from the vector register dedicated memory space through the vector access unit and placed in the compact VRF. The vector processing unit receives the input vector register in the compact VRF, performs operation according to the operation code parsed by the vector operation decoding unit, and stores the operation result in the output vector register in the compact VRF.

[0041] In this embodiment, the compact VRF adopts the organizational form of a circular FIFO queue. The head pointer of the circular FIFO queue always points to the register with the longest residence time in the compact VRF, and the tail pointer points to the next free vector register slot. When a missing vector register is read from the vector register dedicated memory space through the vector access unit, if the circular FIFO queue is not full, the read vector register is stored in the free vector register slot pointed to by the tail pointer, and the tail pointer is moved to the next register slot position. If the circular FIFO queue is full, the read vector register replaces the register with the longest residence time pointed to by the head pointer, and the head pointer is moved to the next register slot position.

[0042] In the above description, VRF stands for Vector Register File. The final calculation results can be output through the data memory interface.

[0043] In this embodiment, four vector register files are stored in the compact VRF. The total number of vector registers defined by the general RISC-V architecture is 32. The number of vector registers stored in the compact VRF is much smaller than the total number of vector registers defined by the general RISC-V architecture. Therefore, the space of the register file can be greatly saved and the hardware cost can be reduced.

[0044] The dynamic register management system described in the present invention can be used in a low-power RISC-V vector processor architecture for edge computing devices. It optimizes hardware resources by dynamically managing vector register files and is suitable for data parallel computing scenarios such as machine learning acceleration.

[0045] Example 2

[0046] This embodiment discloses a dynamic register management method for a vector processor. This method is implemented based on the system described in Example 1. Figure 2 As shown, the method includes:

[0047] Step S01: fetch a vector operation instruction and decode it by a vector operation decoding unit to parse out the vector operation to be executed and the input vector register and output vector register corresponding to the vector operation;

[0048] Step S02: Determine whether the parsed input vector register and output vector register are both in the compact VRF. If so, transfer the labels of the input vector register and output vector register to the compact VRF. The vector processing unit reads the value of the input vector register from the compact VRF, performs calculations, and stores the output data in the output vector register.

[0049] Step S03: If both the input vector register and the output vector register are not in the compact VRF, first determine whether the compact VRF is full. If so, read the missing vector operands from the vector register dedicated memory space to the slot pointed to by the head pointer, and then move the head pointer to the next register slot. If not, read the missing vector operands from the vector register dedicated memory space to the free slot pointed to by the tail pointer.

[0050] S04. The vector processing unit reads the value of the input vector register from the compact VRF, performs calculations, and stores the output data into the output vector calculator.

[0051] The following describes this method with a specific vector operation:

[0052] Assuming the compact VRF size is 4 physical registers (v0 is fixed storage and does not participate in replacement), the current compact VRF content (FIFO order) is as follows:

[0053] Slot0 (head pointer): v5,

[0054] Slot1:v3,

[0055] Slot2:v7,

[0056] Slot3 (tail pointer): idle,

[0057] Execute the multiply-accumulate instruction "vmacc v1,v2,v3".

[0058] S1. During instruction decoding (ID stage), check whether operands v1 (destination), v2 (source 1), and v3 (source 2) are in the compact VRF:

[0059] v1: miss (not in compact VRF),

[0060] v2: miss (not in compact VRF),

[0061] v3: Hit (located in Slot 1).

[0062] S2. Process the missed operand and first load v1. The compact VRF has a free slot (Slot3), so v1 is directly loaded into Slot3 and the tail pointer is moved to Slot0.

[0063] S3, loading v2, the compact VRF is full (Slot0 and Slot3 are both occupied), triggering FIFO replacement:

[0064] Replace Slot0(v5) and write it back to memory.

[0065] Load v2 into Slot0 and move the head pointer to Slot1.

[0066] S4. Update the compact VRF state. The new compact VRF content is:

[0067] Slot0:v2,

[0068] Slot1:v3,

[0069] Slot2:v7,

[0070] Slot3:v1.

[0071] S5. Enter the execution (EX) stage, read v1 (Slot3), v2 (Slot0), and v3 (Slot1) from the compact VRF, and execute the vmacc.vv instruction.

[0072] This method can be implemented on a computer hardware device, which includes a processor and a memory. Optionally, the device can also include a communication interface and a bus. The processor, communication interface, and memory can communicate with each other via the bus. The communication interface can be used for information transmission. The processor can call logic instructions in the memory to execute the dynamic register management method for a vector processor according to the above embodiment.

[0073] In addition, the logic instructions in the above-mentioned memory can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0074] Memory, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as the program instructions / modules corresponding to the methods in the embodiments of the present disclosure. The processor executes the program instructions / modules stored in the memory to perform functional applications and data processing, thereby implementing the dynamic register management method for a vector processor in the above-mentioned embodiments.

[0075] The memory may include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function; the data storage area may store data generated based on the use of the terminal device. Furthermore, the memory may include high-speed random access memory and non-volatile memory.

[0076] The method may also be solidified in a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned dynamic register management method for a vector processor.

[0077] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0078] The technical solution of the embodiments of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiments of the present disclosure. The aforementioned storage medium may be a non-transitory storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program code, or a transient storage medium.

[0079] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible variations. Unless explicitly required, separate components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terms used in this application are only used to describe the embodiments and are not used to limit the scope of protection. As used in the description in the text, unless the context clearly indicates otherwise, the singular forms of "a", "an" and "the" are intended to also include plural forms. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of one or more associated listings. In addition, when used in this application, the term "comprise" and its variations "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, an element defined by the statement "comprises a..." does not exclude the presence of other identical elements in the process, method or device that includes the element. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments can be referenced to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can be found in the description of the method part.

[0080] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. The technicians will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0081] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units can be merely a logical functional division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, the functional units in the embodiments of the present disclosure may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

Claims

1. A dynamic register management system for a vector processor, characterized in that: Includes instruction fetch unit, instruction decoding unit and execution unit; The instruction fetch unit is used to fetch vector operation instructions and send the vector operation instructions to the instruction decoding unit; The instruction decoding unit is connected to the instruction fetch unit, and is used to receive the vector operation instructions sent by the instruction fetch unit and decode the vector operation instructions, parse the vector operation to be executed and the input vector register and output vector register corresponding to the vector operation, and then determine whether the parsed input vector register and output vector register are both in the compact VRF. If so, the labels of the input vector register and output vector register are transferred to the compact VRF. If not, a signal is sent to the execution unit to make it read the value of the missing vector register and its label from the vector register dedicated memory space into the compact VRF. The vector register dedicated memory space is set in the memory subsystem and is used to store information of all vector registers. The execution unit is connected to the instruction decoding unit. A compact VRF is provided in the execution unit. The compact VRF stores the values of the most recently accessed vector registers and their labels. The number of vector registers stored is less than the total number of vector registers defined by the general RISC-V architecture. When executing a vector operation instruction, the execution unit reads the value of the input vector register from the compact VRF, and stores the output data in the output vector register after executing the vector operation.

2. The dynamic register management system for a vector processor according to claim 1, wherein: The instruction fetch unit includes an instruction cache, an instruction memory interface and a program counter. The instruction memory interface is connected between the external module and the instruction cache, and the program counter is connected to the instruction cache. When fetching a vector operation instruction, the vector operation instruction adjacent to the instruction pointed to by the current program counter is first stored in the instruction cache through the instruction memory interface, and then the vector operation instruction pointed to by the current program counter in the instruction cache is taken out and sent to the instruction decoding unit.

3. The dynamic register management system for a vector processor according to claim 1, wherein: The instruction decoding unit includes a vector operation decoding unit, a compact VRF label queue and a register dispersion control module. The vector operation decoding unit is connected to the instruction fetch unit and is used to receive vector operation instructions from the instruction fetch unit, parse the vector operation to be executed and send it to the execution unit, and parse the input vector register and output vector register corresponding to the vector operation and send them to the register dispersion control module. The compact VRF label queue stores the vector register labels in the current compact VRF. The register dispersion control module determines whether the input vector register and output vector register corresponding to the vector operation are both in the compact VRF according to the vector register labels in the compact VRF label queue. If so, the register dispersion control module transmits the labels of the input vector register and the output vector register to the compact VRF. If not, the register dispersion control module sends a signal to the execution unit to read the missing vector register value and its label from the vector register dedicated memory space into the compact VRF, and update the value of the compact VRF label queue at the same time.

4. The dynamic register management system for a vector processor according to claim 3, wherein: The execution unit also includes a vector access unit and a vector processing unit. The compact VRF is connected between the register distribution control module and the vector processing unit. The vector processing unit is also connected to the vector operation decoding unit. The vector access unit is connected to the register distribution control module and the vector register dedicated memory space. During the execution of the vector operation instruction, according to the instruction of the register distribution control module, if the input vector register and the output vector register are both in the compact VRF, the value of the input vector register is transferred to the vector processing unit for calculation, and the calculation result is output to the output vector register. If the input vector register and the output vector register are not both in the compact VRF, the missing vector register is read from the vector register dedicated memory space through the vector access unit and placed in the compact VRF. The vector processing unit reads the value of the input vector register in the compact VRF, and performs calculations according to the operation code parsed by the vector operation decoding unit, and stores the calculation results in the output vector register in the compact VRF.

5. The dynamic register management system for a vector processor according to claim 4, characterized in that: Compact VRF is organized as a circular FIFO queue. The head pointer of the circular FIFO queue always points to the register with the longest resident time in the compact VRF, and the tail pointer points to the next free vector register slot. When a missing vector register is read from the vector register dedicated memory space through the vector access unit, if the circular FIFO queue is not full, the read vector register is stored in the free vector register slot pointed to by the tail pointer, and the tail pointer is moved to the next register slot. If the circular FIFO queue is full, the register with the longest residence time pointed to by the head pointer is replaced with the read vector register, and the head pointer is moved to the next register slot position.

6. The dynamic register management system for a vector processor according to claim 1, wherein: It also includes an instruction fetch / decode buffer, and the instruction fetch unit and the instruction decode unit are connected through the instruction fetch / decode buffer.

7. The dynamic register management system for a vector processor according to claim 1, wherein: It also includes a decoding / execution buffer, and the instruction decoding unit and the execution unit are connected through the decoding / execution buffer.

8. The dynamic register management system for a vector processor according to claim 2, wherein: The instruction cache consists of ICACHE and instruction prefetch buffer.

9. A dynamic register management method for a vector processor, characterized in that: include: Step S01: fetch a vector operation instruction and decode it by a vector operation decoding unit to parse out the vector operation to be executed and the input vector register and output vector register corresponding to the vector operation; Step S02: Determine whether the parsed input vector register and output vector register are both in the compact VRF. If so, transfer the labels of the input vector register and output vector register to the compact VRF. The vector processing unit reads the value of the input vector register from the compact VRF, performs calculations, and stores the output data in the output vector register. Step S03: If both the input vector register and the output vector register are not in the compact VRF, the values and labels of the missing vector registers are read from the vector register dedicated memory space into the compact VRF. The execution unit reads the values of the input vector registers from the compact VRF, performs the vector operation, and stores the output data into the output vector register.

10. The dynamic register management method for a vector processor according to claim 9, characterized in that: When executing step S03, first determine whether the compact VRF is full. If it is full, read the missing vector operands from the vector register dedicated memory space to the slot pointed to by the head pointer, and then move the head pointer to the next register slot position; if it is not full, read the missing vector operands from the vector register dedicated memory space to the free slot pointed to by the tail pointer.

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