Multifunctional system-on-chip debugging device

Abstract

The invention discloses a multifunctional system-on-chip debugging device, and relates to the technical field of chip debugging, the multifunctional system-on-chip debugging device comprises a simulation debugging upper computer and a simulator, the simulation debugging upper computer is used for controlling the simulator to send a debugging signal and debugging and monitoring the real-time state of each module of a chip; the emulator is connected and communicated with the simulation debugging upper computer through a USB data line, and the signal output end of the emulator is connected and communicated with a target chip pin. When the simulation debugging system is used, any pin can be switched, the debugging flexibility is high, multiple communication formats are supported, the practical application limitation is few, the SPI communication format is selected, the communication speed is high, and the real-time performance is good; a single-wire communication format is selected, pin resources can be saved, the device achieves flexible adaptation with low cost and design, the debugging device can be switched to a normal working mode and can be adapted to SPI / I IC / UART and other functions through setting, and the chip function is improved with low overhead.

Description

Technical Field

[0001] The present invention relates to the technical field of chip debugging, and in particular to a multifunctional system-on-chip debugging device. Background Art

[0002] The chip real-time simulation debugging process mainly uses a single debugging communication format. The number of pins used and the debugging speed are limited by the single format, and the debugging function can only be used on specific pins. The present invention can solve the above problems. The communication format can be switched and can be used on any distributed pins.

[0003] Prior art 1: There is a patent application number CN115658412A filed by Shenzhen Siyuan Semiconductor Co., Ltd., which discloses a single-line debugging method, device, MCU chip, debugger and system. The single-line debugging method applied to the MCU chip includes step S100, obtaining a request instruction sent by the debugger through the first pin, and the encoding method of the request instruction is different from the encoding method of the normal working instruction; step S110, switching from the normal working mode to the single-line debugging mode in response to the request instruction; step S130, exchanging debugging data with the debugger through the first pin to perform single-line debugging operations; step S140, when receiving an exit debugging instruction sent by the debugger through the first pin, switching from the single-line debugging mode to the normal working mode in response to the exit debugging instruction. The present invention discloses a single-line debugging method that does not require reserving pins specifically for debugging, nor does it require the cooperation of other pins to enter single-line debugging mode, thereby concisely and effectively maximizing the use of the pin resources of the MCU chip. This solution uses the first pin to input a debugging command and then obtain debugging permission to perform chip debugging simulation, which can reduce the number of pins used and has a signal rate of less than or equal to 1000K.

[0004] Prior art 2: Existing patents such as the announcement number CN118132431A applied by Zhuhai Shengsheng Microelectronics Co., Ltd. disclose a debugging device and method capable of switching between single and double lines. The device includes a single-line debugging module, a dual-line debugging module, a debug bus two-to-one selector, a debugging core module, a system debugging bus, and a first OR gate. The single-line debugging module is used to convert the single-line clock-free serial signal transmitted by the first input and output pin into parallel data and read / write control signals and output them by the first bus. The dual-line debugging module is used to convert the clock and data signals transmitted by the first and second input and output pins into parallel data and read / write control signals and output them by the second bus. The output end of the single-line debugging module is connected to the debug bus two-to-one selector through the first bus, and the output end of the debug bus two-to-one selector is connected to the debugging core module. The debugging core module outputs through the system debugging bus. The present invention has a simple structure and is easy to implement. It can be flexibly switched according to actual needs, thereby improving the efficiency and flexibility of chip debugging.

[0005] Although the patent provides single- and dual-wire switching capabilities, practical applications may still face the limitations of a single communication format. As technology continues to evolve, different application scenarios may require different communication formats. If a chip only supports a limited number of communication formats, it may limit its application in a wider range of fields, thereby increasing additional costs for users, such as requiring additional converters or adapters to match different communication standards.

[0006] While this patent aims to improve debugging flexibility by designing a single-wire debug module and a dual-wire debug module, in practice, only one of these debug modules is often used. This means that the other debug module remains idle in most cases, which not only wastes hardware resources but also potentially increases the overall cost of the chip. Especially in cost-sensitive applications, this design can lead to unnecessary cost increases, impacting the product's market competitiveness. To address this issue, we propose a multifunctional system-on-chip debugging device. Summary of the Invention

[0007] The purpose of the present invention is to provide a debugging device and method that can realize multiple communication formats. The device supports three standard debugging modes of UART / IIC / SPI and can be switched freely. In non-debugging mode, the device can support four working modes, namely UART / IIC / SPI / signal collection and decoding. The device can effectively utilize the debugging module to convert it into a normal working module, with a high chip module utilization rate and reduced overall chip cost. In addition, the debugging function can be reused on any general pin of the target chip.

[0008] In order to achieve the above-mentioned purpose, the present invention specifically adopts the following technical solutions:

[0009] A multifunctional system-on-chip debugging device, comprising

[0010] The simulation debugging host computer is used to control the simulator to send debugging signals and debug and monitor the real-time status of each module of the chip;

[0011] The emulator is connected and communicated with the simulation debugging host computer via a USB data cable, and the emulator is connected and communicated with the target chip via a GPIO pin. The emulator inputs a single-line synchronization frame through an external single pin within 5ms after the chip is reset to start the debugging function of the device. After sending the synchronization frame command through the single line, the simulation pin is determined. After using the single pin to input the debug pin selection frame, the chip can select the debug command communication format according to the debug pin selection frame command. The communication format includes but is not limited to single-line debugging / UART / IIC / SPI format.

[0012] Furthermore, the simulator includes a high-speed signal processor for parsing and transmitting debugging instructions sent by the simulation debugging host computer to the target chip, and receiving debugging information fed back by the target chip and transmitting it back to the simulation debugging host computer.

[0013] Furthermore, the simulation debugging host computer includes but is not limited to keil software.

[0014] Furthermore, the target chip has an automatic calibration function, which can automatically detect and automatically calibrate communication parameters between target chips according to parameters sent by the simulator before debugging begins, thereby ensuring the accuracy and consistency of the debugging environment.

[0015] Furthermore, the simulator can test the chip function through a specific timing sequence, and can detect whether the target chip is normal during the debugging process.

[0016] The beneficial effects of the present invention are as follows:

[0017] The present invention can switch any pin when in use, not just the first pin, resulting in high debugging flexibility, more diverse communication formats, fewer practical application restrictions, and the option of an SPI communication format when high-speed communication is required. According to its own design, this debugging method can achieve a communication speed of tens of megabits per second. SPI is a full-duplex, synchronous communication bus with high communication speed and good real-time performance. A single-line communication format can also be selected, saving pins. This allows for more flexible adaptation at a lower cost and design level, and is innovative. Furthermore, the debugging device can be switched to a normal operating mode, enabling communication data transmission using UART / IIC / SPI, etc., according to different configurations. This significantly enhances chip functionality while adding minimal overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1It is a system structure diagram of the present invention;

[0019] Figure 2 It is a debugging flow chart of the present invention. DETAILED DESCRIPTION

[0020] To make the objectives, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0021] See also Figure 1-Figure 2 The present invention provides a multifunctional system-on-chip debugging device, comprising

[0022] The simulation debugging host computer is used to control the simulator to send debugging signals and debug and monitor the real-time status of each module of the chip;

[0023] The emulator is connected to the simulation debugging host computer for communication via a USB data cable, and the signal output end of the emulator is connected to the target chip pin for communication. The emulator inputs a single-line synchronization frame through an external single pin within 5ms after the chip is reset to start the debugging function of the device. After sending the synchronization frame command through the single line, the simulation pin is determined. After using the single pin to input the debug pin selection frame, the chip can select the debug command communication format according to the debug pin selection frame command. The communication format includes but is not limited to single-line debugging / UART / IIC / SPI format.

[0024] The working principle and usage process of the present invention: When using this device, it is first necessary to reset the chip. After the reset is completed, the device will automatically open a 5-millisecond time window. Within this short time window, the communication task with the chip must be completed. This process includes confirming whether it is necessary to enter the simulation mode of the chip, and when it is confirmed that the debugging function needs to be turned on, sending the synchronization frame and the debug pin selection frame through a single line. After selecting the corresponding debug pin, the next step is to execute a communication command unlocking operation on the chip. This is done to make it clear that the chip is ready to enter the debugging state. Once the unlocking is completed, the device can start the debugging process and enter the debugging state.

[0025] In the debugging state, the debugging format needs to be configured based on the specific requirements for data real-time performance. Users can choose any of the single-wire debugging, UART, IIC, or SPI formats, and then configure the pins accordingly to facilitate communication testing. This design effectively meets the specific needs of different customers.

[0026] The emulator sends test signals to the target chip via the chip debug bus, receives debug information from the target chip, and transmits it back to the emulator debugging host computer. The emulator debugging host computer parses and processes the received debug information and presents it to the user in an intuitive manner. The user can view key information such as the chip's debug status, register values, and memory contents in real time through the emulator debugging host computer interface.

[0027] If the target chip fails to confirm entry into debug mode within the 5-millisecond communication window, the module can, after the chip is operating normally, transform into an IIC, SPI, or UART communication module based on software configuration. This design not only reuses resources but also effectively improves chip performance. It also controls costs, making the device both innovative and highly practical.

[0028] When the present invention is used, any pin can be switched, not a specific first pin, with high debugging flexibility, more diverse communication formats, fewer practical application restrictions, and the highest selectable SPI communication format. According to its own design, the debugging method can reach a communication speed of tens of megabits, SPI full-duplex, synchronous communication bus, high communication speed and good real-time performance, and can also select a single-line communication format, saving pins, achieving more flexible adaptation at a lower cost and design, and possessing innovation. At the same time, the debugging device can be switched to a normal working mode, greatly enhancing the chip function with less added overhead.

[0029] In this embodiment, preferably, the simulator includes a high-speed signal processor for parsing and transmitting debugging instructions sent by the simulation debugging host computer to the target chip, and receiving debugging information fed back by the target chip and transmitting it back to the simulation debugging host computer.

[0030] In this embodiment, preferably, the simulator further includes a built-in storage unit for temporarily storing key data and instructions during the debugging process, thereby ensuring the continuity and stability of the debugging process. This multifunctional system-on-chip debugging device greatly improves the efficiency and accuracy of chip debugging through an innovative debugging method.

[0031] In this embodiment, preferably, the simulation debugging host computer includes but is not limited to keil software.

[0032] In this embodiment, preferably, the simulation debugging host computer also has an automatic calibration function, which can automatically detect and calibrate the communication parameters between the simulator and the target chip before debugging begins, thereby ensuring the accuracy and consistency of the debugging environment.

[0033] In this embodiment, preferably, the simulation debugging host computer also supports a remote debugging function. The debugging personnel can remotely access the simulation debugging host computer through a network connection to achieve remote debugging and monitoring of the chip, which greatly improves the flexibility and convenience of debugging.

[0034] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multifunctional system-on-chip debugging device, characterized by: include The emulator is connected to the target chip via GPIO. Within 5ms after chip reset, the target emulator inputs a single-line synchronization frame via a single external pin to activate the device's debugging function. After sending a synchronization frame command via the single line, the emulator determines the emulation pin. After using the single pin to input a debug pin selection frame, the chip can select a debug command communication format based on the debug pin selection frame command. The communication formats include but are not limited to single-line debugging, UART, IIC, or SPI formats. The emulator communicates with the emulation debugging host computer via a USB data cable to complete debugging and configuration of the target chip.

2. The multifunctional system-on-chip debugging device according to claim 1, wherein: The simulator includes a high-speed signal processor for parsing and transmitting debugging instructions sent by the simulation debugging host computer to the target chip, and receiving debugging information fed back by the target chip and transmitting it back to the simulation debugging host computer.

3. The multifunctional system-on-chip debugging device according to claim 1, wherein: The simulator and the target chip support multiple communication formats, which can be switched to a normal communication module after the debugging function is turned off, and can realize single-line communication / UART / IIC / SPI and other communication data transmission according to different configurations.

4. The multifunctional system-on-chip debugging device according to claim 1, wherein: The simulation debugging host computer includes but is not limited to the visual interface of keil software.

5. The multifunctional system-on-chip debugging device according to claim 1, wherein: The target chip can have an automatic calibration function according to the timing of the emulator sending commands, and can automatically detect and calibrate the communication parameters between the emulator and the target chip before debugging begins, ensuring the accuracy and consistency of the debugging environment.

6. The multifunctional system-on-chip debugging device according to claim 1, wherein: The simulation debugging host computer also supports the function of detecting the characteristics of the target chip, and can detect the chip function through a specific timing, and can detect whether the target chip is normal during the debugging process.

Images