circuit boards

Abstract

This application provides a circuit board, applicable to the field of circuit board technology. The circuit board may include: a universal substrate; multiple devices and a first management controller, disposed on the universal substrate; the first management controller interconnecting with a second management controller on a server motherboard via a motherboard bus using multiple communication protocols; and interconnecting with the multiple devices via substrate buses using multiple communication protocols, respectively. The number of multiple motherboard buses is less than the number of multiple substrate buses.

Description

Technical Field

[0001] The present application relates to the technical field of circuit boards, and in particular to a circuit board. Background Art

[0002] With the rapid development and widespread application of artificial intelligence (AI) technology, the complexity of AI (Artificial Intelligence) server architectures has increased. However, this complex architecture has limited the quality of interconnections between server motherboards and various components on general-purpose substrates. Summary of the Invention

[0003] In view of the above problems, the present application provides a circuit board.

[0004] According to the first aspect of the present application, a circuit board is provided, comprising a universal substrate; and a plurality of devices and a first management controller, which are arranged on the universal substrate; the first management controller is configured to be interconnected with a second management controller of a server motherboard via a motherboard bus of a plurality of communication protocols; and the substrate buses of a plurality of communication protocols are respectively interconnected with the plurality of devices; wherein the plurality of the motherboard buses is less than the plurality of the substrate buses.

[0005] According to an embodiment of the present application, when a first management controller is provided on a universal substrate, a small number of pins of a second management controller can be interconnected with the first management controller via a relatively small number of motherboard buses, and the first management controller can be directly interconnected with a variety of devices on the universal substrate via a relatively large number of multiple substrate buses based on a relatively large number of multiple communication protocols. In this way, while occupying only a small number of pins of the second management controller on the server motherboard, the second management controller can be interconnected with devices on the universal substrate using a smaller number of communication protocols. This at least partially avoids the need for the second management controller to be interconnected with devices on the universal substrate via a conversion circuit provided on the universal substrate for converting communication protocols, at least partially avoids the degradation of interconnection signal quality caused by the use of the conversion circuit, reduces the length of the interconnection line between the server motherboard and the universal substrate, and improves the quality of the interconnection between the server motherboard and the devices on the universal substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The above contents and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0007] Figure 1 A schematic diagram of a circuit board according to an embodiment of the present application is shown.

[0008] Figure 2 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0009] Figure 3 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0010] Figure 4 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0011] Figure 5 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0012] Figure 6 A schematic diagram of a circuit board according to another embodiment of the present application is shown. DETAILED DESCRIPTION

[0013] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present application. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present application. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present application.

[0014] The terms used herein are only for describing specific embodiments and are not intended to limit this application. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0015] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0016] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0017] AI servers face complex architectures, long management buses, and limited pin count for the Universal Baseboard (UBB) connector connecting to the host. The Open Accelerator Infrastructure-Universal Baseboard (OAI-UBB) management solution primarily relies on the host-side Baseboard Management Controller (BMC) and serializer (SERDES) interconnect. The OAI-UBB specification, based on eight Open Accelerator Modules (OAMs), defines the host interface, power supply, cooling, management interface, and inter-card interconnection topology for each of the eight OAM baseboards.

[0018] This management solution is difficult to implement in server board design. Furthermore, implementation requires significant debugging time to ensure signal integrity. Some solutions still rely on the server motherboard's baseboard management controller (BMC) for open acceleration module management, interconnect management, and thermal management. This requires pre-connecting the server motherboard's BMC to the backplane via various management buses. Furthermore, management signals such as the Inter-Integrated Circuit (I2C), Joint Test Action Group (JTAG), Universal Serial Bus (USB), and Universal Asynchronous Receiver-Transmitter (UART) signals on the universal baseboard must be obtained from the midplane. In this scenario, since these low-speed bus signals originate from the server motherboard's BMC and are transmitted through the printed circuit board (PCB) traces and cables of various boards to the universal baseboard, the cumulative signal loss is excessive, compromising signal integrity. Therefore, various devices such as repeaters and buffers must be placed along the signal transmission path to improve signal quality. However, in actual measurements, the waveform quality of signals such as integrated circuit bus signals and joint test working group signals remains difficult to guarantee.

[0019] Furthermore, the design of the high-density connector connecting the universal baseboard to the host is defined by standard universal baseboard specifications, such as the OAI-UBB 2.0 design specification. To reduce server development costs, the design of the high-density connector connecting the universal baseboard to the host is essentially consistent with the design requirements of the graphics processing unit (GPU) board in some architectures, allowing the same server to accommodate both GPUs. This presents a problem: the high-density connector lacks many pins for bus management. Necessary signals, such as Universal Serial Bus (USB), Joint Test Working Group (JTWG), and Universal Asynchronous Receiver / Transmitter (UART) signals, require conversion via specialized conversion circuitry on the universal baseboard before they can be used by components on the baseboard. In some solutions, servers typically include a baseboard management controller (BMC) on the host side of the server motherboard to manage the entire system. Furthermore, due to the limited number of BMC interfaces and the limited interconnection signals between boards, the host-side BMC struggles to fully monitor the specific status of each board or node. This can affect the BMC's monitoring and management coverage when there are many interconnected boards or the system is complex.

[0020] For AI servers using universal substrates, both in terms of mechanical and circuit architecture design, the image processing node on which the universal substrate resides is typically placed separately in a strategic location. This node is characterized by numerous and complex high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) devices, a harsh heat dissipation environment, and a high failure rate. In the management bus design of a typical baseboard management controller, this node is typically located at the very end of the bus, making signal quality tuning at this node the most difficult and posing challenges to the interconnection quality between the server motherboard and the universal substrate. In view of this, the present application provides a circuit board that can improve the interconnection quality between the server motherboard and the universal substrate.

[0021] Figure 1 A schematic diagram of a circuit board according to an embodiment of the present application is shown.

[0022] like Figure 1 As shown, the circuit board of this embodiment may include a universal substrate, and a first management controller and various devices arranged on the universal substrate.

[0023] The various devices provided on the universal substrate may include programmable devices, open acceleration modules, and substrate power supply units, among others. For example, the programmable device may be a complex programmable logic device (CPLD). The CPLD may be electrically connected to the open acceleration module to monitor the operating status of the open acceleration module, among other things. However, it should be understood that the embodiments of the present application are not limited to this. In some implementations, the CPLD may also perform other operations on the open acceleration module, such as burning firmware. The substrate power supply unit may be used to power various devices, such as the programmable device.

[0024] The first management controller can be electrically connected to the second management controller on the server motherboard via a motherboard bus using multiple communication protocols. For example, both the first management controller and the second management controller are baseboard management controllers. In this case, the first management controller can be interconnected with the second management controller on the server motherboard via a motherboard bus using multiple communication protocols, thereby synchronizing information between the first management controller and the second management controller on the server motherboard. For example, the motherboard bus using multiple communication protocols can include, but is not limited to, at least one of an integrated circuit bus and a universal serial bus.

[0025] The first management controller can also be electrically connected to various devices on the universal substrate via substrate buses of multiple communication protocols. In this case, the first management controller can be interconnected with the various devices via substrate buses of multiple communication protocols. For example, substrate buses of multiple communication protocols may include, but are not limited to, at least one of an integrated circuit bus, a joint test working group bus, a universal asynchronous receiver and transmitter bus, a management data clock bus (MDC), or a management data input / output bus (MDIO).

[0026] For example, a programmable device collects log data from multiple devices, such as temperature data, power-on status data, and operating status data of multiple devices, and sends the log data to a first management controller via an integrated circuit bus among multiple baseboard buses. The first management controller can then send the log data to a second management controller via a universal serial bus among multiple motherboard buses.

[0027] For another example, the second management controller can directly send the firmware data to the first management controller via various motherboard buses. The first management controller can write the firmware data into the memory of various devices, thereby completing the burning of the firmware data.

[0028] In the present application, multiple motherboard buses are less than multiple baseboard buses. For example, the number of communication protocols supported by multiple motherboard buses can be less than the number of communication protocols supported by multiple baseboard buses. For another example, the number of buses of multiple motherboard buses can be less than the number of buses of multiple baseboard buses.

[0029] Based on this, when the first management controller is set on a universal substrate, a small number of pins of the second management controller can be interconnected with the first management controller through a relatively small number of motherboard buses, and the first management controller can be directly interconnected with multiple devices on the universal substrate based on a relatively large number of multiple communication protocols through a relatively large number of multiple substrate buses.

[0030] In this way, the second management controller can be interconnected with devices of more communication protocols on the universal substrate through fewer communication protocols while occupying only fewer pins of the second management controller on the server motherboard, at least partially avoiding the second management controller from being interconnected with devices on the universal substrate through a conversion circuit for converting communication protocols provided on the universal substrate, at least partially avoiding the reduction in quality of the interconnection signal due to the use of the conversion circuit, reducing the length of the interconnection line between the server motherboard and the universal substrate, and improving the interconnection quality between the server motherboard and the devices on the universal substrate.

[0031] In one embodiment of the present application, a first management controller can receive a status indication signal from a second management controller via at least one of multiple motherboard buses (e.g., an integrated circuit bus). The status indication signal can indicate the status of the second management controller. Specifically, the status indication signal can indicate the power status of the host, etc. If the status indication signal indicates that the second management controller is in a target operating state, the operating states of the various components are controlled to match the target operating state of the second management controller. Specifically, if the status indication signal indicates that the power status of the host is powered off, the first management controller can control the baseboard power supply unit to operate at low power consumption, so that the operating states of the various components of the first management controller match the operating state of the second management controller, that is, the operating state of the host. The various components disposed on the universal baseboard may also include a fan for dissipating heat from the universal baseboard. For example, when the second management controller is in the target operating state, the fan can be turned off to prevent heat dissipation. However, it should be understood that this is merely an example and is not intended to limit the technical solutions of the present application.

[0032] On this basis, the first management controller can receive a status indication signal from the second management controller via the motherboard bus, and thus can control the working status of multiple devices to match the target working status of the second management controller based on the status indication signal, thereby achieving high-quality interconnection between the second management controller of the server motherboard and the devices of the universal substrate.

[0033] In one embodiment of the present application, the first management controller is installed on a universal baseboard in a vertical plug-in format. For example, using a standard design based on the OAI-UBB 2.0 specification, the first management controller can be integrated into a 1U management board, which can be installed on the universal baseboard in a vertical plug-in format. 1U refers to the unit height of a server. For example, the management board can be a small-sized 1U vertical plug-in management board equipped with the ASPEED AST2600 BMC circuit.

[0034] Since the universal baseboard has a large area and the three-dimensional space above the universal baseboard is relatively ample, the first management controller is not installed onboard. Instead, the first management controller is integrated on the 1U management board, thereby achieving decoupling of the first management controller from the universal baseboard. In this way, by setting the first management controller on the universal baseboard in a vertical plug-in manner, the longitudinal space above the universal baseboard can be utilized, so that a variety of first management controllers can be customized through the second management controller on the server motherboard. On this basis, a variety of 1U management boards can be replaced, that is, the first management controller can be replaced. Since there are many manufacturers and models of open acceleration modules, different first management controllers can be used to match different baseboard management and control functions for different open acceleration modules, making configuration switching more flexible, thereby achieving high-quality interconnection between the server motherboard and the universal baseboard.

[0035] In one embodiment of the present application, the multiple motherboard buses may include a first motherboard bus. The multiple substrate buses may include the first substrate bus. The first motherboard bus and the first substrate bus support different communication protocols. For example, the first motherboard bus may be the Universal Serial Bus (USB) described above. The first substrate bus may be a Joint Test Working Group (JTWG) bus. The first management controller is electrically connected to a first device among the multiple devices via the first substrate bus. For example, the first device may be a programmable device.

[0036] The first management controller may receive a first data signal from the second management controller via the first motherboard bus. For example, the first data signal may include first firmware data to be burned. The first firmware data to be burned may be firmware data to be burned into the first device. The communication protocol of the first data signal may be a communication protocol supported by the first motherboard bus, such as a Universal Serial Bus (USB) protocol.

[0037] Then, the first management controller can generate a target data signal based on the first data signal. For example, the first management controller can parse the first data signal to obtain the device identification and the first firmware data to be burned in the first data signal. The device identification can be the device identification of the first device, for example, it can be but not limited to at least one of the name identification or the address identification. Then, based on the device identification, a communication protocol that matches the device identification can be determined. For example, the first management controller can pre-deploy a mapping relationship between multiple device identifications and multiple communication protocols. In this way, based on the device identification, by querying the mapping relationship, a communication protocol that matches the device identification can be determined. Thereafter, the first management controller can use the pre-deployed firmware to generate a target data signal based on the device identification, the first firmware data to be burned, and the communication protocol. For example, a target data signal belonging to the communication protocol can be generated, including the device identification and the first firmware data to be burned. In this way, the communication protocol of the target data signal can be a communication protocol supported by the first substrate bus.

[0038] On this basis, the first management controller, based on the first data signal from the second management controller, directly provides a target data signal with a different communication protocol than the first data signal to the first device via the first substrate bus. This at least partially avoids the degradation of interconnect signal quality caused by the use of a conversion circuit, thereby improving the quality of the interconnection between the server motherboard and the various components on the universal substrate. Subsequently, the target data signal can be sent to the first device via the first substrate bus to write the first firmware data to be burned into the memory of the first device, completing the firmware burning operation for the first device. In this way, by directly sending the target data signal to the first device via the first substrate bus, the first firmware data to be burned can be directly burned into the first device, at least partially avoiding the degradation of the accuracy of the first firmware data to be burned due to the use of a conversion circuit, thereby improving the quality of the interconnection between the server motherboard and the various components on the universal substrate.

[0039] Figure 2 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0040] like Figure 2 As shown, the first device may include a programmable device. The first firmware data to be burned may include device firmware data of the programmable device. Based on this, the first management controller may send a target data signal including the device firmware data to the programmable device via the first substrate bus to write the device firmware data into the memory of the programmable device, thereby burning the device firmware data into the programmable device.

[0041] In addition, the first device may also include an open acceleration module electrically connected to the programmable device. The first firmware data to be burned may also include module firmware data of the open acceleration module. In this way, the first management controller may also send a target data signal including the module firmware data to the programmable device via the first substrate bus, so as to write the module firmware data into the memory of the open acceleration module via the programmable device, thereby burning the module firmware data into the open acceleration module connected to the programmable device.

[0042] On this basis, the first management controller arranged on the universal substrate directly sends the target data signal to the programmable device or the open acceleration module connected to the programmable device via the first substrate bus, so that the corresponding firmware data can be directly burned into the programmable device or the open acceleration module, at least partially avoiding the situation where the accuracy of the device firmware data or the module firmware data is reduced due to the use of the conversion circuit, thereby improving the interconnection quality between the server motherboard and the various devices on the universal substrate.

[0043] Figure 3 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0044] exist Figure 3 In the illustrated circuit board, BMC BD may refer to the first management controller described above. ExaMAXCONN may be an interface used by the first management controller to connect to the second management controller. SEC CPLD corresponds to the programmable device described above. GPIO0 may be an interface for electrically connecting the SEC CPLD to the BMC BD. JTAG_BMC_OAM may be an interconnection signal between the SEC CPLD and the BMC BD. JTAG_MUX[15:0] may be a multiplexer within the SEC CPLD. GPIO1 and GPIO2 may be interfaces used by the SEC CPLD to electrically connect to the open acceleration module. OAM[7:0]_L_JTAG may be an interconnection signal between JTAG_MUX[15:0] and GPIO1. OAM[7:0]_H_JTAG may be an interconnection signal between JTAG_MUX[15:0] and GPIO2.

[0045] The CPLD logic level can represent the logic layer architecture of the CPLD. BMC_JTAG_C and SOURCE_SEL can be the interconnect signals between GPIO0 and JTAG_MUX[15:0]. BMC_JTAG_C can be a data signal, and SOURCE_SEL can be a selection control signal used to control the multiplexer.

[0046] Continue to refer Figure 3The blocks OAM0_L_JTAG, OAM1_L_JTAG, OAM2_L_JTAG, OAM3_L_JTAG, OAM4_L_JTAG, OAM5_L_JTAG, OAM6_L_JTAG, OAM7_L_JTAG, OAM0_H_JTAG, OAM1_H_JTAG, OAM2_H_JTAG, OAM3_H_JTAG, OAM4_H_JTAG, OAM5_H_JTAG, OAM6_H_JTAG, and OAM7_H_JTAG may correspond to respective open acceleration modules. The OAM0_L_JTAG, OAM1_L_JTAG, OAM2_L_JTAG, OAM3_L_JTAG, OAM4_L_JTAG, OAM5_L_JTAG, OAM6_L_JTAG, OAM7_L_JTAG, OAM0_H_JTAG, OAM1_H_JTAG, OAM2_H_JTAG, OAM3_H_JTAG, OAM4_H_JTAG, OAM5_H_JTAG, OAM6_H_JTAG, and OAM7_H_JTAG on the lines represent the interconnection signals between the SEC CPLD and each open acceleration module. Figure 3 Components not described above are also shown, such as interfaces. Specifically, the interface may include Figure 3 The XDP CONN interface and JTAG Header interface are shown in FIG. Figure 3 Also shown are the interconnection signals XDP_PRSNT_N, DEBUG_OAM_TEST[14:0], and XDP_JTAG between XDP CONN and CPLD, as well as the interconnection signal SEC_CPLD_JTAG between JTAGHeader and SEC CPLD, and the interconnection signal PRI_CPLD_JTAG between JTAG Header and PRI CPLD. PRI CPLD can also be a programmable device. P3V3_STBY can be a power supply signal. Vref can be a reference signal. It should be understood that Figure 3 The contents shown in the figure are for illustration only and are not intended to limit the solutions of the present application. For ease of understanding, the Universal Serial Bus is referred to as USB and the Joint Test Association Group is referred to as JTAG.

[0047] On this basis, in some solutions, the second management controller of the server motherboard can only provide one set of JTAG links to the outside world, which is generally used to burn the firmware of the CPLD on the server motherboard. For artificial intelligence servers configured with a universal baseboard, the JTAG link needs to be extended across the board to the universal baseboard. This method is risky and difficult for debugging actual signals. If the USB signal is converted to JTAG signal, a conversion circuit needs to be set between the second management controller of the server motherboard and the universal baseboard, such as Figure 3 The USB2.0 Hub GL850G (Reserver), USB2.0 to JTAG CH347 and the resistors in the dotted box are shown in Figure 3 However, the conversion circuit will affect the accuracy of the signal. Therefore, in this application, the structure related to the conversion circuit described above is removed, that is, Figure 3 The structure marked with CN in the figure directly connects the ExaMAX CONN to the BMC BD, and also directly connects the BMC BD to the SEC CPLD. This allows the BMC BD to directly output a clean, high-quality JTAG signal to the SEC CPLD. The signal is then expanded and directed to the eight open acceleration modules, allowing firmware to be refreshed. This improves the accuracy of firmware flashing to the open acceleration modules by the server motherboard's second management controller, thereby improving the interconnection quality between the server motherboard's second management controller and the open acceleration modules.

[0048] In another embodiment of the present application, the multiple substrate buses further include a fourth substrate bus. The fourth substrate bus, the first substrate bus, and the first mainboard bus support different data protocols. For example, the fourth substrate bus may support a universal asynchronous receiver / transmitter protocol. The programmable device may collect log data of an open acceleration module connected to the programmable device and send a log data signal including the log data to the first management controller via the fourth substrate bus.

[0049] The first management controller can receive a log data signal from the programmable device via the fourth baseboard bus. For example, the log data signal can be a universal asynchronous receiver / transmitter protocol signal including log data. Then, the first management controller can generate a target log signal based on the log data signal. For example, the first management controller can parse the log data signal to obtain log data. Afterwards, the log data can be processed using pre-deployed firmware according to the communication protocol of the first mainboard bus to generate a target log signal belonging to the communication protocol and including log data. Thereafter, the first management controller can send the target log signal to the second management controller via the first mainboard bus.

[0050] On this basis, the first management controller set on the universal substrate directly receives the log data signal from the programmable device, so that the target log signal can be sent to the second management controller via the first motherboard bus based on the log data signal, at least partially avoiding the situation where the accuracy of the log data is reduced due to the use of the conversion circuit, thereby improving the interconnection quality between the server motherboard and the devices on the universal substrate.

[0051] Figure 4 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0052] like Figure 4 As shown, similar to the above, for ease of understanding, the universal serial bus is referred to as USB and the universal asynchronous receiver and transmitter is referred to as UART. BMC BD can refer to the first management controller described above. ExaMAX CONN can be the interface used by the first management controller to connect to the second management controller. SEC CPLD corresponds to the programmable device described above. UART MUX can be a serial multiplexer. USB MUX can be a USB multiplexer. UART to USB CP2108 can be a conversion circuit between the CPLD and the UART, used to perform protocol conversion between the USB protocol of the CPLD and the UART protocol of the UART MUX. Micro USB can be a USB interface. OAM0, OAM1, OAM2, OAM3, OAM4, OAM5, OAM6, and OAM7 can be open acceleration modules.

[0053] In some solutions, the out-of-band method is mainly used, using the UART interface on the board. The operator connects the UART signal from the UART interface with a debug cable in order to analyze the problem, but this operation requires powering off the board, removing the board, connecting the cable, and then powering on again. In this way, the original problem will be lost and the problem can only be reproduced, which reduces the debugging efficiency, and this hardware debugging method also has the risk of collision. For the in-band method, a conversion circuit is required to realize the conversion from USB signal to UART signal. As described above, this method will reduce the signal quality. Therefore, in the solution of this application, reference Figure 4, the SEC CPLD sends a UART signal containing the log data of OAM0, OAM1, OAM2, OAM3, OAM4, OAM5, OAM6, and OAM7 to the BMC BD. This UART signal can be used as a dedicated debug signal for the open acceleration module. In this way, the present application combines the advantages of in-band and out-of-band log capture. It can capture the log data of the open acceleration module, such as register logs, at any time when a problem occurs without accessing debugging tools to reproduce it. It also at least partially avoids the problems of poor signal quality and prone to errors in log capture caused by using in-band methods to collect log data.

[0054] In addition, the programmable device can also detect the electrical connection status between the open acceleration module and the programmable device. In this way, when it is detected that the open acceleration module is electrically connected to the programmable device, the programmable device can collect the initial log data of the open acceleration module. Since the production organizations of different open acceleration modules may be different, the data formats of the log data collected from different types of open acceleration modules may be different. Among them, different types of open acceleration modules can refer to open acceleration modules with at least one different model, platform and specification. In this way, the data format of the initial log data may not match the data format of the first management controller.

[0055] Based on this, the programmable device can determine the type information of the open acceleration module based on the initial log data. For example, the programmable device can parse the initial log data to determine the data format of the initial log data. Then, the programmable device can determine the type information that matches the initial log data based on the data format of the log data using a pre-built mapping relationship. Among them, the mapping relationship can be built based on multiple predetermined data formats and multiple predetermined type information of the open acceleration module. Then, the editable device can determine the target firmware that matches the type information from the multiple pre-deployed firmwares based on the type information. Among them, the multiple firmwares can be used to process log data of multiple data formats into log data of the data format belonging to the first management controller. Specifically, the target firmware is the predetermined firmware used to process the data format of the above-mentioned initial log data into the data format of the first management controller. Based on this, after determining the target firmware, the editable device can use the target firmware to process the initial log data to obtain the log data of the open acceleration module. The log data matches the data format of the first management controller.

[0056] In this way, the programmable device can collect the initial log data of the open acceleration module and, based on the initial log data, determine the type of the open acceleration module. It can then determine target firmware matching the type of the open acceleration module from among the various pre-deployed firmwares. This target firmware can then be used to process the initial log data of the open acceleration module into a data format that can be sent to the first management controller. This improves the interconnection quality between various types of open acceleration modules and the first management controller, and further improves the interconnection quality between various types of open acceleration modules and the second management controller.

[0057] In some solutions, the baseboard management controller's firmware can be burned out-of-band via a port physical layer (PHY) circuit and a media access control (MAC) network link. In the present application, a second management controller can directly send controller firmware data to the first management controller via multiple motherboard buses, writing the controller firmware data into the first management controller's memory, thereby completing the burning of the controller firmware data. Specifically, the multiple motherboard buses can include a second motherboard bus. For example, the second motherboard bus can be an integrated circuit bus. Upon receiving the controller firmware data via the second motherboard bus, the first management controller can update the original firmware data deployed by the first management controller with the controller firmware data. In this case, there is no need to use a separate network link to burn the firmware to the first management controller. Furthermore, the second management controller can directly update the firmware of the first management controller, at least partially avoiding the loss of firmware data accuracy caused by the use of a conversion circuit, thereby improving the interconnection quality between the server motherboard and components on the universal baseboard.

[0058] Furthermore, the multiple substrate buses may include a second substrate bus. The second substrate bus supports the same communication protocol as the second substrate bus. For example, the second substrate bus may also be an integrated circuit bus. The first management controller may be electrically connected to a second device among the multiple devices via the second substrate bus. For example, the second device may be a retimer or the like.

[0059] The first management controller can receive a second data signal via the second motherboard bus. The second data signal includes the second firmware data to be burned. Then, without generating signals of other communication protocols, the first management controller can directly send the second data signal to the second device via the second substrate bus to write the second firmware data to be burned into the memory of the second device, thereby completing the firmware burning of the second device. In this way, the first management controller set on the universal substrate directly sends the second data signal to the second device via the first substrate bus to directly burn the corresponding firmware data to the second device, at least partially avoiding the situation where the accuracy of the firmware data is reduced due to the use of the conversion circuit, thereby improving the interconnection quality between the server motherboard and the devices on the universal substrate.

[0060] Figure 5 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0061] like Figure 5 As shown, the second device may include a retimer that supports the high-speed serial computer expansion bus standard protocol, that is, Figure 5 For ease of description, the PCIE retimer in the present invention is referred to as the PCIE retimer below. The second firmware data to be burned may include the first retimer firmware data. For example, the first retimer firmware data may be firmware data to be deployed on the PCIE retimer. The first management controller may send a second data signal to the PCIE retimer via the second baseboard bus to write the first retimer firmware data into the memory of the PCIE retimer, thereby completing the firmware burning operation for the PCIE retimer.

[0062] In some implementations, due to limited IC bus resources on the server motherboard's second management controller (e.g., a limited number of pins capable of delivering IC bus signals, but this is not a limitation), only one IC bus is routed to the universal baseboard. The firmware for each of the eight PCIE retimers is then flashed sequentially through the switching unit. Due to the low speed of the IC bus and the large size of the PCIE retimer firmware, this serial flashing method significantly reduces flashing efficiency.

[0063] However, when the first management controller provided on the universal substrate of the present application is used, since the integrated circuit bus of the first management controller on the universal substrate only needs to manage the devices related to the universal substrate, the resources of the integrated circuit bus can no longer be limited, and multiple integrated circuit buses can be used to connect to multiple PCIE retimers respectively, for example, 2 integrated circuit buses or 4 integrated circuit buses, etc. In this way, the firmware of multiple PCIE retimers can be burned at the same time, thereby greatly improving the burning rate. In addition, the first management controller provided on the universal substrate directly sends the second data signal to the PCIE retimer via the first substrate bus, so that the corresponding firmware data can be directly burned to the retimer, and the firmware of multiple PCIE retimers can be burned at the same time, so that the firmware of the PCIE retimer is burned in time, thereby realizing the corresponding functions in time, thereby improving the interconnection quality between the server motherboard and the devices on the universal substrate.

[0064] For another example, the multiple baseboard buses may also include a third baseboard bus. For example, the third baseboard bus may support a management data clock bus protocol or a management data input / output bus protocol. The multiple devices may also include a physical layer retimer (PHY retimer). The first management controller may be electrically connected to the PHY retimer via the third baseboard bus. The first management controller may send a third data signal including second retimer firmware data to the PHY retimer via the third baseboard bus to burn the second retimer firmware data into the PHY retimer. The second retimer firmware data may be firmware data that needs to be deployed on the PHY retimer. In this way, the first management controller, disposed on the universal baseboard, may directly send the third data signal to the PHY retimer via the first baseboard bus, thereby directly burning the corresponding firmware data into the PHY retimer. This at least partially avoids the reduction in firmware data accuracy caused by the use of a conversion circuit, thereby improving the interconnection quality between the server motherboard and the devices on the universal baseboard.

[0065] On this basis, the management and firmware refresh of the physical layer retimer rely on a third baseboard bus, the MDC / MDIO bus. However, in the Data Center Ready Security Control Module 2.0 (DC-SCM 2.0) specification, the two MDC / MDIO bus groups of the baseboard management controller share pins. Due to the limited application scenarios of this bus and the extremely limited resources for integrated circuit buses in architectural design, the baseboard management controller of a typical server motherboard rarely has spare integrated circuit bus resources to connect a separate bus across the board to the physical layer timer. Furthermore, the MDC / MDIO bus has a higher speed than the integrated circuit bus, making signal quality more difficult to ensure. In this application, however, since the first management controller is provided on a universal baseboard, the second and third baseboard buses are electrically connected to different pins of the first management controller. In other words, by providing the first management controller on a universal baseboard, this application exempts the first management controller from the aforementioned restrictions, allowing the second and third baseboard buses to be connected to different pins. This at least partially prevents the signals of the second and third baseboard buses from interfering with each other, thereby improving the interconnect quality between the server motherboard and the components on the universal baseboard. Thus, ample integrated circuit bus resources and shorter trace distances allow the third substrate bus to be easily connected to the physical layer retimer.

[0066] In addition, the physical layer retimer also relies on the direct management of the first management controller. For example, the first management controller set on the universal substrate is directly electrically connected to the physical layer retimer through the third substrate bus, which can facilitate the first management controller to load the firmware of the physical layer retimer through the third substrate bus configuration during the initialization phase.

[0067] Thus, the firmware refresh process for PCIE retimers, physical layer timers, programmable devices, and open acceleration modules that require firmware refresh is described above. Compared to the online burning method with pin number and wiring distance restrictions in some solutions, this application sets a first management controller on the universal substrate, so that the firmware of multiple devices can be updated separately through multiple substrate buses, breaking through the limitations of the online burning solution and improving the quality of the interconnection between the server motherboard and the devices on the universal substrate.

[0068] In addition, the open acceleration module can be electrically connected to the programmable device through a connector (e.g., a slot, etc.) provided on the universal substrate. When the first management controller detects through the programmable device that the open acceleration module is electrically disconnected from the connector, that is, the open acceleration module is electrically disconnected from the universal substrate, the first management controller can manage the function to check whether there are any abnormalities in other devices on the universal substrate. For example, the various devices may also include a substrate power supply unit and a clock unit. The substrate power supply unit and the clock unit are connected to the connector to respectively provide power signals and clock signals to the open acceleration module via different pins in the connector. The first management controller can determine whether the electrical connection status between the open acceleration module and the connector cannot be properly detected due to problems with the substrate power supply unit and the clock unit.

[0069] Specifically, the first management controller can obtain at least one of a power signal and a clock signal from the programmable device when it detects that the connector is electrically disconnected from the open acceleration module. The first management controller can then analyze the at least one signal to obtain an analysis result. For example, it can determine whether the voltage of the power signal is a preset value, whether the frequency of the clock signal is a preset frequency, or whether the power signal or clock signal should be received, etc. Taking the voltage of the power signal as an example, if the voltage value of the power signal is a preset value, it is determined that there is no abnormality in the power signal of the substrate power supply unit; otherwise, it is determined that there is an abnormality in the power signal provided by the substrate power supply unit to the connector. If the analysis result indicates that there is an abnormality in at least one signal, abnormal prompt information about the at least one signal is generated and sent to the second management controller. The abnormal prompt information can be used to indicate the presence of an abnormal signal, thereby facilitating maintenance of components on the universal substrate.

[0070] Based on this, when the first management controller detects that the connector is electrically disconnected from the open acceleration module, the power signal and clock signal provided by the power supply unit and the clock unit to the open acceleration module respectively can be obtained from the programmable device and analyzed. Therefore, when at least one of the power signal and the clock signal is abnormal, an abnormal prompt information is sent to the second management controller, so that at least one of the power supply unit or the clock unit of the open acceleration module can be adjusted in time, thereby improving the interconnection quality between the open acceleration module and the first management controller, and further improving the interconnection quality between the open acceleration module and the second management controller.

[0071] Figure 6 A schematic diagram of a circuit board according to another embodiment of the present application is shown.

[0072] exist Figure 6In the illustrated embodiment, the second management controller of the server motherboard is connected to the first management controller on the universal baseboard via a first and second motherboard buses. Hereinafter, the first motherboard bus is referred to as the USB bus, and the second motherboard bus is referred to as the I2C bus. For ease of understanding, the baseboard bus is also described in this manner. For example, the first management controller on the universal baseboard is electrically connected to a PCIE retimer, a PRI CPLD, a SEC CPLD, a temperature sensor, and other sensors via multiple I2C buses, to a baseboard power supply unit via an ADC (analog-to-digital conversion) bus, to an OAM CPLD via a JTAG bus, to an open acceleration module via a UART bus, and to a liquid leakage detection unit via an ALERT bus. The sensors and physical layer retimers within the same dashed box can be coupled. For example, the physical layer retimer can improve signal transmission integrity based on the data collected by the sensors. The sensors, OAM CPLD, and open acceleration module within the same dashed box can be electrically connected. For detailed functions, please refer to the previous description and are not elaborated here. Among them, SEC CPLD, PRI CPLD and OAM CPLD are programmable devices. It should be noted that Figure 6 The components shown in the figure are for illustration only and are not intended to limit the present application. For example, they are not intended to limit the number of components in the present application.

[0073] Furthermore, various devices may also include a liquid cooling unit ( Figure 6 (not shown). The baseboard power supply unit can supply power to various devices, for example, it can supply power to high-power devices, such as switching units among the various devices.

[0074] The liquid leakage detection unit can detect liquid leakage in the liquid cooling unit and, upon detecting a liquid cooling unit leak, send an abnormality indication signal to the first management controller. The abnormality indication signal can be used to indicate a liquid cooling unit leak. The first management controller can then control the substrate power supply unit to stop operating upon receiving the abnormality indication signal from the liquid leakage detection unit, thereby promptly shutting off power to high-power devices and performing other operations when a leak occurs. In this way, the first management controller, disposed on the universal substrate, controls the substrate power supply unit to stop operating upon receiving the abnormality indication signal from the liquid leakage detection unit. This can at least partially prevent short circuits in traces on the universal substrate caused by liquid cooling unit leaks, at least partially prevent component failures on the universal substrate, and at least partially prevent the quality of interconnections between the server motherboard and components on the universal substrate from being affected by component failures on the universal substrate, thereby improving the quality of interconnections between the server motherboard and components on the universal substrate.

[0075] In one embodiment, the universal substrate may be multi-layered. Each layer of the multi-layer universal substrate is provided with a substrate power supply unit, a liquid cooling unit, and a liquid leakage detection unit. The substrate power supply unit of each layer of the substrate is used to power the components provided on that layer of the substrate.

[0076] The first management controller can be electrically connected to the substrate power supply unit, liquid cooling unit and leakage detection unit of any layer of the substrate, and can control the power supply unit of any substrate layer to stop working when receiving a leakage indication signal from the leakage detection unit of any substrate layer, so as to at least partially avoid the connection quality between the server mainboard and the components on the universal substrate being affected due to the failure of the components of the universal substrate, thereby improving the connection quality between the server mainboard and the components on the universal substrate.

[0077] Based on the above, during the product design phase, due to the large number of boards and complex structures in artificial intelligence servers, the link lengths of many bus signals can easily exceed the limit, necessitating the introduction of devices such as buffers in the line, or even requiring changes to the solution due to failure to meet line length requirements. This application sets a first management controller on the universal baseboard, allowing PCIE-related devices to switch to accessing the bus through the first management controller when accessing, at least partially avoiding the limitations of the structure and other solutions caused by line loss. During the project development phase, server system testing will encounter many image processor-related problems. The technical solution of this application enables R&D personnel to quickly locate problems in both bare board and complete machine environments, at least partially avoiding delays in analysis time caused by repeated reproduction. In addition, the solution of this application is highly maintainable. After mass production, if it is found that the firmware of the device on the universal baseboard needs to be upgraded, or if a fault occurs and the status of the device on the board needs to be remotely captured, it can be directly connected to the first management controller through the second management controller to perform direct operations, which can reduce the risk of collision caused by manual disassembly and assembly. Based on this, the quality of the device interconnection between the server motherboard and the universal baseboard is improved.

[0078] Those skilled in the art will appreciate that the features described in the various embodiments of this application may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in this application. In particular, the features described in the various embodiments of this application may be combined and / or coupled in various ways without departing from the spirit and teachings of this application. All such combinations and / or couplings fall within the scope of this application.

[0079] The embodiments of the present application have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present application. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present application, those skilled in the art may make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present application.

Claims

1. A circuit board, characterized in that: include: Universal substrate; as well as A plurality of devices and a first management controller are provided on the universal substrate; The first management controller is configured to interconnect with a second management controller of a server motherboard via a motherboard bus of multiple communication protocols; and to interconnect with the multiple devices via baseboard buses of multiple communication protocols; wherein the multiple motherboard buses are less than the multiple baseboard buses; the multiple baseboard buses further include a fourth baseboard bus; and the multiple devices include programmable devices; The programmable device is used for: When it is detected that the open acceleration module is electrically connected to the programmable device, collecting initial log data of the open acceleration module; a data format of the initial log data does not match a data format of the first management controller; Determining type information of the open acceleration module based on the initial log data; Based on the type information, determining a target firmware that matches the type information from a plurality of pre-deployed firmwares; Processing the initial log data using the target firmware to obtain log data of the open acceleration module; wherein the log data matches a data format of the first management controller; The first management controller is further configured to: receive a log data signal from the programmable device via the fourth substrate bus; the log data signal includes the log data of the open acceleration module.

2. The circuit board according to claim 1, wherein: The plurality of motherboard buses include a first motherboard bus; the plurality of substrate buses include a first substrate bus; the first motherboard bus and the first substrate bus support different communication protocols; The first management controller is connected to a first device among the plurality of devices via the first substrate bus; The fourth substrate bus, the first substrate bus and the first mainboard bus support different data protocols; The first management controller is further configured to: receiving a first data signal from the second management controller via the first motherboard bus; generating a target data signal according to the first data signal; wherein the first substrate bus supports a communication protocol of the target data signal; The target data signal is sent to the first device via the first substrate bus.

3. The circuit board according to claim 2, wherein: The target data signal includes first firmware data to be burned; The first management controller is further configured to send the target data signal via the first substrate bus to burn the first firmware data to the first device.

4. The circuit board according to claim 3, wherein: The first device includes a programmable device; the first firmware data to be burned includes device firmware data of the programmable device or module firmware data of an open acceleration module; The first management controller is further configured to: sending a target data signal including the device firmware data to the programmable device via the first substrate bus, so as to burn the device firmware data into the programmable device; or A target data signal including the module firmware data is sent to the programmable device via the first substrate bus, so as to burn the module firmware data into an open acceleration module connected to the programmable device via the programmable device.

5. The circuit board according to claim 4, characterized in that The first management controller is further configured to: generating a target log signal according to the log data signal; wherein the first mainboard bus supports a communication protocol of the target log signal; The target log signal is sent to the second management controller via the first mainboard bus.

6. The circuit board according to claim 1, wherein: The open acceleration module is electrically connected to the programmable device via a connector on the universal substrate; The multiple devices further include a substrate power supply unit and a clock unit; the substrate power supply unit and the clock unit are connected to the connector to respectively provide a power signal and a clock signal to the open acceleration module via different pins in the connector; The first management controller is further configured to: acquiring at least one of the power supply signal and the clock signal from the programmable device when detecting that the connector is electrically disconnected from the open acceleration module; Analyzing the at least one signal to obtain an analysis result; In a case where the analysis result indicates that an abnormal condition exists in the at least one signal, abnormal prompt information about the at least one signal is generated and sent to the second management controller.

7. The circuit board according to any one of claims 1 to 6, wherein: The plurality of motherboard buses further include a second motherboard bus; the plurality of substrate buses include a second substrate bus; the second motherboard bus and the second substrate bus support the same communication protocol; the first management controller is electrically connected to a second device among the plurality of devices via the second substrate bus; The first management controller is further configured to: receiving a second data signal via the second mainboard bus; the second data signal includes second firmware data to be burned; The second data signal is sent to the second device via the second substrate bus to burn the second firmware data to the second device.

8. The circuit board according to claim 7, wherein: The second device includes a retimer supporting a high-speed serial computer expansion bus standard protocol; the second firmware data to be burned includes the first retimer firmware data; The first management controller is further configured to send the second data signal to the retimer via the second baseboard bus, so as to burn the first retimer firmware data into the retimer.

9. The circuit board according to claim 8, wherein: The plurality of substrate buses further include a third substrate bus; the plurality of devices further include a physical layer retimer; the first management controller is connected to the physical layer retimer via the third substrate bus; The first management controller is further configured to send a third data signal including second retimer firmware data to the physical layer retimer via the third baseboard bus, so as to burn the second retimer firmware data into the physical layer retimer.

10. The circuit board according to claim 9, wherein: The second baseboard bus and the third baseboard bus are connected to different pins of the first management controller.

11. The circuit board according to claim 7, wherein: The first management controller is further configured to update original firmware data originally deployed by the first management controller to the controller firmware data when the controller firmware data is received via the second motherboard bus.

12. The circuit board according to any one of claims 1 to 6, characterized in that: The multiple devices include a substrate power supply unit, a liquid cooling unit and a liquid leakage detection unit; the substrate power supply unit is used to supply power to the multiple devices; The liquid leakage detection unit is used to: detecting a liquid leakage condition of the liquid cooling unit; When a liquid leak is detected in the liquid cooling unit, an abnormality indication signal is sent; The first management controller is further configured to control the substrate power supply unit to stop working when receiving an abnormality indication signal from the liquid leakage detection unit.

13. The circuit board according to any one of claims 1 to 6, characterized in that: The first management controller is further configured to: receiving a status indication signal from the second management controller via at least one of the plurality of motherboard buses; In a case where the state indication signal indicates that the second management controller is in a target working state, the working states of the multiple devices are controlled to match the target working state of the second management controller.

14. The circuit board according to any one of claims 1 to 6, characterized in that: The first management controller is arranged on the universal substrate in a vertical plug-in manner.

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