Pixel driving circuit, display panel and display device

Abstract

The embodiment of the invention relates to a pixel driving circuit, a display panel and a display device. The circuit comprises a time schedule controller, a scanning driving module, a data line, a first switch module, a second switch module and a pixel capacitor, the time sequence controller responds to the target turn-off moment when the current moment reaches the target turn-off moment in the state that the first switch module is turned on and sends a switch signal to the scanning driving module, and the scanning driving module drives the first switch module to be turned off and drives the second switch module to be turned on, so that the control end of the first switch module and the preset level end are turned on. According to the embodiment of the invention, at the turn-off moment, the control end of the first switch module is immediately connected to the preset level and is quickly turned off, the driving voltage in each scanning period is not influenced by parasitic capacitance and parasitic resistance of a panel, the display problems of color cast, edge sawteeth and the like caused by pixel electrical fault-tolerant charging in a high-refresh-rate scene are solved, and the display effect is improved. And the voltage of the pixel capacitor does not need to be increased, so that the power consumption of the panel is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to a pixel driving circuit, a display panel, and a display device. Background Art

[0002] As LCD panel technology matures, panels are gradually moving towards larger sizes, higher resolutions, and higher refresh rates. High-refresh-rate displays, in particular, can refresh more frames per second, reducing image smearing and tearing, making dynamic images smoother and more coherent. This is particularly evident in applications such as gaming, video playback, and graphic design. However, as the refresh rate increases, the effective charging time of each pixel in the LCD panel is greatly shortened. This shortened charging time can lead to problems such as color cast, blurred edges, insufficient brightness, and incorrect charging, resulting in poor image quality.

[0003] In order to replenish the pixel capacitor with sufficient power in a short period of time, the current method is to increase the pixel voltage (such as Line OD technology), that is, to charge the pixel capacitor with a higher voltage within the same time. However, this method also requires sufficient time to charge the pixel capacitor. Especially in some high-refresh products with dual-gate architecture, the pixel capacitor cannot be fully charged within the limited charging time. Moreover, increasing the pixel voltage will increase the power consumption and temperature of the product. Summary of the Invention

[0004] In view of this, in order to solve some or all of the above technical problems, the embodiments of the present application provide a pixel driving circuit, a display panel and a display device.

[0005] In a first aspect, an embodiment of the present application provides a pixel driving circuit, which includes: a timing controller, a scan driving module, a data line, a first switch module, a second switch module, and a pixel capacitor; the timing controller is connected to the scan driving module; the input end of the first switch module is connected to the data line, the output end of the first switch module is connected to the pixel capacitor, and the control end of the first switch module is connected to the scan driving module; the input end of the second switch module is connected to the preset level end, the output end of the second switch module is connected to the control end of the first switch module, and the control end of the second switch module is connected to the scan driving module; at the target shutdown moment, the first switch module is controlled to be turned off, and the second switch module is controlled to be turned on.

[0006] In one possible embodiment, the control end of the first switch module is connected to the first scan line, and the first scan line is connected to the first scan signal output end of the scan driving module; the control end of the second switch module is connected to the second scan line, and the second scan line is connected to the second scan signal output end of the scan driving module, wherein the second scan signal output end is separated from the first scan signal output end by a preset number of scan signal output ends; at the target shutdown moment, the voltage levels on the first scan line and the second scan line are inverted.

[0007] In a possible implementation manner, the input end of the second switch module is connected to the low level end.

[0008] In a possible implementation, the control end of the first switch module and the control end of the second switch module are both connected to the first scan line, and the first scan line is connected to the first scan signal output end of the scan driving module.

[0009] In one possible embodiment, the preset level end is a low level end; the second switch module includes a first switch tube, a control end of the first switch tube is connected to the first scan line, an input end of the first switch tube is connected to the low level end, and an output end of the first switch tube is connected to the first scan line; at the target shutdown time, the first switch tube is controlled to be turned on, and the first switch module is controlled to be turned off.

[0010] In one possible embodiment, the second switch module includes a second switch tube and a third switch tube, the control end of the second switch tube is connected to the first scan line, the input end of the second switch tube is connected to the first preset level end, the output end of the second switch tube is connected to the control end of the third switch tube, the input end of the third switch tube is connected to the second preset level end, and the output end of the second switch is connected to the first scan line; at the target shutdown time, the second switch tube and the third switch tube are controlled to be turned on, and the first switch module is controlled to be turned off.

[0011] In a possible implementation manner, the first preset level end is a high level end, and the second preset level end is a low level end.

[0012] In a possible implementation, an absolute value of a turn-on threshold voltage of the second switch module is smaller than an absolute value of a turn-on threshold voltage of the first switch module.

[0013] In the second aspect, an embodiment of the present application provides a display panel, which includes: a timing controller, a scan driving module, a data driving module, a first preset number of scan lines, a second preset number of data lines, and a pixel charging control module array; the timing controller is connected to the scan driving module and the data driving module, the first preset number of scan lines is connected to the scan driving module, and the second preset number of data lines is connected to the data driving module; each pixel charging control module in the pixel charging control module array includes a first switch module, a second switch module and a pixel capacitor; the first switch module, the second switch module and the pixel capacitor included in each pixel charging control module, together with the timing controller and the scan driving module, constitute the above-mentioned pixel driving circuit.

[0014] In a third aspect, an embodiment of the present application provides a display device, comprising: a display panel, a panel frame, a power module and a data receiving module as described above; the display panel is installed on the panel frame, the power supply end of the display panel is connected to the power module, and the signal receiving end of the display panel is connected to the data receiving module.

[0015] The pixel driving circuit, display panel, and display device provided by the embodiments of the present application are configured with a first switch module, a second switch module, and a pixel capacitor for each pixel. The input terminal of the first switch module is connected to the scan driver module, the output terminal is connected to the pixel capacitor, and the control terminal is connected to the scan driver module. The input terminal of the second switch module is connected to the preset level terminal, the output terminal is connected to the control terminal of the first switch module, and the control terminal of the second switch module is connected to the scan driver module. When the first switch module is in the on state, the timing controller sends a switching signal to the scan driver module in response to the current time reaching the target off time. The scan driver module drives the first switch module to turn off and drives the second switch module to turn on, so that the control terminal of the first switch module is connected to the preset level terminal. The embodiments of the present application achieve that at the off time, the control terminal of the first switch module is immediately connected to the preset level and quickly turned off. The driving voltage in each scanning cycle is not affected by the parasitic capacitance and parasitic resistance of the panel. The pixel capacitor has sufficient time to charge, so there is no need to increase the anti-mischarge time in a scanning cycle. This solves the display problems such as color shift and edge jaggedness caused by mischarge of the pixel capacitor in high refresh rate scenarios, and does not need to increase the voltage of the pixel capacitor, which helps to reduce the power consumption of the panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0019] Figure 1 is a structural diagram of an existing pixel driving circuit;

[0020] Figure 2 It is the timing diagram of the ideal scan drive signal and data signal;

[0021] Figure 3 The timing diagram of the scan drive signal and data signal with delay phenomenon;

[0022] Figure 4 A schematic structural diagram of a pixel driving circuit provided in an embodiment of the present application;

[0023] Figure 5 A schematic structural diagram of another pixel driving circuit provided in an embodiment of the present application;

[0024] Figure 6 A timing diagram of scan drive signals and data signals according to an embodiment of the present application;

[0025] Figure 7 A schematic structural diagram of another pixel driving circuit provided in an embodiment of the present application;

[0026] Figure 8 A schematic structural diagram of another pixel driving circuit provided in an embodiment of the present application;

[0027] Figure 9 A schematic structural diagram of another pixel driving circuit provided in an embodiment of the present application;

[0028] Figure 10 A schematic structural diagram of another pixel driving circuit provided in an embodiment of the present application;

[0029] Figure 11 A schematic structural diagram of a display panel provided in an embodiment of the present application;

[0030] Figure 12 A schematic structural diagram of a display device provided in an embodiment of the present application.

[0031] Reference numerals:

[0032] 400-pixel driving circuit; 401-timing controller; 402-scanning driving module; 403-data line; 404-first switching module; 405-second switching module; 4051-first switching tube; 4052-second switching tube; 4053-third switching tube; 406-pixel capacitor; 1100-display panel; 1101-data driving module; 1102-pixel charging control module; 1200-display device; 1201-panel frame; 1202-power module; 1203-data receiving module. DETAILED DESCRIPTION

[0033] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It is apparent that the described embodiments are only a portion of the embodiments of the present application, rather than all of the embodiments. It should be noted that, unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions, and numerical values described in these embodiments do not limit the scope of the present application.

[0034] Those skilled in the art will understand that the terms "first" and "second" in the embodiments of the present application are only used to distinguish between different steps, devices, modules and other objects, and neither represent any specific technical meaning nor indicate the logical order between them.

[0035] It should also be understood that in this embodiment, “a plurality of” may refer to two or more than two, and “at least one” may refer to one, two or more than two.

[0036] It should also be understood that any component, data or structure mentioned in the embodiments of the present application can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0037] In addition, the term "and / or" in this application is simply a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this application generally indicates that the related objects are in an "or" relationship.

[0038] It should also be understood that the description of each embodiment in this application focuses on the differences between the embodiments, and the same or similar aspects can be referenced with each other. For the sake of brevity, they will not be described one by one.

[0039] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0040] Technologies, circuits, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the above-mentioned technologies, circuits, and devices should be considered part of the specification.

[0041] It should be noted that like reference numerals and letters refer to like items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0042] It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of this application can be combined with each other. To facilitate understanding of the embodiments of this application, the application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0043] Figure 1 The figure shows the pixel equivalent circuit diagram of a conventional TFT-LCD (Thin film transistor liquid crystal display). Figure 2 The following diagram shows the ideal voltage waveforms for the display panel's gate and data lines. Taking row n as an example, when Gn is high, it precharges the pixel capacitors Cst and Clc. When data line Dn arrives, Gn is fully open and begins charging the pixel capacitors. The charging time is the time between the current moment and the moment Gn turns off.

[0044] However, in actual panels, the scan lines and data lines have parasitic resistance R and parasitic capacitance C, which will cause a delay (RC delay) effect. Figure 3 As shown in the figure, after the Gate and Data signals go through the RC delay, the rising and falling edges of the signals will become tilted, that is, the rising and falling speeds will slow down. The slower falling speed of the Gn signal will cause the TFT to turn off more slowly, and the data of the n+1 row will be charged to the nth row, which will cause incorrect charging. In order to prevent incorrect charging, it is necessary to increase the anti-incorrect charging time. Figure 3 As shown in the figure, t1 is the effective charging time of the nth row of data, t2 is the error-proof charging time of the nth row of data, and t1+t2 equals the setup time of one row of data (1H). Therefore, in high refresh rate scenarios, the shorter the charging time, the more likely it is to cause problems such as color shift and jagged edges.

[0045] Figure 4This is a structural schematic diagram of a pixel driving circuit 400 provided in an embodiment of the present application. The circuit is generally used in a display panel, and specifically includes: a timing controller 401, a scan driving module 402, a data line 403, a first switch module 404, a second switch module 405, and a pixel capacitor 406.

[0046] The timing controller 401 is connected to the scan driver module 402. The timing controller 401 can be a component with logic processing capabilities, such as a SOC (System on Chip). The timing controller 401 can send a switching signal to the scan driver module 402 according to a preset scan timing. The scan driver module 402 drives the first switch module 404 or the second switch module 405 to turn on or off by outputting a level signal that matches the first switch module 404 and the second switch module 405. The first switch module 404, the second switch module 405, and the pixel capacitor 406 can correspond to a pixel unit in the nth row of the display panel. The scan driver module 402 can be connected to the first switch module 404 via a scan line Gn.

[0047] In this embodiment, the input end of the first switch module 404 is connected to the data line 403 , the output end of the first switch module 404 is connected to the pixel capacitor 406 , and the control end of the first switch module 404 is connected to the scan driving module 402 .

[0048] The first switch module 404 may include at least one switching element (e.g., one or more TFTs). The control terminal of the first switch module 404 receives an input control signal, which drives the first switch module 404 to be turned on or off. For example, if the first switch module 404 includes a TFT switch tube, its control terminal is the gate, the input terminal is the drain, and the output terminal is the source. During the on-state period, the first switch module 404 pre-charges the pixel capacitor 406 through the input terminal and the output terminal. When the voltage corresponding to the currently input data is generated on the data line 403, the pixel capacitor 406 reaches the voltage corresponding to the data, and this voltage drives the liquid crystal molecules to deflect, displaying the corresponding color.

[0049] In this embodiment, the input end of the second switch module 405 is connected to the preset level end (V), the output end of the second switch module 405 is connected to the control end of the first switch module 404 , and the control end of the second switch module 405 is connected to the scan driving module 402 .

[0050] The preset level terminal is used to provide a level, such as a low level (VGL), to turn off the first switch module 404. The second switch module 405 may include at least one switching element (e.g., one or more TFTs). The control terminal of the second switch module 405 receives an input control signal, which drives the second switch module 405 to be turned on or off. For example, if the second switch module 405 includes a TFT switch tube, its control terminal is the gate, the input terminal is the drain, and the output terminal is the source. When the second switch module 405 is turned on, the second switch module 405 transmits the preset level to the control terminal of the first switch module 404 to turn off the first switch module 404.

[0051] In this embodiment, the timing controller 401 is used to: when the first switch module 404 is turned on, in response to the current moment reaching the target turn-off moment, send a switching signal to the scan drive module 402, and the scan drive module 402 drives the first switch module 404 to be turned off, and drives the second switch module 405 to be turned on, so that the control end of the first switch module 404 is connected to the preset level end.

[0052] The target turn-off moment is the end moment of the scan cycle of the current row of pixels (row n). At the target turn-off moment, the timing controller 401 sends a switch signal corresponding to the row of pixels to the scan driver module 402. The scan driver module 402 outputs a scan drive signal (e.g., a low-level signal) to the first switch module 404 based on the switch signal. At the same time, the scan driver module 402 also outputs a drive signal (e.g., a high-level signal) to the second switch module 405 based on the switch signal. The second switch module 405 is turned on and transmits a preset level (e.g., a low level) to the control end of the first switch module 404, thereby quickly causing the control end of the first switch module 404 to reach the preset level, eliminating the drive signal edge delay caused by parasitic capacitance and parasitic resistance.

[0053] The pixel driving circuit provided in the embodiment of the present application is configured with a first switch module 404, a second switch module 405, and a pixel capacitor 406 for each pixel. The input end of the first switch module 404 is connected to the scan driving module 402, the output end is connected to the pixel capacitor 406, and the control end is connected to the scan driving module 402. The input end of the second switch module 405 is connected to the preset level end, the output end is connected to the control end of the first switch module 404, and the control end of the second switch module 405 is connected to the scan driving module 402. When the first switch module 404 is turned on, the timing controller 401 sends a switching signal to the scan driving module 402 in response to the current time reaching the target turn-off time. The scan driving module 402 drives the first switch module 404 to turn off and drives the second switch module 405 to turn on, so that the control end of the first switch module 404 is turned on and the preset level end is turned on. The embodiment of the present application realizes that at the moment of shutdown, the control end of the first switch module 404 is immediately connected to the preset level and quickly cuts off. The driving voltage in each scanning cycle is not affected by the parasitic capacitance and parasitic resistance of the panel. The pixel capacitor 406 has enough time to charge, so there is no need to increase the anti-mischarging time in a scanning cycle. This solves the display problems such as color deviation and edge jaggedness caused by mischarging of the pixel capacitor 406 in high refresh rate scenarios, and there is no need to increase the voltage of the pixel capacitor 406, which helps to reduce the power consumption of the panel.

[0054] In some optional implementations of this embodiment, such as Figure 5 As shown, the control end of the first switch module 404 is connected to the first scan line Gn, and the first scan line Gn is connected to the first scan signal output end of the scan driving module 402. That is, the first scan signal output end outputs the scan driving signal to the pixel units in the nth row.

[0055] The control end of the second switch module 405 is connected to the second scan line, and the second scan line is connected to the second scan signal output end of the scan driving module 402 .

[0056] The second scanning signal output terminal is spaced apart from the first scanning signal output terminal by a preset number of scanning signal output terminals. Assuming the preset number is N, the second scanning line is represented as Gn+N. As an example, Figure 6 , which shows a waveform diagram of the scan driving signal output on each scan line after applying the circuit provided by this embodiment. Figure 6 The preset number corresponding to the embodiment shown is 4, that is, the second scan line is Gn+4, and its rising edge corresponds to the falling edge of Gn, that is, Gn+4 outputs the scan driving signal while driving the second scan driving module 402 to turn on.

[0057] The timing controller 401 is also used to: when the first switch module 404 is in the on state, in response to the current moment reaching the target off time, send a switch signal to the scan drive module 402, and the scan drive module 402 outputs a cut-off signal to the first scan signal output end to cut off the first switch module 404, and outputs a conduction signal to the second scan signal output end to turn on the second switch module 405.

[0058] like Figure 6 As shown, when the scan driver module 402 outputs a cutoff signal to the first scan signal output terminal, the first scan line Gn changes from a high level to a low level. Simultaneously, the scan driver module 402 outputs a turn-on signal to the second scan signal output terminal, causing the second scan line Gn+4 to change from a low level to a high level. This means that the voltage levels on the second scan line and the first scan line are opposite, driving the second switch module 405 to turn on. The second switch module 405 then transmits a preset voltage level to the first scan line Gn, quickly turning off the first switch module 404.

[0059] In this embodiment, the two different scan signal output terminals of the scan driver module 402 are connected to the control terminals of the first switch module 404 and the second switch module 405, respectively. When the first switch module 404 is turned off, the second scan line controls the second switch module 405 to be turned on, thereby allowing the first scan line to quickly reach a preset level. This can reduce the influence of parasitic capacitance and parasitic resistance on the level jump speed on the first scan line, and avoid mischarging caused by level jump delay.

[0060] In some optional implementations of this embodiment, such as Figure 7 As shown, the input end of the second switch module 405 is connected to the low level end (VGL).

[0061] The timing controller 401 is also used to: when the first switch module 404 is in the on state, in response to the current moment reaching the target turn-off moment, send a switch signal to the scan drive module 402, and the scan drive module 402 outputs a low-level signal to the first scan signal output end to turn off the first switch module 404; and outputs a high-level signal to the second scan signal output end to turn on the second switch module 405.

[0062] That is, at the target turn-off moment, the first scan line Gn jumps from a high level to a low level, and the first switch module 404 is turned off; the second scan line jumps from a low level to a high level, and the second switch module 405 is turned on, and at the same time transmits the low level to the first scan line Gn, so that the first switch module 404 accelerates the turn-off speed. Figure 7 As shown, the first switch module 404 and the second switch module 405 are both N-type TFT switch tubes.

[0063] This embodiment realizes setting the first switch module 404 and the second switch module 405 as the same type of switch tubes, using the same voltage level to drive the two switch tubes to be turned on or off. It only needs to connect the scan drive signal from other rows to achieve the effect of accelerating the signal jump speed on the first scan line, which helps to reduce the difficulty of circuit design and manufacturing.

[0064] In some optional implementations of this embodiment, such as Figure 8 As shown, the control end of the first switch module 404 and the control end of the second switch module 405 are both connected to the first scan line Gn, and the first scan line Gn is connected to the first scan signal output end of the scan driving module 402 .

[0065] That is, the first scan line Gn outputs the same scan drive signal to the first switch module 404 and the second switch module 405, which drives the first switch module 404 off and the second switch module 405 on. The second switch module 405 transmits the voltage at the preset voltage level to the first scan line Gn, causing the first scan line Gn to quickly reach the preset voltage level, thereby driving the first switch module 404 to quickly turn off. Because the first switch module 404 and the second switch module 405 switch to different states under the same scan drive signal, the first switch module 404 and the second switch module 405 are of different types. For example, the first switch module 404 may include an N-type TFT switch tube, and the second switch module 405 may include a P-type TFT switch tube.

[0066] This embodiment outputs the same scan drive signal to the first switch module 404 and the second switch module 405 via the same scan line, enabling rapid termination of the first switch module 404. This eliminates the need to provide the second switch module 405 with a separate drive signal from another scan line, thereby simplifying the circuit structure and improving circuit design and manufacturing efficiency. Furthermore, the control of the second switch module in this embodiment is independent of the timing of other scan lines and does not depend on the timing of other scan lines, thus making this circuit more flexible and scalable.

[0067] In some optional implementations of this embodiment, such as Figure 9 As shown, the second switch module 405 includes a first switch tube 4051, the control end of the first switch tube 4051 is connected to the first scan line Gn, the input end of the first switch tube 4051 is connected to the low level end, and the output end of the first switch tube 4051 is connected to the first scan line Gn.

[0068] The timing controller 401 is also used to: when the first switch module 404 is in the on state, in response to the current moment reaching the target turn-off moment, send a switch signal to the scan drive module 402, and the scan drive module 402 outputs a low level to the first scan line Gn, and drives the first switch tube 4051 to be turned on, so that the control end of the first switch module 404 is connected to the low level end, so that the first switch module 404 is turned off.

[0069] That is, the second switch module 405 of this embodiment consists of a single switch transistor, which is turned on when controlled by a low level. Specifically, the first switch transistor 4051 may be a P-type TFT switch transistor. At the target turn-off time, the first scan line Gn switches to a low level, and the first switch module 404 is turned off when driven by a low level. Therefore, the first switch module 404 may be an N-type TFT switch transistor. Simultaneously, the first switch transistor 4051 is turned on when driven by a low level, transmitting the low-level signal VGL to the first scan line Gn, causing the first scan line Gn to quickly switch to a low level, thereby quickly turning off the first switch module 404.

[0070] It should be noted that to ensure that the first switch 4051 can be turned on when the first scan line Gn switches to a low level, the low level initially switched to by the first scan line Gn must be lower than the level at the VGL terminal. In other words, the voltage difference Vgs between the gate and source of the first switch 4051 must be lower than 0, so that the first switch 4051 can be effectively turned on.

[0071] In this embodiment, the function of the second switch module 405 is realized by a first switch tube 4051 , so that the circuit structure can be made simpler, and the efficiency of circuit design and manufacturing of the display panel can be further improved.

[0072] In some optional implementations of this embodiment, such as Figure 10 As shown, Figure 9 In a different embodiment, the second switch module 405 includes a second switch tube 4052 and a third switch tube 4053. The second switch tube 4052 and the third switch tube 4053 are of different types, for example, Figure 10 The second switch tube 4052 shown is a P-type TFT switch tube, and the third switch tube 4053 is an N-type TFT switch tube.

[0073] The control end of the second switch tube 4052 is connected to the first scan line Gn, the input end of the second switch tube 4052 is connected to the first preset level end, the output end of the second switch tube 4052 is connected to the control end of the third switch tube 4053, the input end of the third switch tube 4053 is connected to the second preset level end, and the output end of the second switch is connected to the first scan line Gn.

[0074] The first preset level terminal and the second preset level terminal can be connected to different levels, for example, Figure 10 The first preset level shown is connected to a high level (VGH), and the second preset level is connected to a low level (VGL).

[0075] The timing controller 401 is further configured to: when the first switch module 404 is in the on state, in response to the current moment reaching the target off moment, send a switch signal to the scan drive module 402, and the scan drive module 402 outputs a scan drive signal to the first scan line Gn, and drives the second switch tube 4052 and the third switch tube 4053 to be turned on, so that the control end of the first switch module 404 is turned on to the second preset level end, and the first switch module 404 is turned off.

[0076] That is, at the target turn-off time, the scan drive signal output by the first scan line Gn drives the first switch module 404 to turn off. Simultaneously, the scan drive signal drives the second switch transistor 4052 to turn on. The second switch transistor 4052 transmits the first preset voltage level to the input terminal of the third switch transistor 4053, and the third switch transistor 4053 transmits the second preset voltage level to the first scan line Gn. The voltage level on the first scan line Gn quickly reaches the second preset voltage level, thereby quickly turning off the first switch module 404.

[0077] In this embodiment, by configuring two different types of switch tubes to form the second switch module 405, it is possible to ensure that both the second switch tube 4052 and the third switch tube 4053 can stably switch between switch states without considering the voltage difference between the voltage on the first scan line Gn and the second preset voltage at the target turn-off time, thereby improving the stability of the circuit operation. Figure 10 As shown, if the first preset level is a high level VGH, connected to the source of the second switch tube 4052, and the second preset level is a low level VGL, connected to the source of the third switch tube 4053, then when the second switch tube 4052 is turned on, the voltage difference Vgs between the gate and the source of the third switch tube 4053 can be guaranteed to be greater than the turn-on threshold voltage of the switch tube, and this Vgs is not affected by the voltage difference between VGL and Gn. Compared with the above Figure 9 In the embodiment shown, the switch state is more stable.

[0078] In some optional implementations of this embodiment, the first preset level end is a high level end, and the second preset level end is a low level end.

[0079] The timing controller 401 is also used to: when the first switch module 404 is turned on, in response to the current moment reaching the target turn-off moment, send a switch signal to the scan driver module 402, and the scan driver module 402 outputs a low-level signal to the first scan line Gn, and drives the second switch tube 4052 and the third switch tube 4053 to be turned on, so that the control end of the first switch module 404 is turned on to the low-level end, so that the first switch module 404 is turned off.

[0080] That is, at the target turn-off moment, the first scan line Gn switches from a high level to a low level, and the first switch module 404 is turned off under the low level drive (for example, the first switch module 404 is Figure 9 At the same time, the second switch tube 4052 is turned on under low level driving (for example, the second switch tube 4052 is Figure 9 The P-type TFT switch tube shown in FIG) transmits the high-level signal to the third switch tube 4053, and the third switch tube 4053 is turned on under the high-level drive (for example, the third switch tube 4053 is Figure 9 The N-type TFT switch tube shown in FIG2 transmits a low-level signal to the first scan line Gn, so that the first scan line Gn is quickly switched to a low level, thereby quickly turning off the first switch.

[0081] In this embodiment, by connecting the second switch tube 4052 and the third switch tube 4053 to a high level and a low level respectively, when the first scan line is switched to a low level, the second switch tube 4052 and the third switch tube 4053 can be quickly actuated to ensure a stable output of a low-level signal to the first scan line, thereby improving the stability of the circuit operation.

[0082] In some optional implementations of this embodiment, the absolute value of the turn-on threshold voltage of the second switch module 405 is smaller than the absolute value of the turn-on threshold voltage of the first switch module 404 .

[0083] That is, when the level on the scan line jumps, due to the effect of RC delay, the level change on the scan line slows down, and the second switch module 405 can switch to the on or off state more quickly, thereby causing the first switch module 404 to switch state as soon as possible, thereby improving the speed of the scan line level switching and further reducing the risk of incorrect charging.

[0084] Figure 11 A schematic diagram of the structure of a display panel 1100 provided in an embodiment of the present application is shown in FIG. Figure 11As shown, the display panel specifically includes: a timing controller 401, a scan driving module 402, a data driving module 1101, a first preset number of scan lines (including G1 to GN), a second preset number of data lines 403 (including D1 to DM), and a pixel charging control module array 1102 (including C11 to CNM);

[0085] The timing controller 401 is connected to the scan driving module 402 and the data driving module. A first preset number of scan lines are connected to the scan driving module 402 , and a second preset number of data lines 403 are connected to the data driving module.

[0086] Each pixel charging control module in the pixel charging control module array 1102 includes a first switch module 404 , a second switch module 405 and a pixel capacitor 406 .

[0087] Each pixel charging control module includes a first switch module 404 , a second switch module 405 and a pixel capacitor 406 , which together with the timing controller 401 and the scan driving module 402 constitute the pixel driving circuit described in the above embodiments.

[0088] That is, the first switch module 404, the second switch module 405, and the pixel capacitor 406 in each pixel charging control module are connected according to the connection method of the above-mentioned pixel driving circuit. For a pixel unit in a certain column of a row, the corresponding pixel charging control module, including the first switch module 404, the second switch module 405, and the pixel capacitor 406, operates according to the operation method described in the above embodiment to drive the corresponding pixel unit to display the corresponding color.

[0089] The display panel provided by the embodiment of the present application uses the above-mentioned pixel driving circuit in the panel, so that at the turn-off moment of each row of scanning lines, the control end of the first switch module is immediately connected to the preset level and quickly cuts off. The driving voltage in each scanning cycle is not affected by the parasitic capacitance and parasitic resistance of the panel. The pixel capacitor has enough time to charge, so there is no need to increase the anti-mischarging time in a scanning cycle. This solves the display problems such as color deviation and edge jaggedness caused by mischarging of the pixel capacitor in high refresh rate scenarios, and there is no need to increase the voltage of the pixel capacitor, which helps to reduce the power consumption of the panel.

[0090] Figure 12 A schematic diagram of the structure of a display device 1200 provided in an embodiment of the present application is shown in FIG. Figure 12 As shown, the display device includes:

[0091] Display panel 1100, panel frame 1201, power module 1202 and data receiving module 1203;

[0092] The display panel 1100 may be Figure 11The display panel 1100 is shown. The display panel 1100 is mounted on a panel frame 1201.

[0093] The power supply end of the display panel 1100 is connected to the power module 1202 , and the signal receiving end of the display panel 1100 is connected to the data receiving module 1203 .

[0094] The power module 1202 can provide the display panel 1100 with the power required for operation. The data receiving module 1203 can receive input data, and the display panel 1100 drives corresponding pixels to display corresponding colors according to the received data.

[0095] In addition, the display device Figure 12 In addition to the parts shown, it may also include a memory for storing data and programs, a processor for running application programs, a data transmission bus, various data interfaces (such as a network interface, a user interface), etc.

[0096] The display device provided in the embodiment of the present application, by applying the above-mentioned display panel, realizes that at the turn-off moment of each row of scanning lines, the control end of the first switch module is immediately connected to the preset level and quickly cuts off. The driving voltage in each scanning cycle is not affected by the parasitic capacitance and parasitic resistance of the panel. The pixel capacitor has enough time to charge, so there is no need to increase the anti-mischarging time in a scanning cycle. This solves the display problems such as color deviation and edge jaggedness caused by mischarging of pixel capacitors in high refresh rate scenarios, and there is no need to increase the voltage of the pixel capacitor, which helps to reduce the power consumption of the panel.

[0097] Professionals should also be further aware that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different circuits to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0098] The steps of the circuits or algorithms described in conjunction with the embodiments disclosed herein may be implemented using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0099] It should be understood that the terms used herein are for the purpose of describing specific example embodiments only and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "comprise", "include", "contain" and "have" are inclusive and therefore specify the presence of stated features, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The steps, processes, and operations described herein are not to be construed as necessarily requiring them to be performed in the specific order described or illustrated, unless the order of execution is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0100] The foregoing is merely a list of specific embodiments of the present application, intended to enable those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the broadest scope consistent with the principles and novel features of the present application.

Claims

1. A pixel driving circuit, characterized in that: The circuit includes: a timing controller, a scan driving module, a data line, a first switch module, a second switch module, and a pixel capacitor; The timing controller is connected to the scan driving module; The input end of the first switch module is connected to the data line, the output end of the first switch module is connected to the pixel capacitor, and the control end of the first switch module is connected to the scan driving module; The input end of the second switch module is connected to the preset level end, the output end of the second switch module is connected to the control end of the first switch module, and the control end of the second switch module is connected to the scan driving module; At the target turn-off time, the first switch module is controlled to be turned off, and the second switch module is controlled to be turned on.

2. The circuit according to claim 1, characterized in that The control end of the first switch module is connected to the first scan line, and the first scan line is connected to the first scan signal output end of the scan driving module; The control end of the second switch module is connected to the second scan line, and the second scan line is connected to the second scan signal output end of the scan driving module, wherein the second scan signal output end is separated from the first scan signal output end by a preset number of scan signal output ends; At the target turn-off moment, the voltage levels on the first scan line and the second scan line are inverted.

3. The circuit according to claim 2, characterized in that The input end of the second switch module is connected to the low level end.

4. The circuit according to claim 1, wherein: The control end of the first switch module and the control end of the second switch module are both connected to the first scan line, and the first scan line is connected to the first scan signal output end of the scan driving module.

5. The circuit according to claim 4, characterized in that The preset level end is a low level end; The second switch module includes a first switch tube, a control end of the first switch tube is connected to the first scan line, an input end of the first switch tube is connected to the low level end, and an output end of the first switch tube is connected to the first scan line; At the target turn-off time, the first switch tube is controlled to be turned on, and the first switch module is controlled to be turned off.

6. The circuit according to claim 4, characterized in that The second switch module includes a second switch tube and a third switch tube, wherein the control end of the second switch tube is connected to the first scan line, the input end of the second switch tube is connected to the first preset level end, the output end of the second switch tube is connected to the control end of the third switch tube, the input end of the third switch tube is connected to the second preset level end, and the output end of the second switch tube is connected to the first scan line; At the target turn-off time, the second switch tube and the third switch tube are controlled to be turned on, and the first switch module is controlled to be turned off.

7. The circuit according to claim 6, characterized in that The first preset level end is a high level end, and the second preset level end is a low level end.

8. The circuit according to any one of claims 1 to 7, characterized in that: An absolute value of a turn-on threshold voltage of the second switch module is smaller than an absolute value of a turn-on threshold voltage of the first switch module.

9. A display panel, characterized in that: include: A timing controller, a scan driver module, a data driver module, a first preset number of scan lines, a second preset number of data lines, and a pixel charging control module array; The timing controller is connected to the scan driving module and the data driving module, the first preset number of scan lines is connected to the scan driving module, and the second preset number of data lines is connected to the data driving module; Each pixel charging control module in the pixel charging control module array includes a first switch module, a second switch module and a pixel capacitor; The first switch module, the second switch module and the pixel capacitor included in each pixel charging control module, together with the timing controller and the scan driving module, constitute the pixel driving circuit according to any one of claims 1 to 8.

10. A display device, characterized in that: include: The display panel, panel frame, power module and data receiving module as claimed in claim 9; The display panel is mounted on the panel frame, a power supply end of the display panel is connected to the power module, and a signal receiving end of the display panel is connected to the data receiving module.

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