Power supply circuit, semiconductor device, and electronic device

Abstract

Embodiments of the present disclosure may provide a memory device including a semiconductor package on which a memory and a power circuit are disposed. A power supply circuit included in the semiconductor package may control supply of an internal driving voltage based on whether or not an external driving voltage is supplied, and may improve supply efficiency of a voltage for driving the semiconductor package by adjusting the supply of the internal driving voltage according to an operation state of a memory.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0019394, filed on February 8, 2024, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure generally relate to a power supply circuit, a semiconductor device, and an electronic device. Background Art

[0004] A storage device may include at least one memory for storing data. The storage device may include a controller for controlling the operation of the memory (i.e., a memory controller). The controller may control the operation of writing data to the memory and the operation of reading data written to the memory.

[0005] The memory and controller included in the storage device may be provided as a single semiconductor package. Alternatively, the memory and controller may be provided in separate semiconductor packages.

[0006] Therefore, the types of memory devices may vary, and a power supply for supplying voltage to drive the memory and the controller may be required in each type of memory device. Therefore, a method for effectively controlling the power supply according to the various types of memory devices is required. Summary of the Invention

[0007] Various embodiments of the present disclosure are directed to providing measures capable of efficiently setting and managing a power supply that supplies a driving voltage to at least one of a memory and a controller included in a storage device.

[0008] In an embodiment of the present disclosure, a semiconductor device may include: a packaging substrate including a plurality of packaging balls; at least one memory electrically connected to a first driving voltage packaging ball among the plurality of packaging balls through a first external voltage interconnect; and a power supply circuit electrically connected to the first driving voltage packaging ball through the first external voltage interconnect, electrically connected to the at least one memory through a first internal voltage interconnect, and configured to adjust a voltage state of the first internal voltage interconnect based on a voltage level of the first driving voltage packaging ball.

[0009] In an embodiment of the present disclosure, an electronic device may include: a semiconductor package; and a power management circuit configured to supply an external driving voltage through a package ball included in the semiconductor package, the semiconductor package including: at least one memory; a power circuit configured to supply an internal driving voltage to the at least one memory; and a first external voltage interconnect electrically connected to the at least one memory and the power circuit, and electrically connected to the package ball electrically isolated from the power management circuit.

[0010] In an embodiment of the present disclosure, an electronic device may include: a semiconductor package; and a power management circuit configured to supply an external driving voltage through a package ball included in the semiconductor package, the semiconductor package including: at least one memory; a power circuit configured to supply an internal driving voltage to the at least one memory; a first external voltage interconnect electrically connected between the package ball electrically connected to the power management circuit and the at least one memory, and electrically connected to the power circuit; and a first internal voltage interconnect electrically connected between the power circuit and the at least one memory.

[0011] In an embodiment of the present disclosure, a power supply circuit may include: a voltage generation unit circuit configured to generate a first internal driving voltage; and a voltage output unit circuit electrically connected to a first external voltage interconnect and a first internal voltage interconnect, and configured to compare a voltage level of the first external voltage interconnect and a level of the first internal driving voltage, and when the voltage level of the first external voltage interconnect is equal to or higher than the level of the first internal driving voltage, set the first internal voltage interconnect to a high impedance state.

[0012] In an embodiment of the present disclosure, a semiconductor device may include: at least one memory; a controller configured to control the operation of the at least one memory; and a power supply circuit configured to supply an internal driving voltage to the at least one memory and the controller, wherein the power supply circuit stops generating or outputting the internal driving voltage when a preset time passes after a level of an operating signal received from at least one of the at least one memory and the controller changes from a first level to a second level.

[0013] In an embodiment of the present disclosure, a semiconductor device may include: at least one memory; and a power supply circuit configured to supply an internal driving voltage to the at least one memory, receive an operation-ready signal from the at least one memory, and stop generating or outputting the internal driving voltage when a preset time passes after a level of the operation-ready signal changes from a first level to a second level.

[0014] In an embodiment of the present disclosure, an electronic device may include: a semiconductor package; and a power management circuit configured to supply an external driving voltage to the semiconductor package, the semiconductor package including: at least one memory; and a power circuit configured to generate an internal driving voltage based on the external driving voltage, supply the internal driving voltage to the at least one memory, and stop generating or outputting the internal driving voltage based on the operating state of the at least one memory during at least one period other than an active period of the at least one memory.

[0015] In an embodiment of the present disclosure, a power supply circuit may include: a voltage generating unit circuit, configured to generate an internal driving voltage based on an external driving voltage; and a voltage output unit circuit, configured to output the internal driving voltage based on an operation signal received from the outside, and stop generating or outputting the internal driving voltage when a preset time passes after the level of the operation signal changes from a first level to a second level.

[0016] According to the embodiments of the present disclosure, it is possible to efficiently set and manage a power supply that supplies a voltage for driving a memory or the like according to various types of memory devices including a memory or a memory and a controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a diagram illustrating a configuration of a storage device according to an embodiment of the present disclosure.

[0018] Figure 2 The present invention is shown in the embodiment of the present invention. Figure 1 Schematic diagram of the configuration of the semiconductor package shown in .

[0019] Figure 3 and Figure 4 It is used to describe the embodiment according to the present disclosure. Figure 2 Schematic diagram of an operating method of a semiconductor package shown in .

[0020] Figure 5 The present invention is shown in FIG. Figure 2 ] is a diagram of a configuration of a power supply circuit included in a semiconductor package shown in .

[0021] Figure 6 and Figure 7 It is used to describe the embodiment according to the present disclosure. Figure 5 Schematic diagram of the operating method of the power supply circuit shown in .

[0022] Figures 8 to 10 It is used to describe the embodiment according to the present disclosure. Figure 5 The operation of the power supply circuit is shown in the timing diagram.

[0023] Figure 11 is a diagram illustrating a structure of a semiconductor package according to an embodiment of the present disclosure.

[0024] Figure 12 is a diagram illustrating a configuration of a storage device according to an embodiment of the present disclosure.

[0025] Figure 13 The present invention is shown in the embodiment of the present invention. Figure 12 Schematic diagram of the configuration of the semiconductor package shown in .

[0026] Figure 14The present invention is shown in the embodiment of the present invention. Figure 12 A diagram of the configuration of the power supply circuit shown in .

[0027] Figure 15 It is used to describe the embodiment according to the present disclosure. Figure 14 Schematic diagram of the operation of the power supply circuit shown in . DETAILED DESCRIPTION

[0028] Examples or embodiments of the present disclosure will be described below with reference to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of illustration, and in the accompanying drawings, the same figure numerals and symbols may be used to represent the same or similar parts even if they are shown in different figures. Further, in the following description of the examples or embodiments of the present disclosure, when it is determined that a detailed description of well-known functions and components incorporated herein may obscure the subject matter in some embodiments of the present disclosure, such detailed description will be omitted. Terms such as "including", "having", "comprising", "constituting", "forming", etc. used herein are generally intended to allow the addition of other parts unless used with the term "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0029] Terms such as "first," "second," "A," "B," "(A)," or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define an element, sequence, order, quantity, etc., but is only used to distinguish the corresponding element from other elements.

[0030] When referring to a first element being “connected or coupled” or “contacting or overlapping” with a second element, it should be understood that not only the first element may be “directly connected or coupled” or “directly contacting or overlapping” with the second element, but also a third element may be “interposed” between the first and second elements, or the first and second elements may be “connected or coupled” or “contacting or overlapping” with each other via a fourth element, etc. Here, the second element may be included in at least one of the two or more elements that are “connected or coupled” or “contacting or overlapping” with each other, etc.

[0031] When time relative terms such as "after", "after...", "next", "before" and the like are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, unless these terms are used with the terms "directly" or "immediately", these terms may be used to describe non-continuous or non-sequential processes or operations.

[0032] In addition, when referring to any dimension, relative dimension, etc., even if no relevant description is specified, it should be considered that the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature includes a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). Furthermore, the term "may" fully encompasses all meanings of the term "can."

[0033] Hereinafter, various embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0034] Figure 1 is a diagram illustrating a configuration of a storage device 100 according to an embodiment of the present disclosure.

[0035] Reference Figure 1 , the memory device 100 may include at least one memory 210. The memory device 100 may include a controller 300 that controls the operation of the memory 210.

[0036] The memory 210 and the controller 300 may be semiconductor chips (or semiconductor dies). The memory 210 and the controller 300 may be provided as separate packages. For example, the memory 210 may be provided in the form of a semiconductor package 200. In this disclosure, the semiconductor package 200 may be referred to as a semiconductor device. The controller 300 may be implemented as a single chip or, depending on the circumstances, in a form including multiple chiplets. In the latter case, each of the multiple chiplets may perform at least a portion of the functions to be performed by the controller 300.

[0037] For example, the memory 210 may be implemented as various types such as NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory, phase change random access memory, magnetoresistive random access memory, ferroelectric random access memory, and spin transfer torque random access memory, but the embodiments of the present disclosure are not limited thereto. The memory 210 may be implemented as a three-dimensional array structure. The embodiments of the present disclosure are applicable not only to flash memories having a charge storage layer configured by a floating gate, but also to charge trap flash memories having a charge storage layer configured by an insulating layer.

[0038] For another example, the memory 210 may be a volatile memory such as DRAM, SDRAM, DDR SDRAM, or LPDDR SDRAM.

[0039] According to circumstances, a portion of the memory 210 included in the storage device 100 may be a nonvolatile memory, and another portion may be a volatile memory.

[0040] The controller 300 may control the operation of the memory 210 according to a command received from the outside or according to its own command.

[0041] The controller 300 may control writing data to the memory 210 or reading data written to the memory 210. Depending on the type of the memory 210, the controller 300 may control erasing data written to the memory 210 or refreshing data written to the memory 210.

[0042] The memory device 100 may be supplied with a driving voltage by an external power management circuit (PMIC) 400. The memory device 100 may be supplied with at least one voltage by the PMIC 400. The memory device 100 may directly use the voltage supplied by the PMIC 400 or use it by adjusting the voltage level.

[0043] For example, the power management circuit 400 may be provided on a printed circuit board mounted with the semiconductor package 200 and the controller 300. Alternatively, the power management circuit 400 may be located in a host device 500 that processes data using the memory device 100 and controls its operation.

[0044] Depending on the situation, the power management circuit 400 may be included in the storage device 100. The power management circuit 400 and the storage device 100 may be collectively referred to as an electronic device. Alternatively, the power management circuit 400, the storage device 100, and the host device 500 may be collectively referred to as an electronic device or a computing device.

[0045] The host device 500 may perform data processing while transmitting and receiving commands or data to and from the memory device 100 .

[0046] For example, host device 500 may be a computer, an ultra-mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet, a mobile phone, a smartphone, a wearable device, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a smart TV, a digital audio recorder, a digital audio player, a digital photo recorder, a digital photo player, a digital video recorder, a digital video player, a storage device configured in a data center, one of various electronic devices configured in a home network, one of various electronic devices configured in a telematics network, an RFID (radio frequency identification) device, a mobile device capable of driving under human control or autonomously (e.g., a vehicle, robot, or drone), etc. Alternatively, host device 500 may be a virtual reality / augmented reality device that provides 2D or 3D virtual reality images or augmented reality images. In addition to the above examples, host device 500 may also be any of various electronic devices that require storage device 100 capable of storing data.

[0047] The host device 500 may include at least one operating system. The operating system may manage and control all functions and operations of the host device 500. The operating system may also control the interaction between the host device 500 and the storage device 100. Depending on the mobility of the host device 500, the operating system may be classified into a general-purpose operating system and a mobile operating system.

[0048] The host device 500 can communicate with the storage device 100 through various interfaces.

[0049] For example, the host device 500 can communicate with the storage device 100 via a Compute Express Link (CXL) interface. The host device 500 can be configured as a CXL root port, and the storage device 100 can be configured as a CXL endpoint. Since the host device 500 communicates with the storage device 100 via the CXL interface, a low-latency, high-bandwidth access environment can be achieved while communicating with the high-capacity storage device 100.

[0050] Alternatively, depending on circumstances, the host device 500 may communicate with the storage device 100 through an interface other than the CXL interface.

[0051] For example, the host device 500 and the storage device 100 may communicate through at least one of various communication interfaces or standards such as a Universal Serial Bus (USB) protocol, a MultiMediaCard (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced MiniDisk Interface (ESDI) protocol, and an Integrated Drive Electronics (IDE) protocol, but the embodiments of the present disclosure are not limited thereto.

[0052] Based on the embodiments of the present disclosure, the type and number of host devices 500 communicating with the storage device 100 and the communication interface between the storage device 100 and the host device 500 may vary.

[0053] The memory device 100 may include a power supply circuit (PSIC) 220 that provides a voltage for driving the memory 210 and can effectively manage the voltage.

[0054] For example, the power supply circuit 220 may be located outside the memory 210. The memory 210 and the power supply circuit 220 may be provided as a semiconductor package 200. The memory 210 and the power supply circuit 220 may be provided on a substrate for packaging. For example, the semiconductor package 200 and the controller 300 may be provided on a printed circuit board, and the memory 210 and the power supply circuit 220 may be provided on the substrate of the semiconductor package 200.

[0055] The power circuit 220 may receive at least one voltage from the power management circuit 400 located outside the semiconductor package 200 .

[0056] The power supply circuit 220 may use the voltage received from the power management circuit 400 to supply a voltage for driving the memory 210. In this disclosure, the voltage provided by the power management circuit 400 may be referred to as an external voltage or an external driving voltage, and the voltage provided by the power supply circuit 220 may be referred to as an internal voltage or an internal driving voltage.

[0057] The power supply circuit 220 may include, for example, a DC-DC converter such as a charge pump or a boost converter, but is not limited thereto.

[0058] The power supply circuit 220 may adjust the level of the voltage received from the power management circuit 400 and supply the voltage to the memory 210. Depending on the situation, the voltage supplied by the power management circuit 400 may be provided to the memory 210 for use. Depending on the types of the memory device 100 and the semiconductor package 200, the method of supplying the voltage for driving the memory 210 may vary.

[0059] Embodiments of the present disclosure may provide a structure of a semiconductor package 200 in which the memory 210 may operate using a voltage supplied by a power supply circuit 220 inside the semiconductor package 200 or a voltage supplied by a power management circuit 400 outside the semiconductor package 200 .

[0060] Figure 2 The present invention is shown in the embodiment of the present invention. Figure 1 2 is a diagram of a configuration of a semiconductor package 200 shown in FIG.

[0061] Reference Figure 2 , the semiconductor package 200 may include a memory 210 and a power supply circuit 220. The semiconductor package 200 may include a plurality of memories.

[0062] The semiconductor package 200 may include one or more driving voltage package balls. For example, the driving voltage package balls may be included in the substrate of the semiconductor package 200. The driving voltage package balls may be located on the back side of the substrate where the memory 210 and the power supply circuit 220 are provided.

[0063] The semiconductor package 200 may include one or more external voltage interconnects electrically connected to the driving voltage package balls. The external voltage interconnects may be electrically connected between the driving voltage package balls and the power supply circuit 220.

[0064] Semiconductor package 200 may include one or more internal voltage interconnects electrically connected between power circuit 220 and memory 210 .

[0065] The external voltage interconnections and the internal voltage interconnections described above may be provided on a substrate of the semiconductor package 200 .

[0066] At least a portion of the driving voltage package balls of semiconductor package 200 may be electrically connected to power management circuit 400 located outside semiconductor package 200. Depending on circumstances, at least one of the driving voltage package balls of semiconductor package 200 may not be electrically connected to power management circuit 400.

[0067] For example, the semiconductor package 200 may include a first driving voltage package ball DPB1 , a second driving voltage package ball DPB2 , and a third driving voltage package ball DPB3 .

[0068] The semiconductor package 200 may include first, second, and third external voltage interconnects OVL1, OVL2, and OVL3. The semiconductor package 200 may include first, second, and third internal voltage interconnects IVL1, IVL2, and IVL3.

[0069] The first external voltage interconnection OVL1 may electrically connect the first driving voltage package ball DPB1 and the power supply circuit 220. The first external voltage interconnection OVL1 may electrically connect the first driving voltage package ball DPB1 and the memory 210.

[0070] The second external voltage interconnect OVL2 may electrically connect the second driving voltage package ball DPB2 and the power supply circuit 220. The second external voltage interconnect OVL2 may not be electrically connected to the memory 210. The third external voltage interconnect OVL3 may electrically connect the third driving voltage package ball DPB3 and the power supply circuit 220. The third external voltage interconnect OVL3 may not be electrically connected to the memory 210.

[0071] The first internal voltage interconnect IVL1 may electrically connect the power supply circuit 220 and the memory 210 .

[0072] The first internal voltage interconnect IVL1 may be electrically connected to the first external voltage interconnect OVL1 .

[0073] Each of the second internal voltage interconnect IVL2 and the third internal voltage interconnect IVL3 may electrically connect the power supply circuit 220 and the memory 210 .

[0074] The second internal voltage interconnect IVL2 may be provided electrically isolated or physically separated from the second external voltage interconnect OVL2. The third internal voltage interconnect IVL3 may be provided electrically isolated or physically separated from the third external voltage interconnect OVL3.

[0075] As such, among the external voltage interconnections provided on the semiconductor package 200 , only a portion of the external voltage interconnections may be electrically connected to the internal voltage interconnections or the memory 210 .

[0076] A point at which the first internal voltage interconnect IVL1 is connected to the first external voltage interconnect OVL1 may be located outside the power supply circuit 220 .

[0077] The point at which the first internal voltage interconnect IVL1 is connected to the memory 210 may be the same as the point at which the first external voltage interconnect OVL1 is connected to the memory 210. The portion where the first internal voltage interconnect IVL1 is connected to the memory 210 and the portion where the first external voltage interconnect OVL1 is connected to the memory 210 may be integrated. That is, the first external voltage interconnect OVL1 may be connected to the memory 210 through the first internal voltage interconnect IVL1.

[0078] The first external voltage interconnection OVL1 electrically connected to the first driving voltage package ball DPB1 may be electrically connected to the power circuit 220 as shown in 'A' and may be electrically connected to the first internal voltage interconnection IVL1 as shown in 'B'.

[0079] The point at which the first external voltage interconnect OVL1 is electrically or physically connected to the power supply circuit 220 may be located between the point at which the first external voltage interconnect OVL1 is connected to the first internal voltage interconnect IVL1 and the first driving voltage package ball DPB1. The first external voltage interconnect OVL1 may be electrically connected to the power supply circuit 220 along a voltage path extending from the first driving voltage package ball DPB1 to the memory 210.

[0080] Based on the structure in which the first external voltage interconnection OVL1 is electrically connected to the power circuit 220 and the memory 210 included in the semiconductor package 200 , a driving voltage to be supplied to the memory 210 may be controlled according to the type of the memory device 100 .

[0081] Figure 3 and Figure 4 It is used to describe the embodiment according to the present disclosure. Figure 2 FIG. 2 is a diagram illustrating an operating method of the semiconductor package 200 shown in FIG.

[0082] Reference Figure 3 , the semiconductor package 200 may be supplied with one or more external driving voltages by a power management circuit 400 located outside the semiconductor package 200 .

[0083] For example, the semiconductor package 200 may include a first driving voltage package ball DPB1, a second driving voltage package ball DPB2, and a third driving voltage package ball DPB3. Each of the first driving voltage package ball DPB1, the second driving voltage package ball DPB2, and the third driving voltage package ball DPB3 may be electrically connected to the power management circuit 400.

[0084] The semiconductor package 200 may be supplied with a first external driving voltage Odrv1 through the first driving voltage package ball DPB1. The semiconductor package 200 may be supplied with a second external driving voltage Odrv2 and a third external driving voltage Odrv3 through the second driving voltage package ball DPB2 and the third driving voltage package ball DPB3, respectively.

[0085] For example, the first external driving voltage Odrv1 may be a voltage higher than the second external driving voltage Odrv2 and the third external driving voltage Odrv3 , but is not limited thereto.

[0086] Each of the first external driving voltage Odrv1 , the second external driving voltage Odrv2 , and the third external driving voltage Odrv3 may be supplied to the power supply circuit 220 included in the semiconductor package 200 .

[0087] The power supply circuit 220 may output at least one internal driving voltage based on the first external driving voltage Odrv1, the second external driving voltage Odrv2, and the third external driving voltage Odrv3. The internal driving voltage may be various voltages used for the operation of the memory 210. The internal driving voltage may be used to drive a driving line (e.g., a word line) included in the memory 210 or to generate a control signal to be transmitted and received in the memory 210, but is not limited thereto.

[0088] For example, the power supply circuit 220 may output an internal driving voltage having the same level as that of the external driving voltage. For another example, the power supply circuit 220 may output an internal driving voltage obtained by adjusting the level of the external driving voltage.

[0089] The power supply circuit 220 may determine whether to output the internal driving voltage based on the external driving voltage.

[0090] For example, the first external voltage interconnect OVL1 electrically connected between the first driving voltage package ball DPB1 and the power circuit 220 may be electrically connected to the memory 210. The first external voltage interconnect OVL1 may be electrically connected to the first internal voltage interconnect IVL1 electrically connected between the power circuit 220 and the memory 210. According to circumstances, the first external voltage interconnect OVL1 may be physically separated from the first internal voltage interconnect IVL1 and electrically connected to the memory 210.

[0091] The power supply circuit 220 may determine whether to output the internal driving voltage to the first internal voltage interconnect IVL1 based on whether the first external driving voltage Odrv1 is received.

[0092] For example, the power supply circuit 220 may generate an internal driving voltage to be supplied through the first internal voltage interconnect IVL1 .

[0093] The power circuit 220 may compare the level of the generated internal driving voltage with the voltage level of the first driving voltage package ball DPB1. The power circuit 220 may check whether the first external driving voltage Odrv1 is received by comparing the level of the generated internal driving voltage with the voltage level of the first driving voltage package ball DPB1.

[0094] When the voltage level of the first driving voltage package ball DPB1 or the level of the first external driving voltage Odrv1 is equal to or higher than the level of the generated internal driving voltage, the power supply circuit 220 may not output the generated internal driving voltage. The power supply circuit 220 may set the first internal voltage interconnect IVL1 to a high impedance state.

[0095] For another example, the power supply circuit 220 may check whether the voltage level of the first driving voltage package ball DPB1 is equal to or higher than a preset reference level. When the voltage level of the first driving voltage package ball DPB1 is equal to or higher than the reference level, the power supply circuit 220 may not generate or output the internal driving voltage to be supplied to the first internal voltage interconnect IVL1. The power supply circuit 220 may set the first internal voltage interconnect IVL1 to a high impedance state.

[0096] According to circumstances, when the voltage level of the first driving voltage package ball DPB1 is equal to or higher than the level of the generated internal driving voltage and equal to or higher than a preset reference level, the power supply circuit 220 may set the first internal voltage interconnect IVL1 to a high impedance state. The power supply circuit 220 may not output the generated internal driving voltage to the first internal voltage interconnect IVL1.

[0097] The power supply circuit 220 can output a second internal driving voltage Idrv2 to the memory 210 based on the second external driving voltage Odrv2. The power supply circuit 220 can output a third internal driving voltage Idrv3 to the memory 210 based on the third external driving voltage Odrv3. When the first internal voltage interconnect IVL1 is set to high impedance, the second internal driving voltage Idrv2 can be supplied through the second internal voltage interconnect IVL2. When the first internal voltage interconnect IVL1 is set to high impedance, the third internal driving voltage Idrv3 can be supplied through the third internal voltage interconnect IVL3.

[0098] The power supply circuit 220 may not output the internal driving voltage to the first internal voltage interconnect IVL1. The first external driving voltage Odrv1 may be supplied to the memory 210 through the first external voltage interconnect OVL1. The first external driving voltage Odrv1 may be supplied to the first external voltage interconnect OVL1 during a period in which the first internal voltage interconnect IVL1 is set to a high impedance state.

[0099] In a structure in which the first external voltage interconnect OVL1 electrically connected to the first driving voltage package ball DPB1 is electrically connected to the power circuit 220 and the memory 210 , the driving voltage to be supplied to the memory 210 may be controlled by voltage comparison by the power circuit 220 .

[0100] According to circumstances, a portion of the external driving voltage may not be supplied by the power management circuit 400. In this case, the voltage driving the memory 210 may be supplied by the power circuit 220.

[0101] For example, refer to Figure 4 , the semiconductor package 200 may include a first driving voltage package ball DPB1 , a second driving voltage package ball DPB2 , and a third driving voltage package ball DPB3 .

[0102] The first driving voltage package ball DPB1 may be electrically isolated from the power management circuit 400. Each of the second driving voltage package ball DPB2 and the third driving voltage package ball DPB3 may be electrically connected to the power management circuit 400. In this case, the first driving voltage package ball DPB1 may be referred to as a dummy package ball.

[0103] The power supply circuit 220 may output the second and third internal driving voltages Idrv2 and Idrv3 by using the second and third external driving voltages Odrv2 and Odrv3 supplied through the second and third driving voltage package balls DPB2 and DPB3 .

[0104] The power supply circuit 220 may generate the first internal driving voltage Idrv1 using at least one of the second external driving voltage Odrv2 and the third external driving voltage Odrv3 .

[0105] The power supply circuit 220 may compare the level of the first internal driving voltage Idrv1 with the voltage level of the first driving voltage package ball DPB1. When the voltage level of the first driving voltage package ball DPB1 is lower than the level of the first internal driving voltage Idrv1, the power supply circuit 220 may output the first internal driving voltage Idrv1 to the first internal voltage interconnect IVL1.

[0106] Optionally, the power circuit 220 may compare the voltage level of the first driving voltage package ball DPB1 with a preset reference level. When the voltage level of the first driving voltage package ball DPB1 is lower than the reference level, the power circuit 220 may output the first internal driving voltage Idrv1 to the first internal voltage interconnect IVL1.

[0107] As such, in the structure where the semiconductor package 200 includes the first driving voltage package ball DPB1 , the power supply circuit 220 may control whether to supply the first internal driving voltage Idrv1 based on the voltage level of the first driving voltage package ball DPB1 or the first external voltage interconnect OVL1 .

[0108] Even in the case where the power management circuit 400 located outside the semiconductor package 200 selectively supplies an external driving voltage, various voltages for driving the memory 210 may be supplied by the power circuit 220 .

[0109] In addition, depending on the situation, even in a structure in which the first driving voltage package ball DPB1 is electrically connected to the power management circuit 400, the first internal driving voltage Idrv1 may be output to the first internal voltage interconnect IVL1 when the voltage level of the first driving voltage package ball DPB1 is lower than the level of the first internal driving voltage Idrv1 or the reference level.

[0110] The power supply circuit 220 may include a configuration to generate an internal driving voltage and a configuration to control whether to output the internal driving voltage.

[0111] Figure 5 The present invention is shown in FIG. Figure 2 2 is a diagram of a configuration of a power supply circuit 220 included in a semiconductor package 200 shown in FIG.

[0112] Reference Figure 5 , the power supply circuit 220 may include a voltage generator 221 , a comparator 222 , and a counter 223 .

[0113] The power supply circuit 220 may receive a high potential voltage VCC and a low potential voltage VSS for its operation from the outside. For example, the power supply circuit 220 may generate an internal driving voltage using at least one of the high potential voltage VCC, the low potential voltage VSS, and the external driving voltage received from the outside.

[0114] The voltage generator 221 may be, for example, a charge pump or a boost converter.

[0115] The voltage generator 221 may generate an internal driving voltage using at least one of voltages received from the outside.

[0116] For example, the voltage generator 221 may generate the first internal driving voltage Idrv1 using at least one of the second external driving voltage Odrv2 and the third external driving voltage Odrv3 received from the power management circuit 400 .

[0117] Depending on the situation, the voltage generator 221 can generate the second internal driving voltage Idrv2, the third internal driving voltage Idrv3, etc. using at least one of the second external driving voltage Odrv2 and the third external driving voltage Odrv3. For example, the voltage generator 221 can generate the first internal driving voltage Idrv1 by increasing the level of the second external driving voltage Odrv2. The voltage generator 221 can generate the second internal driving voltage Idrv2 by decreasing the level of the second external driving voltage Odrv2.

[0118] The first internal driving voltage Idrv1 generated by the voltage generator 221 may be input to the comparator 222 .

[0119] The comparator 222 may be electrically connected to the first external voltage interconnect OVL1 electrically connected to the first driving voltage package ball DPB1. The comparator 222 may compare the voltage level of the first driving voltage package ball DPB1 with the voltage level of the first internal driving voltage Idrv1.

[0120] According to the voltage level comparison result, the comparator 222 may determine whether to output the first internal driving voltage Idrv1 to the first internal voltage interconnect IVL1 .

[0121] In the present disclosure, the voltage generator 221 included in the power supply circuit 220 may be referred to as a voltage generating circuit, and a configuration including the comparator 222 that controls whether to output the first internal driving voltage Idrv1 may be referred to as a voltage output circuit.

[0122] The counter 223 may provide a count value for controlling an operation timing of the power supply circuit 220. The counter 223 may provide a count value for controlling an operation timing of at least one of the voltage generator 221 and the comparator 222.

[0123] For example, the counter 223 may start counting when receiving a power-on signal from the outside. For another example, the counter 223 may start counting when receiving an operation enable signal (Enable) from the outside. The power-on signal or the operation enable signal may be a signal received from the host device 500 or the controller 300.

[0124] The power supply circuit 220 includes a configuration to generate an internal driving voltage, a configuration to compare levels of the internal driving voltage and an external driving voltage, and a configuration to control operation timing, and may control whether to generate the internal driving voltage or whether to output the internal driving voltage.

[0125] Figure 6 and Figure 7 It is used to describe the embodiment according to the present disclosure. Figure 5 2 is a diagram illustrating an operating method of the power supply circuit 220 shown in FIG.

[0126] Reference Figure 6 , a case where the semiconductor package 200 receives the first external driving voltage Odrv1 from the power management circuit 400 is shown as an example.

[0127] The power circuit 220 may receive the first external driving voltage Odrv1 through the first driving voltage package ball DPB1 of the semiconductor package 200. The first external driving voltage Odrv1 may be input to the comparator 222 of the power circuit 220 through the first external voltage interconnect OVL1.

[0128] The voltage generator 221 of the power supply circuit 220 may generate and output the first internal driving voltage Idrv1 .

[0129] The comparator 222 may compare the level of the first driving voltage package ball DPB1, the first external voltage interconnect OVL1, or the first external driving voltage Odrv1 with the level of the first internal driving voltage Idrv1. When the voltage level of the first driving voltage package ball DPB1 is equal to or higher than the level of the first internal driving voltage Idrv1, the comparator 222 may not output the first internal driving voltage Idrv1 to the first internal voltage interconnect IVL1. The power supply circuit 220 may set the first internal voltage interconnect IVL1 to a high impedance state.

[0130] Depending on the situation, the comparator 222 may compare the voltage level of the first driving voltage package ball DPB1 with a preset reference level. When the voltage level of the first driving voltage package ball DPB1 is equal to or higher than the reference level, the voltage generator 221 of the power supply circuit 220 may not generate the first internal driving voltage Idrv1. Alternatively, the voltage generator 221 may generate the first internal driving voltage Idrv1, and the comparator 222 may not output the first internal driving voltage Idrv1 to the first internal voltage interconnect IVL1.

[0131] According to the reception condition of the first external driving voltage Odrv1 , it may be controlled whether to supply the first internal driving voltage Idrv1 .

[0132] For another example, see Figure 7 , a case where the semiconductor package 200 does not receive the first external driving voltage Odrv1 from the power management circuit 400 is shown as an example.

[0133] The first driving voltage package ball DPB1 of the semiconductor package 200 may be electrically isolated from the power management circuit 400 .

[0134] The voltage generator 221 of the power supply circuit 220 may generate a first internal driving voltage Idrv1. The comparator 222 may compare the voltage level of the first driving voltage package ball DPB1 with the level of the first internal driving voltage Idrv1. When the voltage level of the first driving voltage package ball DPB1 is lower than the level of the first internal driving voltage Idrv1, the comparator 222 may output the first internal driving voltage Idrv1 to the first internal voltage interconnect IVL1.

[0135] The comparator 222 may compare the voltage level of the first driving voltage package ball DPB1 with a preset reference level. When the voltage level of the first driving voltage package ball DPB1 is lower than the reference level, the comparator 222 may output the first internal driving voltage Idrv1 to the first internal voltage interconnect IVL1.

[0136] Even when the first driving voltage package ball DPB1 is electrically connected to the power management circuit 400, the first internal driving voltage Idrv1 may be output to the first internal voltage interconnect IVL1 when the voltage level of the first driving voltage package ball DPB1 is lower than the level of the first internal driving voltage Idrv1 or the reference level.

[0137] The first internal driving voltage Idrv1 output through the first internal voltage interconnect IVL1 may be supplied to the memory 210 .

[0138] Since the first internal voltage interconnect IVL1 is electrically connected to the first external voltage interconnect OVL1, the first internal driving voltage Idrv1 supplied through the first internal voltage interconnect IVL1 may be fed back to the power supply circuit 220 through the first external voltage interconnect OVL1 as indicated by “C.” The first internal driving voltage Idrv1 fed back to the power supply circuit 220 may be input to the comparator 222.

[0139] The level of the first internal driving voltage Idrv1 fed back to the comparator 222 may be lower than the level of the first internal driving voltage Idrv1 output to the first internal voltage interconnect IVL1 due to a load of the feedback path.

[0140] Even if the comparator 222 receives the first internal driving voltage Idrv1 fed back through the first external voltage interconnect OVL1 after outputting the first internal driving voltage Idrv1 , the comparator 222 may maintain outputting the first internal driving voltage Idrv1 to the first internal voltage interconnect IVL1 according to the voltage comparison result.

[0141] In the structure in which the first external voltage interconnect OVL1 and the first internal voltage interconnect IVL1 are electrically connected to each other, the first internal driving voltage Idrv1 may be stably supplied to the memory 210 .

[0142] Since the power circuit 220 controls whether to output the first internal driving voltage Idrv1 according to the voltage comparison result of the comparator 222 , it may take a certain amount of time before the first internal driving voltage Idrv1 is output.

[0143] Figures 8 to 10 It is used to describe the embodiment according to the present disclosure. Figure 5 1 is a timing diagram of the operation of the power supply circuit 220 shown in FIG.

[0144] Figure 8 and Figure 9 An example of an operation timing of the semiconductor package 200 included in the memory device 100 after the memory device 100 is started up is shown. Figure 8 An example is shown of a case where the semiconductor package 200 receives the first external driving voltage Odrv1 from the outside. Figure 9 An example is shown of a case where the semiconductor package 200 does not receive the first external driving voltage Odrv1 from the outside.

[0145] Reference Figure 8 During the first period P1, the operation of the memory 210 and the power supply circuit 220 included in the semiconductor package 200 may begin in response to an operation enable signal (Enable). Alternatively, the operation of the semiconductor package 200 may begin in response to a power-on signal. "VI" may represent the level of the first internal driving voltage Idrv1 provided by the power supply circuit 220. "DPB1" may represent the voltage level of the first driving voltage package ball DPB1. "VO" may represent the voltage level output by the power supply circuit 220 to the first internal voltage interconnect IVL1.

[0146] During the first period P1 , an internal driving voltage may be generated according to the operation enable signal and compared with the first driving voltage package ball DBP1 .

[0147] The power supply circuit 220 may compare the voltage level of the first driving voltage package ball DPB1 with the level of the first internal driving voltage Idrv1 or the reference level during a predetermined period by using the counter 223. For example, during the second period P2, the power supply circuit 220 may compare the voltage level of the first driving voltage package ball DPB1 with the level of the first internal driving voltage Idrv1.

[0148] During the second period P2 in which the voltage comparison is performed, the power supply circuit 220 may set the first internal voltage interconnect IVL1 to a high impedance state.

[0149] According to the result of the voltage comparison performed during the second period P2, when the voltage level of the first driving voltage package ball DPB1 is equal to or higher than the level of the first internal driving voltage Idrv1, during the third period P3, the power supply circuit 220 may not output the first internal driving voltage Idrv1 to the first internal voltage interconnect IVL1. During the third period P3, "VO" may maintain a low level and the first internal voltage interconnect IVL1 may maintain a high impedance state.

[0150] For another example, see Figure 9 During the first period P1, the operation of the semiconductor package 200 may be started according to the operation enable signal. During the second period P2, the power supply circuit 220 may compare the voltage level of the first driving voltage package ball DPB1 with the level of the first internal driving voltage Idrv1.

[0151] During the second period P2 in which the voltage comparison is performed, the power supply circuit 220 may set the first internal voltage interconnect IVL1 to a high impedance state.

[0152] According to the result of the voltage comparison during the second period P2, when the voltage level of the first driving voltage package ball DPB1 is lower than the level of the first internal driving voltage Idrv1, during the third period P3, the power supply circuit 220 may output the first internal driving voltage Idrv1 to the first internal voltage interconnect IVL1. During the third period P3, the high impedance state of the first internal voltage interconnect IVL1 may be released, and during the third period P3, the level of "VO" may be a high level.

[0153] In this manner, when the operation of the memory device 100 starts, the power supply circuit 220 may control the voltage to be supplied to the memory 210 by comparing the voltage level of the first driving voltage package ball DPB1 and the level of the first internal driving voltage Idrv1 .

[0154] When generating and supplying the first internal driving voltage Idrv1 to the memory 210 , the power supply circuit 220 may reduce power consumption by adjusting the output of the first internal driving voltage Idrv1 according to the operating state of the memory 210 .

[0155] Reference Figure 10 During the first period P1, the operation of the memory device 100 may start according to the operation enable signal. The power supply circuit 220 may start generating the first internal driving voltage Idrv1.

[0156] During the second period P2, the first internal voltage interconnect IVL1 may be set to a high impedance state.During the second period P2, the voltage level of the first driving voltage package ball DPB1 may be compared with the level of the first internal driving voltage Idrv1.

[0157] When the voltage level of the first driving voltage package ball DPB1 is lower than that of the first internal driving voltage Idrv1, the first internal driving voltage Idrv1 may be output to the first internal voltage interconnect IVL1 during the third periods P31 and P32. The level of 'VO' may change from low to high.

[0158] During the third periods P31 and P32, the count value of the counter 223 may be set to a reference value. The reference value may be a value greater than 0, but depending on circumstances, the reference value may be set to 0. During the third periods P31 and P32, when the operation enable signal maintains a high level, the count value of the counter 223 may maintain the reference value.

[0159] During the first partial period P31 of the third periods P31 and P32 , the level of the operation enable signal may be changed from the first level to the second level. For example, the level of the operation enable signal may be changed from a high level to a low level.

[0160] When the level of the operation enable signal changes from a high level to a low level, the counter 223 may start counting. For example, depending on the reference value, the counter 223 may start counting by decreasing the count value or by increasing the count value. The counter 223 may continue counting until the count value reaches a preset target value.

[0161] For example, during the first partial period P31, the reference value set as the count value of the counter 223 is a value greater than 0, and when the level of the operation enable signal changes, the counter 223 can perform counting in a manner of decreasing the count value. The target value can be, for example, 0, and the counter 223 can perform counting until the target value is reached.

[0162] When the count value of the counter 223 reaches the target value, the power supply circuit 220 may stop generating or outputting the first internal driving voltage Idrv1 during the first partial period P31. The time corresponding to the difference between the reference value and the target value of the counter 223 may be set to be equal to or longer than the time of the operation that takes the longest time among the operations of the memory 210. For example, the reference value or the target value may be set to correspond to the time required to erase and write data to the memory 210, or to the time obtained by adding the delay time to the corresponding time.

[0163] When the count value of the counter 223 reaches the target value, since the generation or output of the first internal driving voltage Idrv1 is stopped during the remaining period of the first partial period P31 , power consumption according to the supply of the first internal driving voltage Idrv1 may be reduced.

[0164] When the level of the operation enable signal changes from the second level to the first level, the power supply circuit 220 may output the first internal driving voltage Idrv1 again. For example, during the second partial period P32 of the third periods P31 and P32, the operation enable signal may change from a low level to a high level.

[0165] The first internal driving voltage Idrv1 may be output, and the count value of the counter 223 may be set to the reference value again.

[0166] When the level of the operation enable signal changes from high to low during the second partial period P32, the counting operation of the counter 223 may be started. When the count value of the counter 223 reaches the target value, the power supply circuit 220 may stop generating or outputting the first internal driving voltage Idrv1.

[0167] In this way, the embodiment of the present disclosure can easily provide a voltage for driving the memory 210 in both the case where the power supply circuit 220 included in the semiconductor package 200 supplies an external driving voltage and the case where the power supply circuit 220 included in the semiconductor package 200 does not supply an external driving voltage. In addition, since the supply time of the internal driving voltage is adjusted using the counter 223 included in or separately added for the operation of the power supply circuit 220, power consumption caused by driving the power supply circuit 220 can be reduced.

[0168] Since the semiconductor package 200 according to the embodiment of the present disclosure has a structure that can operate with and without the external driving voltage being supplied, the semiconductor package 200 can have a structure including a driving voltage package ball for receiving the corresponding external driving voltage regardless of whether the external driving voltage is supplied.

[0169] Figure 11 is a diagram illustrating a structure of a semiconductor package according to an embodiment of the present disclosure.

[0170] Reference Figure 11 , Figure 11 2 shows an example of a structure in which a semiconductor package (eg, 200) is provided on a printed circuit board (PCB) 2200. The semiconductor package may be provided on the printed circuit board 2200, and although Figure 11 Although not shown in the figure, the controller 300 may be provided additionally. According to circumstances, the power management circuit 400 may be provided on the printed circuit board 2200.

[0171] The semiconductor package may include a package substrate 1000. At least one memory 210 may be provided on the package substrate 1000. Figure 11 An example of stacking 16 memory cells 210 is shown. An adhesive layer 1100 may be provided between the 16 memory cells 210 to prevent chip warping during handling. Adhesive layer 1100 may be, for example, through wafer backside lamination (PWBL) tape, but is not limited thereto.

[0172] The power circuit 220 may be provided on the package substrate 1000 of the semiconductor package. The provision position of the power circuit 220 may vary.

[0173] The power circuit 220 may be electrically connected to the package substrate 1000. The power circuit 220 may be electrically connected to the memory 210 through a wire, as indicated by "D."

[0174] A plurality of package balls PB may be provided on the back surface of the package substrate 1000. At least some of the plurality of package balls PB may be package balls PB for receiving a driving voltage. For example, as shown by "E," package balls PB may be provided for receiving a voltage such as a boost voltage VPP. The boost voltage VPP may correspond to the first external driving voltage Odrv1.

[0175] In a structure in which the memory 210 and the power supply circuit 220 are included in a semiconductor package included in a memory device (e.g., 100), package balls PB are included in a package substrate 1000 of the semiconductor package, and voltage supply to the power supply circuit 220 can be controlled based on whether a voltage is received through the corresponding package balls PB. Whether the voltage is supplied through the corresponding package balls PB or not, the voltage for operating the semiconductor package can be stably supplied.

[0176] Figure 11 The example shows a case where only the memory 210 and the power supply circuit 220 are provided in the semiconductor package, but depending on circumstances, the controller 300 may be additionally provided in the semiconductor package.

[0177] Even in the case where the controller 300 is provided in the semiconductor package 200 , it is possible to control the internal driving voltage according to whether the external driving voltage is received, or to control the reduction of power consumption according to the generation of the internal driving voltage.

[0178] Figure 12 is a diagram illustrating a configuration of a storage device 100 according to an embodiment of the present disclosure.

[0179] Reference Figure 12 , the memory device 100 may include a memory 210, a power supply circuit (PSIC) 220, and a controller 300. The memory 210, the power supply circuit 220, and the controller 300 may be provided as a semiconductor package 200. The memory 210, the power supply circuit 220, and the controller 300 may be provided on a substrate for packaging.

[0180] The memory device 100 may be supplied with at least one voltage by an external power management circuit (PMIC) 400. The power management circuit 400 may be located in the host device 500 or on a printed circuit board where the memory device 100 is mounted, depending on circumstances.

[0181] The power supply circuit 220 included in the semiconductor package 200 may supply voltages for driving the memory 210 and the controller 300. In a structure in which the memory 210 and the controller 300 are provided in the semiconductor package 200, the power supply circuit 220 may be provided in the semiconductor package 200 and may supply at least one internal driving voltage.

[0182] The power supply circuit 220 may receive at least one voltage from the power management circuit 400 and may use the received voltage to provide an internal driving voltage. Even in a configuration in which the controller 300 is additionally provided in the semiconductor package 200, the configuration in which the driving voltage package ball is provided as described above may be applied. For example, the semiconductor package 200 may include a first driving voltage package ball DPB1, and the power supply circuit 220 may control whether to generate and provide the first internal driving voltage Idrv1 based on the voltage level of the first driving voltage package ball DPB1.

[0183] Alternatively, the semiconductor package 200 may include a driving voltage package ball to which an external driving voltage is applied by the power management circuit 400. The power circuit 220 may receive some voltages through the driving voltage package ball and supply voltages for driving the memory 210 and the controller 220 by using these voltages.

[0184] In this way, in a structure in which the power supply circuit 220 supplies the internal driving voltage using the external driving voltage, the power supply circuit 220 can operate in a manner of reducing power consumption according to the generation and output of the internal driving voltage.

[0185] Figure 13 The present invention is shown in FIG. Figure 12 2 is a diagram of a configuration of a semiconductor package 200 shown in FIG.

[0186] Reference Figure 13 , the memory 210 , the controller 300 , and the power supply circuit 220 may be provided in the semiconductor package 200 . The power supply circuit 220 may be supplied with some external driving voltages by a power management circuit 400 located outside the semiconductor package 200 .

[0187] For example, the power circuit 220 may be supplied with the second and third external driving voltages Odrv2 and Odrv3 by the power management circuit 400. The power circuit 220 may output at least one internal driving voltage using the second and third external driving voltages Odrv2 and Odrv3.

[0188] The power supply circuit 220 may be electrically connected to the memory 210 through the first, second, and third internal voltage interconnects IVL1, IVL2, and IVL3.

[0189] The power supply circuit 220 may supply the first, second, and third internal driving voltages Idrv1, Idrv2, and Idrv3 to the memory 210 through the first, second, and third internal voltage interconnects IVL1, IVL2, and IVL3, respectively.

[0190] For example, the first internal driving voltage Idrv1 may be a voltage higher than the second and third internal driving voltages Idrv2 and Idrv3 .

[0191] The power supply circuit 220 may generate the first internal driving voltage Idrv1 by increasing the level of the second external driving voltage Odrv2 or the third external driving voltage Odrv3. The power supply circuit 220 may generate the second internal driving voltage Idrv2 or the third internal driving voltage Idrv3 by decreasing the level of the second external driving voltage Odrv2 or the third external driving voltage Odrv3.

[0192] The power supply circuit 220 may supply an internal driving voltage for driving the controller 300. The power supply circuit 220 may be electrically connected to the controller 300 through a third internal voltage interconnect IVL3 and a fourth internal voltage interconnect IVL4. The power supply circuit 220 may supply a third internal driving voltage Idrv3 and a fourth internal driving voltage Idrv4 to the controller 300 through the third internal voltage interconnect IVL3 and the fourth internal voltage interconnect IVL4, respectively.

[0193] The power supply circuit 220 may adjust or stop supplying the internal driving voltage according to the operating state of the memory 210 .

[0194] For example (i.e., case 1), the power supply circuit 220 may adjust the internal driving voltage to be supplied to the memory 210 or the controller 300 based on the operation enable signal (Enable) received from the controller 300. For another example (i.e., case 2), the power supply circuit 220 may adjust the internal driving voltage to be supplied to the memory 210 or the controller 300 based on the operation ready signal (RB) received from the memory 210.

[0195] The operation enable signal or the operation ready signal can be a signal indicating the start of the operation of the memory 210. The operation status of the memory 210 can be checked based on the change of the corresponding signal, and the internal driving voltage to be output by the power supply circuit 220 can be adjusted according to the operation status of the memory 210.

[0196] The internal driving voltages adjusted and output by the power supply circuit 220 may be different, and for example, the power supply circuit 220 may control the output of the first internal driving voltage Idrv1 having the highest level.

[0197] For example, the power supply circuit 220 may adjust the output of the first internal driving voltage Idrv1 using a counter that operates based on an operation enable signal or an operation ready signal.

[0198] Figure 14 The present invention is shown in FIG. Figure 12 2 is a diagram of the configuration of the power supply circuit 220 shown in FIG.

[0199] Reference Figure 14 , the power supply circuit 220 may include a voltage generator 221 and a counter 223 .

[0200] The voltage generator 221 may generate first to fourth internal driving voltages Idrv1 to Idrv4. The internal driving voltage adjusted and output by the voltage generator 221 may be at least one of the above internal driving voltages, but the case of adjusting the output of the first internal driving voltage Idrv1 will be described as an example.

[0201] The voltage generator 221 may generate a first internal driving voltage Idrv1 and output the first internal driving voltage Idrv1 to the memory 210 .

[0202] The voltage generator 221 may receive an operation enable signal or an operation ready signal from the outside. The counter 223 of the voltage generator 221 may perform a counting operation based on the operation enable signal or the operation ready signal. According to the count value of the counter 223, the voltage generator 221 may stop generating or outputting the first internal driving voltage Idrv1.

[0203] For example, the power circuit 220 may adjust the output of the first internal driving voltage Idrv1 to be output to the memory 210 based on the operation enable signal received from the controller 300. The output of the driving voltage to be supplied to the second semiconductor die may be adjusted based on the control signal received from the first semiconductor die.

[0204] For another example, the power supply circuit 220 may adjust the output of the first internal driving voltage Idrv1 to be output to the memory 210 based on the operation ready signal received from the memory 210. The output of the driving voltage to be supplied to the semiconductor die may be adjusted based on the control signal received from the corresponding semiconductor die.

[0205] The counter 223 of the power supply circuit 220 may perform a counting operation according to a level change of the operation enable signal or the operation ready signal and provide a count value to the voltage generator 221. The voltage generator 221 may stop generating or outputting the first internal driving voltage Idrv1 for a certain period based on the count value.

[0206] Figure 15 It is used to describe the embodiment according to the present disclosure. Figure 14 Schematic diagram of the operation of the power supply circuit 220 shown in FIG.

[0207] Reference Figure 15During the first period P1, the power supply circuit 220 may receive an operation enable signal (Enable) from the controller 300. During the first period P1, the power supply circuit 220 may start operating and start generating the first internal driving voltage Idrv1. The voltage level "V1" generated by the voltage generator 221 may rise.

[0208] Since an example is shown in which the power circuit 220 internally generates and outputs the first internal driving voltage Idrv1 , the power circuit 220 may output the first internal driving voltage Idrv1 during second periods P21 and P22 after the first period P1 during which startup is performed.

[0209] The count value of the counter 223 may be set to a reference value according to an operation enable signal input during the first period P1 .

[0210] During the first partial period P21 of the second periods P21 and P22, the count value of the counter 223 may maintain the reference value during the period in which the operation enable signal maintains a high level. When the level of the operation enable signal changes from a high level to a low level during the first partial period P21, the counting operation of the counter 223 may be performed.

[0211] The counting operation of the counter 223 may be performed until the count value reaches the target value. In the case where the counter 223 operates by decreasing the count value, the target value may be set to 0. When the count value becomes 0, the power supply circuit 220 may stop generating or outputting the first internal driving voltage Idrv1. The voltage level "VO" output by the power supply circuit 220 may change from a high level to a low level.

[0212] During the second partial period P22 of the second periods P21 and P22 , the operation enable signal may be changed from a low level to a high level.

[0213] The count value of the counter 223 may be set to the reference value again. During the second partial period P22, the count value may maintain the reference value during the period when the operation enable signal maintains a high level. When the operation enable signal becomes a low level, the counting operation of the counter 223 may be performed. When the count value reaches the target value, the generation or output of the first internal driving voltage Idrv1 may be stopped.

[0214] Although the case where the counter 223 operates according to the level of the operation enable signal has been described as an example, after the startup is completed, the counter 223 may also operate based on the level change of the operation ready signal transmitted from the memory 210. Based on the control signal output by the memory 210, the power supply circuit 220 may control the output of the internal driving voltage supplied to the memory 210.

[0215] The following is a brief description of the above-mentioned embodiments of the present disclosure.

[0216] A semiconductor device based on an embodiment of the present disclosure may include: a packaging substrate including a plurality of packaging balls; at least one memory electrically connected to a first driving voltage packaging ball among the plurality of packaging balls through a first external voltage interconnect; and a power supply circuit electrically connected to the first driving voltage packaging ball through the first external voltage interconnect, electrically connected to the at least one memory through a first internal voltage interconnect, and configured to adjust a voltage state of the first internal voltage interconnect according to a voltage level of the first driving voltage packaging ball.

[0217] The power supply circuit may generate a first internal driving voltage and may set the first internal voltage interconnect to a high impedance state when a voltage level of the first driving voltage package ball is equal to or higher than a level of the first internal driving voltage.

[0218] When the voltage level of the first driving voltage package ball is equal to or higher than a reference level, the power supply circuit may set the first internal voltage interconnect to a high impedance state.

[0219] The first internal voltage interconnection may be in a high impedance state, and a first external driving voltage may be supplied to at least one memory through the first external voltage interconnection.

[0220] The power supply circuit may generate a first internal driving voltage and may output the first internal driving voltage to the first internal voltage interconnection when a voltage level of the first driving voltage package ball is lower than a level of the first internal driving voltage.

[0221] When the voltage level of the first driving voltage package ball is lower than a reference level, the power supply circuit may output the first internal driving voltage generated therein to the first internal voltage interconnection.

[0222] When the first internal driving voltage generated by the power supply circuit is supplied to the first internal voltage interconnection, a voltage level of the first internal voltage interconnection may be higher than a voltage level of the first external voltage interconnection.

[0223] The power circuit may be electrically connected to a second driving voltage package ball among the plurality of package balls through a second external voltage interconnection and may generate a first internal driving voltage to be supplied to the first internal voltage interconnection using a second external driving voltage received through the second external voltage interconnection.

[0224] The power supply circuit may generate the first internal driving voltage by boosting a voltage level of the second external driving voltage, and may generate the second internal driving voltage by lowering a voltage level of the second external driving voltage.

[0225] The power supply circuit may supply the second internal driving voltage through a second internal voltage interconnection electrically connected to the at least one memory and electrically isolated from the second external voltage interconnection.

[0226] When a power-on signal or an operation enable signal is received from the outside, the power supply circuit may set the first internal voltage interconnection to a high impedance state within a preset time.

[0227] The first external voltage interconnection may be electrically connected to the first internal voltage interconnection.

[0228] A portion of the first external voltage interconnection connected to the at least one memory may be integrated with a portion of the first internal voltage interconnection connected to the at least one memory.

[0229] A point at which the first external voltage interconnection is connected to the power supply circuit may be located between a point at which the first external voltage interconnection is connected to the first driving voltage package ball and a point at which the first external voltage interconnection is connected to the at least one memory.

[0230] The voltage output through the first internal voltage interconnection may be fed back to the power supply circuit through the first external voltage interconnection.

[0231] The power supply circuit may include a voltage generator configured to generate a first internal driving voltage; and a comparator configured to compare the first internal driving voltage with a voltage input through a first external voltage interconnection and determine an output voltage.

[0232] The power supply circuit may receive an operation-ready signal from at least one memory, and may stop generating or outputting the first internal driving voltage when a preset time elapses after a level of the operation-ready signal changes from a first level to a second level.

[0233] An electronic device based on an embodiment of the present disclosure may include: a semiconductor package; and a power management circuit configured to supply an external driving voltage through a package ball included in the semiconductor package, the semiconductor package including: at least one memory; a power circuit configured to supply an internal driving voltage to the at least one memory; and a first external voltage interconnect electrically connected to the at least one memory and the power circuit, and electrically connected to the package ball electrically isolated from the power management circuit.

[0234] The semiconductor package may include a first internal voltage interconnect electrically connected between the at least one memory and the power supply circuit and electrically connected to the first external voltage interconnect.

[0235] When a power-on signal or an operation enable signal is received from the outside, the power supply circuit may set the first internal voltage interconnection to a high impedance state within a preset time.

[0236] A point at which the first internal voltage interconnection is connected to the at least one memory may be the same as a point at which the first external voltage interconnection is connected to the at least one memory.

[0237] The first internal driving voltage may be supplied through the first internal voltage interconnection, and may be fed back to the power supply circuit through the first external voltage interconnection.

[0238] When a voltage level fed back to the power supply circuit through the first external voltage interconnection is equal to or lower than a level of the first internal driving voltage, the power supply circuit may maintain output of the first internal driving voltage.

[0239] The semiconductor package may include a second external voltage interconnect electrically connected to a package ball electrically connected to the power management circuit, electrically connected to the power circuit, and electrically isolated from the at least one memory.

[0240] The power supply circuit may receive the second external driving voltage through the second external voltage interconnection and may output the first internal driving voltage by adjusting a level of the second external driving voltage.

[0241] The power supply circuit may receive an operation-ready signal from at least one memory, and may stop outputting the first internal driving voltage when a preset time elapses after a level of the operation-ready signal changes from a first level to a second level.

[0242] An electronic device based on an embodiment of the present disclosure may include: a semiconductor package; and a power management circuit configured to supply an external driving voltage through a package ball included in the semiconductor package, the semiconductor package including: at least one memory; a power circuit configured to supply an internal driving voltage to the at least one memory; a first external voltage interconnect electrically connected between the package ball electrically connected to the power management circuit and the at least one memory, and electrically connected to the power circuit; and a first internal voltage interconnect electrically connected between the power circuit and the at least one memory.

[0243] The first external voltage interconnect may be electrically connected to a first internal voltage interconnect external to the power supply circuit.

[0244] When the first external driving voltage is supplied to at least one memory through the first external voltage interconnection, the first internal voltage interconnection may be in a high impedance state.

[0245] Before the first external driving voltage is supplied to the at least one memory, the first internal voltage interconnection may be in a high impedance state for a preset time.

[0246] The semiconductor package may include a second internal voltage interconnect electrically connected between the power supply circuit and the at least one memory, and a second internal driving voltage may be supplied through the second internal voltage interconnect during at least a portion of a period in which the first internal voltage interconnect is in a high impedance state.

[0247] The semiconductor package may include a second external voltage interconnect electrically connected between a package ball electrically connected to the power management circuit and the power circuit, and may generate the second internal driving voltage using a second external driving voltage supplied through the second external voltage interconnect.

[0248] A power supply circuit based on an embodiment of the present disclosure may include: a voltage generation circuit configured to generate a first internal driving voltage; and a voltage output circuit electrically connected to a first external voltage interconnect and a first internal voltage interconnect, and configured to compare a voltage level of the first external voltage interconnect and a level of the first internal driving voltage, and when the voltage level of the first external voltage interconnect is equal to or higher than the level of the first internal driving voltage, set the first internal voltage interconnect to a high impedance state.

[0249] The voltage output circuit may output the first internal driving voltage to the first internal voltage interconnection when the voltage level of the first external voltage interconnection is lower than the level of the first internal driving voltage.

[0250] The power supply circuit may include a counter configured to operate when the level of an operation-ready signal received from the outside changes from a first level to a second level, and when a count value of the counter becomes a preset target value before the level of the operation-ready signal changes from the second level to the first level, generation or output of the first internal driving voltage may be stopped.

[0251] When a power-on signal or an operation enable signal is received from the outside, the voltage output circuit may set the first internal voltage interconnect to a high impedance state within a preset time.

[0252] The voltage generating circuit may receive a second external driving voltage through a second external voltage interconnection different from the first external voltage interconnection, and may generate the first internal driving voltage using the second external driving voltage.

[0253] The first external voltage interconnection and the first internal voltage interconnection may be electrically connected to each other externally.

[0254] A semiconductor device based on an embodiment of the present disclosure may include: at least one memory; a controller configured to control the operation of the at least one memory; and a power supply circuit configured to supply an internal driving voltage to the at least one memory and the controller, wherein the power supply circuit stops generating or outputting the internal driving voltage when a preset time passes after a level of an operation signal received from at least one of the at least one memory and the controller changes from a first level to a second level.

[0255] The power circuit may start generating the internal driving voltage when receiving the operation signal of the first level.

[0256] When the level of the operation signal changes from the second level to the first level before the preset time elapses, the power supply circuit may generate or output the sustain internal driving voltage.

[0257] The power supply circuit may include a counter that operates based on the operation signal, and when the operation signal is received, a count value of the counter may be set as a reference value.

[0258] The power supply circuit may maintain the count value of the counter at a reference value during a period in which the level of the operation signal is the first level.

[0259] When the level of the operation signal changes to the second level, the power supply circuit may start a counting operation of the counter, and when the count value of the counter reaches a preset target value, may stop generating or outputting the internal driving voltage.

[0260] The preset target value may be equal to or greater than a delay value according to an erase operation of the at least one memory.

[0261] When the level of the operation signal changes from the second level to the first level, the power supply circuit may set the count value of the counter to the reference value again.

[0262] A semiconductor device based on an embodiment of the present disclosure may include: at least one memory; and a power supply circuit configured to supply an internal driving voltage to the at least one memory, receive an operation-ready signal from the at least one memory, and stop supplying the internal driving voltage when a preset time passes after the level of the operation-ready signal changes from a first level to a second level.

[0263] A semiconductor device may include a package substrate on which at least one memory and a power supply circuit are disposed and includes a plurality of package balls, and the power supply circuit may be electrically connected to a first external voltage interconnect electrically connected to a first drive voltage package ball among the plurality of package balls, may be electrically connected to a second external voltage interconnect electrically connected to a second drive voltage package ball, and may generate an internal drive voltage using an external drive voltage input through the second external voltage interconnect.

[0264] The second driving voltage package ball may be electrically connected to a power management circuit located externally, and the first driving voltage package ball may be electrically isolated from the power management circuit.

[0265] The first external voltage interconnection may connect the power supply circuit and the at least one memory, and may be electrically connected to the first internal voltage interconnection to which the internal driving voltage is supplied.

[0266] The first internal voltage interconnection may be set to a high impedance state when a power-on signal is received from the outside, and a voltage level of the first internal voltage interconnection may rise when an operation-ready signal of a first level is received.

[0267] An electronic device based on an embodiment of the present disclosure may include: a semiconductor package; and a power management circuit configured to supply an external driving voltage to the semiconductor package, the semiconductor package including: at least one memory; and a power circuit configured to generate an internal driving voltage using the external driving voltage, supply the internal driving voltage to the at least one memory, and stop supplying the internal driving voltage based on the operating state of the at least one memory during at least one period other than an active period of the at least one memory.

[0268] The power circuit may stop generating or outputting the internal driving voltage when a preset time elapses after a level of an operation enable signal received from a controller located inside or outside the semiconductor package changes from a first level to a second level.

[0269] The power supply circuit may stop generating or outputting the internal driving voltage when a preset time elapses after a level of the operation enable signal received from the at least one memory is changed from a first level to a second level.

[0270] The preset time may be equal to or longer than a delay time according to an erase operation of the at least one memory.

[0271] The semiconductor package may include dummy package balls that are electrically isolated from the power management circuit and electrically connected to the power circuit.

[0272] The dummy package balls may be electrically connected to the at least one memory.

[0273] The dummy package balls may be electrically connected to interconnections through which an internal driving voltage is supplied to the at least one memory.

[0274] A power supply circuit based on an embodiment of the present disclosure may include: a voltage generating circuit configured to generate an internal driving voltage using an external driving voltage; and a voltage output circuit configured to output the internal driving voltage based on an operation signal received from the outside, and stop outputting the internal driving voltage when a preset time has passed after the level of the operation signal changes from a first level to a second level.

[0275] The voltage output circuit may receive an operating signal from the semiconductor die and may provide an internal driving voltage to the semiconductor die.

[0276] The voltage output circuit may output a first internal driving voltage to the first semiconductor die, may output a second internal driving voltage to the second semiconductor die, and may control the output of the first internal driving voltage based on an operation signal received from the second semiconductor die.

[0277] Although various embodiments of the present disclosure have been described with specific details and variations for illustrative purposes, it will be understood by those skilled in the art that various modifications, additions, and substitutions may be made based on the contents disclosed or described in the present disclosure without departing from the spirit and scope of the present disclosure as defined in the appended claims. Furthermore, the embodiments may be combined to form further embodiments.

Claims

1. A semiconductor device comprising: a package substrate comprising a plurality of package balls; at least one memory electrically connected to a first driving voltage package ball among the plurality of package balls through a first external voltage interconnect; as well as A power supply circuit is electrically connected to the first drive voltage package ball through the first external voltage interconnect, is electrically connected to the at least one memory through a first internal voltage interconnect, and adjusts a voltage state of the first internal voltage interconnect based on a voltage level of the first drive voltage package ball.

2. The semiconductor device according to claim 1, wherein The power supply circuit: generating a first internal driving voltage; as well as When the voltage level of the first driving voltage package ball is equal to or higher than the level of the first internal driving voltage, or when the voltage level of the first driving voltage package ball is equal to or higher than a reference level, the first internal voltage interconnect is set to a high impedance state.

3. The semiconductor device according to claim 1, wherein When a first external driving voltage is supplied to the at least one memory through the first external voltage interconnection, the first internal voltage interconnection is in a high impedance state.

4. The semiconductor device according to claim 1, wherein The power supply circuit: generating a first internal driving voltage; as well as When the voltage level of the first driving voltage package ball is lower than the level of the first internal driving voltage, or when the voltage level of the first driving voltage package ball is lower than a reference level, the first internal driving voltage is output to the first internal voltage interconnection.

5. The semiconductor device according to claim 1, wherein When the first internal driving voltage generated by the power supply circuit is supplied to the first internal voltage interconnection, a voltage level of the first internal voltage interconnection is higher than a voltage level of the first external voltage interconnection. The semiconductor device according to claim 1 , wherein: The power circuit is electrically connected to a second driving voltage package ball among the plurality of package balls through a second external voltage interconnection, and generates a first internal driving voltage to be supplied to the first internal voltage interconnection based on a second external driving voltage received through the second external voltage interconnection.

7. The semiconductor device according to claim 6, wherein The power supply circuit generates the first internal driving voltage by increasing a voltage level of the second external driving voltage, and generates the second internal driving voltage by decreasing a voltage level of the second external driving voltage.

8. The semiconductor device according to claim 7, wherein The power supply circuit supplies the second internal driving voltage through a second internal voltage interconnect electrically connected to the at least one memory and electrically isolated from the second external voltage interconnect.

9. The semiconductor device according to claim 1, wherein When a power-on signal or an operation enable signal is received from the outside, the power supply circuit sets the first internal voltage interconnect to a high impedance state within a preset time.

10. The semiconductor device according to claim 1, wherein The first external voltage interconnect is electrically connected to the first internal voltage interconnect.

11. The semiconductor device according to claim 1, wherein The first external voltage interconnect is connected to the at least one memory through the first internal voltage interconnect.

12. The semiconductor device according to claim 1, wherein A point at which the first external voltage interconnect is connected to the power circuit is located between a point at which the first external voltage interconnect is connected to the first driving voltage package ball and a point at which the first external voltage interconnect is connected to the at least one memory.

13. The semiconductor device according to claim 1, wherein The voltage output through the first internal voltage interconnect is fed back to the power supply circuit through the first external voltage interconnect.

14. The semiconductor device according to claim 1, wherein The power supply circuit comprises: a voltage generator that generates a first internal driving voltage; and a comparator that compares the first internal drive voltage with a voltage input through the first external voltage interconnection to determine an output voltage, and The power controller: receiving an operation-ready signal from the at least one memory; and When a preset time passes after the level of the operation-ready signal changes from the first level to the second level, the generation or output of the first internal driving voltage is stopped.

15. An electronic device comprising: semiconductor packaging; as well as a power management circuit that supplies an external driving voltage through package balls included in the semiconductor package, Wherein, the semiconductor package comprises: at least one memory; a power supply circuit for supplying an internal driving voltage to the at least one memory; and A first external voltage interconnect is electrically connected to the at least one memory and the power circuit and is electrically connected to a package ball that is electrically isolated from the power management circuit.

16. The electronic device according to claim 15, wherein The semiconductor package further includes a first internal voltage interconnect electrically connected between the at least one memory and the power supply circuit and electrically connected to the first external voltage interconnect.

17. The electronic device according to claim 16, wherein: When a power-on signal or an operation enable signal is received from the outside, the power supply circuit sets the first internal voltage interconnect to a high impedance state within a preset time.

18. The electronic device according to claim 16, wherein: supplying a first internal drive voltage via the first internal voltage interconnect; feeding back the first internal drive voltage to the power supply circuit via the first external voltage interconnect, and When a voltage level fed back to the power supply circuit through the first external voltage interconnection is equal to or lower than a level of the first internal driving voltage, the power supply circuit maintains output of the first internal driving voltage.

19. The electronic device according to claim 18, wherein: The semiconductor package further includes a second external voltage interconnect electrically connected to a package ball, the package ball electrically connected to the power management circuit, electrically connected to the power circuit and electrically isolated from the at least one memory, and The power supply circuit: receiving a second external drive voltage via the second external voltage interconnect; as well as The first internal driving voltage is outputted by adjusting the level of the second external driving voltage.

20. An electronic device comprising: semiconductor packaging; as well as a power management circuit that supplies an external driving voltage through package balls included in the semiconductor package, Wherein, the semiconductor package comprises: at least one memory; a power supply circuit for supplying an internal driving voltage to the at least one memory; a first external voltage interconnect electrically connected between a package ball electrically connected to the power management circuit and the at least one memory, and electrically connected to the power circuit; and A first internal voltage interconnect is electrically connected between the power supply circuit and the at least one memory.

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