Storage unit, memory, storage method and vehicle
The polarization flip of the semiconductor layer is achieved through light triggering, which solves the problems of large power consumption and slow response speed of existing memory and improves the writing speed.
Patent Information
- Application Number
- CN202411380222.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2025-08-12
AI Technical Summary
The triggering method of existing memories is voltage triggering, which leads to large power consumption and limited response speed, limiting the write speed.
The light triggering method is used instead of voltage triggering, and polarization flips are achieved through the semiconductor layer under the action of the light source to record the logic value.
Reduces power consumption and significantly improves write speed.
Smart Images
Figure CN120472964A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of storage technology, and in particular to a storage unit, a memory, a storage method and a vehicle. Background Art
[0002] In the related art, the memory is triggered by voltage. Voltage-triggered memory consumes a lot of power and has a limited response speed, which greatly limits the writing speed of the memory. Summary of the Invention
[0003] The embodiments of the present application provide a storage unit, a memory, a storage method and a vehicle, which replace voltage triggering with light triggering, thereby improving the writing speed of the memory to at least partially solve the above-mentioned technical problems.
[0004] In order to achieve the above-mentioned object, according to a first aspect of the present application, a storage unit is provided, comprising:
[0005] a semiconductor layer having a crystalline structure, capable of spontaneous polarization and polarization reversal under the action of a first light source;
[0006] A source electrode and a drain electrode are spaced apart and arranged on the semiconductor layer;
[0007] The semiconductor layer has a polarization state and a polarization reversal state, and the storage unit is configured to record a first logic value when the semiconductor layer is in the polarization state, and to record a second logic value when the semiconductor layer is in the polarization reversal state.
[0008] Optionally, in the polarization state, the semiconductor layer has a first resistance value, and in the polarization reversal state, the semiconductor layer has a second resistance value, and the resistance value is different from the second resistance value.
[0009] Optionally, the storage unit further includes:
[0010] a light-triggered layer capable of generating photoelectrons under the action of a second light source, wherein the semiconductor layer is stacked on the light-triggered layer to receive the photoelectrons, and wherein the semiconductor layer can also undergo polarization reversal under the action of the photoelectrons, wherein the direction of polarization reversal of the semiconductor layer by the photoelectrons is opposite to the direction of polarization reversal of the semiconductor layer by the first light source, so that the semiconductor layer switches from the polarization reversal state to the polarization state;
[0011] Wherein, the wavelength of the second light source is smaller than the wavelength of the first light source.
[0012] Optionally, the semiconductor layer includes a two-dimensional ferroelectric material layer.
[0013] Optionally, the light-triggered layer includes a perovskite light-triggered layer.
[0014] According to a second aspect of the present application, a memory is provided, comprising:
[0015] grassroots;
[0016] The storage unit as described above;
[0017] There are at least two storage units, and each storage unit is stacked on the base layer.
[0018] Optionally, the memory further includes:
[0019] a first light source, for irradiating the semiconductor layer;
[0020] a second light source, for illuminating the light-triggering layer of the storage unit;
[0021] Wherein, the wavelength of the second light source is smaller than the wavelength of the first light source.
[0022] Optionally, the wavelength of the first light source is λ1, which satisfies the following condition: λ1>400 nanometers.
[0023] Optionally, the wavelength of the second light source is λ2, which satisfies: 10 nanometers ≤ λ2 ≤ 400 nanometers.
[0024] Optionally, each of the memory cells corresponds to one source and one drain, or two adjacent memory cells correspond to one source and one drain.
[0025] According to a third aspect of the present application, a storage method is further provided, which is applied to the aforementioned memory, and the storage method includes:
[0026] In response to the semiconductor layer being in a polarization state, the memory records a first logic value; in response to the semiconductor layer being in a polarization-reversed state, the memory records a second logic value.
[0027] According to a fourth aspect of the present application, a vehicle is also provided, comprising the memory as described above.
[0028] In the storage unit, memory, storage method and vehicle of the embodiments of the present application, polarization reversal of the semiconductor layer is achieved by illumination by a first light source, which can reduce power consumption compared to the related art in which polarization reversal is achieved by voltage. Moreover, since the response time of illumination is much greater than the response time of voltage, the writing speed can be greatly improved.
[0029] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.
[0031] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.
[0032] Figure 1 is a schematic structural diagram of a storage unit provided in an exemplary embodiment of the present disclosure;
[0033] Figure 2 is one of the structural diagrams of a memory provided in an exemplary embodiment of the present disclosure;
[0034] Figure 3 This is the second structural diagram of the memory provided in the exemplary embodiment of the present disclosure;
[0035] Figure 4 is a correspondence table between the first light source and the second light source and the semiconductor layer state provided in an exemplary embodiment of the present disclosure.
[0036] Description of reference numerals:
[0037] 10. Source;
[0038] 20. Drain;
[0039] 30. Semiconductor layer;
[0040] 40. Light triggering layer;
[0041] 50. Grassroots. DETAILED DESCRIPTION
[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.
[0043] According to the first aspect of this application, referring to Figures 1 to 4The present disclosure provides a memory cell. The memory cell includes a source electrode 10, a drain electrode 20, and a semiconductor layer 30. The semiconductor layer 30 has a crystalline structure. The semiconductor layer 30 can be spontaneously polarized and polarization-reversed under the action of a first light source. The source electrode 10 and the drain electrode 20 are spaced apart on the semiconductor layer 30. The semiconductor layer 30 has a polarization state and a polarization-reversed state. The memory cell is configured to record a first logic value when the semiconductor layer 30 is in a polarization state, and to record a second logic value when the semiconductor layer 30 is in a polarization-reversed state.
[0044] In the embodiment of the present application, polarization reversal of the semiconductor layer 30 is achieved by illumination by the first light source. Compared with the related art in which polarization reversal is achieved by voltage, power consumption can be reduced. Moreover, since the response time of illumination is much longer than the response time of voltage, the writing speed can be greatly improved.
[0045] The semiconductor layer 30 in the embodiment of the present application has the characteristic of spontaneous polarization, and can be polarized and reversed under the action of the first light source. Specifically, under the action of the first light source, the positions of the positive ions and negative ions in the semiconductor layer 30 in the lattice are no longer completely symmetrical. That is, ion dislocation occurs in the semiconductor layer 30, causing lattice distortion, thereby forming an electrostatic charge distribution. Thus, an electric dipole can be formed under the action of ion dislocation and electronic polarization. The first light source acts directly on the semiconductor layer 30 as an alternating electromagnetic wave, which can induce electric polarization in the semiconductor layer 30. Since the frequency of the first light source is relatively high, the electric dipole cannot change with the light field, and the ferroelectric photovoltaic effect based on the semiconductor layer 30 affects the electric polarization, thereby being able to directly produce spatial charge separation and achieve polarization reversal.
[0046] The semiconductor layer 30 may have a preset logic value. The preset logic value may be "0" or "1". The first logic value may be "0" and the second logic value may be "1". Alternatively, the first logic value may be "1" and the second logic value may be "0".
[0047] If the first logic value is "0" and the second logic value is "1," when the semiconductor layer 30 switches from a polarization state to a polarization-reversed state under the influence of the first light source, the semiconductor layer 30 stores the data as a logic value of 1, thereby enabling data writing. After storage, the data can be output, enabling data reading. When the semiconductor layer 30 is not exposed to the first light source, the semiconductor layer 30 remains in a polarization state, and the semiconductor layer 30 stores the data as a logic value of 0, thereby enabling data writing. After storage, the data can be output, enabling data reading.
[0048] If the first logic value is "1" and the second logic value is "0," when the semiconductor layer 30 switches from its polarization state to its polarization-reversed state under the influence of the first light source, the semiconductor layer 30 stores the data as a logic value of 0, enabling data writing. After storage, the data can be output, enabling data reading. When the semiconductor layer 30 is not exposed to the first light source, the semiconductor layer 30 remains in its polarization state, and the semiconductor layer 30 stores the data as a logic value of 1, enabling data writing. After storage, the data can be output, enabling data reading.
[0049] One memory cell only stores one data, that is, the semiconductor layer 30 of one memory cell only stores one "0" or one "1".
[0050] In the embodiment of the present application, the source electrode 10 is disposed on a side of the semiconductor layer 30 away from the light-triggered layer 40 and is configured to be connected to a signal output terminal. The drain electrode 20 is disposed on a side of the semiconductor layer 30 away from the light-triggered layer 40 and is configured to be connected to a load. The source electrode 10 and the drain electrode 20 are spaced apart.
[0051] It is understood that each memory has a source 10 and a drain 20. When the first light source and / or the second light source is applied, a conductive channel can be formed between the source 10 and the drain 20. Electrons or holes can flow in the conductive channel, thereby realizing a switching function.
[0052] In some embodiments, in the polarized state, the semiconductor layer 30 has a first resistance value, and in the polarization-reversed state, the semiconductor layer 30 has a second resistance value that is different from the second resistance value.
[0053] It is understood that the polarization state of the semiconductor layer 30 corresponds to a first logic value, and the polarization reversal state of the semiconductor layer 30 corresponds to a second logic value. The two logic values can be specifically embodied in the form of resistance. Specifically, in the polarization state, the memory cell stores and / or outputs the first logic value, corresponding to the semiconductor layer 30 being at the first resistance value. In the polarization reversal state, the memory cell stores and / or outputs the second logic value, corresponding to the semiconductor layer 30 being at the second resistance value.
[0054] The semiconductor layer 30 in the embodiment of the present application stores data by means of resistance. Since the resistance of the semiconductor layer 30 is non-volatile, the logic calculation function of the storage unit is also non-volatile.
[0055] In some embodiments, the first resistance value is greater than the second resistance value. At this time, the semiconductor layer 30 in the polarized state corresponds to the semiconductor layer 30 being in a high resistance state, and the semiconductor layer 30 in the polarization reversal state corresponds to the semiconductor layer 30 being in a low resistance state.
[0056] In some embodiments, the first resistance value is less than the second resistance value. At this time, the semiconductor layer 30 in the polarized state corresponds to the semiconductor layer 30 being in a low resistance state, and the semiconductor layer 30 in the polarization reversal state corresponds to the semiconductor layer 30 being in a high resistance state.
[0057] In some embodiments, the semiconductor layer 30 may be in a high resistance state corresponding to a logic value “1” stored in the semiconductor layer 30 , and the semiconductor layer 30 may be in a low resistance state corresponding to a logic value “0” stored in the semiconductor layer 30 .
[0058] In some embodiments, the semiconductor layer 30 may be in a high resistance state corresponding to a logic value “0” stored in the semiconductor layer 30 , and the semiconductor layer 30 may be in a low resistance state corresponding to a logic value “1” stored in the semiconductor layer 30 .
[0059] like Figure 1 As shown, in some embodiments, the storage unit further includes a photo-triggered layer 40. The photo-triggered layer 40 can generate photoelectrons under the influence of a second light source. The semiconductor layer 30 is superimposed on the photo-triggered layer 40 to receive the photoelectrons. The semiconductor layer 30 can also undergo polarization flipping under the influence of the photoelectrons. The direction of polarization flipping of the semiconductor layer 30 by the photoelectrons is opposite to the direction of polarization flipping of the semiconductor layer 30 by the first light source, causing the semiconductor layer 30 to switch from a polarization flipped state to a polarized state. The wavelength of the second light source is shorter than that of the first light source.
[0060] It is understood that the semiconductor layer 30 can be switched from its polarization state to a polarization reversal state by illumination from the first light source, and can also be switched from its polarization reversal state to its polarization state by photoelectrons provided by the light triggering layer 40. Based on the access to the light triggering layer 40 and the second light source, the storage unit can be endowed with computing capabilities, capable of performing basic logical operations, thus achieving integrated storage and computing capabilities.
[0061] The second light source acts on the light-triggering layer 40 to generate photoelectrons. These photoelectrons can only switch the semiconductor layer 30 from a polarization-reversed state to a polarized state, but cannot switch the semiconductor layer 30 from a polarization state to a polarization-reversed state. Therefore, when the first light source is not acting on the semiconductor layer 30, the semiconductor layer 30 remains in a polarized state under the influence of the light-triggering layer 40 and the second light source.
[0062] For example, the first logic value can be "0" and the second logic value can be "1." After the semiconductor layer 30 switches from its polarization state to its polarization-reversed state under the action of the first light source, if the second light source is not applied to the light-triggered layer 40, the semiconductor layer 30 remains in the polarization-reversed state, and the semiconductor layer 30 stores a logic value of 1. After the semiconductor layer 30 switches from its polarization state to its polarization-reversed state under the action of the first light source, if the second light source is applied to the light-triggered layer 40, causing the light-triggered layer 40 to generate photoelectrons and inject them into the semiconductor layer 30, the semiconductor layer 30 switches from the polarization-reversed state to the polarization state, and the semiconductor layer 30 stores a logic value of 0. When the semiconductor layer 30 is not applied by the first light source, the semiconductor layer 30 remains in its polarization state. At this time, regardless of whether the second light source is applied to the light-triggered layer 40, the semiconductor layer 30 stores a logic value of 0.
[0063] For example, the first logic value can be "1" and the second logic value can be "0." After the semiconductor layer 30 switches from its polarization state to its polarization-reversed state under the action of the first light source, if the second light source is not applied to the light-triggered layer 40, the semiconductor layer 30 remains in the polarization-reversed state, and the semiconductor layer 30 stores a logic value of 0. After the semiconductor layer 30 switches from its polarization state to its polarization-reversed state under the action of the first light source, if the second light source is applied to the light-triggered layer 40, causing the light-triggered layer 40 to generate photoelectrons and inject them into the semiconductor layer 30, the semiconductor layer 30 switches from its polarization-reversed state to its polarization state, and the semiconductor layer 30 stores a logic value of 1. When the semiconductor layer 30 is not applied by the first light source, the semiconductor layer 30 remains in its polarization state. At this time, regardless of whether the second light source is applied to the light-triggered layer 40, the semiconductor layer 30 stores a logic value of 1.
[0064] The light triggering layer 40 can generate photoelectrons under the irradiation of the second light source. The light triggering layer 40 and the semiconductor layer 30 are attached to each other, so that the photoelectrons can be injected into the semiconductor layer 30.
[0065] In the present application, the wavelengths of the first light source and the second light source are different, so that the first light source can only act on the semiconductor layer 30 and the second light source can only act on the light triggering layer 40 .
[0066] The first light source is visible light or infrared light, and the second light source is ultraviolet light.
[0067] like Figure 4 As shown, in some embodiments, when the semiconductor layer 30 is in a polarized state, the semiconductor layer 30 is not illuminated by the first light source. Alternatively, the semiconductor layer 30 is illuminated by the first light source, and the light triggering layer 40 is illuminated by the second light source.
[0068] It is understandable that since photoelectrons can only switch the semiconductor layer 30 from a polarization reversal state to a polarization state, they cannot switch the semiconductor layer 30 from a polarization state to a polarization reversal state. Therefore, when the first light source acts on the semiconductor layer 30, the semiconductor layer 30 remains in a polarization state under the action of the light triggering layer 40 and the second light source. After the first light source acts on the semiconductor layer 30, the semiconductor layer 30 switches from a polarization state to a polarization reversal state. At this time, using the second light source to act on the light triggering layer 40, the light triggering layer 40 can generate photoelectrons and inject them into the semiconductor layer 30. At this time, the photoelectrons can drive the semiconductor layer 30 to switch from a polarization reversal state to a polarization state.
[0069] like Figure 4 As shown, in some embodiments, when the semiconductor layer 30 is in a polarization-reversed state, the semiconductor layer 30 is irradiated by a first light source, and the light-triggered layer 40 is not irradiated by a second light source.
[0070] It is understood that when the first light source acts on the semiconductor layer 30, the semiconductor layer 30 switches from a polarized state to a polarization-reversed state. At this point, if the second light source is not acting on the light-triggered layer 40, the light-triggered layer 40 will not generate photoelectrons, and the semiconductor layer 30 will remain in the polarization-reversed state.
[0071] When a first light source illuminates the semiconductor layer 30, it switches from a polarized state to a polarization-reversed state. After the first light source is removed, the state of the semiconductor layer 30 does not switch, remaining in the polarization-reversed state. When a second light source illuminates the light-triggered layer 40, it injects photoelectrons into the semiconductor layer 30, switching the semiconductor layer 30 from the polarization-reversed state to the polarized state. After the second light source is removed, the state of the semiconductor layer 30 does not switch, remaining in the polarized state. Consequently, once data is stored, there is no need for regular updates.
[0072] In the embodiments of the present application, the first and second light sources induce differences in the potential distribution of semiconductor layer 30 under different polarization states. When polarization flips in semiconductor layer 30, the equivalent height and width of the tunneling barrier change, corresponding to a change in the resistance of semiconductor layer 30, i.e., a change from a high-resistance state to a low-resistance state. Thus, the first and second light sources can be used to achieve non-volatile switching of the high-resistance and low-resistance states of the memory cell, corresponding to the memory programming process.
[0073] When the first light source is not irradiated, the electric dipoles of the semiconductor layer 30 are randomly distributed in different directions. At this time, the sum of the electric dipole moments is zero and the electric polarization intensity is zero. When the first light source and / or the second light source are irradiated, the electric dipoles of the semiconductor layer 30 are acted upon by light, so that the directions of the electric dipoles are rotated and remain consistent. At this time, the polarization intensity increases. When the electric dipoles in the semiconductor layer 30 are fully oriented and reach a saturated state, the polarization intensity will no longer be affected by the light source change. At this time, after the first light source is turned off, the electric dipoles in the semiconductor layer 30 show a hysteresis behavior, i.e., the original direction rotates, completing the reversal of the ferroelectric polarization, and this reversal does not make it return to its initial state.
[0074] Based on the above principle, the semiconductor layer 30 realizes the storage function under the action of the first light source.
[0075] When the semiconductor layer 30 is in a polarization-flipped state, if a second light source illuminates the light-triggered layer 40, the light-triggered layer 40 can generate photoelectrons and inject them into the semiconductor layer 30. At this point, the semiconductor layer 30 can undergo polarization flipping under the influence of the photoelectrons, and the flipping direction under the influence of the photoelectrons is opposite to the flipping direction under the influence of the first light source, thereby enabling the semiconductor layer 30 to switch from the polarization-flipped state to the polarization-flipped state. This provides computing power to the storage unit, and the switching between the polarization-flipped state and the polarization-flipped state can be controlled based on the on / off selection of the second light, realizing the storage unit's integrated computing and storage capabilities.
[0076] In some embodiments, semiconductor layer 30 includes a two-dimensional ferroelectric material layer.
[0077] The use of a two-dimensional ferroelectric semiconductor layer allows the semiconductor layer 30 to undergo spontaneous ferroelectric polarization, ensuring its spontaneous polarization. Furthermore, two-dimensional ferroelectric materials possess semiconducting properties, enabling integration with mainstream semiconductor processes. Their ultra-thin nature provides significant advantages in memory device miniaturization, significantly increasing memory integration.
[0078] For example, the semiconductor layer 30 can be made of a two-dimensional ferroelectric material with in-plane polarization. This allows for a device configuration in which a metal-semiconductor-metal stack is vertically arranged, thereby improving its integration. Alternatively, the semiconductor layer 30 can be made of a ferroelectric material with out-of-plane polarization. This allows for a short-channel planar device configuration, thereby improving its integration.
[0079] In related art, the gate of a memory device is typically 10 microns thick. In the embodiment of the present application, the thickness of the semiconductor layer 30 is nanometers, which significantly reduces the thickness of the semiconductor layer 30 and reduces the overall thickness of the memory device. For example, it can be set to 1-100 nanometers.
[0080] For example, two-dimensional ferroelectric semiconductor layers are made of materials such as SnSe (tin selenide), SnTe (tin telluride), and WTe2 (tungsten ditelluride). This results in a large number of free electrons within the two-dimensional ferroelectric semiconductor layer, resulting in a low polarization intensity and a high depolarization field. Furthermore, the Coulomb screening effect of the two-dimensional ferroelectric semiconductor layer is weak, and the exciton effect is more pronounced, enabling the control of polarization by an external light field.
[0081] In some embodiments, the photo-triggered layer 40 includes a perovskite photo-triggered layer.
[0082] Based on the light triggering layer 40 being set as a perovskite light triggering layer, it can have both light absorption and insulating properties. On the one hand, the light triggering layer 40 with light absorption properties can absorb ultraviolet light and generate photoelectrons under the irradiation of ultraviolet light. The photoelectrons can be injected into the semiconductor layer 30, thereby affecting the electric polarization of the semiconductor (i.e., switching the semiconductor layer 30 from a polarized state to a polarization reversal state, or keeping the semiconductor in a polarized state). On the other hand, the light triggering layer 40 with insulating properties can also provide insulating protection for the semiconductor layer 30.
[0083] In the embodiment of the present application, based on the material selection of the semiconductor layer 30 and the light-triggered layer 40, the area and volume of the memory can be greatly reduced, and the integration of the memory can be improved, which can break through the capacity bottleneck of the current memory.
[0084] According to a second aspect of the present disclosure, a memory is provided, comprising the above-mentioned storage unit. The memory has all the beneficial effects of the above-mentioned storage unit, which will not be described in detail in this disclosure.
[0085] like Figure 2 As shown, in some embodiments, the memory further includes a base layer 50. There are at least two memory cells, each of which is stacked on the base layer 50.
[0086] It is understandable that, since each storage unit only stores one logic value, the storage unit only stores one data. Based on the need to store a large amount of data, the storage unit is set to at least two to achieve sufficient memory.
[0087] like Figure 3 As shown, in some embodiments, each two adjacent storage cells are spaced apart. The spacing between each two adjacent storage cells can be the same or different. In the embodiments of the present application, it is preferred that the spacing between each two adjacent storage cells is the same to facilitate the production of the memory. The spacing between each two adjacent storage cells is selected based on actual conditions.
[0088] For example, every two adjacent storage units are distributed in a matrix, or every two adjacent storage units are distributed in an interval-like disordered manner.
[0089] In some embodiments, at least two memory cells are disposed in series. For example, at least two memory cells are sequentially connected on the base layer 50 to form a square or rectangular shape.
[0090] In some embodiments, the memory further includes a first light source and a second light source. The first light source is used to illuminate the semiconductor layer 30. The second light source is used to illuminate the light triggering layer 40. The wavelength of the second light source is smaller than that of the first light source.
[0091] It is understood that the first light source is used to illuminate the semiconductor layer 30, causing the semiconductor layer 30 to switch from a polarization state to a polarization reversal state based on a light triggering method. The second light source is used to illuminate the light triggering layer 40, causing the light triggering layer 40 to generate photoelectrons and inject them into the semiconductor layer 30, thereby switching the semiconductor layer 30 from a polarization reversal state to a polarization state. In this way, the memory achieves integrated storage and computing.
[0092] In some embodiments, the wavelength of the first light source is λ1, which satisfies: λ1>400 nanometers.
[0093] Specifically, the first light source is visible light and / or infrared light. The wavelength of visible light is λ1x, satisfying the following: 400 nanometers < λ1x ≤ 740 nanometers. The wavelength of infrared light is λ1y, satisfying the following: λ1y > 740 nanometers. For example, the first light source is red light, green light, or natural light. Alternatively, the first light source is infrared light. Alternatively, the first light source is a mixed light source of visible light and infrared light.
[0094] In some embodiments, the wavelength of the second light source is λ2, which satisfies: 10 nanometers ≤ λ2 ≤ 400 nanometers.
[0095] Specifically, the second light source is ultraviolet light.
[0096] In some embodiments, each memory cell corresponds to a source 10 and a drain 20 , or two adjacent memory cells correspond to a source 10 and a drain 20 .
[0097] It can be understood that each memory cell corresponds to a source electrode 10 and a drain electrode 20, which can facilitate memory manufacturing. Stacking a source electrode 10 and a drain electrode 20 on each memory cell facilitates standardized mass production. Two adjacent memory cells correspond to a source electrode 10 and a drain electrode 20, so the two adjacent memory cells share a single source electrode 10 and a single drain electrode 20. This reduces memory production costs and allows for a miniaturized, integrated design.
[0098] According to a third aspect of the present disclosure, a storage method is provided, which is applied to the aforementioned memory, and the storage method includes:
[0099] In response to the semiconductor layer 30 being in the polarization state, the memory records a first logic value. In response to the semiconductor layer 30 being in the polarization-reversed state, the memory records a second logic value.
[0100] The semiconductor layer 30 may have a preset logic value. The preset logic value may be "0" or "1". The first logic value may be "0" and the second logic value may be "1". Alternatively, the first logic value may be "1" and the second logic value may be "0".
[0101] If the first logic value is "0" and the second logic value is "1," when the semiconductor layer 30 switches from a polarization state to a polarization-reversed state under the influence of the first light source, the semiconductor layer 30 stores the data as a logic value of 1, thereby enabling data writing. After storage, the data can be output, enabling data reading. When the semiconductor layer 30 is not exposed to the first light source, the semiconductor layer 30 remains in a polarization state, and the semiconductor layer 30 stores the data as a logic value of 0, thereby enabling data writing. After storage, the data can be output, enabling data reading.
[0102] If the first logic value is "1" and the second logic value is "0," when the semiconductor layer 30 switches from its polarization state to its polarization-reversed state under the influence of the first light source, the semiconductor layer 30 stores the data as a logic value of 0, enabling data writing. After storage, the data can be output, enabling data reading. When the semiconductor layer 30 is not exposed to the first light source, the semiconductor layer 30 remains in its polarization state, and the semiconductor layer 30 stores the data as a logic value of 1, enabling data writing. After storage, the data can be output, enabling data reading.
[0103] In some embodiments, in the polarized state, the semiconductor layer 30 has a first resistance value, and in the polarization-reversed state, the semiconductor layer 30 has a second resistance value that is different from the second resistance value.
[0104] It is understood that the polarization state of the semiconductor layer 30 corresponds to a first logic value, and the polarization reversal state of the semiconductor layer 30 corresponds to a second logic value. The two logic values can be specifically embodied in the form of resistance. Specifically, in the polarization state, the semiconductor layer 30 stores and / or outputs the first logic value, corresponding to the semiconductor layer 30 being at a first resistance value. In the polarization reversal state, the semiconductor layer 30 stores and / or outputs the second logic value, corresponding to the semiconductor layer 30 being at a second resistance value.
[0105] The semiconductor layer 30 in the embodiment of the present application stores data by means of resistance. Since the resistance of the semiconductor layer 30 is non-volatile, the logic calculation function of the storage unit is also non-volatile.
[0106] In some embodiments, the first resistance value is greater than the second resistance value. At this time, the semiconductor layer 30 in the polarized state corresponds to the semiconductor layer 30 being in a high resistance state, and the semiconductor layer 30 in the polarization reversal state corresponds to the semiconductor layer 30 being in a low resistance state.
[0107] In some embodiments, the first resistance value is less than the second resistance value. At this time, the semiconductor layer 30 in the polarized state corresponds to the semiconductor layer 30 being in a low resistance state, and the semiconductor layer 30 in the polarization reversal state corresponds to the semiconductor layer 30 being in a high resistance state.
[0108] In some embodiments, the semiconductor layer 30 may be in a high resistance state corresponding to a logic value “1” stored in the semiconductor layer 30 , and the semiconductor layer 30 may be in a low resistance state corresponding to a logic value “0” stored in the semiconductor layer 30 .
[0109] In some embodiments, the semiconductor layer 30 may be in a high resistance state corresponding to a logic value “0” stored in the semiconductor layer 30 , and the semiconductor layer 30 may be in a low resistance state corresponding to a logic value “1” stored in the semiconductor layer 30 .
[0110] In some embodiments, the semiconductor layer 30 is in a polarized state when the following conditions are met:
[0111] The semiconductor layer 30 is not illuminated by the first light source. Alternatively, the semiconductor layer 30 is illuminated by the first light source, and the light triggering layer 40 stacked with the semiconductor layer 30 is illuminated by the second light source.
[0112] It is understandable that the second light source acts on the light triggering layer 40 to generate photoelectrons. These photoelectrons can only cause the semiconductor layer 30 to switch from a polarization reversal state to a polarized state, but cannot cause the semiconductor layer 30 to switch from a polarization state to a polarization reversal state. Because photoelectrons can only cause the semiconductor layer 30 to switch from a polarization reversal state to a polarized state, but cannot cause the semiconductor layer 30 to switch from a polarization state to a polarization reversal state. Therefore, when the first light source acts on the semiconductor layer 30, the semiconductor layer 30 remains in a polarized state under the action of the light triggering layer 40 and the second light source. After the first light source acts on the semiconductor layer 30, the semiconductor layer 30 switches from a polarization state to a polarization reversal state. At this time, using the second light source to act on the light triggering layer 40, the light triggering layer 40 can generate photoelectrons and inject them into the semiconductor layer 30. At this time, the photoelectrons can drive the semiconductor layer 30 to switch from a polarization reversal state to a polarized state.
[0113] For example, the first logic value can be "0" and the second logic value can be "1." After the semiconductor layer 30 switches from its polarization state to its polarization-reversed state under the action of the first light source, if the second light source is not applied to the light-triggered layer 40, the semiconductor layer 30 remains in the polarization-reversed state, and the semiconductor layer 30 stores a logic value of 1. After the semiconductor layer 30 switches from its polarization state to its polarization-reversed state under the action of the first light source, if the second light source is applied to the light-triggered layer 40, causing the light-triggered layer 40 to generate photoelectrons and inject them into the semiconductor layer 30, the semiconductor layer 30 switches from the polarization-reversed state to the polarization state, and the semiconductor layer 30 stores a logic value of 0. When the semiconductor layer 30 is not applied by the first light source, the semiconductor layer 30 remains in its polarization state. At this time, regardless of whether the second light source is applied to the light-triggered layer 40, the semiconductor layer 30 stores a logic value of 0.
[0114] For example, the first logic value can be "1" and the second logic value can be "0." After the semiconductor layer 30 switches from its polarization state to its polarization-reversed state under the action of the first light source, if the second light source is not applied to the light-triggered layer 40, the semiconductor layer 30 remains in the polarization-reversed state, and the semiconductor layer 30 stores a logic value of 0. After the semiconductor layer 30 switches from its polarization state to its polarization-reversed state under the action of the first light source, if the second light source is applied to the light-triggered layer 40, causing the light-triggered layer 40 to generate photoelectrons and inject them into the semiconductor layer 30, the semiconductor layer 30 switches from its polarization-reversed state to its polarization state, and the semiconductor layer 30 stores a logic value of 1. When the semiconductor layer 30 is not applied by the first light source, the semiconductor layer 30 remains in its polarization state. At this time, regardless of whether the second light source is applied to the light-triggered layer 40, the semiconductor layer 30 stores a logic value of 1.
[0115] The light triggering layer 40 can generate photoelectrons under the irradiation of the second light source. The light triggering layer 40 and the semiconductor layer 30 are attached to each other, so that the photoelectrons can be injected into the semiconductor layer 30.
[0116] In the present application, the wavelengths of the first light source and the second light source are different, so that the first light source can only act on the semiconductor layer 30 and the second light source can only act on the light triggering layer 40 .
[0117] The first light source is visible light or infrared light, and the second light source is ultraviolet light.
[0118] In some embodiments, the semiconductor layer 30 is in a polarization reversal state when the following conditions are met:
[0119] The semiconductor layer 30 is illuminated by the first light source, and the light-triggered layer 40 overlapping the semiconductor layer 30 is not illuminated by the second light source.
[0120] It is understood that when the first light source acts on the semiconductor layer 30, the semiconductor layer 30 switches from a polarized state to a polarization-reversed state. At this point, if the second light source is not acting on the light-triggered layer 40, the light-triggered layer 40 will not generate photoelectrons, and the semiconductor layer 30 will remain in the polarization-reversed state.
[0121] The first light source irradiating the semiconductor layer 30 can cause the semiconductor layer 30 to switch from a polarized state to a polarization-reversed state. After the first light source is removed, the state of the semiconductor layer 30 does not switch and remains in the polarization-reversed state. When the second light source irradiates the light-triggering layer 40, the light-triggering layer 40 injects photoelectrons into the semiconductor layer 30, causing the semiconductor layer 30 to switch from the polarization-reversed state to a polarized state. After the second light source is removed, the state of the semiconductor layer 30 does not switch and remains in the polarization state.
[0122] According to a fourth aspect of the present disclosure, a vehicle is provided, which includes the above-mentioned memory. The vehicle has all the beneficial effects of the above-mentioned memory, which will not be repeated in this disclosure.
[0123] The vehicle may be a fuel vehicle, a plug-in hybrid vehicle, a new energy vehicle, etc., and this disclosure does not make any specific limitations on this.
[0124] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.
[0125] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0126] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.
[0127] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.
Claims
1. A storage unit, characterized in that: include: a semiconductor layer having a crystalline structure, capable of spontaneous polarization and polarization reversal under the action of a first light source; A source electrode and a drain electrode are spaced apart and arranged on the semiconductor layer; The semiconductor layer has a polarization state and a polarization reversal state, and the storage unit is configured to record a first logic value when the semiconductor layer is in the polarization state, and to record a second logic value when the semiconductor layer is in the polarization reversal state.
2. The storage unit according to claim 1, wherein In the polarization state, the semiconductor layer has a first resistance value, and in the polarization-reversed state, the semiconductor layer has a second resistance value, which is different from the second resistance value.
3. The storage unit according to claim 1 or 2, characterized in that The storage unit further includes: a light-triggered layer capable of generating photoelectrons under the action of a second light source, wherein the semiconductor layer is stacked on the light-triggered layer to receive the photoelectrons, and wherein the semiconductor layer can also undergo polarization reversal under the action of the photoelectrons, wherein the polarization reversal direction of the semiconductor layer caused by the photoelectrons is opposite to the polarization reversal direction of the semiconductor layer caused by the first light source, thereby switching the semiconductor layer from the polarization reversal state to the polarization state; Wherein, the wavelength of the second light source is smaller than the wavelength of the first light source.
4. The storage unit according to claim 1, wherein The semiconductor layer includes a two-dimensional ferroelectric material layer.
5. The storage unit according to claim 3, wherein: The light triggering layer includes a perovskite light triggering layer.
6. A memory, characterized in that: include: grassroots; The storage unit according to any one of claims 1 to 5; There are at least two storage units, and each storage unit is stacked on the base layer.
7. The memory according to claim 6, wherein: The memory further comprises: a first light source, for irradiating the semiconductor layer; a second light source, for illuminating the light-triggering layer of the storage unit; Wherein, the wavelength of the second light source is smaller than the wavelength of the first light source.
8. The memory according to claim 7, wherein: The wavelength of the first light source is λ1, which satisfies: λ1>400 nanometers.
9. The memory according to claim 7, wherein: The wavelength of the second light source is λ2, which satisfies: 10 nanometers ≤ λ2 ≤ 400 nanometers.
10. The memory according to any one of claims 6 to 9, characterized in that Each of the memory cells corresponds to one source and one drain, or two adjacent memory cells correspond to one source and one drain.
11. A storage method, characterized in that: Applied to the memory according to any one of claims 6 to 10, the storage method comprises: In response to the semiconductor layer being in a polarization state, the memory records a first logic value; in response to the semiconductor layer being in a polarization-reversed state, the memory records a second logic value.
12. A vehicle, characterized in that: Comprising the memory according to any one of claims 6 to 10.