Chip testing method
By filtering out abnormal sectors and writing ‘00’ in chip tests, the entire column of memory cells is prevented from leaking due to the failed storage unit, which solves the problem that the entire column of memory cells is written ‘00’, and improves the quality and reliability of the chip.
Patent Information
- Application Number
- CN202510558988.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-29
- Publication Date
- 2025-08-12
- Estimated Expiration
- 2045-04-29
AI Technical Summary
During the chip production process, the erase operation of the failed memory cell causes the suppression voltage of the entire column of memory cells to be pulled down, causing the entire column of memory cells to be written '00', thereby affecting the chip quality.
During the chip test, after the sectors where the test abnormality was erased were filtered out, all storage units of the abnormal sector were written to '00', and erasing operations were prohibited to prevent the entire column of storage units from being written to '00' due to leakage of power in the failed storage unit.
The quality of the chip is improved, and write interference caused by leakage of the failed memory unit in the entire column is prevented due to leakage of the failure memory unit in the abnormal sector, ensuring the reliability and quality of the chip.
Smart Images
Figure CN120472967A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a chip testing method. Background Art
[0002] During the chip production process, due to process or design problems, a small number of defective chips will appear. If the defective chips cannot be effectively screened out and sent to the client, it will increase the difficulty of solving the problem later and increase the cost investment. Split-gate flash memory is a device in the chip. Its failure can directly cause the failure of the chip. There will be multiple split-gate flash memories on a wafer at the same time, and the multiple split-gate flash memories are arranged in multiple rows and columns. Please refer to Figure 1 The split-gate flash memory includes: a substrate 101; a gate oxide layer 102 and a source line polysilicon 103, wherein the gate oxide layer 102 and the source line polysilicon 103 are respectively located on the substrate 101, and the gate oxide layer 102 is located on both sides of the source line polysilicon 103; a floating gate 104, wherein the floating gate 104 is located on the surface of a portion of the gate oxide layer 102; a first spacer 105 and a second spacer 106, wherein the first spacer 105 is located on the surface of the floating gate 104, and the second spacer 106 is located between the source line polysilicon 103 and the first spacer 105, the floating gate 104, and the gate oxide layer 102; a word line polysilicon 107, wherein the word line polysilicon 107 is separated from the floating gate 104, the first spacer 105, and the surface of the substrate 101 by a tunnel oxide layer 108; and a word line spacer 109, wherein the word line spacer 109 is located on the surface of the substrate 201 and covers the sidewalls of the word line polysilicon 107 and the tunnel oxide layer 108. There is a channel 200 between adjacent memory cells. During the manufacturing process of the split gate flash memory, various abnormalities may occur, such as Figure 2 The floating gate 104 on the right side of the word line polysilicon 107 has an abnormal morphology. The floating gate 104 on the right side of the word line polysilicon 107 is less etched during the formation process, so that the polysilicon that should have been etched is not etched, resulting in the floating gate 104 being too close to the channel 200, which may cause channel leakage.
[0003] The existing method for screening split-gate flash memories with abnormal floating gate morphology is to determine the memory cell as failed during the first erase test and add it to the area to be repaired. Then, the split-gate flash memories in the area to be repaired are repaired.
[0004] However, during subsequent chip testing, the sector containing the failed memory cell will still be erased during the erase operation, which may cause the failed memory cell to be gradually fully erased. This will cause the channel next to the failed memory cell to open, which will cause the inhibition voltage of the entire column of memory cells to be lowered, causing the entire column of memory cells to be written with "00", resulting in serious quality problems. Summary of the Invention
[0005] The present invention aims to provide a chip testing method that, after identifying memory cells that have failed to be erased, prohibits erasing operations on the failed memory cells during chip testing. This prevents the channel adjacent to the failed memory cell from opening, lowering the inhibition voltage of an entire column of memory cells, and preventing the entire column of memory cells from being written with "00," thereby improving chip quality.
[0006] In order to achieve the above object, the present invention provides a chip testing method, comprising:
[0007] Providing a chip to be tested, the chip comprising a plurality of memory cells in multiple rows and columns, wherein the word lines of the memory cells in each row are connected, the bit lines of the memory cells in each column are connected, 2N adjacent rows of the memory cells form a sector, where N is a positive integer greater than or equal to 1, and multiple rows of the memory cells form multiple sectors;
[0008] Performing an erase test on the plurality of sectors in sequence, and determining whether there is a sector with an erase test abnormality;
[0009] If there is a sector with an abnormal erase test, it will be considered as an abnormal sector;
[0010] Writing "00" to all storage cells included in the abnormal sector;
[0011] An erasing operation is performed on the non-abnormal sectors. At this time, an erasing operation is prohibited on the abnormal sectors.
[0012] Optionally, in the chip testing method, the erase test is performed on the multiple sectors in sequence according to the addresses of the storage units.
[0013] Optionally, in the chip testing method, the method of sequentially performing erase tests on the plurality of sectors and determining whether there is an erase test abnormal sector includes:
[0014] S11: performing an erase test on the sector;
[0015] S12: Read the value of the memory cell after the erase test;
[0016] S13: Determine the value of the memory cell read. If the read value is 0, it is considered that the erase test of the memory cell is abnormal.
[0017] S14: looping steps S11 to S13 to obtain the values after reading all the storage cells. If the erase test of at least one of the storage cells is abnormal, it is considered that the erase test of the sector where the storage cell is located is abnormal.
[0018] Optionally, in the chip testing method, if there is no storage unit with an erase test exception, the chip test is qualified.
[0019] Optionally, in the chip testing method, the sector includes 2 rows of storage cells.
[0020] Optionally, in the chip testing method, the storage unit includes:
[0021] substrate;
[0022] A gate oxide layer and a source line polysilicon, wherein the gate oxide layer and the source line polysilicon are respectively located on the substrate, and the gate oxide layer is located on both sides of the source line polysilicon;
[0023] a floating gate, the floating gate being located on a surface of a portion of the gate oxide layer;
[0024] a first sidewall spacer and a second sidewall spacer, wherein the first sidewall spacer is located on the surface of the floating gate, and the second sidewall spacer is located between the source line polysilicon and the first sidewall spacer, the floating gate, and the gate oxide layer;
[0025] word line polysilicon, the word line polysilicon is located on a side of the first sidewall opposite to the source line polysilicon, and the word line polysilicon is separated from the floating gate and the first sidewall by a tunnel oxide layer;
[0026] The word line sidewalls are located on the surface of the substrate and cover the sidewalls of the word line polysilicon and the tunnel oxide layer.
[0027] Optionally, in the chip testing method, there is a channel between adjacent storage cells.
[0028] Optionally, in the chip testing method, the memory cell with an erase test abnormality includes a memory cell with an abnormal floating gate morphology, and the memory cell with an abnormal floating gate morphology includes:
[0029] The area of the floating gate located on the second sidewall spacer and the word line sidewall spacer exceeds a set value.
[0030] Optionally, in the chip testing method, the distance between the floating gate and the channel of the memory cell with abnormal floating gate morphology is smaller than a set value.
[0031] The chip testing method provided by the present invention includes: providing a chip to be tested, the chip including multiple memory cells in the form of multiple rows and multiple columns, the word lines of each row of memory cells being connected, the bit lines of each column of memory cells being connected, 2N adjacent rows of memory cells forming a sector, wherein N is a positive integer greater than or equal to 1, and multiple rows of memory cells forming multiple sectors; performing an erase test on the multiple sectors in sequence, and determining whether there is a sector with an erase test abnormality; if there is a sector with an erase test abnormality, it is regarded as an abnormal sector; writing "00" to all memory cells contained in the abnormal sector; performing an erase operation on the non-abnormal sector, at which time, prohibiting the erase operation on the abnormal sector. The present invention prohibits the erase operation on the sector where the failed memory cell is located during the chip testing process, thereby preventing some memory cells in the entire column of memory cells from being written "00" due to write interference caused by leakage of the failed memory cell in the abnormal sector, thereby improving chip quality. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 It is a schematic diagram of the structure of the split gate memory;
[0033] Figure 2 It is a structural schematic diagram of a split-gate memory with abnormal floating gate morphology;
[0034] Figure 3 is a flow chart of a chip testing method according to an embodiment of the present invention;
[0035] Figure 4 Schematic diagram of the distribution of multiple rows and columns of storage units according to an embodiment of the present invention;
[0036] In the figure: 101 - substrate, 102 - gate oxide layer, 103 - source line polysilicon, 104 - floating gate, 105 - first spacer, 106 - second spacer, 107 - word line polysilicon, 108 - tunneling oxide layer, 109 - channel. DETAILED DESCRIPTION
[0037] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.
[0038] Hereinafter, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if a method described herein comprises a series of steps, the order in which the steps are presented herein is not necessarily the only order in which the steps may be performed, and some of the steps described may be omitted and / or other steps not described herein may be added to the method.
[0039] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be directly on another layer or substrate, and / or intervening layers can also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or one or more intervening layers can also be present. Additionally, references to being "on" and "under" various layers can be made based on the accompanying drawings.
[0040] Please refer to Figure 3 The present invention provides a chip testing method, comprising:
[0041] S1: Provide a chip to be tested, the chip including multiple memory cells in multiple rows and columns, the word lines of each row of memory cells are connected, the bit lines of each column of memory cells are connected, 2N adjacent rows of memory cells form a sector, where N is a positive integer greater than or equal to 1, and multiple rows of memory cells form multiple sectors;
[0042] S2: Performing erase tests on multiple sectors in sequence and determining whether there are any sectors with abnormal erase tests;
[0043] S3: If there is a sector with an erase test abnormality, it is considered an abnormal sector;
[0044] S4: Write “00” to all storage cells in the abnormal sector;
[0045] S5: Perform an erase operation on the non-abnormal sectors. At this time, the erase operation on the abnormal sectors is prohibited.
[0046] In the embodiment of the present invention, please refer to Figure 1The memory cell includes: a substrate 101; a gate oxide layer 102 and a source line polysilicon 103, wherein the gate oxide layer 102 and the source line polysilicon 103 are respectively located on the substrate 101, and the gate oxide layer 102 is located on both sides of the source line polysilicon 103; a floating gate 104, wherein the floating gate 104 is located on the surface of a portion of the gate oxide layer 102; a first spacer 105 and a second spacer 106, wherein the first spacer 105 is located on the surface of the floating gate 104, and the second spacer 106 is located between the source line polysilicon 103 and the first spacer 106. Between the sidewall 105, the floating gate 104 and the gate oxide layer 102; the word line polysilicon 107, which is located on the side of the first spacer 105 opposite to the source line polysilicon 103, and is separated from the floating gate 104, the first spacer 105 and the surface of the substrate 101 by the tunnel oxide layer 108; the word line spacer 109, which is located on the surface of the substrate 201 and covers the sidewalls of the word line polysilicon 107 and the tunnel oxide layer 108. There is a channel 200 between adjacent memory cells. Please refer to Figure 4 The chip includes multiple memory cells in the form of multiple rows and columns. The source line polysilicon 103 of each row of memory cells serves as a source line and is connected. The word line polysilicon 107 serves as a word line and is connected. For example, word line 0 and word line 1 share a source line. The drain area of each column of memory cells serves as a bit line and is connected. For example, bit line 0 and bit line 1 share a source line. Since there are multiple rows and columns, multiple row addresses and column addresses are set. The corresponding memory cell can be found according to the row address and column address. Each memory cell has a unique address. Adjacent 2N rows of memory cells form a sector, where N is a positive integer greater than or equal to 1, and multiple rows of memory cells form multiple sectors.
[0047] Memory cells with abnormal erase tests may include memory cells with abnormal floating gate morphology. Memory cells with abnormal floating gate morphology include: the area of the floating gate located on the second sidewall and wordline sidewall exceeds a set value, and the set value may be a set value, which is the value of a normal memory cell. If the area of the floating gate located on the second sidewall and wordline sidewall is too large, the wordline polysilicon may be connected to the floating gate. In addition, if the area of the floating gate located on the second sidewall and wordline sidewall is too large, the distance between the floating gate and the channel may be less than the set value. During the erase process, erase electrons enter the channel, causing the channel to open.
[0048] In the embodiment of the present invention, multiple sectors are erased and tested sequentially according to the addresses of the storage units. Figure 4, a sector can include 2 rows of storage cells. Word line 0 and word line 1 can be used as the first sector, and word line 2 and word line 3 can be used as the second sector. If the erase test of a storage cell on word line 0 or word line 1 fails, the first sector will be treated as an abnormal sector. When performing step S4, it is necessary to write "00" to all the storage cells contained in the entire first sector, that is, the storage cells of word line 0 and word line 1, rather than just the storage cells with abnormal erase test. In the subsequent step S5, all storage cells in the first sector are no longer erased. This prevents the first sector from being opened in the subsequent continuous erasure process, preventing the channel next to the failed storage cell from being opened. And writing "00" in advance further avoids the failure of the terminal user to write "1" due to leakage of the word line channel. The reliability risk of the terminal user is reduced.
[0049] In this embodiment of the present invention, if the read value is 0, the erase test of the memory cell is considered normal. The memory cell undergoing the erase test does not need to be extracted. After the erase test of all memory cells is completed, if there are no memory cells with abnormal erase tests, the chip is considered to have passed this test and can proceed to the next functional test.
[0050] In an embodiment of the present invention, a method for sequentially performing an erase test on multiple sectors and determining whether a sector has an erase test abnormality includes: S11: performing an erase test on the sector; S12: reading the value of a storage cell after the erase test; S13: determining the value of the read storage cell; if the read value is 0, the erase test of the storage cell is considered abnormal; if the read value is 1, the erase test of the storage cell is considered normal; S14: looping steps S11 to S13 to obtain the values after reading all storage cells; if the erase test of at least one storage cell is abnormal, the erase test of the sector containing the storage cell is considered abnormal. When the number of sectors with an erase test abnormality is greater than or equal to 1, it is considered that a sector has an erase test abnormality.
[0051] In summary, the chip testing method provided in the embodiment of the present invention includes: providing a chip to be tested, the chip including multiple storage cells in the form of multiple rows and multiple columns, the word lines of each row of storage cells are connected, the bit lines of each column of storage cells are connected, and 2N adjacent rows of storage cells form a sector, wherein N is a positive integer greater than or equal to 1, and multiple rows of storage cells form multiple sectors; performing erase tests on multiple sectors in sequence, and determining whether there are sectors with erase test abnormalities; if there are sectors with erase test abnormalities, they are treated as abnormal sectors; writing "00" to all storage cells contained in the abnormal sector; performing an erase operation on non-abnormal sectors, at this time, prohibiting the erase operation on the abnormal sector. The present invention prohibits the erase operation on the sector where the failed storage cell is located during the chip test process, thereby preventing some storage cells in the entire column of storage cells from being written "00" due to write interference caused by leakage of failed storage cells in the abnormal sector, thereby improving chip quality.
[0052] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.
Claims
1. A chip testing method, characterized in that: include: Providing a chip to be tested, the chip comprising a plurality of memory cells in multiple rows and columns, wherein the word lines of the memory cells in each row are connected, the bit lines of the memory cells in each column are connected, 2N adjacent rows of the memory cells form a sector, where N is a positive integer greater than or equal to 1, and multiple rows of the memory cells form multiple sectors; Performing an erase test on the plurality of sectors in sequence, and determining whether there is a sector with an erase test abnormality; If there is a sector with an abnormal erase test, it will be considered as an abnormal sector; Writing "00" to all storage cells contained in the abnormal sector; An erasing operation is performed on the non-abnormal sectors. At this time, an erasing operation is prohibited on the abnormal sectors.
2. The chip testing method according to claim 1, wherein: The erase test is performed on the plurality of sectors in sequence according to the addresses of the storage units.
3. The chip testing method according to claim 1, wherein: The method of sequentially performing an erase test on a plurality of sectors and determining whether there is an abnormal sector in the erase test includes: S11: performing an erase test on the sector; S12: Read the value of the memory cell after the erase test; S13: Determine the value of the memory cell read. If the read value is 0, it is considered that the erase test of the memory cell is abnormal. S14: looping steps S11 to S13 to obtain the values after reading all the storage cells. If the erase test of at least one of the storage cells is abnormal, it is considered that the erase test of the sector where the storage cell is located is abnormal.
4. The chip testing method according to claim 1, wherein: If there is no memory cell with an erase test exception, the chip passes the test.
5. The chip testing method according to claim 1, wherein: The sector includes two rows of memory cells.
6. The chip testing method according to claim 1, wherein: The storage unit includes: substrate; A gate oxide layer and a source line polysilicon, wherein the gate oxide layer and the source line polysilicon are respectively located on the substrate, and the gate oxide layer is located on both sides of the source line polysilicon; a floating gate, the floating gate being located on a surface of a portion of the gate oxide layer; a first sidewall spacer and a second sidewall spacer, wherein the first sidewall spacer is located on the surface of the floating gate, and the second sidewall spacer is located between the source line polysilicon and the first sidewall spacer, the floating gate, and the gate oxide layer; word line polysilicon, the word line polysilicon is located on a side of the first sidewall opposite to the source line polysilicon, and the word line polysilicon is separated from the floating gate and the first sidewall by a tunnel oxide layer; The word line sidewalls are located on the surface of the substrate and cover the sidewalls of the word line polysilicon and the tunnel oxide layer.
7. The chip testing method according to claim 6, wherein: There is a channel between adjacent memory cells.
8. The chip testing method according to claim 7, wherein: The memory cell with an abnormal erase test includes a memory cell with an abnormal floating gate morphology, and the memory cell with an abnormal floating gate morphology includes: The area of the floating gate located on the second sidewall spacer and the word line sidewall spacer exceeds a set value.
9. The chip testing method according to claim 8, wherein: The distance between the floating gate and the channel of the memory cell with abnormal floating gate morphology is smaller than a set value.
Citation Information
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