Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method thereof. The semiconductor device includes a substrate, a gate structure, source and drain electrodes, a plurality of barrier patterns disposed on the source and drain electrodes, respectively, and first and second silicide layers. The substrate includes an isolation structure defining an active region. The gate structure is disposed on the active region of the substrate. The source electrode and the drain electrode are respectively disposed in opposite sides of the substrate in the first direction of the gate structure. The source and drain each include a plurality of first regions covered by the barrier pattern and a second region exposed by the barrier pattern. The first silicide layer and the second silicide layer are buried in the second regions of the source electrode and the drain electrode, respectively. The first silicide layer and the second silicide layer each include a plurality of first portions and second portions between the first portions, and the length of the first portions in the first direction is smaller than the length of the second portions in the first direction.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same. Background Art

[0002] Power semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), are commonly used in analog and / or digital circuits. Based on the direction of current flow, they can be categorized as planar or vertical. In planar power semiconductor devices, the horizontal area and / or channel length of the power semiconductor device are generally positively correlated with the operating voltage of the semiconductor device.

[0003] However, because power semiconductor devices generally have higher channel lengths and / or higher operating voltages than logic semiconductor devices, the threshold voltage at the edges of the power semiconductor device, along the width perpendicular to the channel extension, will be different from the threshold voltage at the center. This can cause a double-hump phenomenon in the bulk current (e.g., the current flowing from the source to the drain), making model fitting difficult or leading to undesirable amplifier behavior. Therefore, those skilled in the art continue to strive to address the impact of the double-hump phenomenon on power semiconductor devices. Summary of the Invention

[0004] The present invention provides a semiconductor device and a method for forming the same, wherein a first silicide layer and a second silicide layer respectively embedded in the second region of a source and a drain each include a plurality of first portions and a second portion between the first portions, and the length of the first portion in the first direction is smaller than the length of the second portion in the first direction. This increases the resistance of the semiconductor device at the edge in the width direction of the vertical channel extension direction (i.e., the first direction), thereby allowing the critical voltage of the semiconductor device to mainly depend on the critical voltage at the center of the semiconductor device in the width direction, thereby improving the double peak phenomenon of the substrate current.

[0005] One embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming a gate stack structure on a substrate, wherein the substrate includes an active region defined by an isolation structure and the gate stack structure is disposed in the active region; forming a source and a drain in the active region of the substrate, wherein the source and the drain are respectively formed on opposite sides of the gate stack structure in a first direction; forming a barrier layer on the source and the drain, wherein the source and the drain each include a plurality of first regions covered by the barrier layer and a second region exposed by the barrier layer; and performing a silicidation process to form a first silicide layer and a second silicide layer in the second regions of the source and the drain, respectively. The first silicide layer and the second silicide layer each include a plurality of first portions and a second portion between the first portions, wherein the length of the first portion in the first direction is less than the length of the second portion in the first direction.

[0006] In some embodiments, the first silicide layer and the second silicide layer are spaced apart from each other at the second portion by a distance smaller than the distance the first silicide layer and the second silicide layer are spaced apart from each other at the first portion.

[0007] In some embodiments, the barrier layer includes a first barrier pattern and a second barrier pattern spaced apart from each other in a second direction intersecting the first direction, and the first barrier pattern and the second barrier pattern cover a top surface and a sidewall of the gate stack structure.

[0008] In some embodiments, the method of forming a semiconductor device further includes removing portions of the first barrier pattern and the second barrier pattern on the top surface of the gate stack structure to form a plurality of patterns spaced apart from each other and respectively covering the first regions of the source and the drain.

[0009] In some embodiments, the first silicide layer is not formed in the first region of the source, and the second silicide layer is not formed in the first region of the drain.

[0010] One embodiment of the present invention provides a semiconductor device comprising a substrate, a gate structure, a source and a drain, a plurality of barrier patterns, and a first silicide layer and a second silicide layer. The substrate comprises an isolation structure defining an active region. The gate structure is disposed on the active region of the substrate. The source and the drain are respectively disposed on opposite sides of the substrate in a first direction relative to the gate structure. The barrier patterns are disposed on the source and the drain, respectively. The source and the drain each comprise a plurality of first regions covered by the barrier patterns and a second region exposed by the barrier patterns. The first silicide layer and the second silicide layer are respectively buried in the second regions of the source and the drain. The first silicide layer and the second silicide layer each comprise a plurality of first portions and a second portion between the first portions. The length of the first portion in the first direction is less than the length of the second portion in the first direction.

[0011] In some embodiments, the pattern of the first silicide layer is mirror-symmetrical to the pattern of the second silicide layer in the first direction.

[0012] In some embodiments, the first silicide layer and the second silicide layer are spaced apart from each other at the second portion by a distance smaller than the distance the first silicide layer and the second silicide layer are spaced apart from each other at the first portion.

[0013] In some embodiments, each barrier pattern covers a sidewall of the gate structure.

[0014] In some embodiments, the first silicide layer is not formed in the first region of the source, and the second silicide layer is not formed in the first region of the drain.

[0015] Based on the above, in the above-mentioned semiconductor device and its formation method, the first silicide layer and the second silicide layer respectively buried in the second region of the source and the drain each include multiple first parts and second parts between the first parts, and the length of the first part in the first direction is smaller than the length of the second part in the first direction. In this way, the resistance of the semiconductor device at the edge in the width direction of the vertical channel extension direction (i.e., the first direction) can be increased, so that the critical voltage of the semiconductor device depends on the critical voltage at the center of the semiconductor device in the width direction, thereby improving the double peak phenomenon of the substrate current. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1A to 5C FIG. 1 is a schematic diagram of a method for forming a semiconductor device according to an embodiment of the present invention.

[0017] Explanation of symbols

[0018] 10: Semiconductor devices

[0019] 100: Base

[0020] 102: Isolation Structure

[0021] 110: Gate stack structure

[0022] 112: dielectric layer

[0023] 114: Sacrificial gate layer

[0024] 116, 117: gap wall

[0025] 120S: Source

[0026] 120D: Drain

[0027] 130: barrier layer

[0028] 132a, 132b, 132c, 132d: Pattern / blocking pattern

[0029] A1, A2, A3, A4: Area

[0030] D1: First direction

[0031] D2: Second direction

[0032] HM: Hard Mask Layer

[0033] 140: first silicide layer / second silicide layer / silicide layer

[0034] 140a: Part 1

[0035] 140b: Part 2

[0036] 150: Etching stop material layer

[0037] 152: Etching stop layer

[0038] 160: dielectric material layer

[0039] 162: dielectric layer

[0040] 210: Sacrificial gate structure

[0041] 214: Metal gate

[0042] 310: Gate structure DETAILED DESCRIPTION

[0043] The present invention will be more fully described with reference to the accompanying drawings illustrating the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the accompanying drawings may be exaggerated for clarity. Identical or similar reference numbers denote identical or similar elements, and detailed descriptions will not be repeated in the following paragraphs.

[0044] It should be understood that when an element is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or there may be an intermediate element. If an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connection" may refer to physical and / or electrical connection, while "electrical connection" or "coupling" may refer to the presence of other elements between two elements. As used herein, "electrical connection" may include physical connection (e.g., wired connection) and physical disconnection (e.g., wireless connection).

[0045] As used herein, "about," "approximately," or "substantially" includes the stated value and the average within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the particular amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, or ±5%. Furthermore, as used herein, "about," "approximately," or "substantially" may be selected based on the optical property, etching property, or other property, and may not apply to all properties with a single standard deviation.

[0046] The terms used herein are intended to illustrate exemplary embodiments only and are not intended to limit the present invention. In this case, unless the context otherwise indicates, the singular includes the plural.

[0047] Figures 1A to 5C FIG. 1 is a schematic diagram of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 1A 、 Figure 2A 、 Figure 3A 、 Figure 4A and Figure 5A It is a top view schematic diagram. Figure 1B and Figure 1C They are Figure 1A Schematic cross-sectional view taken along line AA' and line BB'. Figure 2B and Figure 2C They are Figure 2A Schematic cross-sectional view taken along line AA' and line BB'. Figure 3B and Figure 3C They are Figure 3A Schematic cross-sectional view taken along line AA' and line BB'. Figure 4B and Figure 4C They are Figure 4A Schematic cross-sectional view taken along line AA' and line BB'. Figure 5B and Figure 5C They are Figure 5A Schematic diagram of the cross section taken along line A-A' and line BB'. For the convenience of explanation, Figure 4A The etching stop material layer 150 and the dielectric layer 162 are omitted. Figure 5A The etch stop layer 152 and the dielectric layer 162 are omitted from illustration.

[0048] In some embodiments, a semiconductor device (such as Figure 5A The method of manufacturing the semiconductor device 10 may include the following steps.

[0049] First, on a substrate (e.g. Figures 2A to 2C A gate stack structure (eg, Figures 2A to 2C In some embodiments, the gate stack structure may be formed on a substrate in the following manner.

[0050] Please refer to Figures 1A to 1C An isolation structure 102 defining an active region is formed in the substrate 100. Next, a doping process is performed on the active region of the substrate 100 to form a well region. The substrate 100 may include a semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or SOI substrate may include an elemental semiconductor, an alloy semiconductor, or a compound semiconductor. For example, an elemental semiconductor may include Si or Ge. An alloy semiconductor may include SiGe, SiGeC, etc. A compound semiconductor may include SiC, a III-V semiconductor material, or a II-VI semiconductor material. A III-V semiconductor material may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNPs, GaNAs, GaPAs, AlNPs, AlNAs, AlPAs, InNPs, InNAs, InPAs, GaAlNPs, GaAlNAs, GaAlPAs, GaInNPs, GaInNAs, GaInPAs, InAlNPs, InAlNAs, or InAlPAs. The II-VI semiconductor material may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, or HgZnSTe. The semiconductor material may be doped with a dopant of a first conductivity type or a dopant of a second conductivity type complementary to the first conductivity type. For example, the first conductivity type may be N-type, and the second conductivity type may be P-type. The isolation structure 102 may include a material suitable for an isolation structure, such as an oxide (e.g., silicon oxide). In some embodiments, the isolation structure 102 may include a shallow trench isolation (STI) structure.

[0051] Please refer to Figures 2A to 2C, a gate stack structure 110 is formed on a substrate 100. The gate stack structure 110 is disposed in the active region and includes a dielectric layer 112, a sacrificial gate layer 114, and a hard mask layer HM sequentially formed on the substrate 100, and spacers 116 formed on opposite sidewalls of the stack structure consisting of the dielectric layer 112, the sacrificial gate layer 114, and the hard mask layer HM.

[0052] In some embodiments, the dielectric layer 112 may include a gate dielectric layer, a high-k dielectric layer, and a cap layer sequentially formed on the substrate 100. The gate dielectric layer may include a material suitable for a gate dielectric layer, such as silicon oxide. The high-k dielectric layer may include a dielectric material having a high k dielectric constant. For example, the dielectric material having a high k dielectric constant may be a material having a k dielectric constant greater than that of silicon oxide (approximately 3.9). In some embodiments, the high-k dielectric layer may include HfO2, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, Al2O3, Si3N4, SiON, or a combination thereof. The cap layer may include TiN.

[0053] In some embodiments, the sacrificial gate layer 114 may include polysilicon. In some embodiments, the hard mask layer HM may include oxide, nitride, or a combination thereof. In some embodiments, the spacer 116 may include silicon oxide, silicon nitride, or a combination thereof.

[0054] Next, please refer to Figures 3A to 3C A source 120S and a drain 120D are formed in the active region of the substrate 100, wherein the source 120S and the drain 120D are respectively formed on opposite sides of the gate stack structure 110 in the first direction D1. In some embodiments, the source 120S and the drain 120D can be formed in the substrate 100 on opposite sides of the gate stack structure 110 in the first direction D1 by performing a doping process on the active region of the substrate 100.

[0055] Then, a blocking layer 130 is formed on the source 120S and the drain 120D, wherein the source 120S and the drain 120D each include a plurality of first regions (e.g., region A1, region A2, region A3, and region A4) covered by the blocking layer 130 and a second region exposed by the blocking layer 130 (i.e., the region on which the silicide layer 140 is subsequently formed). In some embodiments, the blocking layer 130 may be a film layer that blocks silicide from being formed thereon, also referred to as a silicide blocking layer, and may include a material suitable for a silicide blocking layer, such as an oxide. In some embodiments, as Figure 3AAs shown, the barrier layer 130 includes first barrier patterns (eg, Figure 3A ) and a second barrier pattern (eg, a left barrier layer 130 shown in FIG. 1 ) Figure 3A ), wherein the first barrier pattern and the second barrier pattern cover the top surface and sidewalls of the gate stack structure 110. The second direction D2 intersects the first direction D1. In some embodiments, the second direction D2 is perpendicular to the first direction D1.

[0056] A silicidation process is then performed to form a first silicide layer 140 and a second silicide layer 140 in the second regions of the source 120S and the drain 120D, respectively. The first silicide layer 140 and the second silicide layer 140 may each include tungsten silicide, titanium silicide, cobalt silicide, zirconium silicide, platinum silicide, molybdenum silicide, copper silicide, nickel silicide, or a combination thereof. Because the first regions (e.g., regions A1, A2, A3, and A4) of the source 120S and the drain 120D are covered by the barrier layer 130, the silicide layer 140 is not formed in regions A1, A2, A3, and A4 during the silicidation process. That is, the formed first and second silicide layers 140 and 140 each include a plurality of first portions 140 a and second portions 140 b between the first portions 140 a, and the length of the first portions 140 a in the first direction D1 is shorter than the length of the second portions 140 b in the first direction D1. Consequently, regions A1, A2, A3, and A4 of the source 120S and drain 120D where the silicide layer 140 is not formed have a higher resistance than other regions where the silicide layer 140 is formed. This results in a higher resistance at the edges of the semiconductor device (i.e., the region passing through line AA') in the width direction (i.e., the second direction D2) perpendicular to the channel extension direction (i.e., the first direction D1). Consequently, the threshold voltage of the semiconductor device primarily depends on the threshold voltage at the center of the semiconductor device in the width direction (i.e., the region passing through line BB'), thereby improving the double peak phenomenon of the substrate current. In some embodiments, the first and second silicide layers 140 and 140 are spaced apart from each other by a distance smaller than the distance at the first and second silicide layers 140 and 140 are spaced apart from each other at the second portion 140 b .

[0057] Next, please refer to Figures 4A to 4C , remove the portion of the barrier layer 130 located on the top surface of the gate stack structure 110 and the hard mask layer HM of the gate stack structure 110 below the portion to form first regions (e.g., Figure 3AThe plurality of patterns (e.g., pattern 132a, pattern 132b, pattern 132c, and pattern 132d) of the regions A1, A2, A3, and A4 (shown) and the sacrificial gate structure 210 are formed. In some embodiments, during the step of removing the portion of the barrier layer 130 located on the top surface of the gate stack structure 110 and the hard mask layer HM of the gate stack structure 110, the barrier layer 130 and a portion of the spacers 116 located on the side surfaces of the hard mask layer HM are also removed, so that the sacrificial gate structure 210 includes the spacers 117, and the barrier layer 130 is formed into patterns 132a, 132b, 132c, and 132d that are spaced apart from each other and cover the sidewalls of the sacrificial gate structure 210. In some embodiments, as Figure 4A As shown, the pattern 132a and the pattern 132c are spaced apart from each other in the second direction D2, and the pattern 132b and the pattern 132d are spaced apart from each other in the second direction D2.

[0058] Then, an etch stop material layer 150 and a dielectric material layer 160 are sequentially formed on the substrate 100. The etch stop material layer 150 may be conformally formed on the surfaces of the substrate 100 and the sacrificial gate structure 210. The dielectric material layer 160 may cover the sacrificial gate structure 210. The etch stop material layer 150 may include a material such as silicon nitride. The dielectric material layer 160 may include a dielectric material such as silicon oxide.

[0059] Afterwards, please refer to Figures 5A to 5C A planarization process such as chemical mechanical polishing (CMP) is performed on the dielectric material layer 160 and the etch stop material layer 150 to form an etch stop layer 152 and a dielectric layer 162 .

[0060] Then, the sacrificial gate layer 114 in the sacrificial gate structure 210 is removed, and a metal material is filled into the space formed by removing the sacrificial gate layer 114. A planarization process such as CMP is performed to form a gate structure 310 including the metal gate 214. The metal material may include tantalum nitride (TaN), nickel silicon (NiSi), cobalt silicon (CoSi), molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), zirconium (Zr), platinum (Pt), or other suitable materials.

[0061] Based on the above, in the method for forming the semiconductor device 10 in the above embodiment, the first silicide layer 140 and the second silicide layer 140 respectively buried in the second region of the source 120S and the drain 120D each include a plurality of first portions 140 a and second portions 140 b between the first portions 140 a, and the length of the first portions 140 a in the first direction D1 is smaller than the length of the second portions 140 b in the first direction D1. In this way, the resistance of the semiconductor device 10 at the edge in the width direction (i.e., the second direction D2) perpendicular to the channel extension direction (i.e., the first direction D1) can be increased, so that the threshold voltage of the semiconductor device 10 mainly depends on the threshold voltage at the center of the semiconductor device 10 in the width direction, thereby improving the double peak phenomenon of the substrate current.

[0062] The following will be Figures 5A to 5C The semiconductor device 10 is described below. The semiconductor device 10 can be formed by the method described above, but the present invention is not limited thereto.

[0063] The semiconductor device 10 includes a substrate 100, a gate structure 310, a source 120S and a drain 120D, a plurality of barrier patterns 132a, 132b, 132c, 132d, and a first silicide layer 140 and a second silicide layer 140. The substrate 100 includes an isolation structure 102 that defines an active region. The gate structure 310 is disposed on the active region of the substrate 100. The source 120S and the drain 120D are respectively disposed on opposite sides of the substrate 100 in a first direction D1. A plurality of barrier patterns 132a, 132b, 132c, 132d are respectively disposed on the source 120S and the drain 120D, wherein the source 120S and the drain 120D each include a plurality of first regions (such as 132a, 132b, 132c, 132d) covered by the barrier patterns 132a, 132b, 132c, 132d. Figure 3A The illustrated areas A1, A2, A3, and A4) and the second areas exposed by the blocking patterns 132a, 132b, 132c, and 132d (such as the areas A1, A2, A3, and A4) are shown. Figure 3A The first silicide layer 140 and the second silicide layer 140 are respectively buried in the second regions of the source 120S and the drain 120D. The first silicide layer 140 and the second silicide layer 140 each include a plurality of first portions 140a and second portions 140b between the first portions 140a, and the length of the first portions 140a in the first direction D1 is less than the length of the second portions 140b in the first direction D1.

[0064] In some embodiments, the pattern of the first silicide layer 140 (on the source 120S) is mirror-symmetrical to the pattern of the second silicide layer 140 (on the drain 120D) in the first direction D1. In some embodiments, the distance between the first silicide layer 140 and the second silicide layer 140 at the second portion 140b is smaller than the distance between the first silicide layer 140 and the second silicide layer 140 at the first portion 140a. In some embodiments, each of the barrier patterns 132a, 132b, 132c, and 132d covers the sidewalls of the gate structure 310. In some embodiments, the first silicide layer 140 is not formed in the first region of the source 120S, and the second silicide layer 140 is not formed in the first region of the drain 120D.

[0065] To summarize, in the above-mentioned semiconductor device and the method for forming the semiconductor device, the first silicide layer and the second silicide layer respectively buried in the second region of the source and the drain each include a plurality of first portions and a second portion between the first portions, and the length of the first portion in the first direction is smaller than the length of the second portion in the first direction. In this way, the resistance of the semiconductor device at the edge in the width direction (i.e., the second direction) along the vertical channel extension direction (i.e., the first direction) can be increased, so that the critical voltage of the semiconductor device depends on the critical voltage at the center of the semiconductor device in the width direction, thereby improving the double peak phenomenon of the substrate current.

Claims

1. A method for forming a semiconductor device, comprising: forming a gate stack structure on a substrate, wherein the substrate includes an active region defined by an isolation structure and the gate stack structure is disposed in the active region; forming a source and a drain in the active region of the substrate, wherein the source and the drain are respectively formed at opposite sides of the gate stack structure in a first direction; forming a barrier layer on the source electrode and the drain electrode, wherein the source electrode and the drain electrode each include a plurality of first regions covered by the barrier layer and a second region exposed by the barrier layer; and performing a silicidation process to form a first silicide layer and a second silicide layer in the second regions of the source and the drain, respectively; The first silicide layer and the second silicide layer each include a plurality of first portions and a second portion between the first portions, and a length of the first portion in the first direction is smaller than a length of the second portion in the first direction. 2 . The method of claim 1 , wherein the first silicide layer and the second silicide layer are spaced apart from each other at the second portion by a distance smaller than the first silicide layer and the second silicide layer are spaced apart from each other at the first portion.

3. The method of claim 1 , wherein the barrier layer comprises a first barrier pattern and a second barrier pattern spaced apart from each other in a second direction, the second direction intersecting the first direction, the first barrier pattern and the second barrier pattern covering a top surface and sidewalls of the gate stack structure.

4. The method of claim 3, further comprising: Portions of the first barrier pattern and the second barrier pattern on the top surface of the gate stack structure are removed to form a plurality of patterns that are spaced apart from each other and respectively cover the first regions of the source and the drain. 5 . The method of claim 1 , wherein the first silicide layer is not formed in the first region of the source, and the second silicide layer is not formed in the first region of the drain.

6. A semiconductor device comprising: a substrate including an isolation structure defining an active region; a gate structure, disposed on the active region of the substrate; a source electrode and a drain electrode, respectively disposed on opposite sides of the substrate in the first direction from the gate structure; a plurality of blocking patterns, respectively disposed on the source electrode and the drain electrode, wherein the source electrode and the drain electrode each include a plurality of first regions covered by the blocking patterns and a second region exposed by the blocking patterns; as well as A first silicide layer and a second silicide layer are respectively buried in the second regions of the source and the drain, The first silicide layer and the second silicide layer each include a plurality of first portions and a second portion between the first portions, and a length of the first portion in the first direction is smaller than a length of the second portion in the first direction. 7 . The semiconductor device according to claim 6 , wherein a pattern of the first silicide layer and a pattern of the second silicide layer are mirror-symmetrical in the first direction.

8. The semiconductor device according to claim 6, wherein the distance at which the first silicide layer and the second silicide layer are spaced apart from each other at the second portion is smaller than the distance at which the first silicide layer and the second silicide layer are spaced apart from each other at the first portion. 9 . The semiconductor device according to claim 6 , wherein each of the barrier patterns covers a sidewall of the gate structure. 10 . The semiconductor device according to claim 6 , wherein the first silicide layer is not formed in the first region of the source, and the second silicide layer is not formed in the first region of the drain.

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