Packaging method of super-current planar IGBT chip

Abstract

This invention relates to the field of semiconductor packaging technology, and more particularly to a packaging method for ultra-high current planar IGBT chips. The technical solution includes the following steps: Step 1, providing a copper-molybdenum alloy substrate with a high thermal conductivity and a thermal expansion coefficient close to that of silicon; Step 2, bonding the IGBT chip to the upper surface of the substrate using silver sintering technology in a pressure bonding process; Step 3, employing a multi-point voltage equalization wiring structure to achieve parallel current distribution across multiple chips, wherein each chip path undergoes thermal resistance and resistive coupling design; Step 4, introducing a position-dependent variable coefficient thermal resistance adjustment method during the packaging process; Step 5, passivating the chip surface through plasma treatment, and completing the structure curing using a low-stress molding packaging material. This invention, through the synergistic design of the copper-molybdenum gradient substrate and the current equalization packaging structure, achieves improved thermal stress relief, current equalization, and interface reliability, thereby enhancing the packaging performance and lifespan of ultra-high current IGBT chips.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a packaging method for an ultra-high current planar IGBT chip. Background Technology

[0002] Insulated Gate Bipolar Transistors (IGBTs), as power electronic devices that combine the high-speed switching capability of MOSFETs with the high-current carrying capacity of BJTs, have extremely broad application prospects in high-power applications such as new energy vehicles, rail transportation, power conversion, and high-voltage direct current transmission. With the continuous improvement of power density, planar IGBT chips with ultra-high current ratings (≥800A) are gradually becoming the mainstream choice for module packaging.

[0003] However, in the current technology, IGBT chip packaging still faces the following key technical challenges:

[0004] The problem of thermal expansion mismatch between the chip and the substrate is serious: IGBT chips are usually made of silicon or SiC materials, while the thermal expansion coefficient of traditional substrates differs greatly from that of the chip. This causes periodic stress at the interface during power thermal cycling, which can easily cause microcracks in the silver sintering layer and ultimately lead to package failure.

[0005] Uneven current density causes hot spot concentration: Under high current operating conditions, if the wiring structure on the chip surface is not properly optimized, current concentration paths are easily generated, leading to local overheating or electromigration failure.

[0006] Substrate thermal conductivity and structural matching are difficult to balance: Traditional copper-molybdenum alloys are homogeneous structures that cannot simultaneously meet the stress buffering requirements of the upper layer and the heat dissipation and thermal conductivity requirements of the lower layer, resulting in high thermal resistance and limited overall package stability.

[0007] Package lifespan is limited by structural rigidity: Under high voltage and high current conditions, the chip structure is subjected to large shear stress during thermal cycling, and the interface design of traditional packaging structures cannot effectively release thermomechanical strain.

[0008] To address this issue, we propose a packaging method for ultra-high current planar IGBT chips. Summary of the Invention

[0009] The purpose of this invention is to address the problems existing in the background art by proposing a packaging method for ultra-high current planar IGBT chips.

[0010] To achieve the above objectives, the present invention provides the following technical solution: a packaging method for an ultra-high current planar IGBT chip, comprising the following steps:

[0011] Step 1: Provide a copper-molybdenum alloy substrate with a high thermal conductivity and a coefficient of thermal expansion close to that of silicon.

[0012] Step 2: The IGBT chip is bonded to the upper surface of the substrate using silver sintering technology in the pressure bonding process to achieve chip fixation with high thermal performance and high mechanical strength.

[0013] Step 3: A multi-point voltage equalization wiring structure is adopted to realize the parallel distribution of current of multiple chips. Each chip path is designed with thermal resistance and resistance coupling to ensure the balanced current distribution of each current path in the package structure and avoid single-point thermal failure caused by current concentration.

[0014] Step 4: During the packaging process, a thermal resistance adjustment method based on position-dependent variable coefficients is introduced to control the uniformity of heat flow diffusion inside the chip or at different locations of the module, thereby enhancing the overall heat dissipation performance.

[0015] Step 5: Passivate the chip surface through plasma treatment and solidify the structure using low-stress molding packaging material to improve the long-term reliability and breakdown resistance of the chip under high temperature and high current density conditions.

[0016] Preferably, in step 4, the thermal diffusion design achieves non-uniform distribution control of thermal resistance by constructing a function model with the spatial position of the chip surface as the variable. In this function model, the center point of the chip has the minimum thermal resistance value, while the thermal resistance gradually increases towards the edge of the chip. The increase is related to the sum of the squares of the chip coordinates by a certain power function. This model can more realistically reflect the changing trend of heat flux density inside the package, thereby effectively mitigating the problem of thermal stress concentration.

[0017] Preferably, in the design of current distribution between parallel chip paths in step 3, a current distribution function model is established, and the comprehensive resistance and thermal resistance coupling factor of each path are used as weighting criteria to ensure that the total current is reasonably distributed according to the path performance ratio. This method significantly improves the uneven current phenomenon caused by impedance differences in traditional parallel packaging.

[0018] Preferably, in step 2, the thickness of the silver sintered layer between the chip and the substrate exhibits a periodic variation trend during the sintering temperature change. This variation trend is regulated by the thermal expansion compensation factor to ensure that the sintered layer still has good interfacial contact and thermal conductivity under high temperature conditions. By constructing a thickness variation model based on temperature variables, this method further improves the reliability of the chip in high temperature environments.

[0019] Preferably, in step 5, the encapsulation structure reduces the thermomechanical mismatch stress at the material interface by minimizing the welding stress. This method uses an equivalent stress function to express the thermal stress synthesis effect, comprehensively considering the influence of transverse and longitudinal thermal stress, as well as the material Poisson effect on the overall stress field, thereby improving the overall mechanical strength and thermal shock resistance of the encapsulation.

[0020] Preferably, in step 3, the thermal density optimization design establishes a relationship model between the power load per unit package area and the average thermal resistance, thereby achieving dynamic matching between the package heat dissipation capacity and the power handling capacity. This model helps to determine the optimal ratio of package area to power density, thereby improving the overall heat dissipation efficiency of the device without increasing the package size.

[0021] Preferably, the power cycle life assessment model in step 5 is based on the coupling relationship between temperature cycle amplitude, average junction temperature and material activation energy, and uses an exponential function established by empirical fitting parameters for prediction. This model can be used to accurately predict the fatigue life of the packaging structure under long-cycle, high-power cycling, thereby providing a theoretical basis for the selection of packaging materials and structural optimization.

[0022] Preferably, in step 4, the temperature distribution inside the package is established based on a Gaussian distribution superposition model according to the dual heat source diffusion effect. This model describes that the temperature is highest at the center of the chip, decreases exponentially in both directions, and eventually approaches the substrate temperature. This temperature distribution model can effectively reflect the location and area of ​​hot spots inside the package, which helps to assist in wiring and module layout design to avoid hot spot risks.

[0023] Preferably, the copper-molybdenum alloy substrate adopts a multi-layer gradient structure design, wherein the arrangement ratio of copper layers to molybdenum layers is non-linearly distributed along the thickness direction, so that the overall thermal expansion coefficient of the substrate is more precisely matched with the silicon material on the side closer to the chip, thereby reducing the thermal stress coupling between the chip and the substrate. The non-linear distribution relationship is as follows: the proportion of copper layer is the smallest near the chip interface, and the proportion of copper layer increases with the distance from the chip surface. The specific trend of change satisfies a power function model that changes along the thickness direction, so as to optimize the thermal stress gradient distribution and improve the thermal shock life.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0025] Dynamic thermal stress adaptive release: The copper-molybdenum alloy gradient structure substrate is adopted, and the copper volume fraction is distributed and controlled along the thickness direction by a nonlinear power function. This gives the chip interface area a low coefficient of thermal expansion, and the middle and bottom areas gradually transition to high thermal conductivity areas. While maintaining mechanical integrity, it effectively releases thermal shock stress and improves the stability and reliability of the packaging interface.

[0026] Packaging thermal resistance is reduced by more than 10%: The high copper content in the lower part of the gradient copper-molybdenum structure provides an excellent heat conduction channel, which works in synergy with the stress buffer area at the top, resulting in a significant reduction in the overall thermal resistance of the package and a significant drop in the chip junction temperature, meeting the requirements of long-term high-current operation scenarios.

[0027] Improve the consistency of current sharing among multiple chips: The top wiring of the chip introduces a multi-point current sharing structure, combined with the thermal resistance-resistance coupling optimization design of the wiring path, effectively controlling the current deviation of each chip, with a maximum deviation of less than ±5%, avoiding failure caused by local overload or hot spots.

[0028] Enhanced reliability of silver sintered interface: By optimizing the thermal expansion matching relationship of the substrate and surface plasma cleaning / passivation treatment, the adhesion performance and thermal cycle life of the silver sintered layer are significantly improved. After 3000 power cycles, the interface resistance increases by less than 10%, and there are no detectable cracks.

[0029] Compatible with mass production process routes: The copper-molybdenum composite material, silver sintering process, and molding packaging method adopted are all highly compatible with the existing high-end IGBT module production line processes, without the need for large-scale equipment replacement, and have good industrial feasibility and promotion prospects;

[0030] In summary, the method proposed in this invention not only has significant innovation in structural design, but also achieves technological breakthroughs in thermal performance, electrical balance and packaging stability. It is applicable to planar IGBT module packaging with current ratings of 1200A and above, and is especially suitable for industrial and new energy applications with high reliability and long lifespan requirements. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the copper-molybdenum alloy substrate structure of the present invention;

[0032] Figure 2 For the present invention Figure 1 A schematic diagram showing the distribution of text descriptions along the thickness direction;

[0033] Figure 3 This is a schematic diagram of the gradient copper content function of the present invention. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] Example 1

[0036] like Figures 1-3 As shown, the present invention proposes a packaging method for an ultra-high current planar IGBT chip, comprising the following steps:

[0037] Step 1: A high thermal conductivity copper-molybdenum alloy substrate with a thermal expansion coefficient close to that of silicon is provided. The copper-molybdenum alloy substrate adopts a multi-layer gradient structure design, in which the arrangement ratio of copper layers to molybdenum layers is non-linearly distributed along the thickness direction. This is to make the overall thermal expansion coefficient of the substrate more accurately match that of silicon material on the side near the chip, thereby reducing the thermal stress coupling between the chip and the substrate. The non-linear distribution relationship is as follows: the proportion of copper layer is the smallest near the chip interface, and the proportion of copper layer increases layer by layer with increasing distance from the chip surface. The specific trend of change satisfies a power function model that changes along the thickness direction, which is used to optimize the thermal stress gradient distribution and improve the thermal shock lifetime. The volume fraction C(h) of the copper layer at a depth h from the chip contact surface satisfies the following power function relationship:

[0038]

[0039] Of the parameters mentioned above: This represents the volume fraction of the copper layer at a depth h from the chip surface.

[0040] h represents the depth from the chip contact surface, ranging from 0 to H;

[0041] H represents the total thickness of the entire copper-molybdenum alloy substrate;

[0042] This represents the initial volume fraction of copper at the substrate surface (h=0).

[0043] The maximum volume fraction of copper at the bottom of the substrate (h=H);

[0044] k is the power exponent controlling the curvature of the volume fraction change, and its value is greater than zero.

[0045] By adjusting the parameters , The value of k allows the proportion of copper layer to gradually increase from the surface to the interior, making the thermal expansion behavior of the area near the chip closer to the characteristics of silicon chip, effectively reducing the interface stress concentration caused by thermal mismatch, and improving the mechanical stability and thermal reliability of the packaging structure under thermal cycling conditions.

[0046] Step 2 involves bonding the IGBT chip to the upper surface of the substrate using silver sintering technology in a pressure bonding process. This achieves chip fixation with high thermal performance and high mechanical strength. In Step 2, the thickness of the silver sintered layer between the chip and the substrate exhibits a periodic variation trend during sintering temperature changes. This trend is regulated by a thermal expansion compensation factor, ensuring that the sintered layer maintains good interfacial contact and thermal conductivity even at high temperatures. By constructing a thickness variation model based on temperature variables, this method further improves the chip's reliability in high-temperature environments. The thickness of the silver sintered layer satisfies a dynamic optimization function relationship.

[0047]

[0048] in:

[0049] The thickness of the sintered silver layer at temperature T (K);

[0050] The initial sintering thickness at room temperature is ;

[0051] It is the thermal expansion compensation factor;

[0052] This is the highest temperature during the sintering process.

[0053] Step 3 employs a multi-point voltage-equalizing wiring structure to achieve parallel current distribution across multiple chips. Each chip path undergoes thermal and resistive coupling design to ensure balanced current distribution across all current paths within the package structure, preventing single-point thermal failure caused by current concentration. In the current distribution design between parallel chip paths in Step 3, a current distribution function model is established, using the combined resistance and thermal coupling factor of each path as weighting criteria to ensure the total current is rationally distributed according to the path performance ratio. This method significantly improves the uneven current distribution caused by impedance differences in traditional parallel packaging. Its current sharing function satisfies the following distribution optimization conditions:

[0054]

[0055] in:

[0056] This represents the actual operating current of the i-th parallel chip path.

[0057] For the total design current,

[0058] It is the thermal-resistance coupling coefficient of the i-th path (reflecting the influence of linewidth, solder layer, and copper foil thermal resistance).

[0059] Furthermore, in step 3, the thermal density optimization design establishes a relationship model between the power load per unit package area and the average thermal resistance, achieving a dynamic match between the package's heat dissipation capacity and power handling capacity. This model helps determine the optimal ratio of package area to power density, thereby improving the overall heat dissipation efficiency of the device without increasing the package size. The objective function for optimizing the package thermal density is:

[0060]

[0061] in:

[0062] The heat power density per unit area (W / mm²·K)

[0063] For the maximum operating power of the package,

[0064] To encapsulate the projected area,

[0065] This represents the average thermal resistance.

[0066] Step 4 introduces a position-dependent variable coefficient-based thermal resistance adjustment method during the packaging process to control the uniformity of heat diffusion within the chip or at different locations within the module, thereby enhancing overall heat dissipation performance. In Step 4, the thermal diffusion design achieves non-uniform distribution control of thermal resistance by constructing a function model with the spatial position on the chip surface as the variable. In this model, the chip center has the minimum thermal resistance value, while the thermal resistance gradually increases towards the chip edge, with the increase being a power-law function of the sum of the squares of the chip coordinates. This model can more realistically reflect the changing trend of heat flux density within the package, thus effectively mitigating the problem of thermal stress concentration. Its thermal diffusion equilibrium function is defined as:

[0067]

[0068] in:

[0069] The reference value for thermal resistance at the center point of the chip (unit: K / W).

[0070] (x,y) represents the coordinates of any point on the chip (unit: mm).

[0071] The chip side length (unit: mm).

[0072] , The nonlinear expansion coefficient and exponent of the material's thermal flux are independent of each other.

[0073] Furthermore, in step 4, the temperature distribution inside the package is established using a Gaussian distribution superposition model based on the dual heat source diffusion effect. This model describes the highest temperature at the chip center, which decreases exponentially in both directions, eventually approaching the substrate temperature. This temperature distribution model effectively reflects the location and area of ​​hot spots inside the package, helping to assist in wiring and module layout design to avoid hot spot risks. Its internal temperature distribution function is approximately a double Gaussian superposition model.

[0074]

[0075] in:

[0076] The temperature at any point inside the package.

[0077] The maximum temperature rise at the center point

[0078] ( , () represents the location of the heat source center.

[0079] , For the standard deviation of thermal diffusivity,

[0080] This represents the substrate temperature.

[0081] Step 5 involves passivating the chip surface using plasma treatment and then curing the structure using low-stress molding packaging material. This enhances the chip's long-term reliability and breakdown resistance under high temperature and high current density conditions. In Step 5, the packaging structure reduces thermomechanical mismatch stress at the material interface by minimizing welding stress. This method uses an equivalent stress function to express the thermal stress synthesis effect, comprehensively considering the influence of transverse and longitudinal thermal stresses, as well as the material's Poisson effect on the overall stress field. This improves the overall mechanical strength and thermal shock resistance of the package. The welding stress minimization function is:

[0082]

[0083] in:

[0084] For equivalent stress,

[0085] , Thermal stress along the X and Y axes,

[0086] Let be the Poisson's ratio of the material.

[0087] Furthermore, in step 5, the power cycle life assessment model is based on the coupling relationship between temperature cycle amplitude, average junction temperature, and material activation energy. It uses an exponential function established by empirically fitted parameters for prediction. This model can be used to accurately predict the fatigue life of the packaging structure under long-cycle, high-power cycling, thus providing a theoretical basis for packaging material selection and structural optimization. Its power cycle life prediction function is:

[0088]

[0089] in:

[0090] To predict the number of power cycles,

[0091] This refers to the temperature difference circulation amplitude.

[0092] For the average junction temperature,

[0093] As the reference temperature,

[0094] For material activation energy,

[0095] Boltzmann's constant,

[0096] , This is an empirical constant for the packaging structure.

[0097] The above specific embodiments are merely several preferred embodiments of the present invention. Based on the technical solutions of the present invention and the relevant teachings of the above embodiments, those skilled in the art can make various alternative improvements and combinations to the above specific embodiments.

[0098] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within the present invention.

Claims

1. A packaging method for an ultra-high current planar IGBT chip, characterized in that, Includes the following steps: Step 1: Provide a copper-molybdenum alloy substrate with a high thermal conductivity and a coefficient of thermal expansion close to that of silicon. Step 2: The IGBT chip is bonded to the upper surface of the substrate using silver sintering technology in the pressure bonding process to achieve chip fixation with high thermal performance and high mechanical strength. Step 3: A multi-point voltage equalization wiring structure is adopted to realize the parallel distribution of current of multiple chips. Each chip path is designed with thermal resistance and resistance coupling to ensure the balanced current distribution of each current path in the package structure and avoid single-point thermal failure caused by current concentration. Step 4: During the packaging process, a thermal resistance adjustment method based on position-dependent variable coefficients is introduced to control the uniformity of heat flow diffusion inside the chip or at different locations of the module, thereby enhancing the overall heat dissipation performance. Step 5: Passivate the chip surface through plasma treatment and solidify the structure using low-stress molding packaging material to improve the long-term reliability and breakdown resistance of the chip under high temperature and high current density conditions. The copper-molybdenum alloy substrate adopts a multi-layer gradient structure design, in which the arrangement ratio of copper and molybdenum layers is non-linearly distributed along the thickness direction. This allows the overall thermal expansion coefficient of the substrate to be more precisely matched with the silicon material on the side closer to the chip, thereby reducing the thermal stress coupling between the chip and the substrate. The non-linear distribution relationship is as follows: the proportion of copper layer is the smallest near the chip interface, and the proportion of copper layer increases with the distance from the chip surface. The specific trend of change satisfies a power function model that changes along the thickness direction, which is used to optimize the thermal stress gradient distribution and improve the thermal shock life.

2. The packaging method for an ultra-high current planar IGBT chip according to claim 1, characterized in that: In step 4, the thermal diffusion design achieves non-uniform distribution control of thermal resistance by constructing a function model with the spatial position of the chip surface as the variable. In this function model, the center point of the chip has the minimum thermal resistance value, while the thermal resistance gradually increases towards the edge of the chip, and the increase is in a certain power exponential relationship with the sum of the squares of the chip coordinates.

3. The packaging method for an ultra-high current planar IGBT chip according to claim 1, characterized in that... The characteristic lies in: in the design of current distribution between parallel chip paths in step 3, by establishing electrical... The current distribution function model uses the combined resistance and thermal resistance coupling factor of each path as weighting criteria to ensure that the total current is reasonably distributed according to the performance ratio of each path.

4. The packaging method for an ultra-high current planar IGBT chip according to claim 1, characterized in that: In step 2, the thickness of the silver sintered layer between the chip and the substrate exhibits a periodic variation trend during the sintering temperature change. This variation trend is regulated by the thermal expansion compensation factor to ensure that the sintered layer still has good interfacial contact and thermal conductivity under high temperature conditions, thus constructing a thickness variation model based on temperature variables.

5. The packaging method for an ultra-high current planar IGBT chip according to claim 1, characterized in that: In step 5, the encapsulation structure reduces the thermomechanical mismatch stress at the material interface by minimizing the welding stress. This method uses an equivalent stress function to express the thermal stress synthesis effect, comprehensively considering the influence of transverse and longitudinal thermal stress, as well as the material Poisson effect on the overall stress field.

6. The packaging method for an ultra-high current planar IGBT chip according to claim 1, characterized in that: In step 3, the thermal density optimization design establishes a relationship model between the power load per unit package area and the average thermal resistance, thereby achieving a dynamic match between the package's heat dissipation capability and power handling capability. This model helps determine the optimal ratio of package area to power density.

7. The packaging method for a high-current planar IGBT chip according to claim 1, characterized in that: In step 5, the power cycle life assessment model is based on the coupling relationship between temperature cycle amplitude, average junction temperature and material activation energy. It uses an exponential function established by empirical fitting parameters for prediction. This model is used to accurately predict the fatigue life of the package structure under long-cycle, high-power cycling.

8. The packaging method for an ultra-high current planar IGBT chip according to claim 1, characterized in that: In step 4, the temperature distribution inside the package is established based on a Gaussian distribution superposition model according to the dual heat source diffusion effect. This model describes that the temperature is highest at the center of the chip, decreases exponentially in both directions, and eventually approaches the substrate temperature. This temperature distribution model can effectively reflect the location and area of ​​hot spots inside the package.

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