Wafer defect detection method

Abstract

A wafer defect detection method comprises the following steps: providing a sample wafer, and forming a layer to be detected on the sample wafer; forming an isolation layer on the to-be-tested layer; an etching process is carried out on the isolation layer, and the etching rate of the etching process on the isolation layer is smaller than the etching rate of the etching process on the to-be-tested layer; and carrying out defect detection on the sample wafer. According to the scheme, the signal-to-noise ratio of the wafer surface defects can be increased, the defect detection quality is improved, timely monitoring of a production line is enhanced, and the yield is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device detection, and in particular to a method for detecting wafer surface defects. Background Art

[0002] Defect detection is a crucial step in semiconductor manufacturing. Promptly identifying process defects and machine anomalies helps improve chip performance and device yield. For example, defect detection for scratches on wafer surfaces after chemical mechanical polishing (CMP) is a key method for improving yield.

[0003] However, existing defect detection technologies have limited detection capabilities for recessed defects such as scratches, especially micro-scratches (e.g., less than 60nm), resulting in poor detection quality. This results in existing technologies being unable to effectively monitor defects on wafer surfaces after CMP processes, seriously impacting wafer yield. Summary of the Invention

[0004] The technical problem solved by the present invention is how to improve the detection quality of wafer surface defects after semiconductor processing.

[0005] To solve the above technical problems, an embodiment of the present invention provides a wafer defect detection method, comprising: providing a sample wafer, on which a layer to be tested is formed; forming an isolation layer on the layer to be tested; performing an etching process on the isolation layer, wherein the etching rate of the etching process on the isolation layer is lower than the etching rate on the layer to be tested; and performing defect detection on the sample wafer.

[0006] Optionally, the step of forming an isolation layer on the layer to be measured specifically includes: forming the isolation layer on the layer to be measured using a first deposition process, where the first deposition process is, for example, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

[0007] Optionally, if the surface of the layer to be measured has defects, the isolation layer is formed to expose at least a portion of the surface defects of the layer to be measured.

[0008] Optionally, the etching process includes a wet etching process and / or a dry etching process; wherein, the etching solution used in the wet etching process includes one or more of ammonia water, potassium hydroxide aqueous solution, and hydrofluoric acid; the etching gas used in the dry etching process includes one or more of octafluoroisobutylene, hydrobromic acid, boron trichloride, carbon tetrafluoride, chlorine, and trifluoromethane.

[0009] Optionally, the layer to be tested is obtained through a pretreatment process, and the pretreatment process is, for example, a grinding process, a doping process, a cleaning process, or a second deposition process.

[0010] Optionally, the isolation layer has a thickness of 20 to 50 angstroms.

[0011] Optionally, the etching process is a wet etching process, the etching solution used in the wet etching process is ammonia water, and the etching process takes 30 to 60 seconds.

[0012] Optionally, the etching rate of the isolation layer by the etching process is 0.1 to 0.5 angstroms / second, and the etching rate of the layer to be tested by the etching process is 20 to 30 angstroms / second.

[0013] Optionally, the defect type includes a depression type.

[0014] Optionally, the material of the layer to be tested includes amorphous silicon; and / or the material of the isolation layer includes titanium nitride.

[0015] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0016] An embodiment of the present invention provides a wafer defect detection method, comprising: providing a sample wafer, on which a layer to be tested is formed; forming an isolation layer on the layer to be tested; performing an etching process on the isolation layer, wherein the etching rate of the isolation layer by the etching process is lower than the etching rate of the layer to be tested; and performing defect detection on the sample wafer.

[0017] Compared with the existing problems of weak detection capability for wafer surface scratch defects and yield impact in the prior art, this embodiment amplifies the defect signal by enlarging the defect size, improves the signal-to-noise ratio of wafer surface defects, improves the quality of defect detection, and is conducive to detecting tiny scratches (for example, scratches with a fitting size less than 60nm), strengthening timely monitoring of the production line, and improving the yield. Specifically, after the wafer is processed by a process such as a grinding process, a concave type defect may be formed on the wafer surface. To this end, this embodiment forms an additional isolation layer on the layer to be tested on the surface of the wafer, and performs an etching process on the isolation layer. By controlling the process parameters of the first deposition process for forming the isolation layer, the isolation layer is fractured at the defect location where the layer to be tested may exist, and cannot completely cover the defect location of the layer to be tested, resulting in at least partial exposure of the defect of the layer to be tested. Then, by controlling the difference in etching rate of the etching process on the layer to be tested and the isolation layer, the etching mainly acts on the defect location where the layer to be tested may exist on the surface of the wafer, thereby achieving the expansion of the defect size.

[0018] Furthermore, the isolation layer is formed using a first deposition process. By controlling the relevant parameters of the first deposition process, when the isolation layer is formed on the surface of the layer to be tested, a window exposing the defect is naturally formed at a defect that may exist on the surface of the layer to be tested. When the isolation layer is etched, the etching process can specifically etch the layer to be tested at the defect through the window, thereby enlarging the size of the defect. Furthermore, the non-defective areas on the surface of the wafer layer to be tested are effectively protected by the isolation layer and are not affected by the etching process, so that the defect is enlarged more significantly than the non-defective areas, which is conducive to improving the defect detection rate.

[0019] Furthermore, the material of the test layer includes amorphous silicon, the material of the isolation layer includes titanium nitride, and the etching process is ammonia wet etching. Thus, by utilizing a specially designed Si-ASi-TiN wafer structure (i.e., forming an amorphous silicon test layer on a silicon sample wafer, followed by a titanium nitride isolation layer), combined with the characteristics of ammonia etching, the signal-to-noise ratio of micro-scratch defects on the wafer surface after a chemical mechanical polishing process is improved, thereby enhancing detection quality and strengthening timely monitoring of the production line. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a flow chart of a wafer defect detection method according to an embodiment of the present invention;

[0021] Figures 2 to 5 Schematic diagram of the device cross-sectional structure corresponding to each step in the wafer defect detection method according to an embodiment of the present invention;

[0022] Figure 6 3 is a comparison chart of wafer defect detection results before and after adopting the wafer defect detection method described in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] As mentioned in the background art, existing defect detection technologies have poor detection quality for concave defects, which affects the yield.

[0024] Specifically, in the prior art, in the field of scratch monitoring on the wafer surface after various processes, there is a problem that tiny scratches are difficult to detect, which affects the wafer yield. For example, in the CMP process, due to the serious roughness of the wafer surface after CMP, the defect signal-to-noise ratio is very low, resulting in it being difficult to detect micro scratches smaller than 60nm both in the production line (inline) and the testing stage (offline). If micro scratch defects are found on the polysilicon surface after CMP (poly line end cut etch, P1LEC-ET) and pseudo-polysilicon removal, the timeliness of defect monitoring has been lost. Therefore, improving the detection quality of wafer surface defects (such as micro scratches) after the CMP process is very important for timely and effective monitoring of wafer surface defects.

[0025] Taking the FinFET process as an example, micro-scratches after polysilicon CMP (Chemical Polishing) can cause an abnormal polysilicon profile, resulting in polysilicon residue during dummy polysilicon removal. Experiments have shown that when a micro-scratch size (here referring to the fitted dimensions of length, width, and height) is approximately 60nm, it can affect one poly line in a 14nm process with a 96nm polypitch; and two poly lines in a 7nm process with a 60nm polypitch. This shows that the more advanced the process, the greater the impact of micro-scratches.

[0026] One existing defect detection solution amplifies defect signals by adding an additional coating. However, this solution is only effective for raised defects and is ineffective for sunken defects. It cannot amplify defect signals in sunken areas, resulting in poor detection quality for these defects.

[0027] Another existing defect detection scheme is to immerse the defective wafer in a liquid solution to expand the concave micro-scratch defects on the wafer surface into free polygons, pyramids, cylinders, cubes, etc. In this scheme, the defect-free areas and defective areas on the wafer surface are wet-processed under the same conditions. However, the wafer itself is often made of silicon-containing materials. When the entire wafer is immersed in an alkaline solution to expand the surface defects, the defect-free areas on the wafer surface will inevitably be partially eroded by the alkaline solution. This results in the defect being enlarged to a lesser extent than the defect-free areas, and the improvement in defect detection quality is naturally very limited.

[0028] To solve the above technical problems, an embodiment of the present invention provides a wafer defect detection method, comprising: providing a sample wafer, on which a layer to be tested is formed; forming an isolation layer on the layer to be tested; performing an etching process on the isolation layer, wherein the etching rate of the etching process on the isolation layer is lower than the etching rate on the layer to be tested; and performing defect detection on the sample wafer.

[0029] By adopting this embodiment, the defect signal is amplified by enlarging the defect size, the signal-to-noise ratio of the wafer surface defects is improved, the defect detection quality is improved, and it is conducive to strengthening the timely monitoring of the production line and improving the yield. Specifically, after the wafer is processed by a process such as a grinding process, a concave type defect may be formed on the wafer surface. In this regard, this embodiment forms an additional isolation layer on the layer to be tested on the surface of the wafer, and performs an etching process on the isolation layer. By controlling the process parameters of the first deposition process for forming the isolation layer, the isolation layer is fractured at the defect position where the layer to be tested may exist, and cannot completely cover the defect position of the layer to be tested, resulting in at least partial exposure of the defect of the layer to be tested. Then, the difference in the etching rate of the etching process on the material of the layer to be tested and the material of the isolation layer is controlled, so that the etching mainly acts on the defect position where the layer to be tested may exist on the surface of the wafer, thereby achieving the expansion of the defect size.

[0030] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] Figure 1 This is a flow chart of a wafer defect detection method according to an embodiment of the present invention.

[0032] This embodiment can be applied to the machine testing process (offline), such as in the monitoring scenario of a process machine. By performing defect detection on sample wafers (also called control wafers), machine abnormalities can be monitored in a timely manner.

[0033] The process tool in this embodiment can specifically be a tool that uses a processing technique that is likely to cause pitting defects on the wafer surface. Such processing techniques can include, for example, grinding, doping, cleaning, or deposition processes. Accordingly, the process tools that can be monitored using the method of this embodiment include, for example, grinding, doping, cleaning, and deposition tools.

[0034] Next, using a polishing machine as an example, we will detail the specific process for detecting defects on wafer surfaces caused by the chemical mechanical polishing (CMP) process. For example, if a CMP machine is suspected of causing scratches on the wafer surface, this implementation uses a control chip to monitor the CMP machine, promptly identifying the abnormality and improving process stability.

[0035] Specifically, refer to Figure 1 The wafer defect detection method of this embodiment may include the following steps:

[0036] Step S101, providing a sample wafer, on which a layer to be tested is formed;

[0037] Step S102, forming an isolation layer on the layer to be tested;

[0038] Step S103, performing an etching process on the isolation layer, wherein the etching rate of the isolation layer by the etching process is lower than the etching rate of the layer to be measured;

[0039] Step S104: performing defect detection on the sample wafer.

[0040] More specifically, the layer to be tested can be obtained through a pre-treatment process, which is a processing process performed on a machine that is susceptible to causing the aforementioned pit-like defects on the wafer surface to be monitored. For example, the pre-treatment process can be a grinding process, a doping process, a cleaning process, or a second deposition process.

[0041] Furthermore, in the present embodiment, the isolation layer formed on the surface of the layer to be measured is not a uniform, continuous, and complete layered structure when the surface of the layer to be measured has defects (for example, recessed scratches), but a window appears at the defective position on the surface of the layer to be measured, that is, the defective position of the layer to be measured is not completely covered by the isolation layer, so that in step S103, the same etching process can simultaneously etch the isolation layer and the portion of the layer to be measured exposed by the window.

[0042] Furthermore, the distribution of windows on the formed isolation layer is correlated with the distribution of defects on the surface of the layer to be measured. If the surface of the layer to be measured has defects, the isolation layer formed exposes at least part of the area of defects on the surface of the layer to be measured, that is, the isolation layer has one-to-one corresponding windows generated by the defects on the surface of the layer to be measured. The defect and the adjacent defect-free area form a step, that is, there is a height difference between the defect and the area adjacent to the defect, and the window at least partially exposes the step. The etching process in step S103 can be understood as a selective etching process. Selective etching in this step means that by controlling the difference in etching rate of the isolation layer and the layer to be measured by the etching process, the etching mainly acts on the defects on the surface of the wafer layer to be measured exposed by the window, thereby achieving the amplification of the defect size.

[0043] Next, combine Figures 2 to 5 Each of the above steps is explained in detail.

[0044] In one specific implementation, reference Figure 2 A sample wafer 201 is provided, and an original layer 202 is formed on the surface of the sample wafer 201. The sample wafer 201 may include a semiconductor substrate, and the material of the semiconductor substrate may include silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0045] The original layer 202 can be formed on the surface of the sample wafer 201 by a deposition process. For example, the original layer 202 can be formed on the surface of the sample wafer 201 by using processes such as chemical vapor deposition (CVD) and physical vapor deposition (PVD).

[0046] In some embodiments, the thickness of the original layer 202 formed on the sample wafer 201 falls within the process specification range for the standard thickness of the original layer 202. Specifically, the process specification range for the standard thickness refers to the process specification range that the tool performing the deposition process needs to meet when depositing the original layer 202 during formal production. In other words, the sample wafer 201 provided in step S101 is prepared to simulate the actual production process as much as possible to ensure that the state of the sample wafer 201 arriving at the grinding machine to be monitored is close to the state of the wafer during production on the production line.

[0047] In other embodiments, the sample wafer 201 may also be a wafer extracted during the actual production process. In this case, the sample wafer 201 is prepared by the actual production process, so the stability of the actual production machine and the actual production process can be monitored.

[0048] In some embodiments, the thickness of the original layer 202 may be in the range of 800 to 1300 angstroms.

[0049] In some embodiments, the material of the original layer 202 includes amorphous silicon.

[0050] In one specific implementation, reference Figure 3 The sample wafer 201 can be placed on a grinding machine to grind the original layer 202 to obtain a test layer 203.

[0051] The composition of the test layer 203 and the original layer 202 is the same, except that the thickness of the test layer 203 is slightly smaller than that of the original layer 202, and the surface roughness of the test layer 203 is relatively large and may contain defects 204. The defects 204 may include surface damage such as scratches and nicks.

[0052] Furthermore, the defect 204 and the adjacent defect-free region may form a step 205. The defect-free region may include an area on the surface of the test layer 203 without scratches or scuffs, or an area with very minor scratches that do not materially affect device performance and yield. In some embodiments, the defect-free region may be a flat area or an area with an acceptable roughness.

[0053] Experiments have shown that in the FINFET process, the surface of the test layer 203 obtained after the grinding process is prone to severe roughness and a very low signal-to-noise ratio of the defects 204. If a test machine (also known as a machine that performs defect detection) is used to directly detect the test layer 203 obtained after the grinding process, for example, when an optical scattering signal test machine is used to directly detect the test layer 203, the detection efficiency of small defects (such as micro scratches) with a size less than 60nm is very low. Figure 6 As shown in the two figures to the left of the middle arrow, in this embodiment, optical scattering signals are used to detect defects on the surface of the layer to be tested 203. The sizes of the defects detected by the optical scattering signals are the fitted sizes in the length, width, and height directions. In some embodiments, defects with a minimum size of less than 60 nm in the three directions can be understood as the aforementioned small defects with a size less than 60 nm.

[0054] In some embodiments, the grinding machine may be, for example, a CMP machine. Accordingly, step S101 may specifically include the steps of forming an original layer 202 on the sample wafer, and grinding the original layer 202 using a grinding machine to obtain a layer to be tested 203.

[0055] Furthermore, in some embodiments, the sample wafer 201 is a sample wafer prepared by simulating an actual production process. In order to ensure that the state of the sample wafer 201 arriving at the grinding machine is close to the state of the wafer during production on the production line, the process parameters used in the step of grinding the original layer 202 are consistent with the standard process parameters of the grinding process. Specifically, the standard process parameters of the grinding process may refer to the process parameters used by the grinding machine that performs the grinding process during actual production. Similar to the principle of depositing the original layer 202, when forming the layer to be tested 203, the processing process of the grinding machine grinding the wafer in the actual production process is simulated as much as possible, so that the surface damage of the layer to be tested 203 obtained by grinding is close to the processing result of the grinding machine during actual production, so as to obtain more accurate machine monitoring results.

[0056] In some embodiments, different grinding machines may have different standard process parameters when performing grinding. Accordingly, when executing step S101 , the original layer 202 is ground according to the standard process parameters of the grinding machine that needs to be monitored this time.

[0057] In some embodiments, after the grinding process, the thickness of the test layer 203 may be 600-1000 angstroms.

[0058] In a variation, the layer to be tested 203 may be the original layer 202 , so as to monitor the influence of the deposition process and deposition tool used to form the original layer 202 on semiconductor / wafer surface defects.

[0059] In one specific implementation, reference Figure 4 In step S102, a first deposition process may be used to deposit the isolation layer 206 on the test layer 203. The step coverage (also called step coverage) of the first deposition process is weaker than the step coverage of the standard deposition process used in the step of depositing on the test layer 203.

[0060] Generally speaking, a standard deposition process requires the formation of a uniform, continuous layer on the deposited layer (e.g., the test layer 203 in this example). In other words, a standard deposition process has high requirements for step coverage, allowing for complete coverage even if the surface of the deposited layer contains defects. In this embodiment, however, a deposition process with poorer step coverage is selectively used to ensure that, even if the surface of the test layer 203 has defects 204, the isolation layer 206 formed in step S102 does not uniformly and continuously cover the surface of the test layer 203. Furthermore, this unevenness and discontinuity is particularly evident at step 205.

[0061] Therefore, if the layer to be tested 203 has a defect 204 , the formed isolation layer 206 has a window 207 generated by the defect 204 , and the window 207 at least partially exposes the defect 204 .

[0062] In some embodiments, the isolation layer 206 capable of naturally generating a window 207 at the defect 204 can be formed on the surface of the layer to be tested 203 by adjusting relevant process parameters of the first deposition process, such as deposition process type, deposition thickness, deposition material, etc.

[0063] For example, the first deposition process may include a PVD process, and the thickness of the isolation layer 206 may be between 20 and 50 angstroms. The isolation layer 206 may be made of titanium nitride (TiN). Specifically, the interface at the defect 204 is irregular. By controlling the thickness of the titanium nitride and taking advantage of the relatively poor step coverage of the PVD process, the titanium nitride cannot grow continuously at the defect 204 on the surface of the test layer 203, and the interface of the defect 204 cannot be sealed. As a result, a gap is generated in the defect 204 area, forming a window 207.

[0064] Furthermore, due to the naturally formed windows 207 during the formation of isolation layer 206, isolation layer 206 behaves similarly to a photolithography mask used to pattern a photoresist layer in a photolithography process. Therefore, isolation layer 206 can be used as a mask in the subsequent step S103. In this embodiment, the specific pattern formed by patterned isolation layer 206 is determined based on the defect layout on the surface of the test layer 203 obtained by the grinding process in step S101. Therefore, it is expected that this pattern will vary from batch to batch due to factors such as the grinding machine and the grinding process.

[0065] In a specific embodiment, referring to Figure 5 In step S103, the isolation layer 206 is etched. Specifically, the etching process used in step S103 may include a wet etching process, and the etching solution used in the wet etching process may include one or more of ammonia water (NH4OH), potassium hydroxide aqueous solution (KOH), and hydrofluoric acid (HF). For example, the wafer processed in step S102 may be immersed in an etching chamber containing a single etching solution for etching. For another example, multiple etching solutions may be mixed and sprayed on the surface of the wafer processed in step S102 in sequence for etching.

[0066] Furthermore, the etching solution used in the step of etching the isolation layer 206 has an etching rate on the isolation layer 206 that is lower than an etching rate on the layer to be tested 203 .

[0067] Furthermore, in this embodiment, the difference between the etching rate of the etching solution on the isolation layer 206 and the etching rate of the test layer 203 can be minimized. Specifically, the etching solution can hardly etch the isolation layer 206, or the etching solution can etch the test layer 203 much more than the isolation layer 206 within the same etching time, and the difference in etching amount can be clearly detected by the instrument. In practical applications, the difference between the etching rate of the etching solution on the isolation layer 206 and the etching rate of the test layer 203 can be made to fall within a preset range. The preset range of the difference between the two etching rates can be, for example, 15-45 angstroms / second.

[0068] In some embodiments, the original layer 202 is amorphous silicon and the isolation layer 206 is titanium nitride. The etching process can be ammonia wet etching. Specifically, taking advantage of the fact that ammonia has a high etching ratio for amorphous silicon and almost no etching rate for metal, the isolation layer 206 made of titanium nitride is wet-etched for 30 to 60 seconds using ammonia (aqueous solution of 98% concentrated ammonia and pure water in a volume ratio of 1:5). The ammonia reacts with the test layer 203 made of amorphous silicon at the defect 204 along the gap (i.e., window 207) at the discontinuity of the isolation layer 206, thereby expanding the scope of the defect 204 and strengthening the trace of the defect 204.

[0069] Combine Figure 6The two figures to the right of the arrows show that the aforementioned process can consume approximately 200 to 400 angstroms of amorphous silicon in the test layer 203 at the location of the defects 204. Ultimately, the size of most defects 204 on the surface of the test layer 203 is enlarged to greater than 60 nm, making them effectively detectable by the test equipment. It can be seen that compared to directly performing defect detection on the surface of the test layer 203 obtained in step S101, executing steps S102 and S103 effectively enlarges the defects 204, significantly increasing the number of defects 204 that can be detected in step S104.

[0070] Therefore, by utilizing a specially designed Si-ASi-TiN wafer structure (i.e., forming a titanium nitride isolation layer 206 on a silicon sample wafer 201 having an amorphous silicon test layer 203), and based on the characteristics of ammonia etching, the signal-to-noise ratio of micro-scratch defects on the wafer surface after a grinding process (e.g., CMP) is improved, thereby enhancing the detection quality and strengthening timely monitoring of the production line.

[0071] In one variation, the etching process used in step S103 may include a dry etching process. The etching gas used in the dry etching process may include one or more of octafluoroisobutylene (C4F8), hydrobromic acid (HBr), boron trichloride (BCl3), carbon tetrafluoride (CF4), chlorine (CL2), and trifluoromethane (CHF3). For example, during the dry etching, a single etching gas may be delivered into the etching chamber. For another example, a mixed gas formed by multiple etching gases may be used to dry etch the wafer processed in step S103.

[0072] In one variation, in step S103, multiple etching processes may be sequentially applied to the sample wafer having the isolation layer 206 formed thereon to obtain a better etching effect. Specifically, the sample wafer having the isolation layer 206 formed thereon may be etched using a first etching process first, and then further etched using a second etching process.

[0073] For example, the first etching process and the second etching process may both be ammonia wet etching, the difference being that the ammonia concentration in the ammonia ratio used in the first etching process is higher than that in the second etching process.

[0074] For another example, the first etching process and the second etching process may be wet etching using different types of etching solutions. For example, the first etching process may be wet etching using a potassium hydroxide aqueous solution, and the second etching process may be wet etching using ammonia water.

[0075] For another example, the first etching process may be a dry etching process, and the second etching process may be a wet etching process. Specifically, the sample wafer with the isolation layer 206 formed thereon may be etched with an etching gas first, and then the isolation layer 206 and the test layer 203 exposed by the window 207 may be cleaned with an alkaline solution to further enlarge the size of the defect 204.

[0076] In a specific implementation, after step S104, the method described in this embodiment may further include the step of monitoring the operating status of the process machine according to the result of defect detection, wherein the process machine is a machine that performs a pre-treatment process on the original layer 202 to form the layer to be tested 203. Furthermore, the process machine may be, for example, a machine that performs the grinding process (i.e., a grinding machine). Thus, during the machine testing process, by performing defect detection on the sample wafer 201 according to this embodiment, the operating status and performance of the grinding machine can be monitored in real time, and a timely response can be made when a machine abnormality is detected. Furthermore, the detection results of the machine testing stage are used to further control and improve the stability of the machine process during production line production, thereby improving the yield rate.

[0077] In one specific implementation, before executing step S103, the method of this embodiment may further include the step of determining process parameters based on the minimum defect size detectable by a tool performing defect detection (i.e., a test tool). The process parameters are selected from at least one of the following: the material of the test layer 203, the material of the isolation layer 206, the type of etching process, the etching solution (or etching gas) used in the etching process, and the etching time.

[0078] The etching time can be determined based on the etching rate of the etching solution (or etching gas) on the material of the test layer and the isolation layer. For example, the etching rate of amorphous silicon by ammonia water (ammonia solution of 98% by mass concentrated ammonia water and pure water in a volume ratio of 1:5) is approximately 20-30 angstroms / second.

[0079] In this embodiment, the size of defect 204 on test layer 203 is increased by increasing the difference in etching rates between the material of test layer 203 and the material of isolation layer 206. This difference in etching rates is specifically manifested as follows: per unit time, the etching amount of isolation layer 206 is almost zero, while the etching amount of test layer 203 is as large as possible. Accordingly, the etching process is required to have an extremely low etching rate for isolation layer 206, such as 0.1 to 0.5 angstroms per second, while the etching rate for test layer 203 is relatively high, such as 20 to 30 angstroms per second.

[0080] In another specific embodiment, the test layer 203 formed on the wafer 201 may be oxide, the isolation layer 206 formed on the test layer 203 may be aluminum nitride (ALN), and the etching process in step S103 may be a hydrofluoric acid (HF) wet etching process.

[0081] Therefore, according to the detection capability of the test machine (for example, the minimum defect size that the test machine can effectively identify), the material of the layer to be tested 203, the material of the isolation layer 206, the type of etching process, the etching solution (or etching gas) and the etching time are determined to ensure that as many surface defects 204 of the layer to be tested 203 as possible are magnified to a defect size that meets the detection capability.

[0082] From the above, this embodiment is adopted to amplify the defect signal by enlarging the defect size, improve the signal-to-noise ratio of wafer surface defects, improve the quality of defect detection, and help strengthen the timely monitoring of the production line and improve the yield. Specifically, after the use of process treatments such as grinding processes, concave-type defects may be formed on the wafer surface. In this regard, this embodiment forms an additional isolation layer on the layer to be tested on the surface of the wafer, and performs an etching process on the isolation layer. By controlling the process parameters of the first deposition process for forming the isolation layer, the isolation layer is fractured at the defect of the layer to be tested, and cannot completely cover the defect position of the layer to be tested, resulting in at least partial exposure of the defect of the layer to be tested. By controlling the difference in etching rate of the etching process on the material of the layer to be tested and the material of the isolation layer, the etching is mainly applied to the defects that may exist on the surface of the layer to be tested, thereby achieving the expansion of the defect size and improving the quality of defect detection. Furthermore, when the isolation layer is formed, a window exposing at least a part of the defect area is naturally formed at the defect, and then the layer to be tested at the defect is targeted through the window through the etching process to achieve the expansion of the defect size. Furthermore, the defect-free areas on the surface of the wafer layer to be tested are effectively protected by the isolation layer and are not affected by the etching process, so that the defective areas are more significantly enlarged than the defect-free areas, which is conducive to improving the defect detection rate.

[0083] It should be understood that the term "and / or" as used herein simply describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " as used herein indicates that the related objects are in an "or" relationship.

[0084] The first, second, etc. descriptions appearing in the embodiments of this application are only for illustration and distinction of the description objects. There is no order, nor does it indicate any special limitation on the number of devices in the embodiments of this application, and cannot constitute any limitation on the embodiments of this application.

[0085] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A wafer defect detection method, characterized in that: include: Providing a sample wafer, on which a layer to be tested is formed; forming an isolation layer on the layer to be measured; Performing an etching process on the isolation layer, wherein an etching rate of the isolation layer by the etching process is lower than an etching rate of the layer to be measured; Defect detection is performed on the sample wafer.

2. The method according to claim 1, characterized in that The step of forming an isolation layer on the layer to be measured specifically includes: forming the isolation layer on the layer to be measured by a first deposition process, and the first deposition process can be a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

3. The method according to claim 1, characterized in that If the surface of the layer to be measured has defects, the formed isolation layer exposes at least a portion of the surface defects of the layer to be measured.

4. The method according to claim 1, wherein The etching process includes a wet etching process and / or a dry etching process; wherein the etching solution used in the wet etching process includes one or more of ammonia water, potassium hydroxide aqueous solution, and hydrofluoric acid; the etching gas used in the dry etching process includes one or more of octafluoroisobutylene, hydrobromic acid, boron trichloride, carbon tetrafluoride, chlorine, and trifluoromethane.

5. The method according to claim 1, wherein The layer to be tested is obtained through a pretreatment process, and the pretreatment process can be a grinding process, a doping process, a cleaning process or a second deposition process.

6. The method according to claim 1, characterized in that The thickness of the isolation layer is 20 to 50 angstroms.

7. The method according to claim 6, characterized in that The etching process is a wet etching process, the etching solution used in the wet etching process is ammonia water, and the etching process takes 30 to 60 seconds.

8. The method according to claim 1, characterized in that The etching rate of the isolation layer by the etching process is 0.1 to 0.5 angstroms / second, and the etching rate of the layer to be tested by the etching process is 20 to 30 angstroms / second.

9. The method according to any one of claims 1 to 8, characterized in that The types of defects include a pit type.

10. The method according to any one of claims 1 to 8, wherein the material of the layer to be measured comprises amorphous silicon; And / or, the material of the isolation layer includes titanium nitride.

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