A charge pump circuit based on closed loop feedback control

Abstract

The application discloses a charge pump circuit based on closed-loop feedback control and relates to the technical field of analog integrated circuit power management. The charge pump circuit comprises a two-phase non-overlapping clock generating circuit, a control signal generating circuit and a charge pump main circuit. The charge pump main circuit comprises a cross-coupled circuit, a feedback circuit and an operational amplifier circuit. The output voltage of the cross-coupled circuit is output through an output port VCP. The voltage at the output port VCP is processed through the feedback circuit and the operational amplifier circuit in sequence and then fed back to the control signal generating circuit through an operational amplifier output port VPVB, so that the feedback control of the charge pump main circuit is realized, and a high-voltage voltage source is obtained. The high-voltage source voltage is high in precision, and the absolute value of the high-voltage source voltage does not change with the error of an integrated circuit manufacturing process and the change of temperature.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit power management technology, and in particular to a charge pump circuit based on closed-loop feedback control. Background Technology

[0002] The integrated circuit industry is the core of the information technology industry and a strategic, fundamental, and pioneering industry supporting economic and social development and safeguarding national security. With the rapid development of electronic technology, inertial sensors are widely used in navigation, vibration measurement, attitude monitoring, and other fields. In practical applications, due to various external interferences (such as temperature changes, humidity changes, electromagnetic interference, etc.) and internal factors (such as component aging, manufacturing errors, etc.), the output of inertial sensors may exhibit deviations or fluctuations.

[0003] In existing technologies, inertial sensors often employ traditional charge pump circuits, such as Dickson charge pumps, to generate a high-voltage source. To achieve precise feedback control of the inertial sensor, a high-precision, cryogenically drifting high-voltage source is required, and this source must be electrically connected to the inertial sensor. Finally, during power supply, the high-precision, cryogenically drifting high-voltage source is monitored and adjusted in real time to ensure that the supply voltage and current remain within the specified range.

[0004] The drawback of the aforementioned existing technology is that traditional charge pump circuits generate high voltage source voltage, and the absolute value of the high voltage source voltage will vary with the error of integrated circuit manufacturing process and temperature changes. Summary of the Invention

[0005] Therefore, it is necessary to provide a charge pump circuit based on closed-loop feedback control to address the aforementioned technical problems.

[0006] This invention provides a charge pump circuit based on closed-loop feedback control, comprising: a two-phase non-overlapping clock generation circuit, a control signal generation circuit, and a charge pump main circuit;

[0007] The main circuit of the charge pump includes: a cross-coupled circuit, a feedback circuit, and an operational amplifier circuit;

[0008] The input of the cross-coupled circuit is connected to the power supply VDD, the output of the cross-coupled circuit is connected to the output port VCP and the input of the feedback circuit, and the output of the feedback circuit is connected to the operational amplifier circuit.

[0009] The feedback circuit includes a first adjustable resistor R1 and a second adjustable resistor R2; one end of the first adjustable resistor R1 is connected to the output terminal of the cross-coupled circuit, and the other end of the first adjustable resistor R1 is connected to one end of the second adjustable resistor R2 and the operational amplifier circuit; the other end of the second adjustable resistor R2 is grounded.

[0010] The operational amplifier circuit includes a first operational amplifier OP1 and a second operational amplifier OP2. The non-inverting input terminal IN+ of the first operational amplifier OP1 is connected to the feedback circuit, the inverting input terminal IN- of the first operational amplifier OP1 is connected to the reference source port VREF, and the output terminal OUT of the first operational amplifier OP1 is connected to the non-inverting input terminal IN+ of the second operational amplifier OP2. The inverting input terminal IN- of the second operational amplifier OP2 is connected to its output terminal OUT, and both are connected to the operational amplifier output port VPVB. The operational amplifier output port VPVB is connected to the control signal generation circuit.

[0011] The output voltage of the cross-coupled circuit is output through the output port VCP. The voltage at the output port VCP is processed by the feedback circuit and the operational amplifier circuit in sequence, and then fed back to the control signal generation circuit through the operational amplifier output port VPVB to realize the feedback control of the charge pump main circuit and obtain a high voltage source.

[0012] Optionally, the input terminal of the two-phase non-overlapping clock generation circuit is connected to the input port CLKIN, and the two-phase non-overlapping clock generation circuit is connected to the input terminal of the control signal generation circuit through the first output port CLK1, the first inverted output port CLK1N, the second output port CLK2, and the second inverted output port CLK2N.

[0013] The control signal generation circuit is connected to the input terminal of the charge pump main circuit through the first output port CKOUT1, the first inverted output port CKNOUT1, the second output port CKOUT2, and the second inverted output port CKNOUT2.

[0014] The two-phase non-overlapping clock generation circuit, control signal generation circuit, and charge pump main circuit are all connected to power supply VDD and ground.

[0015] Optionally, the cross-coupled circuit includes: module A1, module A2, and module A3; the input terminal of module A1 is connected to power supply VDD, the output terminal of module A1 is connected to the input terminal of module A2, the output terminal of module A2 is connected to the input terminal of module A3, and the output terminal of module A3 is connected to the output port VCP.

[0016] Optionally, module A1 specifically includes: a first capacitor C C1 Second capacitor C C2 The second N-type MOSFET NM2, the third N-type MOSFET NM3, the third P-type MOSFET PM3, and the fourth P-type MOSFET PM4;

[0017] First capacitor C C1 One end is connected to the second output port CKOUT2 of the control signal generation circuit, and the first capacitor C C1The other end is connected to the source (S) terminal of the second N-type MOSFET NM2, the source (S) terminal of the third P-type MOSFET PM3, the gate (G) terminal of the third N-type MOSFET NM3, and the gate (G) terminal of the fourth P-type MOSFET PM4; the drain (D) terminals of the second N-type MOSFET NM2 and the third N-type MOSFET NM3 are connected to the power supply VDD.

[0018] The gate (G) terminal of the second N-type MOSFET NM2, the source (S) terminal of the third N-type MOSFET NM3, the source (S) terminal of the fourth P-type MOSFET PM4, and the gate (G) terminal of the third P-type MOSFET PM3 are connected to the second capacitor C. C2 One end, the second capacitor C C2 The other end is connected to the second inverted output port CKNOUT2 of the control signal generation circuit, and the D terminal of the third P-type MOSFET PM3 and the D terminal of the fourth P-type MOSFET PM4 serve as the output terminals of the A1 module.

[0019] Optionally, module A2 specifically includes: a first capacitor C C1 Second capacitor C C2 The second N-type MOSFET NM2, the third N-type MOSFET NM3, the third P-type MOSFET PM3, and the fourth P-type MOSFET PM4;

[0020] First capacitor C C1 One end is connected to the first output port CKOUT1 of the control signal generation circuit, and the first capacitor C C1 The other end is connected to the source (S) terminal of the second N-type MOSFET NM2, the source (S) terminal of the third P-type MOSFET PM3, the gate (G) terminal of the third N-type MOSFET NM3, and the gate (G) terminal of the fourth P-type MOSFET PM4; the drain (D) terminals of the second N-type MOSFET NM2 and the third N-type MOSFET NM3 are connected to the output terminal of module A1; the gate (G) terminals of the second N-type MOSFET NM2, the source (S) terminal of the third N-type MOSFET NM3, the source (S) terminal of the fourth P-type MOSFET PM4, and the gate (G) terminal of the third P-type MOSFET PM3 are connected to the second capacitor C. C2 One end is connected; the second capacitor C C2 The other end is connected to the first inverted output port CKNOUT1 of the control signal generation circuit, and the D terminal of the third P-type MOSFET PM3 and the D terminal of the fourth P-type MOSFET PM4 serve as the output terminals of the A2 module.

[0021] Optionally, module A3 specifically includes: a first capacitor C C1 Second capacitor C C2 The second N-type MOSFET NM2, the third N-type MOSFET NM3, the third P-type MOSFET PM3, and the fourth P-type MOSFET PM4;

[0022] First capacitor C C1 One end is connected to the second output port CKOUT2 of the control signal generation circuit, and the first capacitor CC1 The other end is connected to the source (S) terminal of the second N-type MOSFET NM2, the source (S) terminal of the third P-type MOSFET PM3, the gate (G) terminal of the third N-type MOSFET NM3, and the gate (G) terminal of the fourth P-type MOSFET PM4; the drain (D) terminals of the second N-type MOSFET NM2 and the third N-type MOSFET NM3 are connected to the output terminal of module A2; the gate (G) terminals of the second N-type MOSFET NM2, the source (S) terminal of the third N-type MOSFET NM3, the source (S) terminal of the fourth P-type MOSFET PM4, and the gate (G) terminal of the third P-type MOSFET PM3 are connected to the second capacitor C. C2 One end is connected; the second capacitor C C2 The other end is connected to the second inverted output port CKNOUT2 of the control signal generation circuit. The D terminal of the third P-type MOSFET PM3 and the D terminal of the fourth P-type MOSFET PM4 are connected to the output port VCP as the output terminals of the A3 module.

[0023] Optionally, the control signal generation circuit includes: a seventh P-type MOSFET PM7, an eighth P-type MOSFET PM8, a ninth P-type MOSFET PM9, a fifth N-type MOSFET NM5, a sixth N-type MOSFET NM6, a tenth P-type MOSFET PM10, an eleventh P-type MOSFET PM11, a twelfth P-type MOSFET PM12, a seventh N-type MOSFET NM7, and an eighth N-type MOSFET NM8;

[0024] The source (S) terminal of the seventh P-type MOSFET PM7 is connected to the power supply VDD; the gate (G) terminal of the seventh P-type MOSFET PM7 is connected to the operational amplifier output port VPVB; the drain (D) terminal of the seventh P-type MOSFET PM7 is connected to the source (S) terminals of the eighth P-type MOSFET PM8 and the ninth P-type MOSFET PM9; the gate (G) terminal of the eighth P-type MOSFET PM8 is connected to the first inverting output port CLK1N of the two-phase non-overlapping clock generation circuit; the drain (D) terminals of the eighth P-type MOSFET PM8 and the fifth N-type MOSFET NM5 are connected to the second output port CKOUT2 of the control signal generation circuit; the fifth N-type MOSFET NM... The G terminal of transistor 5 is connected to the second output port CLK2 of the two-phase non-overlapping clock generation circuit, and the S terminal of the fifth N-type MOSFET NM5 is grounded; the G terminal of the ninth P-type MOSFET PM9 is connected to the second inverting output port CLK2N of the two-phase non-overlapping clock generation circuit, and the D terminal of the ninth P-type MOSFET PM9 and the D terminal of the sixth N-type MOSFET NM6 are connected to the second inverting output port CKNOUT2 of the control signal generation circuit; the G terminal of the sixth N-type MOSFET NM6 is connected to the first output port CLK1 of the two-phase non-overlapping clock generation circuit, and the S terminal of the sixth N-type MOSFET NM6 is grounded;

[0025] The source (S) terminal of the 10th P-type MOSFET PM10 is connected to VDD; the gate (G) terminal of the 10th P-type MOSFET PM10 is connected to the operational amplifier output port VPVB; the drain (D) terminal of the 10th P-type MOSFET PM10 is connected to the source (S) terminals of the 11th P-type MOSFET PM11 and the 12th P-type MOSFET PM12; the gate (G) terminal of the 11th P-type MOSFET PM11 is connected to the first inverting output port CLK1N of the two-phase non-overlapping clock generation circuit; the drain (D) terminals of the 11th P-type MOSFET PM11 and the 7th N-type MOSFET NM7 are connected to the first output port CKOUT1 of the control signal generation circuit; the 7th N-type MOSFET... The gate (G) terminal of the S-type MOSFET NM7 is connected to the second output port CLK2 of the two-phase non-overlapping clock generation circuit. The gate (S) terminal of the seventh N-type MOSFET NM7 is grounded. The gate (G) terminal of the twelfth P-type MOSFET PM12 is connected to the second inverting output port CLK2N of the two-phase non-overlapping clock generation circuit. The drain (D) terminals of the twelfth P-type MOSFET PM12 and the eighth N-type MOSFET NM8 are connected to the first output port CKNOUT1 of the control signal generation circuit. The gate (G) terminal of the eighth N-type MOSFET NM8 is connected to the first output port CLK1 of the two-phase non-overlapping clock generation circuit. The gate (S) terminal of the eighth N-type MOSFET NM8 is grounded.

[0026] The charge pump circuit based on closed-loop feedback control provided in this embodiment of the invention has the following advantages compared with the prior art:

[0027] The output voltage of the cross-coupled circuit of this invention is output through the output port VCP. The voltage at the output port VCP is processed by the feedback circuit and the operational amplifier circuit in sequence, and then fed back to the control signal generation circuit through the operational amplifier output port VPVB to realize the feedback control of the charge pump main circuit and obtain a high voltage source.

[0028] In the above process, the output voltage of the cross-coupled circuit is determined by the resistance values ​​of the first adjustable resistor R1 and the second adjustable resistor R2. The voltage value at the output port VCP can be adjusted by changing the resistance values ​​of the first adjustable resistor R1 and the second adjustable resistor R2, and it is not sensitive to fluctuations in the power supply voltage or the process temperature fluctuations of other devices. Therefore, the high-voltage source of the present invention has high voltage accuracy, and the absolute value of the high-voltage source voltage will not change with the error of the integrated circuit manufacturing process or the temperature variation. Attached Figure Description

[0029] Figure 1 This is a circuit diagram of a charge pump circuit based on closed-loop feedback control provided in one embodiment;

[0030] Figure 2 This is a schematic diagram of a control signal generation circuit for a charge pump circuit based on closed-loop feedback control, provided in one embodiment.

[0031] Figure 3This is a schematic diagram of the main circuit of a charge pump circuit based on closed-loop feedback control, provided in one embodiment. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0033] In one embodiment, a charge pump circuit based on closed-loop feedback control is provided, such as... Figure 1 As shown, it includes: a two-phase non-overlapping clock generation circuit, a control signal generation circuit, and a charge pump main circuit.

[0034] The input terminal of the two-phase non-overlapping clock generation circuit is connected to the input port CLKIN. The two-phase non-overlapping clock generation circuit is connected to the input terminal of the control signal generation circuit through the first output port CLK1, the first inverted output port CLK1N, the second output port CLK2, and the second inverted output port CLK2N.

[0035] The control signal generation circuit is connected to the input terminal of the charge pump main circuit through the first output port CKOUT1, the first inverted output port CKNOUT1, the second output port CKOUT2, and the second inverted output port CKNOUT2.

[0036] In addition, the two-phase non-overlapping clock generation circuit, the control signal generation circuit, and the charge pump main circuit are all connected to the power supply VDD and ground (GND).

[0037] 1. Control signal generation circuit

[0038] like Figure 2 As shown, the control signal generation circuit includes: the seventh P-type MOSFET PM7, the eighth P-type MOSFET PM8, the ninth P-type MOSFET PM9, the fifth N-type MOSFET NM5, the sixth N-type MOSFET NM6, the tenth P-type MOSFET PM10, the eleventh P-type MOSFET PM11, the twelfth P-type MOSFET PM12, the seventh N-type MOSFET NM7, and the eighth N-type MOSFET NM8;

[0039] In this circuit, the source (S) terminal of the seventh P-type MOSFET PM7 is connected to the power supply VDD; the gate (G) terminal of the seventh P-type MOSFET PM7 is connected to the operational amplifier output port VPVB; the drain (D) terminal of the seventh P-type MOSFET PM7 is connected to the source (S) terminals of the eighth P-type MOSFET PM8 and the ninth P-type MOSFET PM9; the gate (G) terminal of the eighth P-type MOSFET PM8 is connected to the first inverting output port CLK1N of the two-phase non-overlapping clock generation circuit; the drain (D) terminals of the eighth P-type MOSFET PM8 and the fifth N-type MOSFET NM5 are connected to the second output port CKOUT2 of the control signal generation circuit; and the fifth N-type MOSFET... The gate (G) terminal of NM5 is connected to the second output port CLK2 of the two-phase non-overlapping clock generation circuit, and the source (S) terminal of the fifth N-type MOSFET NM5 is grounded; the gate (G) terminal of the ninth P-type MOSFET PM9 is connected to the second inverting output port CLK2N of the two-phase non-overlapping clock generation circuit, and the drain (D) terminals of the ninth P-type MOSFET PM9 and the sixth N-type MOSFET NM6 are connected to the second inverting output port CKNOUT2 of the control signal generation circuit; the gate (G) terminal of the sixth N-type MOSFET NM6 is connected to the first output port CLK1 of the two-phase non-overlapping clock generation circuit, and the source (S) terminal of the sixth N-type MOSFET NM6 is grounded.

[0040] The source (S) terminal of the 10th P-type MOSFET PM10 is connected to VDD; the gate (G) terminal of the 10th P-type MOSFET PM10 is connected to the operational amplifier output port VPVB; the drain (D) terminal of the 10th P-type MOSFET PM10 is connected to the source (S) terminals of the 11th P-type MOSFET PM11 and the 12th P-type MOSFET PM12; the gate (G) terminal of the 11th P-type MOSFET PM11 is connected to the first inverting output port CLK1N of the two-phase non-overlapping clock generation circuit; the drain (D) terminals of the 11th P-type MOSFET PM11 and the 7th N-type MOSFET NM7 are connected to the first output port CKOUT1 of the control signal generation circuit; the 7th N-type MOSFET... The gate (G) terminal of the S-type MOSFET NM7 is connected to the second output port CLK2 of the two-phase non-overlapping clock generation circuit. The gate (S) terminal of the seventh N-type MOSFET NM7 is grounded. The gate (G) terminal of the twelfth P-type MOSFET PM12 is connected to the second inverting output port CLK2N of the two-phase non-overlapping clock generation circuit. The drain (D) terminals of the twelfth P-type MOSFET PM12 and the eighth N-type MOSFET NM8 are connected to the first output port CKNOUT1 of the control signal generation circuit. The gate (G) terminal of the eighth N-type MOSFET NM8 is connected to the first output port CLK1 of the two-phase non-overlapping clock generation circuit. The gate (S) terminal of the eighth N-type MOSFET NM8 is grounded.

[0041] 2. Charge pump main circuit

[0042] like Figure 3 As shown, the main circuit of the charge pump includes a cross-coupled circuit, a feedback circuit, and an operational amplifier circuit.

[0043] 2.1 Cross-coupled circuit

[0044] The cross-coupled circuit includes modules A1, A2, and A3. The input of module A1 is connected to the power supply VDD, the output of module A1 is connected to the input of module A2, the output of module A2 is connected to the input of module A3, and the output of module A3 is connected to the output port VCP.

[0045] 2.1.1 Module A1

[0046] Module A1 specifically includes: the first capacitor C C1 Second capacitor C C2 The second N-type MOSFET NM2, the third N-type MOSFET NM3, the third P-type MOSFET PM3, and the fourth P-type MOSFET PM4;

[0047] First capacitor C C1 One end is connected to the second output port CKOUT2 of the control signal generation circuit, and the first capacitor C C1 The other end is connected to the source (S) terminal of the second N-type MOSFET NM2, the source (S) terminal of the third P-type MOSFET PM3, the gate (G) terminal of the third N-type MOSFET NM3, and the gate (G) terminal of the fourth P-type MOSFET PM4. The drain (D) terminals of the second N-type MOSFET NM2 and the third N-type MOSFET NM3 are connected to the power supply VDD.

[0048] The gate (G) terminal of the second N-type MOSFET NM2, the source (S) terminal of the third N-type MOSFET NM3, the source (S) terminal of the fourth P-type MOSFET PM4, and the gate (G) terminal of the third P-type MOSFET PM3 are connected to the second capacitor C. C2 One end, the second capacitor C C2 The other end is connected to the second inverted output port CKNOUT2 of the control signal generation circuit, and the D terminal of the third P-type MOSFET PM3 and the D terminal of the fourth P-type MOSFET PM4 serve as the output terminals of the A1 module.

[0049] 2.1.2 Module A2

[0050] Module A2 specifically includes: the first capacitor C C1 Second capacitor C C2 The second N-type MOSFET NM2, the third N-type MOSFET NM3, the third P-type MOSFET PM3, and the fourth P-type MOSFET PM4;

[0051] First capacitor C C1 One end is connected to the first output port CKOUT1 of the control signal generation circuit, and the first capacitor C C1The other end is connected to the source (S) terminal of the second N-type MOSFET NM2, the source (S) terminal of the third P-type MOSFET PM3, the gate (G) terminal of the third N-type MOSFET NM3, and the gate (G) terminal of the fourth P-type MOSFET PM4; the drain (D) terminals of the second N-type MOSFET NM2 and the third N-type MOSFET NM3 are connected to the output terminal of module A1; the gate (G) terminals of the second N-type MOSFET NM2, the source (S) terminal of the third N-type MOSFET NM3, the source (S) terminal of the fourth P-type MOSFET PM4, and the gate (G) terminal of the third P-type MOSFET PM3 are connected to the second capacitor C. C2 One end is connected; the second capacitor C C2 The other end is connected to the first inverted output port CKNOUT1 of the control signal generation circuit, and the D terminal of the third P-type MOSFET PM3 and the D terminal of the fourth P-type MOSFET PM4 serve as the output terminals of the A2 module.

[0052] 2.1.3 Module A3

[0053] Module A3 specifically includes: the first capacitor C C1 Second capacitor C C2 The second N-type MOSFET NM2, the third N-type MOSFET NM3, the third P-type MOSFET PM3, and the fourth P-type MOSFET PM4;

[0054] First capacitor C C1 One end is connected to the second output port CKOUT2 of the control signal generation circuit, and the first capacitor C C1 The other end is connected to the source (S) terminal of the second N-type MOSFET NM2, the source (S) terminal of the third P-type MOSFET PM3, the gate (G) terminal of the third N-type MOSFET NM3, and the gate (G) terminal of the fourth P-type MOSFET PM4; the drain (D) terminals of the second N-type MOSFET NM2 and the third N-type MOSFET NM3 are connected to the output terminal of module A2; the gate (G) terminals of the second N-type MOSFET NM2, the source (S) terminal of the third N-type MOSFET NM3, the source (S) terminal of the fourth P-type MOSFET PM4, and the gate (G) terminal of the third P-type MOSFET PM3 are connected to the second capacitor C. C2 One end is connected; the second capacitor C C2 The other end is connected to the second inverted output port CKNOUT2 of the control signal generation circuit. The D terminal of the third P-type MOSFET PM3 and the D terminal of the fourth P-type MOSFET PM4 are connected to the output port VCP as the output terminals of the A3 module.

[0055] 2.2 Feedback Circuit

[0056] The feedback circuit includes a first adjustable resistor R1 and a second adjustable resistor R2. One end of the first adjustable resistor R1 is connected to the output terminal of the cross-coupled circuit, and the other end of the first adjustable resistor R1 is connected to one end of the second adjustable resistor R2 and the operational amplifier circuit. The other end of the second adjustable resistor R2 is grounded.

[0057] 2.3 Operational Amplifier Circuit

[0058] The operational amplifier circuit includes a first operational amplifier OP1 and a second operational amplifier OP2. The non-inverting input (IN+) of the first operational amplifier OP1 is connected to the feedback circuit, and the inverting input (IN-) is connected to the reference source port VREF. The output (OUT) of the first operational amplifier OP1 is connected to the non-inverting input (IN+) of the second operational amplifier OP2. The inverting input (IN-) and output (OUT) of the second operational amplifier OP2 are connected to the operational amplifier output port VPVB, which is connected to the control signal generation circuit.

[0059] 3. Working principle

[0060] The specific structure of the operational amplifier circuit can be selected according to the accuracy requirements of VCP, and the voltage at the reference source port VREF is generated by a low-temperature drift reference source. This circuit can generate a high-precision, high-voltage source whose absolute value is independent of power supply and process technology.

[0061] The basic principles of the above technical solution are as follows:

[0062] (1) The overall circuit is divided into three modules. The first module is the main circuit of the charge pump, which is to charge the charge storage capacitor CC alternately under the control of the control signal and output VCP, and at the same time detect the output voltage of the circuit to generate VPVB. The second module is the control signal generation circuit, which is to adjust the amplitude of the charge pump control signal under the control of VPVB and the two-phase non-overlapping clock, and output it to the main circuit of the charge pump. The third module is the two-phase non-overlapping clock generation module, which generates the two-phase non-overlapping clock and outputs it to the charge pump control signal generation module.

[0063] (2) The overall circuit is a closed-loop structure. The output voltage of the cross-coupled circuit is output through the output port VCP, and the voltage at the output port VCP is determined by the feedback coefficient formed by the first adjustable resistor R1 and the second adjustable resistor R2. Among them, V CP V is the voltage value at the output port VCP. REF R1 is the voltage value at the reference source port VREF, R2 is the resistance value of the first adjustable resistor R1, and R2 is the resistance value of the second adjustable resistor R2. The voltage value at the output port VCP can be adjusted by changing the resistance values ​​of the first adjustable resistor R1 and the second adjustable resistor R2.

[0064] (3) Adjust the first adjustable resistor R1 and the second adjustable resistor R2, as well as the first operational amplifier OP1 and the second operational amplifier OP2 according to the magnitude of the output port VCP voltage, to realize the dynamic adjustment of the voltage at the operational amplifier output port VPVB, and at the same time adjust the magnitude of the charge stored on CC in each clock cycle.

[0065] (4) The main circuit of the charge pump adopts a cross-coupled circuit, which can effectively reduce the ripple size and improve efficiency. It should be noted that in order to eliminate the body effect and reduce the leakage current, the substrates of the NMOS and PMOS transistors need to be connected to the source end. Therefore, the BCD process is more efficient.

[0066] (5) The operational amplifier structure, clock frequency and CC capacitor size in this patent can be designed according to the requirements of voltage accuracy of output port VCP, load current and other requirements.

[0067] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A charge pump circuit based on closed loop feedback control, characterized by, The application relates to a two-phase non-overlapping clock generation circuit, a control signal generation circuit and a charge pump main circuit. The charge pump main circuit comprises a cross-coupled circuit, a feedback circuit and an operational amplifier circuit. The cross-coupled circuit comprises an A1 module, an A2 module and an A3 module; the input end of the A1 module is connected with a power supply VDD; the output end of the A1 module is connected with the input end of the A2 module; the output end of the A2 module is connected with the input end of the A3 module; the output end of the A3 module is connected with an output port VCP; the input end of the cross-coupled circuit is connected with the power supply VDD; the output end of the cross-coupled circuit is connected with the output port VCP and the input end of the feedback circuit; the output end of the feedback circuit is connected with the operational amplifier circuit. The feedback circuit comprises a first adjustable resistor R1 and a second adjustable resistor R2; one end of the first adjustable resistor R1 is connected with the output end of the cross-coupled circuit; the other end of the first adjustable resistor R1 is connected with one end of the second adjustable resistor R2 and the operational amplifier circuit; the other end of the second adjustable resistor R2 is grounded. The operational amplifier circuit comprises a first operational amplifier OP1 and a second operational amplifier OP2; the non-inverting input end IN+ of the first operational amplifier OP1 is connected with the feedback circuit; the inverting input end IN- of the first operational amplifier OP1 is connected with a reference source port VREF; the output end OUT of the first operational amplifier OP1 is connected with the non-inverting input end IN+ of the second operational amplifier OP2; the inverting input end IN- and the output end OUT of the second operational amplifier OP2 are connected with an operational amplifier output port VPVB; the operational amplifier output port VPVB is connected with the control signal generation circuit. The output voltage of the cross-coupled circuit is output through the output port VCP; the voltage at the output port VCP is processed through the feedback circuit and the operational amplifier circuit in sequence and then fed back to the control signal generation circuit through the operational amplifier output port VPVB, so that the feedback control of the charge pump main circuit is realized and a high-voltage power supply is obtained. The input end of the two-phase non-overlapping clock generation circuit is connected with an input port CLKIN; the two-phase non-overlapping clock generation circuit is connected with the input end of the control signal generation circuit through a first output port CLK1, a first inverting output port CLK1N, a second output port CLK2 and a second inverting output port CLK2N; 2. A charge pump circuit based on closed loop feedback control as defined in claim 1, characterized in that, The control signal generation circuit is connected with the input end of the charge pump main circuit through a first output port CKOUT1, a first inverting output port CKNOUT1, a second output port CKOUT2 and a second inverting output port CKNOUT2; The two-phase non-overlapping clock generation circuit, the control signal generation circuit and the charge pump main circuit are connected with the power supply VDD and the ground. ​ 3. A charge pump circuit based on closed loop feedback control as defined in claim 1, wherein, The A1 module specifically includes: a first capacitor C C1 , a second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3, and a fourth P-type MOS transistor PM4. The first capacitor C C1 One end of the first capacitor C C1 The other end of the first capacitor C C2 The other end of the second capacitor C C2 The second inverting output port CKNOUT2 of the control signal generation circuit, and the D end of the third P-type MOS tube PM3 and the D end of the fourth P-type MOS tube PM4 as the output end of the A1 module.

4. A charge pump circuit based on closed loop feedback control as defined in claim 1, wherein, The A2 module specifically includes: a first capacitor C C1 , a second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3, and a fourth P-type MOS transistor PM4. One end of the first capacitor C C1 connects a first output port CKOUT1 of the control signal generation circuit, and the other end of the first capacitor C C1 is connected with an S terminal of the second N-type MOS transistor NM2, an S terminal of the third P-type MOS transistor PM3, a G terminal of the third N-type MOS transistor NM3, and a G terminal of the fourth P-type MOS transistor PM4; a D terminal of the second N-type MOS transistor NM2 and a D terminal of the third N-type MOS transistor NM3 are connected with an output terminal of the A1 module, and a G terminal of the second N-type MOS transistor NM2, an S terminal of the third N-type MOS transistor NM3, an S terminal of the fourth P-type MOS transistor PM4, and a G terminal of the third P-type MOS transistor PM3 are connected with one end of the second capacitor C C2 ; the other end of the second capacitor C C2 connects a first inverting output port CKNOUT1 of the control signal generation circuit, and a D terminal of the third P-type MOS transistor PM3 and a D terminal of the fourth P-type MOS transistor PM4 serve as an output terminal of the A2 module.

5. A charge pump circuit based on closed loop feedback control as defined in claim 1, wherein, The A3 module specifically includes: a first capacitor C C1 , a second capacitor C C2 , a second N-type MOS transistor NM2, a third N-type MOS transistor NM3, a third P-type MOS transistor PM3, and a fourth P-type MOS transistor PM4. One end of the first capacitor C C1 is connected to a second output port CKOUT2 of the control signal generation circuit, and the other end of the first capacitor C C1 is connected to the S terminal of the second N-type MOS transistor NM2, the S terminal of the third P-type MOS transistor PM3, the G terminal of the second N-type MOS transistor NM2, and the G terminal of the fourth P-type MOS transistor PM4; the D terminal of the second N-type MOS transistor NM2 and the D terminal of the third N-type MOS transistor NM3 are connected to the output terminal of the A2 module, and the G terminal of the second N-type MOS transistor NM2, the S terminal of the third N-type MOS transistor NM3, the S terminal of the fourth P-type MOS transistor PM4, and the G terminal of the third P-type MOS transistor PM3 are connected to one end of the second capacitor C C2 ; the other end of the second capacitor C C2 is connected to a second inverting output port CKNOUT2 of the control signal generation circuit, and the D terminal of the third P-type MOS transistor PM3 and the D terminal of the fourth P-type MOS transistor PM4 are connected to the output terminal VCP as the output terminal of the A3 module.

6. A charge pump circuit based on closed loop feedback control as defined in claim 1, wherein, The control signal generation circuit comprises a seventh P-type MOS PM7, an eighth P-type MOS PM8, a ninth P-type MOS PM9, a fifth N-type MOS NM5, a sixth N-type MOS NM6, a tenth P-type MOS PM10, an eleventh P-type MOS PM11, a twelfth P-type MOS PM12, a seventh N-type MOS NM7 and an eighth N-type MOS NM8; The S end of the seventh P-type MOS PM7 is connected with a power supply VDD, the G end of the seventh P-type MOS PM7 is connected with an operational amplifier output port VPVB, the D end of the seventh P-type MOS PM7 is connected with the S end of the eighth P-type MOS PM8 and the S end of the ninth P-type MOS PM9; the G end of the eighth P-type MOS PM8 is connected with a first inverting output port CLK1N of the two-phase non-overlapping clock generation circuit, the D end of the eighth P-type MOS PM8 and the D end of the fifth N-type MOS NM5 are connected with a second output port CKOUT2 of the control signal generation circuit, the G end of the fifth N-type MOS NM5 is connected with a second output port CLK2 of the two-phase non-overlapping clock generation circuit, and the S end of the fifth N-type MOS NM5 is grounded; the G end of the ninth P-type MOS PM9 is connected with a second inverting output port CLK2N of the two-phase non-overlapping clock generation circuit, the D end of the ninth P-type MOS PM9 and the D end of the sixth N-type MOS NM6 are connected with a second inverting output port CKNOUT2 of the control signal generation circuit; the G end of the sixth N-type MOS NM6 is connected with a first output port CLK1 of the two-phase non-overlapping clock generation circuit, and the S end of the sixth N-type MOS NM6 is grounded; The S end of the tenth P type MOS transistor PM10 is connected with VDD, the G end of the tenth P type MOS transistor PM10 is connected with the operational amplifier output port VPVB, the D end of the tenth P type MOS transistor PM10 is connected with the S end of the eleventh P type MOS transistor PM11 and the S end of the twelfth P type MOS transistor PM12; the G end of the eleventh P type MOS transistor PM11 is connected with the first inverting output port CLK1N of the two-phase non-overlapping clock generating circuit, the D end of the eleventh P type MOS transistor PM11 and the D end of the seventh N type MOS transistor NM7 are connected with the first output port CKOUT1 of the control signal generating circuit; the G end of the seventh N type MOS transistor NM7 is connected with the second output port CLK2 of the two-phase non-overlapping clock generating circuit, the S end of the seventh N type MOS transistor NM7 is grounded, the G end of the twelfth P type MOS transistor PM12 is connected with the second inverting output port CLK2N of the two-phase non-overlapping clock generating circuit; the D end of the twelfth P type MOS transistor PM12 and the D end of the eighth N type MOS transistor NM8 are connected with the first output port CKNOUT1 of the control signal generating circuit, the G end of the eighth N type MOS transistor NM8 is connected with the first output port CLK1 of the two-phase non-overlapping clock generating circuit, and the S end of the eighth N type MOS transistor NM8 is grounded.

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