Reconfigurable double-frequency variable gain amplifier and transmitter thereof

Abstract

The invention discloses a reconfigurable double-frequency variable gain amplifier and a transmitter thereof. The reconfigurable double-frequency variable gain amplifier comprises an input stage matching circuit, an input common-source amplification circuit, a first phase compensation circuit, a common-gate cross interconnection transistor array, a frequency band reconstruction circuit, an output common-source amplification circuit, a second phase compensation circuit and an output stage matching circuit which are connected in sequence, the input-stage matching circuit is connected with a signal input end, the output-stage matching circuit is connected with a signal output end, the common-gate cross-connected transistor array realizes the change of a gain state through a gain control signal, the number of turned-on and turned-off transistors is the same through a cross-connected structure, and the constant impedance is realized; the first phase compensation circuit and the second phase compensation circuit change the phases of the circuits through a phase control signal, the required millimeter wave frequency band can be covered in a frequency band switching mode, and wide gain change range, high linearity and low phase change are realized in the frequency band.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency integrated circuits, and in particular to a reconfigurable dual-frequency variable gain amplifier and a transmitter thereof. Background Art

[0002] With the development of mobile communication technology, the industry is demanding higher data rates and higher quality. Reconfigurable dual-band transceivers will play an increasingly important role in future wireless communication transceivers. The variable gain amplifier (VGA) is a critical module in phased array transceivers. As the precursor to the power amplifier, its primary function is to adjust the transmitter's gain and drive the amplifier's operation.

[0003] The millimeter wave frequency band is currently attracting considerable attention in communications. Compared to the traditional sub-6 GHz band, it offers advantages such as abundant bandwidth resources and fast transmission speeds. In millimeter wave phased array systems, antenna signal beamforming relies on adjusting the signal's amplitude and phase. Therefore, a variable gain amplifier (VGA) is required in the RF transmitter to adjust the signal's amplitude. In millimeter wave communications and radar applications, the VGA's performance directly impacts beamforming quality, placing high demands on the VGA's gain control range and low phase variation. Furthermore, in transmitter systems, the VGA drives the power amplifier, placing high demands on linearity. To cover the wide millimeter wave frequency band, millimeter wave integrated circuits (ICs) typically utilize an ultra-wideband (UWB) architecture, which incurs significant power consumption. Compared to UWB technology, band-reconfigurable technology covers only a portion of the bandwidth required for communications, switching bandwidth based on different operating scenarios. This achieves the same functionality as UWB systems while reducing cost and power consumption.

[0004] Therefore, in summary, the research work on reconfigurable dual-band variable gain amplifier in the millimeter wave frequency band has important practical significance. Summary of the Invention

[0005] In order to overcome the defects and shortcomings of the existing technology, the present invention provides a reconfigurable dual-band variable gain amplifier and its transmitter. The present invention can cover the required millimeter wave frequency band by switching the frequency band, and achieve a wide gain variation range, high linearity and low phase variation within the frequency band.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] The present invention provides a reconfigurable dual-band variable gain amplifier, comprising: an input stage matching circuit, an input common-source amplifier circuit, a first phase compensation circuit, a common-gate cross-connected transistor array, a frequency band reconstruction circuit, an output common-source amplifier circuit, a second phase compensation circuit, and an output stage matching circuit, which are connected in sequence;

[0008] The input stage matching circuit is connected to the signal input terminal, and the output stage matching circuit is connected to the signal output terminal;

[0009] The common-gate cross-connected transistor array changes the gain state through a gain control signal, and the cross-connected structure makes the number of on and off transistors equal, thereby achieving constant impedance;

[0010] The first phase compensation circuit and the second phase compensation circuit change the phase of the circuit through a phase control signal.

[0011] As a preferred technical solution, the input stage matching circuit includes a first inductor L1, a first capacitor C1 and a gate bias circuit, and the gate bias circuit includes a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5 and a second capacitor C2;

[0012] One end of the first inductor L1 and the first capacitor C1 is connected to the signal input terminal, and the other end of the first inductor L1 and the first capacitor C1 is grounded;

[0013] One end of the second inductor L2 is connected to the first bias power supply, the other end of the second inductor L2 is connected to one end of the fourth inductor L4 and one end of the second capacitor C2, and the other end of the fourth inductor L4 is connected to the input common-source amplifier circuit;

[0014] One end of the third inductor L3 is connected to the first bias power supply, and the other end is connected to one end of the fifth inductor L5 and the other end of the second capacitor C2. The other end of the fifth inductor L5 is connected to the input common-source amplifier circuit.

[0015] The first inductor L1 is coupled to the second inductor L2 and the third inductor L3 respectively.

[0016] As a preferred technical solution, the input common-source amplifier circuit includes a first transistor M1, a second transistor M2, a sixth inductor L6, a seventh inductor L7, a third capacitor C3 and a fourth capacitor C4;

[0017] The gate of the first transistor M1 is connected to the other end of the fourth inductor L4, and the gate of the second transistor M2 is connected to the other end of the fifth inductor L5;

[0018] One end of the sixth inductor L6 is connected to the source of the first transistor M1, and the other end of the sixth inductor L6 is grounded;

[0019] One end of the seventh inductor L7 is connected to the source of the second transistor M2, and the other end of the seventh inductor L7 is grounded;

[0020] One end of the third capacitor C3 is connected to the gate of the first transistor M1, and the other end of the third capacitor C3 is connected to the drain of the second transistor M2;

[0021] One end of the fourth capacitor C4 is connected to the gate of the second transistor M2 , and the other end of the fourth capacitor C4 is connected to the drain of the first transistor M1 .

[0022] As a preferred technical solution, the first phase compensation circuit includes a third transistor M3, a fourth transistor M4, a fifth capacitor C5 and a sixth capacitor C6;

[0023] One end of the fifth capacitor C5 is connected to the drain of the first transistor M1, and the other end is connected to the drain of the third transistor M3. The source of the third transistor M3 is grounded, and the gate is connected to the first phase control signal.

[0024] One end of the sixth capacitor C6 is connected to the drain of the second transistor M2 , and the other end is connected to the drain of the fourth transistor M4 . The source of the fourth transistor M4 is grounded, and the gate is connected to the first phase control signal.

[0025] As a preferred technical solution, the common-gate cross-connected transistor array includes a five-bit inverter group, four six-bit transistor groups, an eighth inductor L8 and a ninth inductor L9;

[0026] The four six-bit transistor groups are a first six-bit transistor group M5, a second six-bit transistor group M6, a third six-bit transistor group M7 and a fourth six-bit transistor group M8, each six-bit transistor group including six transistors of successively increasing sizes;

[0027] The gate of the largest transistor of the first six-bit transistor group M5 is connected to the second bias power supply, and the gates of the remaining five transistors receive a five-bit gain control signal;

[0028] The gate of the largest transistor of the fourth six-bit transistor group M8 is connected to the second bias power supply, and the gates of the remaining five transistors receive a five-bit gain control signal;

[0029] The gate of the largest transistor of the second six-bit transistor group M6 is grounded, and the gates of the remaining five-bit transistors receive a five-bit gain control signal processed by a five-bit inverter group;

[0030] The gate of the largest transistor of the third six-bit transistor group M7 is grounded, and the gates of the remaining five-bit transistors receive a five-bit gain control signal processed by the five-bit inverter group;

[0031] The sources of the first six-bit transistor group M5 and the second six-bit transistor group M6 are connected, and the sources of the third six-bit transistor group M7 and the fourth six-bit transistor group M8 are connected;

[0032] The drains of the first six-bit transistor group M5 and the third six-bit transistor group M7 are connected, and the drains of the second six-bit transistor group M6 and the fourth six-bit transistor group M8 are connected;

[0033] One end of the eighth inductor L8 is connected to the source of the first six-bit transistor group M5, and the other end is connected to the first phase compensation circuit;

[0034] One end of the ninth inductor L9 is connected to the source of the fourth six-bit transistor group M8 , and the other end is connected to the first phase compensation circuit.

[0035] As a preferred technical solution, the frequency band reconstruction circuit includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a seventh capacitor C7, an eighth capacitor C8, a tenth inductor L10, an eleventh inductor L11, a twelfth inductor L12, a thirteenth inductor L13, a fourteenth inductor L14, a fifteenth inductor L15, a sixteenth inductor L16 and a seventeenth inductor L17;

[0036] One end of the tenth inductor L10 is connected to the drain of the first six-bit transistor group M5 and the source of the ninth transistor M9, and the other end is connected to one end of the eleventh inductor L11 and the drain of the ninth transistor M9. The other end of the eleventh inductor L11 is connected to the first drain power source, and the gate of the ninth transistor M9 is connected to the first frequency band switching control signal.

[0037] One end of the twelfth inductor L12 is connected to the drain of the fourth six-bit transistor group M8 and the source of the tenth transistor M10, and the other end is connected to one end of the thirteenth inductor L13 and the drain of the tenth transistor M10. The other end of the thirteenth inductor L13 is connected to the first drain power source, and the gate of the tenth transistor M10 is connected to the first frequency band switching control signal.

[0038] One end of the seventh capacitor C7 is connected to the drain of the first six-bit transistor group M5, and the other end is connected to one end of the fourteenth inductor L14 and the source of the eleventh transistor M11. The other end of the fourteenth inductor L14 is connected to one end of the fifteenth inductor L15 and the drain of the eleventh transistor M11. The other end of the fifteenth inductor L15 is connected to the third bias power supply. The gate of the eleventh transistor M11 is connected to the second frequency band switching control signal.

[0039] One end of the eighth capacitor C8 is connected to the drain of the fourth six-bit transistor group M8, and the other end is connected to one end of the sixteenth inductor L16 and the source of the twelfth transistor M12. The other end of the sixteenth inductor L16 is connected to one end of the seventeenth inductor L17 and the drain of the twelfth transistor M12. The other end of the seventeenth inductor L17 is connected to the third bias power supply. The gate of the twelfth transistor M12 is connected to the second frequency band switching control signal.

[0040] As a preferred technical solution, the output common-source amplifier circuit includes a thirteenth transistor M13, a fourteenth transistor M14, a ninth capacitor C9 and a tenth capacitor C10;

[0041] A gate of the thirteenth transistor M13 is connected to the source of the eleventh transistor M11 , a source of the thirteenth transistor M13 is grounded, and a drain of the thirteenth transistor M13 is connected to the second phase compensation circuit;

[0042] A gate of the fourteenth transistor M14 is connected to the source of the twelfth transistor M12 , a source of the fourteenth transistor M14 is grounded, and a drain of the fourteenth transistor M14 is connected to the second phase compensation circuit;

[0043] One end of the ninth capacitor C9 is connected to the drain of the thirteenth transistor M13, and the other end is connected to the gate of the fourteenth transistor M14;

[0044] One end of the tenth capacitor C10 is connected to the drain of the fourteenth transistor M14 , and the other end is connected to the gate of the thirteenth transistor M13 .

[0045] As a preferred technical solution, the second phase compensation circuit includes an eleventh capacitor C11, a twelfth capacitor C12, a fifteenth transistor M15 and a sixteenth transistor M16;

[0046] One end of the eleventh capacitor C11 is connected to the drain of the thirteenth transistor M13 , and the other end is connected to the drain of the fifteenth transistor M15 . The source of the fifteenth transistor M15 is grounded, and the gate is connected to the second phase control signal.

[0047] One end of the twelfth capacitor C12 is connected to the drain of the fourteenth transistor M14 , and the other end is connected to the drain of the sixteenth transistor M16 . The source of the sixteenth transistor M16 is grounded, and the gate is connected to the second phase control signal.

[0048] As a preferred technical solution, the output stage matching circuit includes a thirteenth capacitor C13, a fourteenth capacitor C14, an eighteenth inductor L18, a nineteenth inductor L19 and a twentieth inductor L20;

[0049] One end of the thirteenth capacitor C13 is connected to the drain of the thirteenth transistor M13 and one end of the eighteenth inductor L18, and the other end is connected to the drain of the fourteenth transistor M14 and one end of the nineteenth inductor L19. The other end of the eighteenth inductor L18 is connected to the second drain power supply, and the other end of the nineteenth inductor L19 is connected to the second drain power supply.

[0050] One end of the twentieth inductor L20 and one end of the fourteenth capacitor C14 are connected to the signal output terminal, and one end of the twentieth inductor L20 and the other end of the fourteenth capacitor C14 are grounded;

[0051] The twentieth inductor L20 is coupled to the eighteenth inductor L18 and the nineteenth inductor L19 respectively.

[0052] The present invention also provides a transmitter provided with the above-mentioned reconfigurable dual-frequency variable gain amplifier.

[0053] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0054] The present invention switches frequency bands by means of transistor switches, can cover the required millimeter-wave frequency bands through frequency band switching, and achieve a wide gain variation range, high linearity, and low phase variation within the frequency band. Specifically, in a common-gate cross-connected transistor array, the transistors that are turned on are the same in different gain states, so that the input and output impedances of the circuit during the gain variation process can be kept constant, thereby reducing the phase variation during the gain variation process. The first phase compensation circuit and the second phase compensation circuit further reduce the phase variation generated by the circuit during the gain variation through the phase control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 Schematic diagram of the overall architecture of the reconfigurable dual-frequency variable gain amplifier of the present invention;

[0056] Figure 2 Schematic diagram of the circuit structure of the reconfigurable dual-frequency variable gain amplifier of the present invention;

[0057] Figure 3 This is a diagram showing the simulation results of gain and return loss of the reconfigurable dual-band variable gain amplifier of the present invention when switching to a low-frequency state.

[0058] Figure 4 This is a diagram showing the simulation results of gain and return loss of the reconfigurable dual-band variable gain amplifier of the present invention when switching to a high-frequency state.

[0059] Figure 5 This is a diagram showing the simulation results of the output 1dB compression point of the reconfigurable dual-band variable gain amplifier of the present invention when switching to a low-frequency state.

[0060] Figure 6 This is a diagram showing the simulation results of the output 1dB compression point of the reconfigurable dual-band variable gain amplifier of the present invention when switching in the high-frequency state.

[0061] Figure 7 This is a diagram showing the simulation results of gain switching when the reconfigurable dual-frequency variable gain amplifier of the present invention switches to a low-frequency state.

[0062] Figure 8 This is a diagram showing the simulation results of gain switching of the reconfigurable dual-frequency variable gain amplifier of the present invention when switching in a high-frequency state.

[0063] Figure 9This is a simulation result diagram of the maximum phase change when the reconfigurable dual-frequency variable gain amplifier of the present invention switches to a low-frequency state.

[0064] Figure 10 This is a simulation result diagram of the maximum phase change of the reconfigurable dual-frequency variable gain amplifier of the present invention when switching in the high-frequency state. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0066] Example 1

[0067] like Figure 1 As shown, this embodiment provides a reconfigurable dual-band variable gain amplifier, comprising: an input stage matching circuit, an input common-source amplifier circuit, a first phase compensation circuit, a common-gate cross-connected transistor array, a frequency band reconstruction circuit, an output common-source amplifier circuit, a second phase compensation circuit, and an output stage matching circuit connected in sequence;

[0068] In this embodiment, the input-stage matching circuit and the output-stage matching circuit adopt a single-ended to double-ended magnetic coupling resonant circuit structure to achieve the conversion of single-ended signals to differential signals. The coupling between the inductors can generate two poles in the input matching, thereby achieving broadband input matching and widening the matching bandwidth of the circuit.

[0069] like Figure 2 As shown, the signal input terminal is Vin, the input stage matching circuit includes a first inductor L1, a first capacitor C1 and a gate bias circuit, and the gate bias circuit includes a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5 and a second capacitor C2;

[0070] One end of the first inductor L1 and the first capacitor C1 is connected to the signal input terminal Vin, and the other end is grounded; one end of the second inductor L2 is connected to the first bias power supply Vg1, and the other end is connected to one end of the fourth inductor L4 and one end of the second capacitor C2; the other end of the fourth inductor L4 is connected to the gate of the first transistor M1; one end of the third inductor L3 is connected to the first bias power supply Vg1, and the other end is connected to one end of the fifth inductor L5 and the other end of the second capacitor C2; the other end of the fifth inductor L5 is connected to the gate of the second transistor M2;

[0071] Furthermore, the first inductor L1 and the second inductor L2 are coupled, and the first inductor L1 and the third inductor L3 are coupled; the same-name end of the first inductor L1 is connected to the signal input terminal Vin, the same-name end of the second inductor L2 is connected to the first bias power supply Vg1, and the same-name end of the third inductor L3 is connected to the first bias power supply Vg1.

[0072] In this embodiment, the input stage matching circuit adopts the form of inductive coupling to complete impedance matching, achieves a wide bandwidth matching bandwidth, and also has the function of providing bias power supply.

[0073] In this embodiment, the input common-source amplifier circuit and the common-gate cross-connected transistor array constitute a common-source-common-gate amplifier circuit, the input-stage matching circuit is connected to the signal input terminal, and the output-stage matching circuit is connected to the signal output terminal;

[0074] like Figure 2 As shown, the input common-source amplifier circuit includes a first transistor M1, a second transistor M2, a sixth inductor L6, a seventh inductor L7, a third capacitor C3, and a fourth capacitor C4, wherein: the gate of the first transistor M1 is connected to the first bias power supply Vg1 through a gate bias circuit; the gate of the second transistor M2 is connected to the first bias power supply Vg1 through a gate bias circuit; one end of the sixth inductor L6 is connected to the source of the first transistor M1, and the other end of the sixth inductor L6 is grounded; one end of the seventh inductor L7 is connected to the source of the second transistor M2, and the other end of the seventh inductor L7 is grounded; one end of the third capacitor C3 is connected to the gate of the first transistor M1, and the other end is connected to the drain of the second transistor M2; one end of the fourth capacitor C4 is connected to the gate of the second transistor M2, and the other end is connected to the drain of the first transistor M1.

[0075] In this embodiment, a common-gate cross-connected transistor array can maintain constant circuit input and output impedance during gain variation, thereby reducing phase variation during gain variation. The common-gate cross-connected transistor array includes a five-bit inverter group and four six-bit transistor groups, wherein the six-bit transistor group Mx<1:6> includes six transistors of successively increasing sizes. The four six-bit transistor groups are identical and are divided into a first six-bit transistor group M5<1:6>, a second six-bit transistor group M6<1:6>, a third six-bit transistor group M7<1:6>, and a fourth six-bit transistor group M8<1:6>.

[0076] In this embodiment, the common-gate cross-connected transistor array has a complementary structure. Specifically, the switching states of the first six-bit transistor group M5<1:6>, the third six-bit transistor group M7<1:6>, the second six-bit transistor group M6<1:6>, and the fourth six-bit transistor group M8<1:6> are complementary.

[0077] like Figure 2 As shown, the common-gate cross-connected transistor array includes a five-bit inverter group, four six-bit transistor groups, an eighth inductor L8, and a ninth inductor L9, wherein the four six-bit transistor groups are respectively a first six-bit transistor group M5, a second six-bit transistor group M6, a third six-bit transistor group M7, and a fourth six-bit transistor group M8. The gate of the largest transistor of the first six-bit transistor group M5 is connected to the second bias power supply Vg2, and the gates of the remaining five transistors receive a five-bit gain control signal; the gate of the largest transistor of the fourth six-bit transistor group M8 is connected to the second bias power supply Vg2, and the gates of the remaining five transistors receive a five-bit gain control signal; the gate of the largest transistor of the second six-bit transistor group M6 is grounded, and the gates of the remaining five transistors receive a signal processed by the five-bit inverter group. The gate of the largest transistor of the third six-bit transistor group M7 is grounded, and the gates of the remaining five transistors receive the five-bit gain control signal processed by the five-bit inverter group; the source of the first six-bit transistor group M5 is connected to the source of the second six-bit transistor group M6, and the source of the third six-bit transistor group M7 is connected to the source of the fourth six-bit transistor group M8; the drain of the first six-bit transistor group M5 is connected to the drain of the third six-bit transistor group M7, and the drain of the second six-bit transistor group M6 is connected to the drain of the fourth six-bit transistor group M8; one end of the eighth inductor L8 is connected to the source of the first six-bit transistor group M5, and the other end is connected to the drain of the first transistor M1; one end of the ninth inductor L9 is connected to the source of the fourth six-bit transistor group M8, and the other end is connected to the drain of the second transistor M2.

[0078] The common-gate cross-connected transistor array in this embodiment can achieve a change in gain state through the control of a gain control signal. Moreover, due to the cross-connected structure, the number of on and off transistors can be made the same, thereby achieving constant impedance and reducing phase variation when the gain state changes.

[0079] In this embodiment, by adjusting the equivalent inductance values of the fourth inductor L4 , the fifth inductor L5 , the eighth inductor L8 , and the ninth inductor L9 , the high-frequency gain of the amplifier can be improved to a certain extent.

[0080] In this embodiment, the frequency band reconstruction circuit includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a seventh capacitor C7, an eighth capacitor C8, a tenth inductor L10, an eleventh inductor L11, a twelfth inductor L12, a thirteenth inductor L13, a fourteenth inductor L14, a fifteenth inductor L15, a sixteenth inductor L16, and a seventeenth inductor L17, wherein one end of the tenth inductor L10 is connected to the drain of the first six-bit transistor group M5, the drain of the ninth transistor M5, the drain of the ninth transistor M5, the drain of the ninth transistor M5, the drain of the ninth transistor M5, the drain of the ninth transistor M5, the drain of the ninth transistor M5, the drain of the ninth transistor M5, the drain of the ninth transistor M5, the drain of the ninth transistor M5, the drain of the ninth transistor M5, the drain of the ninth transistor M5, the drain of the tenth inductor L10, the drain of the first six-bit transistor group ... tenth inductor L10, the drain of the first six-bit transistor group M5, the drain of the ninth transistor M5, the drain of the tenth inductor L10, the drain of the first six-bit transistor group M5, the drain of the ninth transistor M5, the drain of the tenth inductor L10, the drain of the first six-bit transistor group M5, the drain of the first six-bit transistor group M5, the drain of the first six-bit transistor group M5, the drain of the first six-bit transistor group M5, the drain The source of the 12th inductor L12 is connected to the source of the 13th inductor L13 and the drain of the 10th transistor M10, and the other end is connected to one end of the 11th inductor L11 and the drain of the 10th transistor M10. The other end of the 13th inductor L13 is connected to the drain of the 10th transistor M10. The other end of the 13th inductor L13 is connected to the drain of the 10th transistor M10. The first drain power supply Vdd1 is connected to the gate of the tenth transistor M10, and the first frequency band switching control signal Vc1 is connected to the gate of the tenth transistor M10; one end of the seventh capacitor C7 is connected to the drain of the first six-bit transistor group M5, and the other end is connected to one end of the fourteenth inductor L14 and the source of the eleventh transistor M11, the other end of the fourteenth inductor L14 is connected to one end of the fifteenth inductor L15 and the drain of the eleventh transistor M11, the other end of the fifteenth inductor L15 is connected to the third bias power supply Vg3, and the eleventh transistor M The gate of the eighth capacitor C8 is connected to the drain of the fourth six-bit transistor group M8, and the other end is connected to one end of the sixteenth inductor L16 and the source of the twelfth transistor M12. The other end of the sixteenth inductor L16 is connected to one end of the seventeenth inductor L17 and the drain of the twelfth transistor M12. The other end of the seventeenth inductor L17 is connected to the third bias power supply Vg3. The gate of the twelfth transistor M12 is connected to the second frequency band switching control signal Vc2.

[0081] In this embodiment, the first frequency band switching control signal Vc1 and the second frequency band switching control signal Vc2 are adjusted to change the equivalent inductance values of the tenth inductor L10, the twelfth inductor L12, the fourteenth inductor L14, and the sixteenth inductor L16, thereby changing the inter-stage matching structure and achieving frequency band switching.

[0082] In this embodiment, the output common-source amplifier circuit includes a thirteenth transistor M13, a fourteenth transistor M14, a ninth capacitor C9, and a tenth capacitor C10, wherein the gate of the thirteenth transistor M13 is connected to the source of the eleventh transistor M11, and the source of the thirteenth transistor M13 is grounded;

[0083] The gate of the fourteenth transistor M14 is connected to the source of the twelfth transistor M12, and the source of the fourteenth transistor M14 is grounded; one end of the ninth capacitor C9 is connected to the drain of the thirteenth transistor M13, and the other end is connected to the gate of the fourteenth transistor M14; one end of the tenth capacitor C10 is connected to the drain of the fourteenth transistor M14, and the other end is connected to the gate of the thirteenth transistor M13;

[0084] In this embodiment, the first phase compensation circuit and the second phase compensation circuit use transistors as switches to change the equivalent capacitance value, thereby changing the overall phase of the circuit and achieving phase control, thereby further reducing the phase change introduced by the gain change;

[0085] like Figure 2 As shown, the first phase compensation circuit includes a third transistor M3, a fourth transistor M4, a fifth capacitor C5 and a sixth capacitor C6, wherein one end of the fifth capacitor C5 is connected to the drain of the first transistor M1, and the other end is connected to the drain of the third transistor M3, the source of the third transistor M3 is grounded, and the gate is connected to the first phase control signal Vphase1; one end of the sixth capacitor C6 is connected to the drain of the second transistor M2, and the other end is connected to the drain of the fourth transistor M4, the source of the fourth transistor M4 is grounded, and the gate is connected to the first phase control signal Vphase1;

[0086] The second phase compensation circuit includes an eleventh capacitor C11, a twelfth capacitor C12, a fifteenth transistor M15, and a sixteenth transistor M16, wherein one end of the eleventh capacitor C11 is connected to the drain of the thirteenth transistor M13, and the other end is connected to the drain of the fifteenth transistor M15. The source of the fifteenth transistor M15 is grounded, and the gate is connected to the second phase control signal Vphase2. One end of the twelfth capacitor C12 is connected to the drain of the fourteenth transistor M14, and the other end is connected to the drain of the sixteenth transistor M16. The source of the sixteenth transistor M16 is grounded, and the gate is connected to the second phase control signal Vphase2.

[0087] This embodiment adjusts the control signals of the first phase compensation circuit and the second phase compensation circuit to change the equivalent capacitance of the transistor, thereby changing the overall equivalent capacitance of the structure, thereby adjusting the circuit phase and further reducing the phase change of the circuit.

[0088] In this embodiment, the signal output terminal is Vout, and the output stage matching circuit includes a thirteenth capacitor C13, a fourteenth capacitor C14, an eighteenth inductor L18, a nineteenth inductor L19, and a twentieth inductor L20. One end of the thirteenth capacitor C13 is connected to the drain of the thirteenth transistor M13 and one end of the eighteenth inductor L18, and the other end is connected to the drain of the fourteenth transistor M14 and one end of the nineteenth inductor L19. The other end of the eighteenth inductor L18 is connected to the second drain power supply Vdd2, and the other end of the nineteenth inductor L19 is connected to the second drain power supply Vdd2. One end of the twentieth inductor L20 and one end of the fourteenth capacitor C14 are connected to the signal output terminal Vout, and one end of the twentieth inductor L20 and the other end of the fourteenth capacitor C14 are grounded.

[0089] The eighteenth inductor L18 is coupled to the twentieth inductor L20, the nineteenth inductor L19 is coupled to the twentieth inductor L20, the same-name end of the eighteenth inductor L18 is connected to the second drain power supply Vdd2, and the same-name end of the twentieth inductor L20 is connected to the second drain power supply Vdd2;

[0090] In this embodiment, the output stage matching circuit uses a magnetic coupling resonant circuit to achieve power matching, thereby achieving a wider operating bandwidth and improving the linearity of the amplifier.

[0091] Compared with traditional variable gain amplifiers, the reconfigurable dual-band variable gain amplifier of this embodiment introduces two phase compensation structures, which can freely adjust the phase of the amplifier and reduce the phase when the gain state changes; the gain control structure adopts a cross-connected transistor array, which can keep the input and output impedance unchanged when the gain changes, thereby reducing the phase change; the frequency band reconstruction circuit is used between stages, which changes the inter-stage matching by controlling the state of the transistor switch, thereby achieving frequency band switching.

[0092] like Figure 3 As shown in the figure, the gain and return loss simulation results of the reconfigurable dual-band variable gain amplifier in the low-frequency state are obtained. Figure 3 It can be seen that the maximum gain working in the 24~32GHz band is 9.8dB and the S11 parameter is less than -10dB.

[0093] like Figure 4 As shown in the figure, the gain and return loss simulation results of the reconfigurable dual-band variable gain amplifier in the high frequency state are obtained. Figure 4 It can be seen that the maximum gain working in the 32-44 GHz band is 10.2 dB, and the S11 parameter is less than -10 dB.

[0094] like Figure 5 As shown in the figure, the simulation results of the output 1dB compression point of the reconfigurable dual-band variable gain amplifier in the low-frequency state are obtained; Figure 5 It can be seen that the output 1dB compression point working in the 24~32GHz band is 1.8~4.7dBm.

[0095] like Figure 6 As shown in the figure, the simulation results of the output 1dB compression point of the reconfigurable dual-band variable gain amplifier in the high frequency state are obtained; Figure 6 It can be seen that the output 1dB compression point working in the 32~44GHz band is 3.2~5.7dBm.

[0096] like Figure 7 As shown, the gain switching simulation results of the reconfigurable dual-band variable gain amplifier in the low-frequency state are obtained, wherein the average gain variation range is 17dB and the average gain adjustment step is 0.5dB.

[0097] like Figure 8 As shown, the gain switching simulation results of the reconfigurable dual-band variable gain amplifier in the high-frequency state are obtained, wherein the average gain variation range is 15dB and the average gain adjustment step size is 0.5dB.

[0098] like Figure 9 As shown in the figure, the maximum phase change result of the gain switching of the reconfigurable dual-band variable gain amplifier in the low-frequency state is obtained. Figure 9 As can be seen from the figure, the maximum phase change is 4.7°.

[0099] like Figure 10 As shown, the maximum phase change result of the gain switching of the reconfigurable dual-band variable gain amplifier in the high-frequency state is obtained. Figure 10 As can be seen from the figure, the maximum phase change is 1°.

[0100] Example 2

[0101] This embodiment provides a transmitter equipped with the reconfigurable dual-frequency variable gain amplifier of the above-mentioned embodiment 1.

[0102] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be considered as equivalent replacement methods and are included in the scope of protection of the present invention.

Claims

1. A reconfigurable dual-band variable gain amplifier, characterized in that: include: An input stage matching circuit, an input common-source amplifier circuit, a first phase compensation circuit, a common-gate cross-connected transistor array, a frequency band reconstruction circuit, an output common-source amplifier circuit, a second phase compensation circuit, and an output stage matching circuit connected in sequence; The input stage matching circuit is connected to the signal input terminal, and the output stage matching circuit is connected to the signal output terminal; The common-gate cross-connected transistor array changes the gain state through a gain control signal, and the cross-connected structure makes the number of on and off transistors equal, thereby achieving constant impedance; The first phase compensation circuit and the second phase compensation circuit change the phase of the circuit through a phase control signal.

2. The reconfigurable dual-band variable gain amplifier according to claim 1, wherein: The input stage matching circuit includes a first inductor L1, a first capacitor C1 and a gate bias circuit, and the gate bias circuit includes a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5 and a second capacitor C2; One end of the first inductor L1 and the first capacitor C1 is connected to the signal input terminal, and the other end of the first inductor L1 and the first capacitor C1 is grounded; One end of the second inductor L2 is connected to the first bias power supply, the other end of the second inductor L2 is connected to one end of the fourth inductor L4 and one end of the second capacitor C2, and the other end of the fourth inductor L4 is connected to the input common-source amplifier circuit; One end of the third inductor L3 is connected to the first bias power supply, and the other end is connected to one end of the fifth inductor L5 and the other end of the second capacitor C2. The other end of the fifth inductor L5 is connected to the input common-source amplifier circuit. The first inductor L1 is coupled to the second inductor L2 and the third inductor L3 respectively.

3. The reconfigurable dual-band variable gain amplifier according to claim 2, wherein: The input common-source amplifier circuit includes a first transistor M1, a second transistor M2, a sixth inductor L6, a seventh inductor L7, a third capacitor C3 and a fourth capacitor C4; The gate of the first transistor M1 is connected to the other end of the fourth inductor L4, and the gate of the second transistor M2 is connected to the other end of the fifth inductor L5; One end of the sixth inductor L6 is connected to the source of the first transistor M1, and the other end of the sixth inductor L6 is grounded; One end of the seventh inductor L7 is connected to the source of the second transistor M2, and the other end of the seventh inductor L7 is grounded; One end of the third capacitor C3 is connected to the gate of the first transistor M1, and the other end of the third capacitor C3 is connected to the drain of the second transistor M2; One end of the fourth capacitor C4 is connected to the gate of the second transistor M2 , and the other end of the fourth capacitor C4 is connected to the drain of the first transistor M1 .

4. The reconfigurable dual-band variable gain amplifier according to claim 3, wherein: The first phase compensation circuit includes a third transistor M3, a fourth transistor M4, a fifth capacitor C5 and a sixth capacitor C6; One end of the fifth capacitor C5 is connected to the drain of the first transistor M1, and the other end is connected to the drain of the third transistor M3. The source of the third transistor M3 is grounded, and the gate is connected to the first phase control signal. One end of the sixth capacitor C6 is connected to the drain of the second transistor M2 , and the other end is connected to the drain of the fourth transistor M4 . The source of the fourth transistor M4 is grounded, and the gate is connected to the first phase control signal.

5. The reconfigurable dual-band variable gain amplifier according to claim 1, wherein: The common-gate cross-connected transistor array includes a five-bit inverter group, four six-bit transistor groups, an eighth inductor L8 and a ninth inductor L9; The four six-bit transistor groups are a first six-bit transistor group M5, a second six-bit transistor group M6, a third six-bit transistor group M7 and a fourth six-bit transistor group M8, each six-bit transistor group including six transistors of successively increasing sizes; The gate of the largest transistor of the first six-bit transistor group M5 is connected to the second bias power supply, and the gates of the remaining five transistors receive a five-bit gain control signal; The gate of the largest transistor of the fourth six-bit transistor group M8 is connected to the second bias power supply, and the gates of the remaining five transistors receive a five-bit gain control signal; The gate of the largest transistor of the second six-bit transistor group M6 is grounded, and the gates of the remaining five-bit transistors receive a five-bit gain control signal processed by a five-bit inverter group; The gate of the largest transistor of the third six-bit transistor group M7 is grounded, and the gates of the remaining five-bit transistors receive a five-bit gain control signal processed by the five-bit inverter group; The sources of the first six-bit transistor group M5 and the second six-bit transistor group M6 are connected, and the sources of the third six-bit transistor group M7 and the fourth six-bit transistor group M8 are connected; The drains of the first six-bit transistor group M5 and the third six-bit transistor group M7 are connected, and the drains of the second six-bit transistor group M6 and the fourth six-bit transistor group M8 are connected; One end of the eighth inductor L8 is connected to the source of the first six-bit transistor group M5, and the other end is connected to the first phase compensation circuit; One end of the ninth inductor L9 is connected to the source of the fourth six-bit transistor group M8 , and the other end is connected to the first phase compensation circuit.

6. The reconfigurable dual-band variable gain amplifier according to claim 5, characterized in that: The frequency band reconstruction circuit includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a seventh capacitor C7, an eighth capacitor C8, a tenth inductor L10, an eleventh inductor L11, a twelfth inductor L12, a thirteenth inductor L13, a fourteenth inductor L14, a fifteenth inductor L15, a sixteenth inductor L16 and a seventeenth inductor L17; One end of the tenth inductor L10 is connected to the drain of the first six-bit transistor group M5 and the source of the ninth transistor M9, and the other end is connected to one end of the eleventh inductor L11 and the drain of the ninth transistor M9. The other end of the eleventh inductor L11 is connected to the first drain power source, and the gate of the ninth transistor M9 is connected to the first frequency band switching control signal. One end of the twelfth inductor L12 is connected to the drain of the fourth six-bit transistor group M8 and the source of the tenth transistor M10, and the other end is connected to one end of the thirteenth inductor L13 and the drain of the tenth transistor M10. The other end of the thirteenth inductor L13 is connected to the first drain power source, and the gate of the tenth transistor M10 is connected to the first frequency band switching control signal. One end of the seventh capacitor C7 is connected to the drain of the first six-bit transistor group M5, and the other end is connected to one end of the fourteenth inductor L14 and the source of the eleventh transistor M11. The other end of the fourteenth inductor L14 is connected to one end of the fifteenth inductor L15 and the drain of the eleventh transistor M11. The other end of the fifteenth inductor L15 is connected to the third bias power supply. The gate of the eleventh transistor M11 is connected to the second frequency band switching control signal. One end of the eighth capacitor C8 is connected to the drain of the fourth six-bit transistor group M8, and the other end is connected to one end of the sixteenth inductor L16 and the source of the twelfth transistor M12. The other end of the sixteenth inductor L16 is connected to one end of the seventeenth inductor L17 and the drain of the twelfth transistor M12. The other end of the seventeenth inductor L17 is connected to the third bias power supply. The gate of the twelfth transistor M12 is connected to the second frequency band switching control signal.

7. The reconfigurable dual-band variable gain amplifier according to claim 6, wherein: The output common-source amplifier circuit includes a thirteenth transistor M13, a fourteenth transistor M14, a ninth capacitor C9 and a tenth capacitor C10; A gate of the thirteenth transistor M13 is connected to the source of the eleventh transistor M11 , a source of the thirteenth transistor M13 is grounded, and a drain of the thirteenth transistor M13 is connected to the second phase compensation circuit; A gate of the fourteenth transistor M14 is connected to the source of the twelfth transistor M12 , a source of the fourteenth transistor M14 is grounded, and a drain of the fourteenth transistor M14 is connected to the second phase compensation circuit; One end of the ninth capacitor C9 is connected to the drain of the thirteenth transistor M13, and the other end is connected to the gate of the fourteenth transistor M14; One end of the tenth capacitor C10 is connected to the drain of the fourteenth transistor M14 , and the other end is connected to the gate of the thirteenth transistor M13 .

8. The reconfigurable dual-band variable gain amplifier according to claim 7, wherein: The second phase compensation circuit includes an eleventh capacitor C11, a twelfth capacitor C12, a fifteenth transistor M15, and a sixteenth transistor M16; One end of the eleventh capacitor C11 is connected to the drain of the thirteenth transistor M13 , and the other end is connected to the drain of the fifteenth transistor M15 . The source of the fifteenth transistor M15 is grounded, and the gate is connected to the second phase control signal. One end of the twelfth capacitor C12 is connected to the drain of the fourteenth transistor M14 , and the other end is connected to the drain of the sixteenth transistor M16 . The source of the sixteenth transistor M16 is grounded, and the gate is connected to the second phase control signal.

9. The reconfigurable dual-band variable gain amplifier according to claim 7, wherein: The output stage matching circuit includes a thirteenth capacitor C13, a fourteenth capacitor C14, an eighteenth inductor L18, a nineteenth inductor L19 and a twentieth inductor L20; One end of the thirteenth capacitor C13 is connected to the drain of the thirteenth transistor M13 and one end of the eighteenth inductor L18, and the other end is connected to the drain of the fourteenth transistor M14 and one end of the nineteenth inductor L19. The other end of the eighteenth inductor L18 is connected to the second drain power supply, and the other end of the nineteenth inductor L19 is connected to the second drain power supply. One end of the twentieth inductor L20 and one end of the fourteenth capacitor C14 are connected to the signal output terminal, and one end of the twentieth inductor L20 and the other end of the fourteenth capacitor C14 are grounded; The twentieth inductor L20 is coupled to the eighteenth inductor L18 and the nineteenth inductor L19 respectively.

10. A transmitter, characterized in that: A reconfigurable dual-frequency variable gain amplifier according to any one of claims 1 to 9 is provided.

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