Sampling method, motor sampling chip and motor control system
By using at least two low clock frequency sampling in the Sigma-Delta filter instead of one high clock frequency sampling, processing the digital signals output by the modulator, the problem of high frequency pulsation in the Sigma-Delta filter is solved, and signal quality and availability are improved.
Patent Information
- Application Number
- CN202510458630.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-11
- Publication Date
- 2025-08-12
AI Technical Summary
The digital signals obtained by the Sigma-Delta filter have high frequency pulsation, which affects the signal quality and availability, which are mainly caused by the high clock frequency of the Sigma-Delta modulator.
By replacing one high clock frequency sampling, the digital signals output by at least two modulators under the control of low clock frequency are processed, and a digital signal with high clock frequency is generated and sent to a filter for filtering.
Reduces the impact of high-frequency pulsation caused by high-clock frequency sampling, and improves signal quality and availability.
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Figure CN120474555A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of digital signal processing, and in particular to a sampling method, a motor sampling chip, and a motor control system. Background Art
[0002] SDFM (Sigma-Delta Filter Modulator) is a filter that converts analog signals into digital signals through modulation technology, and can include Sigma-Delta filters and Sigma-Delta modulators.
[0003] The digital signal obtained by the Sigma-Delta filter has high-frequency pulsation to a certain extent, which affects the quality and availability of the signal.
[0004] Research has found that high-frequency ripple in digital signals acquired by Sigma-Delta filters is primarily caused by the quantization noise and noise shaping process of the Sigma-Delta modulator. The higher the Sigma-Delta modulator's clock frequency, the less stable the digital conversion, and the more likely it is to cause high-frequency ripple. Summary of the Invention
[0005] The embodiments of the present application provide a sampling method, a motor sampling chip, and a motor control system to reduce the impact of high-frequency pulsation caused by high clock frequency sampling.
[0006] In a first aspect, an embodiment of the present application provides a sampling method, comprising:
[0007] Acquire digital signals of sampling units output by at least two modulators under the control of corresponding first clock signals, where the clock frequency of the first clock signal is lower than a preset frequency;
[0008] Processing the digital signals output by the at least two modulators to obtain a digital signal corresponding to a second clock signal, wherein a clock frequency of the second clock signal is equal to the preset frequency;
[0009] The digital signal corresponding to the second clock signal is sent to a filter, so that the filter performs filtering processing on the received digital signal.
[0010] In a possible implementation, processing the digital signals output by the at least two modulators to obtain a digital signal corresponding to the second clock signal includes:
[0011] generating a preset signal corresponding to each of the modulators according to the second clock signal and the digital signals output by the at least two modulators;
[0012] A logic operation is performed on the second clock signal and the preset signals corresponding to the at least two modulators to obtain a digital signal corresponding to the second clock signal.
[0013] In a possible implementation, there are two modulators, namely a first modulator and a second modulator; the first clock signal corresponding to the second modulator is delayed by a preset period compared to the first clock signal corresponding to the first modulator;
[0014] Performing a logic operation on the second clock signal and the preset signals corresponding to the at least two modulators to obtain a digital signal corresponding to the second clock signal includes:
[0015] Performing an AND operation on the second clock signal and a preset signal corresponding to the first modulator to obtain a first processed signal;
[0016] performing an AND operation on the inverted signal of the second clock signal and the preset signal corresponding to the second modulator to obtain a second processed signal;
[0017] An OR operation is performed on the first processed signal and the second processed signal to obtain a digital signal corresponding to the second clock signal.
[0018] In one possible implementation, the method further includes:
[0019] An exclusive OR operation is performed on the first clock signal corresponding to the first modulator and the first clock signal corresponding to the second modulator to obtain the second clock signal.
[0020] In a second aspect, the present application provides a motor sampling chip, comprising: a processor, and a memory communicatively connected to the processor;
[0021] The memory stores computer-executable instructions;
[0022] The processor executes the computer-executable instructions stored in the memory to implement the sampling method described in the first aspect.
[0023] In a third aspect, the present application provides a motor sampling chip, comprising:
[0024] a motor sampling circuit, wherein the motor sampling circuit is connected to the sampling unit;
[0025] The motor sampling circuit is configured to obtain digital signals of the sampling unit output by at least two modulators under the control of corresponding first clock signals, wherein the clock frequency of the first clock signal is lower than a preset frequency;
[0026] Processing the digital signals of the sampling unit output by the at least two modulators to obtain a digital signal corresponding to a second clock signal, wherein the clock frequency of the second clock signal is equal to the preset frequency;
[0027] The digital signal corresponding to the second clock signal is sent to a filter, so that the filter performs filtering processing on the received digital signal.
[0028] In a possible implementation, the motor sampling circuit includes:
[0029] a digital logic circuit and at least two modulators, each of the modulators being connected to the sampling unit and the digital logic circuit;
[0030] Each of the modulators is configured to collect an analog signal from the sampling unit based on a corresponding first clock signal, convert the analog signal into a digital signal, and output the digital signal to the digital logic circuit;
[0031] The digital logic circuit is used to process the digital signal of the sampling unit output by each modulator to obtain a digital signal corresponding to the second clock signal, where the clock frequency of the second clock signal is equal to the preset frequency; and is also used to send the digital signal corresponding to the second clock signal to the filter so that the filter performs filtering processing on the received digital signal.
[0032] In a possible implementation, the motor sampling chip further includes:
[0033] a filter connected to the motor sampling circuit;
[0034] The filter is used to perform filtering processing on the received digital signal.
[0035] In a possible implementation, the motor sampling chip further includes:
[0036] a crystal oscillator, the crystal oscillator being connected to each of the modulators;
[0037] The crystal oscillator is used to generate at least two first clock signals and send each of the first clock signals to the corresponding modulator.
[0038] In one possible implementation, the digital logic circuit includes:
[0039] a first unit and a second unit, wherein the first unit is connected to the crystal oscillator and the second unit, and the second unit is connected to each of the modulators;
[0040] The crystal oscillator is further used to send each of the first clock signals to the first unit;
[0041] The first unit is configured to perform a logic operation on each of the first clock signals to generate the second clock signal and send the generated second clock signal to the second unit;
[0042] The second unit is used to obtain a digital signal corresponding to the second clock signal based on the second clock signal and the digital signal output by each modulator, and the clock frequency of the second clock signal is equal to the preset frequency; and is also used to send the digital signal corresponding to the second clock signal to the filter so that the filter performs filtering processing on the received digital signal.
[0043] In a fourth aspect, the present application provides a motor control system, comprising the above-mentioned motor sampling chip and a motor, wherein the motor is provided with a corresponding sampling unit;
[0044] The motor sampling chip is connected to the sampling unit;
[0045] The motor sampling chip is used to obtain the analog signal corresponding to the sampling unit, and perform filtering processing after converting the analog signal into a digital signal.
[0046] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the first aspect above and / or various possible implementation methods of the first aspect.
[0047] In a sixth aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the first aspect and / or various possible implementation methods of the first aspect.
[0048] The sampling method, motor sampling chip and motor control system provided in the embodiments of the present application obtain digital signals of the sampling units output by at least two modulators under the control of a clock signal with a low clock frequency, process the digital signals output by at least two modulators under the control of a low clock frequency, and obtain digital signals corresponding to the clock signal with a high clock frequency, thereby providing a high clock frequency digital signal for the filter. In addition, by replacing one high clock frequency sampling with at least two low clock frequency samplings, the high-frequency pulsation effect caused by the high-frequency clock sampling can be reduced, thereby improving the quality and availability of the signal. BRIEF DESCRIPTION OF THE DRAWINGS
[0049] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0050] Figure 1 A sampling diagram provided for this application;
[0051] Figure 2 for Figure 1 A partially enlarged schematic diagram of the sampling schematic diagram shown;
[0052] Figure 3 Another sampling diagram provided for this application;
[0053] Figure 4 for Figure 3 A partially enlarged schematic diagram of the sampling schematic diagram shown;
[0054] Figure 5 A schematic diagram of the sampling method provided for this application;
[0055] Figure 6 A schematic diagram of the structure of the motor sampling chip provided in this application;
[0056] Figure 7 The structure of the motor control system provided in this application is shown as follows: Figure 1 ;
[0057] Figure 8 The structure of the motor control system provided in this application is shown as follows: Figure 2 .
[0058] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION
[0059] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
[0060] A Sigma-Delta Filter Modulator (SDFM) is a filter that converts analog signals into digital signals through modulation techniques. It is often used for high-precision analog-to-digital conversion. For example, it can be used in motor control systems as an advanced digital filter. Advanced digital filtering refers to the use of complex algorithms and techniques in signal processing to achieve efficient and accurate signal filtering.
[0061] The SDFM may include a Sigma-Delta filter and a Sigma-Delta modulator, and the number of the Sigma-Delta filter and the Sigma-Delta modulator may be one or more. The Sigma-Delta filter has four independent input channels, each of which may receive a bit stream from an independent Sigma-Delta modulator, and then transmit the received bit stream to an independent digital decimation filter. The digital decimation filter filters and extracts the bit stream to remove high-frequency noise and reduce the data rate, thereby obtaining a valid digital signal.
[0062] In motor control applications, the input channel of a sigma-delta filter is often used for current measurement. Specifically, a sigma-delta modulator samples the voltage difference across a sampling resistor, converting the current into a voltage signal through the sampling resistor. This voltage signal is then converted into a digital bit stream. Since the voltage is generated by the current, the digital bit stream represents the current. The input channel of the sigma-delta filter receives the digital bit stream from the sigma-delta modulator and transmits it to a digital decimation filter to output a precise digital current value, which can be used to control motor torque and speed.
[0063] The Sigma-Delta filter generally includes three parameters: clock (SD_CLK), over sampling ratio (OSR) and offset address (SH).
[0064] The Sigma-Delta filter clock ensures that the filter receives the bitstream at fixed intervals. A higher clock frequency shortens the intervals between bitstreams received by the filter, allowing the filter to receive and process the bitstream more frequently. A lower clock frequency increases the intervals between bitstreams received by the filter, resulting in slower bitstream reception and processing. Therefore, the Sigma-Delta filter clock determines the filter's computational speed.
[0065] The oversampling rate of a sigma-delta filter refers to the frequency at which the filter samples the bit stream output by the delta-sigma modulator, multiplied by the signal bandwidth. This is typically used to improve signal accuracy and reduce noise. A higher oversampling rate allows for more samples to be taken in the same amount of time. This helps reduce quantization noise and error, improves the signal-to-noise ratio, and enhances the accuracy of the sampling results. Therefore, a higher oversampling rate results in higher data accuracy. For example, at a 20 MHz clock, if the oversampling rate is 250, a complete sigma-delta sampling cycle takes 12.5 μs.
[0066] The offset address of the Sigma-Delta filter is used to locate the position of the bit stream received by the Sigma-Delta filter in the memory. By adjusting the offset address, it can be ensured that the Sigma-Delta filter can correctly locate and receive the required data, so that high-precision filtering and processing can be achieved.
[0067] The applicant has discovered that the digital signal obtained by the Sigma-Delta filter has a certain degree of high-frequency pulsation. High-frequency pulsation refers to the rapid change of signal amplitude, which forms noise or interference, thereby affecting the quality and availability of the signal.
[0068] And through experimental research, the higher the clock frequency of the Sigma-Delta filter, the greater the amplitude of the high-frequency ripple. For example, when the configuration parameters of the Sigma-Delta filter include an oversampling rate of 250, an offset address of 9, and a clock of 18Mhz, if the input signal includes the following conditions: peak voltage (VPP) of 5mV, DC offset (Offset) of 0, no filter capacitor, and the input signal is a sine wave with a frequency of 100Hz, the sampling results obtained are as follows: Figure 1 and Figure 2 As shown, Figure 2 for Figure 1 For example, when the Sigma-Delta filter configuration parameters include an oversampling rate of 250, an offset address of 9, and a clock of 10 MHz, and the input signal has the following conditions: a peak voltage of 5 mV, a DC bias of 0, no filter capacitor, and a sine wave with a frequency of 100 Hz, the sampling results are as follows: Figure 3 and Figure 4 As shown, Figure 4 for Figure 3 Schematic diagram of the enlarged peak in .
[0069] Furthermore, the high-frequency ripple in the digital signal acquired by the Sigma-Delta filter is primarily caused by the quantization noise and noise shaping process of the Sigma-Delta modulator. The higher the Sigma-Delta modulator clock frequency, the less stable the digital conversion, and the more likely it is to cause high-frequency ripple.
[0070] To this end, the present application provides a sampling method that replaces one high clock frequency sampling with at least two low clock frequency samplings to reduce the high frequency pulsation effect caused by high clock frequency sampling.
[0071] The sampling method provided in the present application can be used to sample a motor, and the motor can be controlled by three-phase current, namely phase a, phase b and phase c, with a phase difference of 120 degrees between phase a and phase b, and a phase difference of 120 degrees between phase b and phase c, and the phase difference makes the vector sum of the total current at any time point zero, thereby achieving balanced and efficient power transmission. A sampling unit (such as a sampling resistor) is connected to the phase loop of phase a and phase b. When n (for example, n is an integer greater than 1) modulators are connected to phase a or phase b, the digital signal of the sampling unit output by the n modulators under the control of a first clock signal with a clock frequency lower than a preset frequency can be obtained, and the digital signal output by the n modulators is processed to obtain a digital signal corresponding to a second clock signal with a clock frequency equal to the preset frequency. By replacing one high clock frequency sampling with n low clock frequency samplings, the filter can still receive digital signals at a high clock frequency while reducing the influence of high-frequency pulsation caused by high clock frequency sampling.
[0072] The sampling method provided in this application can also be used for analog-to-digital conversion in communication systems, biomedicine and other fields.
[0073] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.
[0074] Figure 5 The flow chart of the sampling method provided for this application is as follows: Figure 5 As shown, with the sampling chip as the execution subject, the method includes:
[0075] S101: Acquire digital signals of sampling units output by at least two modulators under the control of corresponding first clock signals, where a clock frequency of the first clock signal is lower than a preset frequency.
[0076] In this embodiment of the present application, at least two modulators are connected to the same sampling unit. Each modulator has a corresponding first clock signal. Under the control of the corresponding first clock signal, each modulator collects an analog signal from the sampling unit, converts the analog signal into a digital signal, and outputs it to the sampling chip. Accordingly, the sampling chip can obtain the digital signals output by the at least two modulators under the control of the corresponding first clock signal.
[0077] For example, the sampling chip may include a digital logic circuit. Each modulator collects the analog signal of the sampling unit under the control of the corresponding first clock signal, and may convert the analog signal into a digital signal and output it to the digital logic circuit in the sampling chip.
[0078] For example, the modulator may be a Sigma-Delta modulator, or may be other types of modulators, such as a successive approximation register (SAR) modulator.
[0079] For example, the sampling unit may be a sampling resistor. For example, sampling resistors are connected to the phase loops of two phases in a three-phase current system. The at least two modulators may be connected to any corresponding sampling resistors. Accordingly, the modulator may collect the voltage across the sampling resistors and convert the voltage signal into a digital signal.
[0080] For example, the first clock signal of each modulator may be a clock signal having the same clock frequency but different phases.
[0081] For example, the number of modulators is n, where n can be an integer greater than 1, and the first clock signal of one modulator is delayed by 1 / 2n cycles compared to the first clock signal of another modulator, so that a digital signal of a high clock chip can be generated based on a digital signal of a low clock frequency.
[0082] For example, n is 2, and they are respectively referred to as the first modulator and the second modulator. Then, the first clock signal of the first modulator can be delayed by 1 / 4 cycle compared with the first clock signal of the second modulator.
[0083] S102 . Process the digital signals output by at least two modulators to obtain a digital signal corresponding to a second clock signal, where the clock frequency of the second clock signal is equal to a preset frequency.
[0084] In this step, the digital signals output by the at least two modulators obtained in step S101 are processed to obtain a digital signal corresponding to a second clock signal, where the clock frequency of the second clock signal is greater than the clock frequency of the first clock signal. For example, the clock frequency of the first clock signal is 10 MHz, and the clock frequency of the second clock signal is 20 MHz.
[0085] It is understood that at least two modulators output digital signals corresponding to the low clock frequency under the control of the low clock frequency clock signal. In this step, the low clock frequency digital signals output by the at least two modulators can be converted into a digital signal with a high clock frequency. It should be noted that the terms "high" and "low" mentioned in this application are relative. The lower clock frequency is referred to as the low clock frequency, and the higher clock frequency is referred to as the high clock frequency.
[0086] Table 1
[0087]
[0088] For example, as shown in Table 1, the digital signal corresponding to the first modulator is signal A, signal A includes four bits abcd, the digital signal corresponding to the second modulator is signal B, signal B includes four bits efgh, then the composite signal obtained according to signal A and signal B (the digital signal corresponding to the second clock signal) includes eight bits aebfcgdh.
[0089] In some embodiments, the second clock signal and the digital signals output by at least two modulators can be subjected to logical operations to obtain a digital signal corresponding to the second clock signal. Considering that the clock frequency of the second clock signal is inconsistent with the frequency of the first clock signal corresponding to the modulator, a preset signal corresponding to each modulator is generated based on the second clock signal and the digital signals output by at least two modulators. At this time, the second clock signal and the preset signals corresponding to at least two modulators can be subjected to logical operations, so that based on simple logical operations, a digital signal corresponding to a high-frequency clock can be generated from the digital signal corresponding to a low-frequency clock.
[0090] For example, the digital signal output by the modulator based on the first clock signal can be padded according to the setting signal, and the sum of the number of bits of the setting signal and the number of bits of the digital signal output by the modulator is equal to the number of bits of the preset signal, that is, equal to the number of bits of the second clock signal, so that logical operations can be performed on the second clock signal and the preset signal corresponding to the modulator.
[0091] For example, the number of bits of the setting signal is equal to the number of bits of the second clock signal minus the number of bits of the digital signal output by the modulator based on the first clock signal. For example, if the second clock signal is eight bits and the digital signal output by the modulator based on the first clock signal is four bits, then the number of bits of the setting signal is four bits.
[0092] For example, if the number of bits of the signal is set to four, the signal can be set to 1010, or 0101, etc.
[0093] In some examples, there are two modulators, namely a first modulator and a second modulator. The first clock signal corresponding to the second modulator is delayed by a preset period, for example, 1 / 4 of a period, compared to the first clock signal corresponding to the first modulator. An AND operation is performed on the second clock signal and the preset signal corresponding to the first modulator to obtain a first processed signal. An AND operation is performed on the second clock signal and the preset signal corresponding to the second modulator to obtain a second processed signal. Then, an OR operation is performed on the first processed signal and the second processed signal to obtain a digital signal corresponding to the second clock signal. Thus, through the AND and OR operations, a digital signal corresponding to the high-frequency clock is obtained, simplifying the operation logic.
[0094] Table 2
[0095]
[0096] For example, as shown in Table 2, the digital signal corresponding to the first modulator is the A signal, the preset signal corresponding to the first modulator is the A' signal, the digital signal corresponding to the second modulator is the B signal, the preset signal corresponding to the second modulator is the B' signal, the second clock signal is the C signal, and the inverted signal of the second clock signal is the C' signal.
[0097] The A signal is 0101, the A' signal is 00110011, the B signal is 1010, the B' signal is 01100110, the C signal is 10101010, and the C' signal is 01010101. An AND operation is performed on the A' signal and the C signal to obtain a first processed signal 00100010. An AND operation is performed on the B' signal and the C' signal to obtain a second processed signal 01000100. An OR operation is performed on the first and second processed signals to obtain a composite signal S, which is the digital signal 01100110 corresponding to the second clock signal.
[0098] In other examples, the number of modulators is three, and a digital signal corresponding to the second clock signal can be obtained based on more complex logical operations, which can be specifically determined according to actual conditions.
[0099] In some examples, a first clock signal corresponding to the first modulator and a first clock signal corresponding to the second modulator may be XORed to obtain a second clock signal, thereby obtaining a high-frequency clock signal through simple operations.
[0100] S103: Send the digital signal corresponding to the second clock signal to the filter, so that the filter performs filtering processing on the received digital signal.
[0101] In this step, the digital signal corresponding to the high-frequency clock obtained in step S102 is sent to the filter, so that the filter can still receive the digital signal corresponding to the high-frequency clock when sampling at a low clock frequency. Accordingly, the filter can filter the received high-frequency clock signal.
[0102] The sampling method provided in the present application obtains digital signals output by at least two modulators under the control of a clock signal with a low clock frequency, processes the digital signals output by at least two modulators under the control of a low clock frequency, and obtains a digital signal corresponding to a clock signal with a high clock frequency, thereby providing a high clock frequency digital signal for the filter. In addition, by replacing one high clock frequency sampling with at least two low clock frequency samplings, the high-frequency pulsation effect caused by the high-frequency clock sampling can be reduced, thereby improving the quality and availability of the signal.
[0103] Figure 6 This is a schematic diagram of the structure of the motor sampling chip provided in this application. Figure 6 As shown, the motor sampling chip 40 provided in this embodiment includes: at least one processor 401 and a memory 402. Optionally, the chip 40 also includes a communication component 403. The processor 401, the memory 402, and the communication component 403 are connected via a bus 404.
[0104] In a specific implementation process, at least one processor 401 executes the computer-executable instructions stored in the memory 402, so that the at least one processor 401 performs the above method.
[0105] The specific implementation process of the processor 401 can be found in the above method embodiment. Its implementation principle and technical effects are similar and will not be repeated here in this embodiment.
[0106] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the present invention may be directly implemented by a hardware processor or implemented by a combination of hardware and software modules in the processor.
[0107] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (NVM), such as at least one disk memory.
[0108] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be classified into address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.
[0109] The present application also provides a motor sampling chip, such as Figure 7 As shown, the motor sampling chip 50 provided in the embodiment of the present application includes:
[0110] The motor sampling circuit 501 is connected to the sampling unit R1;
[0111] The motor sampling circuit 501 is used to obtain the digital signals of the sampling unit R1 output by at least two modulators under the control of the corresponding first clock signal, where the clock frequency of the first clock signal is lower than the preset frequency;
[0112] Processing the digital signals of the sampling unit R1 output by at least two modulators to obtain a digital signal corresponding to a second clock signal, where the clock frequency of the second clock signal is equal to a preset frequency;
[0113] The digital signal corresponding to the second clock signal is sent to the filter 502, so that the filter 502 performs filtering processing on the received digital signal.
[0114] In some embodiments, as Figure 7As shown, the motor sampling circuit 501 includes a digital logic circuit 507 and at least two modulators, each of which is connected to the sampling unit R1 and the digital logic circuit 507. Each modulator is used to collect the analog signal of the sampling unit R1 based on the corresponding first clock signal, convert the analog signal into a digital signal, and output it to the digital logic circuit 507, thereby achieving analog-to-digital conversion. Multiple modulators can also achieve low clock frequency sampling, reducing the high-frequency ripple effects caused by high clock frequency sampling. The digital logic circuit 507 is used to process the digital signal of the sampling unit R1 output by each modulator to obtain a digital signal corresponding to the second clock signal. The clock frequency of the second clock signal is equal to a preset frequency. The digital logic circuit 507 is also used to send the digital signal corresponding to the second clock signal to the filter 502, so that the filter 502 performs filtering on the received digital signal.
[0115] For example, Figure 7 As shown, the motor sampling chip 50 includes a first modulator 504 and a second modulator 505, both of which are connected to the sampling unit R1. The first modulator 504 can collect the voltage signal of the sampling unit R1 based on the corresponding clock signal 1, and the second modulator 505 can collect the voltage signal of the sampling unit R1 based on the corresponding clock signal 2. The clock frequency of clock signal 1 and clock signal 2 is consistent, and clock signal 2 is delayed by one quarter of the cycle of clock signal 1. Then, the first modulator 504 converts the collected voltage signal into digital signal 1 and outputs it to the digital logic circuit 507. The second modulator 505 converts the collected voltage signal into digital signal 2 and outputs it to the digital logic circuit 507. Accordingly, the digital logic circuit 507 can generate digital signal 3 (the digital signal corresponding to the second clock signal) based on digital signal 1 and digital signal 2, and send it to the filter 502.
[0116] In some embodiments, as Figure 7 As shown, the motor sampling chip 50 further includes a filter 502 , which is connected to the motor sampling circuit 501 . The filter 502 is used to filter the received digital signal to restore the digital signal representing the current and convert the bit stream output by the modulator into a stable and usable digital signal.
[0117] For example, the filter 502 may include a data pin, and the data pin is used to receive a digital signal corresponding to the second clock signal sent by the digital logic circuit 507 .
[0118] For example, Figure 7As shown, the motor sampling chip 50 may further include a motor controller 503 , and the filter 502 may be provided in the motor controller 503 . The filter 502 may be understood as a functional module in the motor controller 503 .
[0119] In some embodiments, as Figure 7 As shown, the motor sampling chip 50 further includes a crystal oscillator 506 connected to each modulator. The crystal oscillator 506 is used to generate at least one first clock signal and send each first clock signal to a corresponding modulator, thereby providing a corresponding first clock signal to each modulator.
[0120] In some examples, such as Figure 7 As shown, crystal oscillator 506 is also connected to digital logic circuit 501 and is further configured to send each first clock signal to digital logic circuit 501 so that digital logic circuit 501 generates a second clock signal based on each first clock signal. For example, when there are two modulators, crystal oscillator 506 can send the first clock signals of the two modulators to digital logic circuit 507, and digital logic circuit 507 can perform an exclusive-OR operation on the first clock signals of the two modulators to generate a second clock signal.
[0121] In some examples, the digital logic circuit 507 includes a first unit and a second unit, wherein the first unit is connected to the crystal oscillator 506 and the second unit, and the second unit is connected to each modulator. The crystal oscillator 506 is also used to send each first clock signal to the first unit, and the first unit is used to perform a logical operation on each first clock signal to generate a second clock signal and send it to the second unit. The second unit is used to obtain a digital signal corresponding to the second clock signal based on the second clock signal and the digital signal output by each modulator, and the clock frequency of the second digital signal is equal to a preset frequency. The second unit is also used to send the digital signal corresponding to the second clock signal to the filter 502, so that the filter 502 performs filtering processing on the received digital signal.
[0122] The present application also provides a motor control system. Figure 8 As shown, the motor sampling chip 50 and the motor 60 are provided with a corresponding sampling unit, and the motor sampling chip 50 is connected to the sampling unit. The motor sampling chip 50 is used to obtain the analog signal corresponding to the sampling unit and perform filtering after converting the analog signal into a digital signal.
[0123] The present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed by a processor, they are used to implement the methods provided in the various embodiments described above.
[0124] The present application also provides a computer program product, comprising computer instructions stored in a computer-readable storage medium. At least one processor of a device can read the computer instructions from the computer-readable storage medium, and at least one processor can execute the computer instructions so that the device implements the methods provided in the various embodiments described above.
[0125] Finally, it should be noted that those skilled in the art will readily identify other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art not disclosed herein. The present invention is not limited to the precise structure described above and illustrated in the accompanying drawings, and various modifications and variations may be made without departing from the scope thereof. The scope of the present invention is limited solely by the appended claims.
Claims
1. A sampling method, characterized in that: include: Acquire digital signals of sampling units output by at least two modulators under the control of corresponding first clock signals, where the clock frequency of the first clock signal is lower than a preset frequency; Processing the digital signals output by the at least two modulators to obtain a digital signal corresponding to a second clock signal, wherein a clock frequency of the second clock signal is equal to the preset frequency; The digital signal corresponding to the second clock signal is sent to a filter, so that the filter performs filtering processing on the received digital signal.
2. The method according to claim 1, characterized in that The processing of the digital signals output by the at least two modulators to obtain a digital signal corresponding to the second clock signal includes: generating a preset signal corresponding to each of the modulators according to the second clock signal and the digital signals output by the at least two modulators; A logic operation is performed on the second clock signal and the preset signals corresponding to the at least two modulators to obtain a digital signal corresponding to the second clock signal.
3. The method according to claim 2, characterized in that There are two modulators, namely a first modulator and a second modulator; the first clock signal corresponding to the second modulator is delayed by a preset period compared with the first clock signal corresponding to the first modulator; Performing a logic operation on the second clock signal and the preset signals corresponding to the at least two modulators to obtain a digital signal corresponding to the second clock signal includes: Performing an AND operation on the second clock signal and a preset signal corresponding to the first modulator to obtain a first processed signal; performing an AND operation on the inverted signal of the second clock signal and the preset signal corresponding to the second modulator to obtain a second processed signal; An OR operation is performed on the first processed signal and the second processed signal to obtain a digital signal corresponding to the second clock signal.
4. The method according to claim 3, characterized in that The method further comprises: An exclusive OR operation is performed on the first clock signal corresponding to the first modulator and the first clock signal corresponding to the second modulator to obtain the second clock signal.
5. A motor sampling chip, characterized in that: include: a processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the sampling method according to any one of claims 1 to 4.
6. A motor sampling chip, characterized in that: include: a motor sampling circuit, wherein the motor sampling circuit is connected to the sampling unit; The motor sampling circuit is configured to obtain digital signals of the sampling unit output by at least two modulators under the control of corresponding first clock signals, wherein the clock frequency of the first clock signal is lower than a preset frequency; Processing the digital signals of the sampling unit output by the at least two modulators to obtain a digital signal corresponding to a second clock signal, wherein the clock frequency of the second clock signal is equal to the preset frequency; The digital signal corresponding to the second clock signal is sent to a filter, so that the filter performs filtering processing on the received digital signal.
7. The motor sampling chip according to claim 6, characterized in that: The motor sampling circuit includes: a digital logic circuit and at least two modulators, each of the modulators being connected to the sampling unit and the digital logic circuit; Each of the modulators is configured to collect an analog signal from the sampling unit based on a corresponding first clock signal, convert the analog signal into a digital signal, and output the digital signal to the digital logic circuit; The digital logic circuit is used to process the digital signal of the sampling unit output by each modulator to obtain a digital signal corresponding to the second clock signal, where the clock frequency of the second clock signal is equal to the preset frequency; and is also used to send the digital signal corresponding to the second clock signal to the filter so that the filter performs filtering processing on the received digital signal.
8. The motor sampling chip according to claim 7, characterized in that: The motor sampling chip further includes: a filter connected to the motor sampling circuit; The filter is used to perform filtering processing on the received digital signal.
9. The motor sampling chip according to claim 7, characterized in that: The motor sampling chip further includes: a crystal oscillator, the crystal oscillator being connected to each of the modulators; The crystal oscillator is used to generate at least two first clock signals and send each of the first clock signals to the corresponding modulator.
10. The motor sampling chip according to claim 9, characterized in that: The digital logic circuit comprises: a first unit and a second unit, wherein the first unit is connected to the crystal oscillator and the second unit, and the second unit is connected to each of the modulators; The crystal oscillator is further used to send each of the first clock signals to the first unit; The first unit is configured to perform a logic operation on each of the first clock signals to generate the second clock signal and send the generated second clock signal to the second unit; The second unit is used to obtain a digital signal corresponding to the second clock signal based on the second clock signal and the digital signal output by each modulator, and the clock frequency of the second clock signal is equal to the preset frequency; and is also used to send the digital signal corresponding to the second clock signal to the filter so that the filter performs filtering processing on the received digital signal.
11. A motor control system, characterized in that: The motor sampling chip and the motor according to any one of claims 5 to 10 are provided with a corresponding sampling unit; The motor sampling chip is connected to the sampling unit; The motor sampling chip is used to obtain the analog signal corresponding to the sampling unit, and perform filtering processing after converting the analog signal into a digital signal.