Cross-clock domain data processing circuit, method, chip and equipment

Abstract

The invention discloses a cross-clock-domain data processing circuit, method, chip and equipment, relates to the technical field of electronics, and is used for reducing the time delay of cross-clock-domain data processing on the premise that the transmission bandwidth is not reduced. The circuit comprises a phase discriminator, a calculation circuit, a first register, a second register, a phase inverter and a selector, the input end of the phase discriminator is used for receiving a first clock signal and a second clock signal, the output end of the phase discriminator is coupled with the first input end of the calculation circuit, and the second input end of the calculation circuit is used for receiving the second clock signal; the input ends of the two registers are both used for receiving a first data signal, and the clock end of the second register is coupled with the clock end of the first register through the phase inverter and used for receiving a second clock signal; the two input ends of the selector are coupled with the output end of the first register and the output end of the second register respectively, the control end of the selector is coupled with the first output end of the computing circuit, and the output end of the selector is used for outputting a second data signal.

Description

A cross-clock domain data processing circuit, method, chip and device Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a cross-clock domain data processing circuit, method, chip and device. Background Art

[0002] Currently, numerous synchronous logic circuits are found in chips such as application-specific integrated circuits (ASICs), systems on chips (SOCs), programmable gate arrays (PGAs), and complex programmable logic devices (CPLDs). These synchronous logic circuits can be divided into different clock domains based on their operating clocks. When different clock domains within the same chip communicate, the data bus may need to be transferred from one clock domain to another, necessitating cross-clock domain data processing.

[0003] Summary of the Invention

[0004] The present application provides a cross-clock domain data processing circuit, method, chip and device for reducing the latency of cross-clock domain data processing without reducing the transmission bandwidth, thereby reducing cache and power consumption.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a cross-clock domain data processing circuit is provided, which can be used to process a first data signal in a first clock domain into a second data signal in a second clock domain, the clock signal of the first clock domain is a first clock signal, and the clock signal of the second clock domain is a second clock signal, comprising: a phase detector, a calculation circuit, a first register, a second register, a first inverter and a first selector; the two input ends of the phase detector are respectively used to receive the first clock signal and the second clock signal, the output end of the phase detector is coupled to the first input end of the calculation circuit, the second input end of the calculation circuit is used to receive the second clock signal, and the first output end of the calculation circuit is used to output a selection signal; the input end of the first register and the input end of the second register are both used to receive the first data signal, the clock end of the second register is coupled to the clock end of the first register through the first inverter and is used to receive the second clock signal; the two input ends of the first selector are respectively coupled to the output end of the first register and the output end of the second register, the control end of the first selector is used to receive the selection signal, and the output end of the first selector is used to output the second data signal.

[0007] In the above technical solution, the input end of the first register and the input end of the second register are both used to receive the first data signal, and the clock end of the second register is coupled to the clock end of the first register through the first inverter and is used to receive the second clock signal, so that the first register and the second register can respectively sample the first data signal at the rising edge and the falling edge of the second clock signal; the two input ends of the phase detector are respectively used to receive the first clock signal and the second clock signal, the output end of the phase detector is coupled to the first input end of the calculation circuit, the second input end of the calculation circuit is used to receive the second clock signal, and the first output end of the calculation circuit is used to output a selection signal, so that the selection signal indicating the optimal sampling phase can be determined by the phase detector and the calculation circuit; finally, under the control of the selection signal, the first selector can select the sampled data corresponding to the optimal sampling phase to obtain the second data signal, thereby realizing approximately "zero delay" for cross-clock domain data processing, achieving extremely low latency performance, and thereby reducing cache and power consumption.

[0008] In a possible implementation of the first aspect, the phase detector is used to output a phase indication signal based on a first clock signal and a second clock signal, the phase indication signal being used to indicate a phase difference between the first clock signal and the second clock signal; the calculation circuit is used to output a selection signal based on the phase indication signal and the second clock signal, the phase indication signal being used to determine a rising edge and a falling edge in each clock cycle of the second clock signal, the selection signal being used to indicate an edge with a longer sampling duration for the rising edge and the falling edge of each clock cycle for the same data in the first data signal; the first register is used to output a first sampling signal based on the first data signal and the second clock signal; the second register is used to output a second sampling signal based on an inverted clock signal of the first data signal and the second clock signal; and the first selector is used to select, based on the selection signal, the sampling data corresponding to the edge with a longer sampling duration from the first sampling signal and the second sampling signal in each clock cycle to obtain the second data signal. In the above possible implementation, it is possible to achieve near-zero latency in cross-clock domain data processing, achieve extremely low latency performance, and thereby reduce cache and power consumption.

[0009] In one possible implementation of the first aspect, the frequency of the second clock signal is greater than the frequency of the first clock signal; the second output terminal of the calculation circuit is used to output a valid indication signal, and the valid indication signal is used to indicate valid data in the second data signal. In this possible implementation, when the frequency of the second clock signal is greater than the frequency of the first clock signal, the bandwidth of the second clock signal is redundant, and in this case, the calculation circuit can output the valid indication signal to indicate valid data in the second data signal through the valid indication signal.

[0010] In a possible implementation of the first aspect, the cross-clock domain data processing circuit can also be used to process a third data signal in a first clock domain into a second data signal in a second clock domain. The cross-clock domain data processing circuit further includes: a third register, a fourth register, a second inverter, and a second selector; wherein the input end of the third register is used to receive the third data signal, the input end of the fourth register is coupled to the output end of the third register, and the clock end of the fourth register is coupled to the clock end of the third register via the second inverter and is used to receive the first clock signal; the two input ends of the second selector are respectively coupled to the output end of the third register and the output end of the fourth register, and the output end of the second selector is used to output the first data signal. In the above possible implementation, the input end of the third register is used to receive the third data signal, the input end of the fourth register is coupled to the output end of the third register, and the clock end of the fourth register is coupled to the clock end of the third register via the second inverter and is used to receive the first clock signal, so that the third register sends the third data signal at each rising edge of the first clock signal, and the fourth register sends the third data signal at each falling edge of the first clock signal, and the second selector selects data corresponding to the best transmission phase from the transmitted third data signal and outputs it.

[0011] In a possible implementation of the first aspect, the third register is configured to output a third sampling signal based on a third data signal and a first clock signal; the fourth register is configured to output a fourth sampling signal based on the third sampling signal and an inverted clock signal of the first clock signal; and the second selector is configured to output the first data signal based on the third sampling signal and the fourth sampling signal. In this possible implementation, the third register may transmit the third data signal at every rising edge of the first clock signal, and the fourth register may transmit the third data signal at every falling edge of the first clock signal.

[0012] In one possible implementation of the first aspect, the frequency of the first clock signal is greater than the frequency of the second clock signal; the third output terminal of the calculation circuit is used to output a transmission instruction signal, which is used to indicate whether to transmit the third data signal. In this possible implementation, when the frequency of the first clock signal is greater than the frequency of the second clock signal, the bandwidth of the first clock signal is redundant. In this case, the calculation circuit can output the transmission instruction signal to instruct the write side to stop transmitting the first data signal through the transmission instruction signal.

[0013] In a second aspect, a cross-clock domain data processing circuit is provided, which can be used to process a first data signal in a first clock domain into a second data signal in a second clock domain, the clock signal of the first clock domain is a first clock signal, and the clock signal of the second clock domain is a second clock signal, comprising: a phase detector, a calculation circuit, a first register, a second register, an inverter and a selector; the two input ends of the phase detector are respectively used to receive the first clock signal and the second clock signal, the output end of the phase detector is coupled to the first input end of the calculation circuit, the second input end of the calculation circuit is used to receive the first clock signal, and the first output end of the calculation circuit is used to output a selection signal; the input end of the first register is used to receive the first data signal, the input end of the second register is coupled to the output end of the first register, the clock end of the second register is coupled to the clock end of the first register through the inverter and is used to receive the first clock signal; the two input ends of the selector are respectively coupled to the output end of the first register and the output end of the second register, the control end of the selector is used to receive the selection signal, and the output end of the selector is used to output the second data signal.

[0014] In the above technical solution, the input end of the first register is used to receive the first data signal, the input end of the second register is coupled to the output end of the first register, and the clock end of the second register is coupled to the clock end of the first register through the inverter and is used to receive the first clock signal, so that the first register and the second register can send the first data signal on the rising edge and falling edge of the first clock signal respectively; the two input ends of the phase detector are used to receive the first clock signal and the second clock signal respectively, the output end of the phase detector is coupled to the first input end of the calculation circuit, the second input end of the calculation circuit is used to receive the first clock signal, and the first output end of the calculation circuit is used to output a selection signal, so that the phase detector and the calculation circuit can determine the selection signal indicating the optimal transmission phase; finally, the selector can select the data corresponding to the optimal transmission phase according to the selection signal to obtain the second data signal, thereby realizing approximate "zero delay" of cross-clock domain data processing, achieving extremely low latency performance, and thereby reducing cache and power consumption.

[0015] In a possible implementation of the second aspect, the phase detector is used to output a phase indication signal based on the first clock signal and the second clock signal, the phase indication signal being used to indicate the phase difference between the first clock signal and the second clock signal; the calculation circuit is used to output a selection signal based on the phase indication signal and the first clock signal, the phase indication signal being used to determine the rising edge and falling edge of each clock cycle in the first clock signal, the selection signal being used to indicate the rising edge and falling edge of each clock cycle that has a longer sampling duration for the same data in the first data signal; the first register is used to output a first sampling signal based on the first data signal and the first clock signal; the second register is used to output a second sampling signal based on the first sampling signal and the inverted clock signal corresponding to the first clock signal; the selector is used to select the sampling data corresponding to the edge with a longer sampling duration from the first sampling signal and the second sampling signal in each clock cycle based on the selection signal to obtain the second data signal. In the above possible implementation, it is possible to achieve near-zero latency in cross-clock domain data processing, achieve extremely low latency performance, and thereby reduce cache and power consumption.

[0016] In one possible implementation of the second aspect, the frequency of the first clock signal is greater than the frequency of the second clock signal; the second output terminal of the calculation circuit is used to output a transmission indication signal, which is used to indicate whether to transmit the first data signal. In this possible implementation, when the frequency of the first clock signal is greater than the frequency of the second clock signal, the bandwidth of the first clock signal is redundant. In this case, the calculation circuit can output the transmission indication signal to instruct the write side to stop transmitting the first data signal through the transmission indication signal.

[0017] In a third aspect, a cross-clock domain data processing method is provided, which is applied to a cross-clock domain data processing circuit, the cross-clock domain data processing circuit comprising: a phase detector, a calculation circuit, a first register, a second register, a first inverter and a first selector; the method comprising: the phase detector outputting a phase indication signal according to the first clock signal and the second clock signal, the phase indication signal being used to indicate the phase difference between the first clock signal and the second clock signal; the calculation circuit outputting a selection signal according to the phase indication signal and the second clock signal, the phase indication signal being used to determine the rising edge and the falling edge of each clock cycle in the second clock signal, the selection signal being used to indicate the rising edge and the falling edge of each clock cycle for the same data in the first data signal with a longer sampling time; the first register outputting a first sampling signal according to the first data signal and the second clock signal; the second register outputting a second sampling signal according to an inverted clock signal of the first data signal and the second clock signal; the first selector selecting, according to the selection signal, the sampling data corresponding to the edge with a longer sampling time from the first sampling signal and the second sampling signal in each clock cycle to obtain the second data signal.

[0018] In a possible implementation of the third aspect, the frequency of the second clock signal is greater than the frequency of the first clock signal, and the method further includes: the calculation circuit outputting a valid indication signal, where the valid indication signal is used to indicate valid data in the second data signal.

[0019] In a possible implementation of the third aspect, the cross-clock domain data processing circuit further includes: a third register, a fourth register, a second inverter, and a second selector; the method further includes: the third register outputting a third sampling signal based on the third data signal and the first clock signal; the fourth register outputting a fourth sampling signal based on the third sampling signal and an inverted clock signal of the first clock signal; and the second selector outputting the first data signal based on the third sampling signal and the fourth sampling signal.

[0020] In a possible implementation of the third aspect, the frequency of the first clock signal is greater than the frequency of the second clock signal, and the method further includes: the calculation circuit outputting a transmission indication signal, where the transmission indication signal is used to indicate whether to transmit the third data signal.

[0021] In a fourth aspect, a cross-clock domain data processing method is provided, which is applied to a cross-clock domain data processing circuit, the cross-clock domain data processing circuit comprising: a phase detector, a first register of a calculation circuit, a second register, an inverter and a selector; the method comprising: the phase detector outputting a phase indication signal according to a first clock signal and a second clock signal, the phase indication signal being used to indicate a phase difference between the first clock signal and the second clock signal; the calculation circuit outputting a selection signal according to the phase indication signal and the first clock signal, the phase indication signal being used to determine a rising edge and a falling edge of each clock cycle in the first clock signal, the selection signal being used to indicate an edge with a longer sampling duration for the same data in the first data signal of the rising edge and the falling edge of each clock cycle; the first register outputting a first sampling signal according to the first data signal and the first clock signal; the second register outputting a second sampling signal according to the first sampling signal and an inverted clock signal corresponding to the first clock signal; the selector selecting, according to the selection signal, sampling data corresponding to an edge with a longer sampling duration from the first sampling signal and the second sampling signal in each clock cycle to obtain a second data signal.

[0022] In a possible implementation of the fourth aspect, the frequency of the first clock signal is greater than the frequency of the second clock signal, and the method further includes: the calculation circuit outputting a transmission indication signal, where the transmission indication signal is used to indicate whether to transmit the first data signal.

[0023] In another aspect of the present application, a chip is provided, which includes: synchronous logic circuits in different clock domains, and a cross-clock domain data processing circuit provided by the first aspect or any possible implementation of the first aspect.

[0024] In yet another aspect of the present application, an electronic device is provided, comprising: a packaging substrate, and a chip as provided above fixed on the packaging substrate.

[0025] It can be understood that the beneficial effects that can be achieved by any of the chips and electronic devices provided above can correspond to the beneficial effects in the cross-clock domain data processing circuit provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG1 is a schematic structural diagram of a cross-clock domain data processing circuit based on DMUX;

[0027] FIG2 is a signal timing diagram of a cross-clock domain data processing circuit based on DMUX;

[0028] FIG3 is a schematic structural diagram of a FIFO-based cross-clock domain data processing circuit;

[0029] FIG4 is a signal timing diagram of a FIFO-based cross-clock domain data processing circuit;

[0030] FIG5 is a signal timing diagram of another FIFO-based cross-clock domain data processing circuit;

[0031] FIG6 is a schematic structural diagram of a cross-clock domain data processing circuit provided in an embodiment of the present application;

[0032] FIG7 is a signal timing diagram of a cross-clock domain data processing circuit provided by an embodiment of the present application;

[0033] FIG8 is a schematic structural diagram of another cross-clock domain data processing circuit provided in an embodiment of the present application;

[0034] FIG9 is a signal timing diagram of another cross-clock domain data processing circuit provided by an embodiment of the present application;

[0035] FIG10 is a schematic structural diagram of another cross-clock domain data processing circuit provided in an embodiment of the present application;

[0036] FIG11 is a schematic structural diagram of another cross-clock domain data processing circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The following sections discuss the making and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided herein can be implemented in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to implement and use this description and technology and do not limit the scope of this application.

[0038] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0039] Various circuits or other components may be described or referred to as being "configured to" perform one or more tasks. In this case, "configured to" is used to imply structure by indicating that the circuit / component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when a specified circuit / component is not currently operational (e.g., not turned on), the circuit / component may be referred to as being configured to perform the task. Circuits / components used with the phrase "configured to" include hardware, such as circuitry that performs an operation, etc.

[0040] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can be single or multiple.

[0041] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or effects. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or order of execution. The term "coupled" is used to indicate an electrical connection, including direct connection via wires or connectors or indirect connection via other devices. Therefore, "coupling" should be considered a broadly defined electronic communication connection.

[0042] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0043] Before introducing the embodiments of the present application, the relevant background technology involved in the present application is first introduced and explained.

[0044] Chips such as application-specific integrated circuits (ASICs), systems on chips (SOCs), programmable gate arrays (PGAs), and complex programmable logic devices (CPLDs) contain numerous synchronous logic circuits. These circuits can be divided into different clock domains based on their operating clocks. When different clock domains within the same chip communicate, the data bus may need to be transferred from one clock domain to another, necessitating cross-clock domain data processing.

[0045] Figure 1 shows a structural schematic diagram of a cross-clock domain data processing circuit based on a data selector DMUX. The cross-clock domain data processing circuit can be used to process a data signal din in a first clock domain into a data signal dout in a second clock domain. The clock signal in the first clock domain is clk_tx, and the clock signal in the second clock domain is clk_rx.

[0046] The cross-clock domain data processing circuit includes a data selector (DMUX), a trigger, and an asynchronous sampling judgment circuit. The first input of the data selector is used to receive a data signal din, where the clock signal of the clock domain in which the data signal din resides is clk_tx. The output of the data selector is coupled to the input of the trigger. The output of the trigger is coupled to the second input of the data selector. The clock terminal of the trigger is used to receive the clock signal clk_rx. The output of the trigger is also used to output a data signal dout. The first input of the asynchronous sampling judgment circuit is used to receive a first indication signal vld_in, which indicates valid data in the data signal din. The second input of the asynchronous sampling judgment circuit is used to receive the clock signal clk_rx. The first output of the asynchronous sampling judgment circuit is coupled to the control terminal of the data selector. The second output of the asynchronous sampling judgment circuit is used to output a second indication signal vld_out, which indicates valid data in the data signal dout. The timing of the clock signal clk_tx, the first indication signal vld_in, the data signal din, the clock signal clk_rx, the second indication signal vld_out, and the data signal dout is shown in FIG2 . FIG2 also shows two signals within the asynchronous sampling judgment circuit (i.e., the two signals located between clk_rx and vld_out).

[0047] The aforementioned DMUX-based cross-clock domain data processing circuit is only applicable to asynchronous data signal transitions from a slow clock domain to a fast clock domain, i.e., when the frequency of the clock signal clk_tx is less than that of the clock signal clk_rx. This asynchronous sampling and judgment circuit can be used to sample the first indication signal vld_in based on the clock signal clk_rx. When the first indication signal vld_in is valid, it outputs a selection signal to the data selector. This selector, based on the selection signal, outputs the stabilized data signal din to a flip-flop, which then outputs the data signal dout in the second clock domain. However, the asynchronous transmission bandwidth of this solution is limited and cannot reach the line rate of the clock signal clk_tx, resulting in bandwidth waste.

[0048] Figure 3 shows a structural schematic diagram of a cross-clock domain data processing circuit based on first in first out (FIFO). The cross-clock domain data processing circuit can be used to process the data signal din of the first clock domain into the data signal dout of the second clock domain. The clock signal of the first clock domain is clk_wr, and the clock signal of the second clock domain is clk_rd.

[0049] This FIFO-based cross-clock domain data processing circuit includes a random access memory (RAM), a write address control logic device, a read address control logic device, and six flip-flops. The RAM is configured to receive a clock signal clk_wr, a clock signal clk_rd, a binary code write address, a binary code read address, and a data signal din, and output a data signal dout. The write address control logic device is configured to receive the clock signal clk_wr and a first indication signal vld_in, and output a binary code write address and a Gray code write address. The first indication signal vld_in is used to indicate valid data in the data signal din. The read address control logic device is configured to receive the clock signal clk_rd, and output a binary code read address, a Gray code read address, and a second indication signal vld_out. The second indication signal vld_out is used to indicate valid data in the data signal dout. The write address control logic device is also configured to receive a Gray code read address processed by three flip-flops. The read address control logic device is also configured to receive a Gray code write address processed by the three flip-flops. The timing of the clock signal clk_wr, the first indication signal vld_in, the data signal din, the write address, the clock signal clk_rd, the write address transmitted to the read side (i.e., the write address received by the read address control logic device), and the data signal dout is shown in FIG4 . In FIG4 , A, B, and C represent data, N, N+1, and N+2 represent write addresses, and add N, add N+1, and add N+2 represent write addresses transmitted to the read side.

[0050] In the aforementioned FIFO-based cross-clock domain data processing circuit, the data signal din is written to the RAM in a FIFO-based manner according to the binary write address. Simultaneously, the write address control logic converts the write address from binary code to Gray code and passes the Gray code write address to three flip-flops coupled to the read address control logic to eliminate metastable states caused by asynchronous transitions. The read address control logic then converts the Gray code back to a binary read address and retrieves the data from the RAM based on this read address. This scheme achieves a transmission bandwidth that can reach the line rate of the clock signal clk_wr, but the address control logic is relatively complex, and the FIFO buffer depth depends on the latency of the FIFO control path. Taking the timing diagram shown in Figure 5 as an example, the latency from data entry to data retrieval is "one write clock cycle wr_cyc + no less than three read clock cycles rd_cyc × (3 + X), where 0 < X ​​< 1." This results in an overall latency / buffer depth of 5-7 cycles. If the clock frequency is high, the conversion between binary code and Gray code on both the read and write sides requires an additional write clock cycle wr_cyc and a read clock cycle rd_cyc, respectively. The latency is "two write clock cycles + no less than four read clock cycles." Based on the above, if the three read-side flip-flops (i.e., three flip-flops) are insufficient to eliminate metastability and need to be increased to four, the latency is "two write clock cycles + no less than five read clock cycles."

[0051] Based on this, embodiments of the present application provide a cross-clock domain data processing circuit for implementing cross-clock domain data processing without reducing transmission bandwidth, while reducing latency during data processing, thereby reducing cache and power consumption. The cross-clock domain data processing circuit of embodiments of the present application is described in detail below.

[0052] Figure 6 is a schematic diagram of the structure of a cross-clock domain data processing circuit provided in an embodiment of the present application. The cross-clock domain data processing circuit can be used to process a first data signal din in a first clock domain into a second data signal dout in a second clock domain. The clock signal in the first clock domain is the first clock signal clk_wr, and the clock signal in the second clock domain is the second clock signal clk_rd. The first data signal din can also be referred to as a source data signal, and the first clock signal clk_wr can also be referred to as a write-side clock signal or a source clock signal; the second data signal dout can also be referred to as a sink data signal, and the second clock signal clk_rd can also be referred to as a read-side clock signal or a sink-read-side clock signal.

[0053] The cross-clock domain data processing circuit includes a phase detector 11, a calculation circuit 12, a first register 13, a second register 14, an inverter 15, and a selector 16. The two inputs of the phase detector 11 are respectively configured to receive a first clock signal (clk_wr) and a second clock signal (clk_rd). The output of the phase detector 11 is coupled to the first input of the calculation circuit 12. The second input of the calculation circuit 12 is configured to receive the second clock signal (clk_rd), and the first output of the calculation circuit is configured to output a selection signal (slt). The inputs of the first register 13 and the second register 14 are both configured to receive a first data signal (din). The clock terminal of the second register 14 is coupled to the clock terminal of the first register 13 via the inverter 15 and is configured to receive the second clock signal (clk_rd). The two inputs of the selector 16 are respectively coupled to the outputs of the first register 13 and the second register 14. The control terminal of the selector 16 is configured to receive the selection signal (slt), and the output of the selector 16 is configured to output the second data signal (dout). Optionally, the calculation circuit 12 may be a logic calculation circuit or a logic control circuit.

[0054] In this cross-clock domain data processing circuit, the phase detector 11 is configured to output a phase indication signal based on a first clock signal clk_wr and a second clock signal clk_rd, the phase indication signal indicating the phase difference between the first clock signal clk_wr and the second clock signal clk_rd. The calculation circuit 12 is configured to output a selection signal slt based on the phase indication signal and the second clock signal clk_rd. The first register 13 is configured to output a first sampling signal reg1 based on a first data signal din and a second clock signal clk_rd. The second register 14 is configured to output a second sampling signal reg2 based on an inverted clock signal of the first data signal din and the second clock signal clk_rd. The selector 16 is configured to output a second data signal dout based on the first sampling signal reg1 and the second sampling signal reg2 under the control of the selection signal slt. The phase indication signal can be used to determine the rising edge and falling edge of each clock cycle in the second clock signal, and the selection signal slt is configured to indicate the rising edge or falling edge of each clock cycle with the longer sampling duration. The selector 16 is specifically configured to select sampling data corresponding to an edge with a longer sampling duration from the first sampling signal and the second sampling signal in each clock cycle according to the selection signal, so as to obtain the second data signal dout.

[0055] That is, the phase detector 11 can periodically perform phase detection on both clocks (i.e., the first clock signal clk_wr and the second clock signal clk_rd). Based on the phase detection result of the phase detector 11, the calculation circuit 12 can calculate the phase of the two clocks at the phase detection moment. It can also iteratively calculate the phase relationship between each clock edge of the first clock signal clk_wr (i.e., the data transmission moment) and the second clock signal clk_rd based on the clock rate ratio of the two clocks, and output a selection signal slt indicating the optimal sampling phase. The first register 13 samples the first data signal din at each rising edge of the second clock signal clk_rd, and the second register 14 samples the first data signal din at each falling edge of the second clock signal clk_rd. Thus, the selector 16 can select the sampled data corresponding to the optimal sampling phase from the first sampling signal reg1 output by the first register 13 and the second sampling signal reg2 output by the second register 14 based on the selection signal slt, and output the second data signal dout. The rate ratio of the clocks on both sides can be communicated to the calculation circuit 12 via an external indication signal, or can be calculated by the calculation circuit 12 based on the phase detection results of the two outputs of the phase detector 11. This embodiment of the present application does not impose any specific limitation on this. The rising edge and falling edge of the clock signal can also be referred to as the positive edge and negative edge of the clock signal, respectively.

[0056] Optionally, the frequency Frd of the second clock signal clk_rd is greater than the frequency Fwr of the first clock signal clk_wr, that is, Frd>Fwr. In this case, the second output terminal of the calculation circuit 12 is used to output the valid indication signal vld_out, that is, the calculation circuit 12 can also output the valid indication signal vld_out based on the phase indication signal and the second clock signal clk_rd. The valid indication signal vld_out is used to indicate valid data in the second data signal dout.

[0057] That is, when the frequency Frd of the second clock signal clk_rd is greater than the frequency Fwr of the first clock signal clk_wr, the bandwidth of the second clock signal clk_rd is redundant, and the calculation circuit 12 can output the valid indication signal vld_out to indicate the valid data in the second data signal dout through the valid indication signal vld_out.

[0058] The timing of the first clock signal clk_wr, first data signal din, second clock signal clk_rd, first sampling signal reg1, second sampling signal reg2, selection signal slt, second data signal dout, and valid indication signal vld_out is shown in Figure 7. A through H in Figure 7 represent data, while C / D, D / E, E / F, X / A, A / B, and G / H represent unstable (or metastable) sampled data. This is because the sampling clock edge may fall within the variation range of the sampled data. Therefore, the correct selection signal slt should avoid sampling such unstable data.

[0059] Optionally, the cross-clock domain data processing circuit may further include a receiving side register, the input end of the receiving side register may be used to receive the second data signal dout, the clock end of the receiving side register may be used to receive the second clock signal clk_rd, and the output end of the receiving side register may be used to output the data signal dout'.

[0060] The cross-clock domain data processing circuit provided in the embodiment of the present application can sample the first data signal din at the rising edge and the falling edge of the second clock signal clk_rd through the first register 13 and the second register 14, respectively, determine the selection signal indicating the optimal sampling phase through the phase detector 11 and the calculation circuit 12, and enable the selector 16 to select the sampling data corresponding to the optimal sampling phase according to the selection signal to obtain the second data signal dout, thereby realizing approximate "zero delay" of cross-clock domain data processing, achieving extremely low latency performance, and thereby reducing cache and power consumption.

[0061] FIG8 is a schematic diagram of the structure of another cross-clock domain data processing circuit provided in an embodiment of the present application. This cross-clock domain data processing circuit can be used to process a first data signal din in a first clock domain into a second data signal dout in a second clock domain, where the first clock signal in the first clock domain is clk_wr and the second clock signal in the second clock domain is clk_rd. The first data signal din can also be referred to as a source data signal, and the first clock signal clk_wr can also be referred to as a write-side clock signal or a source clock signal; the second data signal dout can also be referred to as a sink data signal, and the second clock signal clk_rd can also be referred to as a read-side clock signal or a sink-read-side clock signal.

[0062] The cross-clock domain data processing circuit includes a phase detector 21, a calculation circuit 22, a first register 23, a second register 24, an inverter 25, and a selector 26. The two inputs of the phase detector 21 are respectively configured to receive a first clock signal (clk_wr) and a second clock signal (clk_rd). The output of the phase detector 21 is coupled to a first input of the calculation circuit 22. The second input of the calculation circuit 22 is configured to receive the first clock signal (clk_wr), and the first output of the calculation circuit 22 is configured to output a selection signal (slt). The input of the first register 23 is configured to receive a first data signal (din). The input of the second register 24 is coupled to the output of the first register 23. The clock terminal of the second register 24 is coupled to the clock terminal of the first register 23 via the inverter 25 and is configured to receive the first clock signal (clk_wr). The two inputs of the selector 26 are respectively coupled to the output of the first register 23 and the output of the second register 24. The control terminal of the selector 26 is configured to receive the selection signal (slt), and the output of the selector 26 is configured to output a second data signal (dout).

[0063] Optionally, the calculation circuit 22 may be a logic calculation circuit or a logic control circuit. In the cross-clock domain data processing circuit, the phase detector 21 is configured to output a phase indication signal based on the first clock signal clk_wr and the second clock signal clk_rd, the phase indication signal being configured to indicate the phase difference between the first clock signal clk_wr and the second clock signal clk_rd; the calculation circuit 22 is configured to output a selection signal based on the phase indication signal and the first clock signal clk_wr; the first register 23 is configured to output a first sampling signal reg1 based on the first data signal din and the first clock signal clk_wr; the second register 24 is configured to output a second sampling signal reg2 based on the first sampling signal and the inverted clock signal corresponding to the first clock signal clk_wr; and the selector 26 is configured to output a second data signal dout based on the first sampling signal reg1 and the second sampling signal reg2 under the control of the selection signal. The phase indication signal may be used to determine the rising edge and falling edge of each clock cycle in the first clock signal, and the selection signal slt is configured to indicate the rising edge or falling edge of each clock cycle with the longer sampling duration. The selector 26 is specifically configured to select sampling data corresponding to an edge with a longer sampling duration from the first sampling signal and the second sampling signal in each clock cycle according to the selection signal, so as to obtain the second data signal dout.

[0064] That is, the phase detector 21 can periodically perform phase detection on the two clocks (i.e., the first clock signal clk_wr and the second clock signal clk_rd). The calculation circuit 22 can calculate the phase of the two clocks at the phase detection moment based on the phase detection result of the phase detector 21, and iteratively calculate the phase relationship between each clock edge in the first clock signal clk_wr (i.e., the data transmission moment) and the second clock signal clk_rd based on the clock rate ratio of the two sides, and output a selection signal slt to indicate the optimal transmission phase. The first register 23 transmits the first data signal din at each rising edge of the first clock signal clk_wr, and the second register 24 transmits the first data signal din at each falling edge of the first clock signal clk_wr. In this way, the selector 26 can select the data corresponding to the optimal transmission phase from the first sampling signal reg1 output by the first register 23 and the second sampling signal reg2 output by the second register 24 based on the selection signal slt to output the second data signal dout. The rate ratio of the clocks on both sides can be communicated to the calculation circuit 22 via an external indication signal, or can be calculated by the calculation circuit 22 based on the phase detection results of the two outputs of the phase detector 21. This embodiment of the present application does not impose any specific limitation on this. The rising edge and falling edge of the clock signal can also be referred to as the positive edge and negative edge of the clock signal, respectively.

[0065] Optionally, the frequency Fwr of the first clock signal clk_wr is greater than the frequency Frd of the second clock signal clk_rd, ie, Fwr>Frd. In this case, the third output terminal of the calculation circuit is used to output a transmission indication signal bp, which is used to indicate whether to transmit the third data signal din'.

[0066] That is, when the frequency Fwr of the first clock signal clk_wr is greater than the frequency Frd of the second clock signal clk_rd, the bandwidth of the first clock signal clk_wr is redundant, and the calculation circuit 12 can output the transmission indication signal bp to instruct the write side to stop transmitting the first data signal din through the transmission indication signal bp.

[0067] Optionally, the cross-clock domain data processing circuit may further include a receiving side register, the input end of the receiving side register may be used to receive the second data signal dout, the clock end of the receiving side register may be used to receive the second clock signal clk_rd, and the output end of the receiving side register may be used to output the data signal dout'.

[0068] For the cross-clock domain data processing circuit, the timing of the first clock signal clk_wr, the transfer indication signal bp, the first sampling signal reg1, the second sampling signal reg2, the selection signal slt, the second data signal dout, the second clock signal clk_rd and the data signal dout' is shown in Figure 9, where A to G in Figure 9 represent data.

[0069] Furthermore, the input end of the second register 24 in FIG. 8 can also be used to receive the first data signal din, without being coupled to the output end of the first register 23. In this case, the structure of the cross-clock domain data processing circuit is shown in FIG. 10 , and the second register 24 is used to output the second sampling signal reg2 based on the first data signal din and the inverted clock signal corresponding to the first clock signal clk_wr. It can be understood that the specific description of the functions of the various components in the cross-clock domain data processing circuit shown in FIG. 10 is similar to the functions of the various components in the cross-clock domain data processing circuit shown in FIG. 8 above. For details, please refer to the description above, and the embodiments of the present application will not be repeated here.

[0070] The cross-clock domain data processing circuit provided in the embodiment of the present application can send the first data signal din at the rising edge and falling edge of the first clock signal clk_wr respectively through the first register 23 and the second register 24, determine the selection signal indicating the optimal transmission phase through the phase detector 11 and the calculation circuit 12, and enable the selector 26 to select the data corresponding to the optimal transmission phase according to the selection signal to obtain the second data signal dout, thereby realizing approximate "zero delay" of cross-clock domain data processing, achieving extremely low latency performance, and thereby reducing cache and power consumption.

[0071] Figure 11 is a schematic diagram of the structure of another cross-clock domain data processing circuit provided in an embodiment of the present application. This cross-clock domain data processing circuit can be used to process a third data signal din' in a first clock domain into a second data signal dout in a second clock domain, where the first clock signal in the first clock domain is clk_wr, and the second clock signal in the second clock domain is clk_rd. The third data signal din' can also be referred to as a source data signal, and the first clock signal clk_wr can also be referred to as a write-side clock signal or a source clock signal. The second data signal dout can also be referred to as a sink data signal, and the second clock signal clk_rd can also be referred to as a read-side clock signal or a sink-read-side clock signal.

[0072] The cross-clock domain data processing circuit is applicable to a situation where the frequency Fwr of the first clock signal clk_wr and the frequency Frd of the second clock signal clk_rd are reversed. In one example, the frequency Fwr of the first clock signal clk_wr changes from greater than Frd to less than Frd, or from less than Frd to greater than Frd. In another example, the frequency Frd of the second clock signal clk_wr changes from greater than Fwr to less than Fwr, or from less than Fwr to greater than Fwr.

[0073] The cross-clock domain data processing circuit includes a phase detector 31, a calculation circuit 32, a first register 33, a second register 34, a first inverter 35, a first selector 36, a third register 37, a fourth register 38, a second inverter 39, and a second selector 40. The two inputs of the phase detector 31 are respectively configured to receive a first clock signal (clk_wr) and a second clock signal (clk_rd). The output of the phase detector 11 is coupled to the first input of the calculation circuit 32. The second input of the calculation circuit 32 is configured to receive the second clock signal (clk_rd), and the first output of the calculation circuit 32 is configured to output a selection signal (slt). The inputs of the first register 33 and the second register 34 are both coupled to the output of the second selector 40, and the output of the second selector 40 is configured to output the first data signal (din). The clock terminal of the second register 34 is coupled to the clock terminal of the first register 33 via the first inverter 35 and is configured to receive the second clock signal (clk_rd). The two inputs of the first selector 36 are respectively coupled to the output of the first register 33 and the output of the second register 34. The control terminal of the first selector 36 is used to receive the selection signal slt, and the output terminal of the first selector 36 is used to output the second data signal dout. The input terminal of the third register 37 is used to receive the third data signal din'. The input terminal of the fourth register 38 is coupled to the output terminal of the third register 37. The clock terminal of the fourth register 38 is coupled to the clock terminal of the third register 37 via a second inverter 39 and is used to receive the first clock signal clk_wr. The two input terminals of the second selector 40 are respectively coupled to the output terminal of the third register 37 and the output terminal of the fourth register 38. Optionally, the calculation circuit 32 can be a logic calculation circuit or a logic control circuit.

[0074] In the cross-clock domain data processing circuit, the phase detector 31 is used to output a phase indication signal based on the first clock signal clk_wr and the second clock signal clk_rd, and the phase indication signal is used to indicate the phase difference between the first clock signal clk_wr and the second clock signal clk_rd; the calculation circuit 32 is used to output a selection signal slt based on the phase indication signal and the second clock signal clk_rd; the first register 33 is used to output a first sampling signal reg1 based on the first data signal din and the second clock signal clk_rd; the second register 34 is used to output a second sampling signal reg2 based on the inverted clock signal of the first data signal din and the second clock signal clk_rd; the first selector 36 is used to output a second data signal dout based on the first sampling signal reg1 and the second sampling signal reg2 under the control of the selection signal slt, for example, according to the selection signal slt, select the sampling data corresponding to the edge with the longer sampling duration from the first sampling signal reg1 and the second sampling signal reg2 in each clock cycle to obtain the second data signal dout. The third register 37 is used to output a third sampling signal reg3 based on the third data signal din' and the first clock signal clk_wr; the fourth register 38 is used to output a fourth sampling signal reg4 based on the third sampling signal reg3 and the inverted clock signal of the first clock signal clk_wr; the second selector 40 is used to output the first data signal din based on the third sampling signal reg3 and the fourth sampling signal reg4.

[0075] That is, the third register 37 transmits the third data signal din' at each rising edge of the first clock signal clk_wr, the fourth register 38 transmits the third data signal din' at each falling edge of the first clock signal clk_wr, and the second selector 40 selects and outputs the data corresponding to the optimal transmission phase from the transmitted third data signal din'. The phase detector 31 can periodically perform phase detection on the two clocks (i.e., the first clock signal clk_wr and the second clock signal clk_rd). The calculation circuit 32 can calculate the phase of the two clocks at the phase detection moment based on the phase detection result of the phase detector 31, and iteratively calculate the phase relationship between each clock edge of the first clock signal clk_wr (i.e., the data transmission moment) and the second clock signal clk_rd based on the clock rate ratio of the two sides, and output a selection signal slt indicating the optimal sampling phase. The first register 33 samples the first data signal din at each rising edge of the second clock signal clk_rd, and the second register 34 samples the first data signal din at each falling edge of the second clock signal clk_rd. In this way, the first selector 36 can select the data corresponding to the optimal transmission phase from the sampled data based on the selection signal slt to output the second data signal dout. The aforementioned rate ratio of the two clocks can be externally communicated to the calculation circuit 32 via an indication signal, or can be calculated by the calculation circuit 32 based on the phase detection results output by the phase detector 31 twice. This embodiment of the present application does not impose specific limitations on this. The rising edge and falling edge of the clock signal can also be referred to as the positive edge and negative edge of the clock signal, respectively.

[0076] Optionally, the second output terminal of the calculation circuit 32 can be used to output a valid indication signal vld_out, and the third output terminal of the calculation circuit can be used to output a transmission indication signal bp. That is, the calculation circuit 32 can also output the valid indication signal vld_out and the transmission indication signal bp based on the phase indication signal and the second clock signal clk_rd. The valid indication signal vld_out is used to indicate valid data in the second data signal dout. The transmission indication signal bp is used to indicate whether to transmit the third data signal din'.

[0077] That is, when the bandwidth of the second clock signal clk_rd is redundant, the calculation circuit 32 can output the valid indication signal vld_out to indicate valid data in the second data signal dout through the valid indication signal vld_out. When the bandwidth of the first clock signal clk_wr is redundant, the calculation circuit 32 can output the transmission indication signal bp to instruct the write side to stop transmitting the third data signal din' through the transmission indication signal bp.

[0078] Furthermore, the input end of the fourth register 38 in FIG11 can also be used to receive the third data signal din', without being coupled to the output end of the third register 37. In this case, in the cross-clock domain data processing circuit, the fourth register 38 can be used to output the fourth sampling signal reg4 based on the third data signal din' and the inverted clock signal corresponding to the first clock signal clk_wr.

[0079] The cross-clock domain data processing circuit provided in the embodiment of the present application can select and transmit the third data signal din' at the rising and falling edges of the first clock signal clk_wr, respectively, through the third register 37, the fourth register 38, and the second selector 40. The data signal output by the second selector 40 is sampled by the first register 33 and the second register 34 at the rising and falling edges of the second clock signal clk_rd, respectively. The phase detector 31 and the calculation circuit 32 determine the selection signal indicating the optimal sampling phase, and the first selector 36 selects the data corresponding to the optimal sampling phase according to the selection signal to obtain the second data signal dout, thereby achieving near "zero latency" for cross-clock domain data processing, achieving extremely low latency performance, and thereby reducing cache and power consumption. In addition, the circuit can also be applied to situations where the frequency Fwr of the first clock signal clk_wr and the frequency Frd of the second clock signal clk_rd are reversed, thereby further improving the performance of the cross-clock domain data processing circuit.

[0080] Based on this, an embodiment of the present application further provides a chip, comprising: synchronous logic circuits for different clock domains, and any one of the cross-clock domain data processing circuits provided in the embodiments of the present application, wherein the cross-clock domain data processing circuit can be used to process a first data signal in a first clock domain into a second data signal in a second clock domain. Optionally, the chip may include, but is not limited to, an application-specific integrated circuit (ASIC), a system on chip (SOC), a programmable gate array (PGA), and a complex programmable logic device (CPLD).

[0081] In another aspect of the present application, an electronic device is provided, comprising: a packaging substrate, and a chip fixed to the packaging substrate, wherein the chip may be the chip provided above. Optionally, the electronic device may include, but is not limited to: a base station, an access point, a mobile phone, a tablet computer, a computer, a laptop computer, a video camera, a camera, a wearable device, an in-vehicle device (e.g., a car, a bicycle, an electric vehicle, an airplane, a ship, a train, a high-speed train, etc.), a virtual reality (VR) device, an augmented reality (AR) device, or an intelligent robot, etc.

[0082] In another aspect of the present application, a cross-clock domain data processing method is also provided, which can be applied to a cross-clock domain data processing circuit. The cross-clock domain data processing circuit includes: a phase detector, a calculation circuit, a first register, a second register, a first inverter, and a first selector. The method includes: the phase detector outputs a phase indication signal based on a first clock signal and a second clock signal, the phase indication signal being used to indicate the phase difference between the first clock signal and the second clock signal; the calculation circuit outputs a selection signal based on the phase indication signal and the second clock signal; the first register outputs a first sampling signal based on a first data signal and a second clock signal; the second register outputs a second sampling signal based on the first data signal din and an inverted clock signal of the second clock signal; and the first selector outputs a second data signal based on the first sampling signal and the second sampling signal under the control of the selection signal.

[0083] Optionally, the frequency of the second clock signal is greater than the frequency of the first clock signal. The method further includes: the calculation circuit outputting a valid indication signal, the valid indication signal being used to indicate valid data in the first data signal.

[0084] Furthermore, the cross-clock domain data processing circuit further includes: a third register, a fourth register, a second inverter, and a second selector. The method further includes: the third register outputting a third sampling signal based on the third data signal and the first clock signal; the fourth register outputting a fourth sampling signal based on the third sampling signal and an inverted clock signal of the first clock signal; and the second selector outputting the first data signal based on the third sampling signal and the fourth sampling signal.

[0085] Optionally, the frequency of the first clock signal is greater than the frequency of the second clock signal. The method further includes: the calculation circuit outputting a transmission indication signal, the transmission indication signal being used to indicate whether to transmit the third data signal.

[0086] In another aspect of the present application, another cross-clock domain data processing method is also provided, which can be applied to a cross-clock domain data processing circuit. The cross-clock domain data processing circuit includes: a phase detector, a first register of a calculation circuit, a second register, an inverter, and a selector. The method includes: the phase detector outputs a phase indication signal based on a first clock signal and a second clock signal, the phase indication signal being used to indicate the phase difference between the first clock signal and the second clock signal; the calculation circuit outputs a selection signal based on the phase indication signal and the first clock signal; the first register outputs a first sampling signal based on a first data signal and a first clock signal; the second register outputs a second sampling signal based on the first sampling signal and an inverted clock signal corresponding to the first clock signal; and the selector outputs a second data signal based on the first sampling signal and the second sampling signal under the control of the selection signal.

[0087] Optionally, the frequency of the first clock signal is greater than the frequency of the second clock signal. The method further includes: the calculation circuit outputting a transmission indication signal, the transmission indication signal being used to indicate whether to transmit the first data signal.

[0088] The detailed description of the cross-clock domain data processing circuit described above can be referenced in the corresponding embodiments of the chip, the electronic device, and the cross-clock domain data processing method, and the embodiments of the present application will not be repeated here. In addition, the solution of the embodiments of the present application can realize cross-clock domain data processing without reducing the transmission bandwidth, while reducing the latency during the data processing process, thereby reducing cache and power consumption.

[0089] In the several embodiments provided in this application, it should be understood that the disclosed chips, electronic devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0090] The units described as separate components may or may not be physically separate, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0091] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0092] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the part of the technical solution of the embodiment of the present application that contributes in essence or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a device (which can be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the method of each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk.

[0093] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A cross-clock domain data processing circuit, characterized in that: include: A phase detector, a calculation circuit, a first register, a second register, a first inverter and a first selector; The two input terminals of the phase detector are respectively used to receive a first clock signal and a second clock signal, the output terminal of the phase detector is coupled to the first input terminal of the calculation circuit, the second input terminal of the calculation circuit is used to receive the second clock signal, and the first output terminal of the calculation circuit is used to output a selection signal; The input end of the first register and the input end of the second register are both used to receive a first data signal, and the clock end of the second register is coupled to the clock end of the first register through the first inverter and is used to receive the second clock signal; Two input terminals of the first selector are respectively coupled to the output terminal of the first register and the output terminal of the second register, the control terminal of the first selector is used to receive the selection signal, and the output terminal of the first selector is used to output a second data signal.

2. The cross-clock domain data processing circuit according to claim 1, characterized in that: The phase detector is used to output a phase indication signal according to the first clock signal and the second clock signal, wherein the phase indication signal is used to indicate a phase difference between the first clock signal and the second clock signal; The calculation circuit is used to output a selection signal according to the phase indication signal and the second clock signal, wherein the phase indication signal is used to determine the rising edge and the falling edge of each clock cycle in the second clock signal, and the selection signal is used to indicate the edge of the rising edge and the falling edge of each clock cycle that has a longer sampling time for the same data in the first data signal; The first register is used to output a first sampling signal according to the first data signal and the second clock signal; The second register is used to output a second sampling signal according to the first data signal and an inverted clock signal of the second clock signal; The first selector is used to select sampling data corresponding to an edge with a longer sampling duration from the first sampling signal and the second sampling signal in each clock cycle according to the selection signal to obtain the second data signal.

3. The cross-clock domain data processing circuit according to claim 1 or 2, characterized in that: The frequency of the second clock signal is greater than the frequency of the first clock signal; The second output terminal of the calculation circuit is used to output a valid indication signal, and the valid indication signal is used to indicate valid data in the second data signal.

4. The cross-clock domain data processing circuit according to any one of claims 1 to 3, characterized in that: Also includes: a third register, a fourth register, a second inverter, and a second selector; The input end of the third register is used to receive a third data signal, the input end of the fourth register is coupled to the output end of the third register, and the clock end of the fourth register is coupled to the clock end of the third register through the second inverter and is used to receive the first clock signal; Two input terminals of the second selector are coupled to an output terminal of the third register and an output terminal of the fourth register respectively, and an output terminal of the second selector is used to output the first data signal.

5. The cross-clock domain data processing circuit according to claim 4, characterized in that: The third register is used to output a third sampling signal according to the third data signal and the first clock signal; The fourth register is used to output a fourth sampling signal according to the third sampling signal and an inverted clock signal of the first clock signal; The second selector is used to output the first data signal according to the third sampling signal and the fourth sampling signal.

6. The cross-clock domain data processing circuit according to claim 4 or 5, characterized in that: The frequency of the first clock signal is greater than the frequency of the second clock signal; The third output terminal of the calculation circuit is used to output a transmission indication signal, and the transmission indication signal is used to indicate whether to transmit the third data signal.

7. A cross-clock domain data processing circuit, characterized in that: include: A phase detector, a calculation circuit, a first register, a second register, an inverter and a selector; The two input terminals of the phase detector are used to receive a first clock signal and a second clock signal respectively, the output terminal of the phase detector is coupled to the first input terminal of the calculation circuit, the second input terminal of the calculation circuit is used to receive the first clock signal, and the first output terminal of the calculation circuit is used to output a selection signal; The input end of the first register is used to receive a first data signal, the input end of the second register is coupled to the output end of the first register, and the clock end of the second register is coupled to the clock end of the first register through the inverter and is used to receive the first clock signal; The two input terminals of the selector are respectively coupled to the output terminal of the first register and the output terminal of the second register, the control terminal of the selector is used to receive the selection signal, and the output terminal of the selector is used to output a second data signal.

8. The circuit according to claim 7, characterized in that The phase detector is used to output a phase indication signal according to the first clock signal and the second clock signal, wherein the phase indication signal is used to indicate a phase difference between the first clock signal and the second clock signal; The calculation circuit is used to output a selection signal according to the phase indication signal and the first clock signal, wherein the phase indication signal is used to determine the rising edge and the falling edge of each clock cycle in the first clock signal, and the selection signal is used to indicate the rising edge and the falling edge of each clock cycle that have a longer sampling time for the same data in the first data signal; The first register is used to output a first sampling signal according to the first data signal and the first clock signal; The second register is used to output a second sampling signal according to the first sampling signal and an inverted clock signal corresponding to the first clock signal; The selector is used to select sampling data corresponding to an edge with a longer sampling duration from the first sampling signal and the second sampling signal in each clock cycle according to the selection signal to obtain the second data signal.

9. The circuit according to claim 7 or 8, characterized in that The frequency of the first clock signal is greater than the frequency of the second clock signal; The second output terminal of the calculation circuit is used to output a transmission indication signal, and the transmission indication signal is used to indicate whether to transmit the first data signal.

10. A method for processing data across clock domains, characterized in that: Applied to a cross-clock domain data processing circuit, the cross-clock domain data processing circuit comprises: a phase detector, a calculation circuit, a first register, a second register, a first inverter and a first selector; the method comprises: The phase detector outputs a phase indication signal according to the first clock signal and the second clock signal, wherein the phase indication signal is used to indicate a phase difference between the first clock signal and the second clock signal; The calculation circuit outputs a selection signal according to the phase indication signal and the second clock signal; The first register outputs a first sampling signal according to the first data signal and the second clock signal, the phase indication signal is used to determine the rising edge and the falling edge of each clock cycle in the second clock signal, and the selection signal is used to indicate the rising edge and the falling edge of each clock cycle to sample the same data in the first data signal with a longer sampling time; The second register outputs the second sampling signal according to the first data signal and an inverted clock signal of the second clock signal; The first selector selects sampling data corresponding to an edge with a longer sampling duration from the first sampling signal and the second sampling signal in each clock cycle according to the selection signal to obtain the second data signal.

11. The method according to claim 10, characterized in that The frequency of the second clock signal is greater than the frequency of the first clock signal, and the method further includes: The calculation circuit outputs a valid indication signal, where the valid indication signal is used to indicate valid data in the second data signal.

12. The method according to claim 10 or 11, characterized in that: The cross-clock domain data processing circuit further includes: a third register, a fourth register, a second inverter and a second selector; the method further includes: The third register outputs a third sampling signal according to a third data signal and the first clock signal; The fourth register outputs a fourth sampling signal according to the third sampling signal and an inverted clock signal of the first clock signal; The second selector outputs the first data signal according to the third sampling signal and the fourth sampling signal.

13. The method according to claim 12, characterized in that The frequency of the first clock signal is greater than the frequency of the second clock signal, and the method further includes: The calculation circuit outputs a transmission indication signal, where the transmission indication signal is used to indicate whether to transmit the third data signal.

14. A method for processing data across clock domains, characterized in that: Applied to a cross-clock domain data processing circuit, the cross-clock domain data processing circuit comprises: a phase detector, a first register of a calculation circuit, a second register, an inverter and a selector; the method comprises: The phase detector outputs a phase indication signal according to the first clock signal and the second clock signal, wherein the phase indication signal is used to indicate a phase difference between the first clock signal and the second clock signal; The calculation circuit outputs a selection signal according to the phase indication signal and the first clock signal, wherein the phase indication signal is used to determine the rising edge and the falling edge of each clock cycle in the first clock signal, and the selection signal is used to indicate the edge of the rising edge and the falling edge of each clock cycle that has a longer sampling time for the same data in the first data signal; The first register outputs the first sampling signal according to the first data signal and the first clock signal; The second register is based on the first sampling signal and the inverted clock signal corresponding to the first clock signal. outputting a second sampling signal; The selector selects sampling data corresponding to an edge with a longer sampling duration from the first sampling signal and the second sampling signal in each clock cycle according to the selection signal to obtain the second data signal.

15. The method according to claim 14, characterized in that The frequency of the first clock signal is greater than the frequency of the second clock signal, and the method further includes: The calculation circuit outputs a transmission indication signal, where the transmission indication signal is used to indicate whether to transmit the first data signal.

16. A chip, characterized in that: The chip comprises: synchronous logic circuits of different clock domains, and the cross-clock domain data processing circuit according to any one of claims 1-9.

17. An electronic device, characterized in that: The electronic device comprises: a packaging substrate, and the chip according to claim 16 fixed on the packaging substrate.

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