Semiconductor device

Abstract

Provided is a transistor capable of achieving miniaturization. Provided is a transistor in which parasitic capacitance is reduced. The semiconductor device includes a transistor and a first insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a second insulating layer. The first insulating layer is on the first conductive layer and includes a first opening. The second conductive layer is located on the first insulating layer. The semiconductor layer has a portion in contact with the first conductive layer, a portion in contact with the second conductive layer, and a portion in contact with a side surface of the first insulating layer inside the first opening. The second insulating layer covers the semiconductor layer in the first opening. The third conductive layer covers the second insulating layer in the first opening. The first conductive layer has a portion in the first opening that does not overlap the third conductive layer and the semiconductor layer.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the same. Another embodiment of the present invention relates to a transistor and a method for manufacturing the same. Another embodiment of the present invention relates to a display device including a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the aforementioned technical fields. Examples of the technical fields of one embodiment of the present invention disclosed in this specification and other related disclosures include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, and methods for driving or manufacturing these devices. A semiconductor device refers to any device that can operate by utilizing semiconductor characteristics. Background Art

[0003] There is a demand for miniaturization of transistors. For example, in display devices, the smaller the area occupied by the transistors used in a pixel, the smaller the pixel size can be, thus achieving higher definition. Furthermore, since the number of transistors that can be arranged per unit area can be increased—that is, a large number of transistors can be arranged within a pixel without increasing the pixel size—it is possible to add correction functions to the pixel.

[0004] In recent years, the advancement of high-definition display panels has been progressing. In addition to tablets, smartphones, and wristwatches, devices requiring high-definition display panels, such as those for virtual reality (VR) and augmented reality (AR), have also been actively developed. High-definition display panels primarily use light-emitting elements such as organic EL (electroluminescence) elements and light-emitting diodes (LEDs).

[0005] Patent Document 1 discloses a high-definition display device using an organic EL device (also referred to as an organic EL element).

[0006] [Prior technical literature]

[0007] [Patent Document]

[0008] [Patent Document 1] International Patent Application Publication No. 2016 / 038508 Summary of the Invention

[0009] Technical problem to be solved by the invention

[0010] One of the purposes of one embodiment of the present invention is to provide a transistor that can be miniaturized. One of the purposes of one embodiment of the present invention is to provide a transistor with good electrical characteristics. Another purpose of one embodiment of the present invention is to provide a transistor that can flow a large current. Another purpose of one embodiment of the present invention is to provide a transistor with an extremely small channel length. Another purpose of one embodiment of the present invention is to provide a transistor with reduced parasitic capacitance. Another purpose of one embodiment of the present invention is to provide a transistor with a small footprint. Another purpose of one embodiment of the present invention is to provide a display device that can easily achieve high definition. Another purpose of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, and display device.

[0011] One object of one embodiment of the present invention is to provide a semiconductor device, a display device, a storage device, or an electronic device having a novel structure. One object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0012] Note that the inclusion of these objectives does not preclude the existence of other objectives. Note that one embodiment of the present invention does not necessarily achieve all of the above objectives. Furthermore, objectives other than those listed above may be extracted from the description of the specification, drawings, claims, etc.

[0013] Means of solving technical problems

[0014] One embodiment of the present invention is a semiconductor device including a transistor and a first insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a second insulating layer. The first insulating layer is located on the first conductive layer and includes a first opening. The second conductive layer is located on the first insulating layer. The semiconductor layer has a portion in contact with the first conductive layer, a portion in contact with the second conductive layer, and a portion in contact with a side surface of the first insulating layer inside the first opening. The second insulating layer covers the semiconductor layer within the first opening. The third conductive layer covers the second insulating layer within the first opening. In addition, the semiconductor device has a portion in a region overlapping with the first opening where the first conductive layer and the third conductive layer do not overlap, and the first conductive layer and the semiconductor layer do not overlap.

[0015] In addition, another embodiment of the present invention is a semiconductor device including a transistor, a base insulating layer, and a first insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a second insulating layer. The first insulating layer is located on the first conductive layer and includes a first opening. The first conductive layer is located on the base insulating layer and includes a second opening. The second opening is located inside the first opening when viewed from above. The second conductive layer is located on the first insulating layer. The semiconductor layer has a portion in contact with the first conductive layer, a portion in contact with the second conductive layer, and a portion in contact with a side surface of the first insulating layer inside the first opening, and includes a third opening located inside the first opening when viewed from above. The second insulating layer has a portion covering the semiconductor layer within the first opening and a portion in contact with the base insulating layer at a position overlapping the second opening and the third opening. The third conductive layer covers the second insulating layer within the first opening.

[0016] In the semiconductor device, the second opening is preferably smaller than the third opening and located inside the third opening when viewed from above. Furthermore, the second insulating layer is preferably in contact with the top surface of the first conductive layer and the side surface of the first conductive layer in the second opening.

[0017] In the semiconductor device, the third opening is preferably smaller than the second opening and located inside the second opening when viewed from above. Furthermore, the semiconductor layer is preferably in contact with the top surface of the first conductive layer, the side surface of the first conductive layer in the second opening, and the base insulating layer.

[0018] One embodiment of the present invention is a semiconductor device including a transistor and a first insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a second insulating layer. The first insulating layer is located on the first conductive layer and includes a first opening. The second conductive layer is located on the first insulating layer. The semiconductor layer has a portion in contact with the first conductive layer, a portion in contact with the second conductive layer, and a portion in contact with a side surface of the first insulating layer inside the first opening. The second insulating layer covers the semiconductor layer within the first opening. The third conductive layer covers the second insulating layer within the first opening and includes a second opening located inside the first opening when viewed from above.

[0019] In the above semiconductor device, a third insulating layer is preferably included on the second conductive layer. Furthermore, the third conductive layer preferably has a portion overlapping the second conductive layer via the third insulating layer. In this case, a fourth conductive layer is preferably included on the third insulating layer. Furthermore, the fourth conductive layer is preferably electrically connected to the third conductive layer and serves as wiring.

[0020] Furthermore, in any of the above semiconductor devices, the angle formed by the side surface of the first insulating layer in the first opening and the bottom surface of the first insulating layer is preferably not less than 75 degrees and not more than 90 degrees.

[0021] In any of the above semiconductor devices, it is preferred that the semiconductor layer comprises a metal oxide, the first insulating layer comprises a first insulating film, a second insulating film, and a third insulating film stacked in this order, the first insulating film and the third insulating film comprise a nitride, and the second insulating film comprises an oxide. In this case, it is preferred that the first insulating film and the third insulating film comprise silicon nitride, and the second insulating film comprise silicon oxide.

[0022] Effects of the Invention

[0023] According to one embodiment of the present invention, a transistor capable of being miniaturized can be provided. In addition, according to one embodiment of the present invention, a transistor with excellent electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a transistor capable of flowing a large current can be provided. In addition, according to one embodiment of the present invention, a transistor with an extremely small channel length can be provided. In addition, according to one embodiment of the present invention, a transistor with reduced parasitic capacitance can be provided. In addition, according to one embodiment of the present invention, a transistor with a small footprint can be provided. In addition, according to one embodiment of the present invention, a display device that can easily achieve high definition can be provided. In addition, according to one embodiment of the present invention, a transistor, a semiconductor device, and a display device with high reliability can be provided.

[0024] According to one embodiment of the present invention, a semiconductor device, a display device, a storage device, or an electronic device having a novel structure can be provided. According to one embodiment of the present invention, at least one of the problems of the prior art can be alleviated.

[0025] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of the above effects. Furthermore, effects other than the above can be extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1A and Figure 1B This is an example of the structure of a semiconductor device.

[0027] Figures 2A to 2C This is an example of the structure of a semiconductor device.

[0028] Figure 3A and Figure 3B This is an example of the structure of a semiconductor device.

[0029] Figure 4A and Figure 4B This is an example of the structure of a semiconductor device.

[0030] Figures 5A to 5C This is an example of the structure of a semiconductor device.

[0031] Figure 6This is an example of the structure of a semiconductor device.

[0032] 7A to 7C This is an example of the structure of a semiconductor device.

[0033] Figures 8A to 8D A diagram illustrating a method for manufacturing a semiconductor device.

[0034] Figure 9A and Figure 9B This is an example of the structure of a semiconductor device.

[0035] 10A to 10C This is an example of the structure of a semiconductor device.

[0036] Figure 11A and Figure 11B This is an example of the structure of a semiconductor device.

[0037] Figure 12 This is an example of the structure of a semiconductor device.

[0038] 13A to 13C This is an example of the structure of a semiconductor device.

[0039] Figure 14A and Figure 14B This is an example of the structure of a semiconductor device.

[0040] Figure 15 This is an example of the structure of a display device.

[0041] Figure 16 This is an example of the structure of a display device.

[0042] Figure 17 This is an example of the structure of a display device.

[0043] Figure 18 This is an example of the structure of a display device.

[0044] Figure 19 This is an example of the structure of a display device.

[0045] 20A to 20F A diagram illustrating a method for manufacturing a display device.

[0046] 21A to 21D This is an example of the structure of an electronic device.

[0047] Figures 22A to 22F This is an example of the structure of an electronic device.

[0048] Figures 23A to 23G This is an example of the structure of an electronic device. DETAILED DESCRIPTION

[0049] The following describes the embodiments with reference to the accompanying drawings. However, those skilled in the art will readily appreciate that the embodiments may be implemented in a variety of different forms, and their methods and details may be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the embodiments described below.

[0050] Note that in the structures of the invention described below, the same reference numerals are used in common across different drawings to represent the same parts or parts having the same function, and their repeated descriptions are omitted. In addition, when parts having the same function are represented, the same hatching is sometimes used without a special reference numeral.

[0051] Note that in the drawings described in this specification, the sizes of components, layer thicknesses, and regions may be exaggerated for clarity, and therefore, the present invention is not limited to the sizes shown in the drawings.

[0052] The ordinal numbers such as “first” and “second” used in this specification and the like are provided to avoid confusion among constituent elements and are not intended to limit the number of constituent elements.

[0053] A transistor is a type of semiconductor element that can amplify current or voltage, control conduction or non-conduction, etc. Transistors in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).

[0054] In addition, the functions of "source" and "drain" may be interchanged when using transistors with different polarities or when the direction of current changes during circuit operation. Therefore, in this specification, "source" and "drain" may be used interchangeably.

[0055] Note that in this specification, etc., the top surface shape of a component refers to the outline shape of the component when viewed from a planar perspective. Furthermore, "viewed from a planar perspective" refers to the situation when viewed from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0056] Note that in this specification, "top surface shapes are generally consistent" means that at least a portion of the edges of each layer in the stack overlap. This includes, for example, cases where the upper and lower layers are processed using the same mask pattern, or a portion of the same mask pattern. However, strictly speaking, there are cases where the edges do not overlap, such as when the upper layer is located inside or outside the lower layer. In these cases, "top surface shapes are generally consistent."

[0057] Note that in the following description, directions such as "upper" and "lower" are generally used in accordance with the directions in the accompanying drawings. However, for the sake of simplicity, the directions indicated by "upper" or "lower" in this specification may not always correspond to the directions in the accompanying drawings. For example, when describing the stacking order (or formation order) of a laminate, even if the surface on which the laminate is disposed (a surface to be formed, a supporting surface, an adhesive surface, a flat surface, etc.) is located on the upper side of the laminate in the accompanying drawings, it may be stated that the surface to be formed is located on the lower side, or that the laminate is located on the upper side.

[0058] In this specification, "film" and "layer" may be used interchangeably. For example, "insulating layer" and "insulating film" may be used interchangeably.

[0059] In this specification, etc., a display panel, which is one form of a display device, refers to a panel that can display (output) images, etc. on a display surface. Therefore, a display panel is one form of an output device.

[0060] In addition, in this specification, etc., a structure in which a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) is installed on the substrate of a display panel, or a structure in which an IC is directly mounted on the substrate using a COG (Chip On Glass) method, etc. is sometimes referred to as a display panel module or display module, or simply as a display panel, etc.

[0061] Note that in this specification and other contexts, a touch panel, one form of a display device, has the following functions: displaying images, etc. on a display surface; and functioning as a touch sensor to detect when a detected object, such as a finger or stylus, touches, presses, or approaches the display surface. Therefore, a touch panel is one form of input / output device.

[0062] A touch panel may also be referred to as a display panel (or display device) with a touch sensor, or a display panel (or display device) with a touch sensor function. A touch panel may include a display panel and a touch sensor panel. Alternatively, a touch sensor function may be provided within or on the surface of a display panel.

[0063] In this specification and other documents, a structure in which a connector or an IC is mounted on a touch panel substrate may be referred to as a touch panel module, a display module, or simply as a touch panel.

[0064] (Implementation Method 1)

[0065] In this embodiment, a semiconductor device according to one embodiment of the present invention is described. Hereinafter, a structure example and a manufacturing method example of a transistor are described as an example of a semiconductor device.

[0066] A transistor according to one embodiment of the present invention includes a semiconductor layer, a gate insulating layer, a gate electrode, a first electrode, and a second electrode. The first electrode serves as one of a source electrode and a drain electrode, and the second electrode serves as the other.

[0067] The second electrode is disposed above the first electrode. An insulating layer serving as a spacer is disposed between the first and second electrodes. The spacer has an opening that reaches the first electrode, and the semiconductor layer is disposed so as to contact the first electrode, the second electrode, and the sidewalls (also referred to as side surfaces) within the opening of the insulating layer. Furthermore, a gate insulating layer and a gate electrode are disposed so as to cover the semiconductor layer.

[0068] The source and drain electrodes of a transistor having the above structure are located at different heights, so the current flowing through the semiconductor flows in the height direction. In other words, the channel length direction can have a component in the height direction (vertical direction), so the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor: vertical field effect transistor), a vertical transistor, a vertical channel transistor, etc. Because the transistor can overlap two or more of the source electrode, semiconductor layer, and drain electrode, the occupied area can be greatly reduced compared to so-called planar transistors (also called lateral transistors, LFETs (Lateral FETs), etc.) in which the semiconductor layer is arranged on a plane.

[0069] By using these vertical transistors in display devices, the area occupied by the transistors can be reduced compared to conventional display devices using lateral transistors, thereby enabling smaller pixels, more multifunctional pixels, and an increase in aperture ratio. This can result in displays with higher definition, higher reliability, and lower power consumption than conventional display devices.

[0070] Here, smaller capacitance between the source electrode and the gate electrode, or between the drain electrode and the gate electrode, is preferred because it allows for faster switching of the transistor. Therefore, attention was focused on the capacitance between the gate electrode and the first electrode at the bottom of the opening in the insulating layer serving as a spacer. One embodiment of the present invention employs a structure in which a region where the gate electrode and the first electrode do not overlap is provided at the bottom of the opening in the insulating layer.

[0071] Furthermore, when a portion of the semiconductor layer located at the bottom of the opening in the insulating layer is used as a source region or a drain region, capacitance may be formed not only between the first electrode and the gate electrode, but also between the semiconductor layer and the gate electrode. Therefore, a region is provided at the bottom of the opening in the insulating layer where the gate electrode and the semiconductor layer do not overlap.

[0072] More specifically, for example, the first electrode includes a second opening located inside the opening (first opening) of the insulating layer serving as a spacer when viewed from a planar surface. Furthermore, the semiconductor layer includes a third opening located inside the first opening when viewed from a planar surface. Furthermore, the second opening and the third opening have overlapping portions. Thus, within the first opening, the portion where the second opening and the third opening overlap becomes a portion where the gate electrode, the first electrode, and the semiconductor layer do not overlap. Therefore, compared to a case where the second opening and the third opening are not provided, the capacitance between the gate electrode and the first electrode can be reduced.

[0073] Hereinafter, a more specific configuration example will be described with reference to the drawings.

[0074] [Structure example]

[0075] Figure 1A and Figure 1B FIG. 1 shows a perspective schematic diagram of the transistor 10. Figure 1A and Figure 1B In FIG, arrows are shown to indicate directions X, Y, and Z. Figure 1A is a perspective view including a cross section of the transistor 10 cut along the XZ plane, Figure 1B It is a perspective view including a cross section of the transistor 10 taken along the YZ plane.

[0076] in addition, Figure 2A shows a plan view of transistor 10, Figure 2B and Figure 2C Shown are the corresponding Figure 2A Schematic diagram of the cross section of the cut lines A1-A2 and B1-B2 in FIG. Figure 2A In the figure, some components (insulating layer, etc.) are omitted.

[0077] Transistor 10 is provided on an insulating layer 11, which is provided on a substrate (not shown). Insulating layer 11 serves as a base insulating layer. Transistor 10 includes a semiconductor layer 21, an insulating layer 22, a portion of which serves as a gate insulating layer, a conductive layer 23, a portion of which serves as a gate electrode, a conductive layer 24, a portion of which serves as one of a source electrode and a drain electrode, and a conductive layer 25, a portion of which serves as the other of the source electrode and the drain electrode.

[0078] Conductive layer 24 is provided on insulating layer 11, and insulating layer 41 is provided on conductive layer 24. Conductive layer 25 is provided on insulating layer 41. Insulating layer 41 includes opening 20a that reaches conductive layer 24. Conductive layer 24 includes opening 20b. Opening 20b is located inside opening 20a when viewed from above.

[0079] The semiconductor layer 21 has a portion in contact with the top surface of the conductive layer 25, a portion in contact with the side surface of the conductive layer 25, a portion in contact with the side surface (also referred to as the inner wall or sidewall) of the insulating layer 41 in the opening 20a, and a portion in contact with the top surface of the conductive layer 24. The semiconductor layer 21 includes an opening 20c. When viewed from a planar perspective, the opening 20c is located inside the opening 20a. Here, the top surface shape of the opening 20b is substantially the same as the top surface shape of the opening 20c.

[0080] The insulating layer 22 is provided so as to cover the insulating layer 41, the conductive layer 25, the semiconductor layer 21, the conductive layer 24, and the insulating layer 11. The portion of the insulating layer 22 located inside the opening 20a is provided along the top surface of the semiconductor layer 21. In addition, the portion of the insulating layer 22 located inside the openings 20c and 20b is in contact with the side surfaces (also referred to as inner walls or sidewalls) of the conductive layer 24 and the top surface of the insulating layer 11.

[0081] The conductive layer 23 is provided so as to cover the insulating layer 22. In this case, the conductive layer 24 and the semiconductor layer 21 include openings 20b and 20c, respectively, located inside the opening 20a. Therefore, a portion of the conductive layer 23 that does not overlap with the conductive layer 24 and the semiconductor layer 21 can be provided inside the opening 20a. This reduces the capacitance (also called parasitic capacitance) between the conductive layer 23 and the conductive layer 24.

[0082] Since the channel length of the transistor 10 can be precisely controlled by the thickness of the insulating layer 41, the deviation of the channel length can be made extremely small compared to a planar transistor. Furthermore, by thinning the insulating layer 41, a transistor with an extremely short channel length can be manufactured. For example, a transistor with a channel length of less than 2 μm, less than 1 μm, less than 500 nm, less than 300 nm, less than 200 nm, less than 100 nm, less than 50 nm, less than 30 nm or less than 20 nm and greater than 5 nm, greater than 7 nm or greater than 10 nm can be manufactured. Thus, a transistor with an extremely small channel length that cannot be achieved by the existing exposure device for mass production of flat panel displays (for example, a minimum line width of about 2 μm or about 1.5 μm) can be realized. In addition, a transistor with a channel length of less than 10 nm can be realized without using the very expensive exposure device used in the most advanced LSI technology.

[0083] The semiconductor layer 21 can be made of various semiconductor materials, with oxide semiconductors including metal oxides being particularly preferred. By using an oxide semiconductor formed under appropriate conditions, a transistor having both high on-state current and extremely low off-state current can be realized at low cost. Below, unless otherwise specified, a preferred structural example is described for the case where an oxide semiconductor is used as the semiconductor layer 21.

[0084] The top surfaces of the conductive layers 24 and 25 are in contact with the semiconductor layer 21. Therefore, when an oxide semiconductor is used for the semiconductor layer 21, there is a concern that the exposed surfaces of the conductive layers 24 and 25 may be oxidized due to the deposition process of the semiconductor film that becomes the semiconductor layer 21 or the influence of subsequent heating, thereby forming an insulating oxide film between the conductive layers 24 and 25 and increasing the contact resistance. Therefore, it is preferable to use an oxide conductor containing a conductive oxide for at least the uppermost portions of the conductive layers 24 and 25. This can prevent an increase in contact resistance caused by surface oxidation of the conductive layers 24 and 25. The conductive layers 24 and 25 may also be referred to as oxide layers, metal oxide layers, or oxide conductor layers.

[0085] A portion of conductive layer 24 can be used as either a source wiring or a drain wiring. Alternatively, a portion of conductive layer 25 can be used as the other of the source wiring and the drain wiring. In this manner, when one or both of conductive layer 24 and conductive layer 25 are used as wiring, the resistance is preferably low. To this end, it is preferred to use a material having a higher conductivity than an oxide conductor, such as a metal, alloy, or nitride thereof. In particular, it is preferred that one or both of conductive layer 24 and conductive layer 25 have a stacked structure comprising layers of such a highly conductive material, with at least the uppermost portion thereof being made of the aforementioned oxide conductor.

[0086] Transistor 10 is provided at the intersection of a conductive layer 23 serving as a gate wiring and a conductive layer 24 serving as a source wiring or a drain wiring. However, in one embodiment of the present invention, since the bottom of opening 20a includes a portion where conductive layer 23, conductive layer 24, and semiconductor layer 21 do not overlap, parasitic capacitance is significantly reduced compared to a case where this portion is not provided (e.g., a case where opening 20b or opening 20c is not provided). Since the parasitic capacitance between the gate wiring and the source wiring or the drain wiring is small, when used in a display device, for example, it can achieve effects such as increasing the frame rate and improving the resolution.

[0087] The insulating layer 41 is used as an interlayer insulating layer (spacer) for insulating the conductive layer 24 from the conductive layer 25. Here, the insulating layer 41 is shown as a laminated film of the insulating layer 41a, the insulating layer 41b, and the insulating layer 41c.

[0088] The semiconductor layer 21 is provided in contact with the inner wall of the opening 20a of the insulating layer 41b. An oxide insulating film is preferably used for the insulating layer 41b. In particular, an oxide insulating film that releases oxygen upon heating is preferably used. In addition, it is preferable to adopt a structure in which the insulating layer 41b is sandwiched between the insulating layer 41a and the insulating layer 41c, which have barrier properties to oxygen. In this way, the oxygen contained in the insulating layer 41b can be confined in the area surrounded by the insulating layer 41a, the insulating layer 41c, and the semiconductor layer 21, and the oxygen in the insulating layer 41b can be prevented from being released and reduced during the process, so that oxygen can be supplied to the semiconductor layer 21 more efficiently.

[0089] The portion of the semiconductor layer 21 in contact with the insulating layer 41b is a region with reduced oxygen vacancies and can be considered an i-type region. On the other hand, the portion not in contact with the insulating layer 41b is preferably an n-type region containing a large number of carriers. In other words, the portion of the semiconductor layer 21 in contact with the insulating layer 41b can be called a channel formation region, and the region outside of it can be called a low-resistance region (also called a source region or a drain region).

[0090] Reference Figure 3A and Figure 3B Describe the channel length, channel width, etc. Figure 3A Shown with Figure 2B Same cross-sectional diagram.

[0091] like Figure 3AAs shown, the channel length L of the transistor 10 can be said to be the length of the portion of the semiconductor layer 21 that contacts the conductive layer 24 and the portion that contacts the conductive layer 25, which is the shortest distance between them. When the angle (θ) of the sidewall of the opening 20a of the insulating layer 41 is 90 degrees, the channel length L is equal to the thickness of the insulating layer 41. By making θ less than 90 degrees (or greater than 90 degrees), the channel length L can be made greater than the thickness of the insulating layer 41. Note that although the channel region of the semiconductor layer 21 is the portion in contact with the insulating layer 41 in this example, it can also be the portion in contact with the insulating layer 41b.

[0092] In addition, the diameter of the opening 20a is R1, the diameter of the opening 20b is R2, and the diameter of the opening 20c is R3. Figure 3A As shown, the diameter of the opening of each layer can be the diameter of the lower end of the layer. Figure 3A In the embodiment, the ends of the conductive layer 24 and the semiconductor layer 21 are tapered, so the diameter R3 of the opening 20c is larger than the diameter R2 of the opening 20b. Note that the diameter of the opening of a layer is not limited to the diameter at the lower end of the layer; the diameter at the upper end or the center of the layer, or the average value or the median value may also be used.

[0093] Because openings 20b and 20c are located inside opening 20a, their diameters R2 and R3 are smaller than diameter R1 of opening 20a. The larger R2 and R3 are, the larger the area of conductive layer 23 that does not overlap with conductive layer 24 and semiconductor layer 21, thereby enhancing the effect of reducing parasitic capacitance. For example, diameters R2 and R3 of openings 20b and 20c are each independently 50% or greater, preferably 60% or greater, more preferably 70% or greater, even more preferably 80% or greater, and even more preferably 90% or greater, of diameter R1 of opening 20a, and less than 100%.

[0094] The channel width W of the transistor 10 depends on the shape of the opening 20 a . Figure 3B From the Z direction, along Figure 3A A plan view of the cross section when the cutting line C1-C2 at the height where the insulating layer 41b is provided is cut. Here, the case where the shape of the opening 20a when viewed from a plane is circular is shown. When the outline of the opening 20a is a circle with a diameter R, the channel width W can be regarded as the circumference of the opening 20a (i.e., W=π×R). Here, when the angle θ of the side wall of the opening 20a of the insulating layer 41b is staggered from 90 degrees, the circumference of the opening 20a varies according to the height. In this case, the circumference of the height (here, the lower end) where the diameter of the opening 20a is the smallest can be regarded as the channel width W. In addition, the circumference of the height of the upper end of the opening 20a can also be regarded as the channel width W.

[0095] The shape of the opening 20a when viewed from a plane can typically be circular. Note that the shape of the opening 20a is not limited to a circle and can also be various shapes. For example, in addition to a circle, it can also be an ellipse, a quadrilateral with rounded corners, etc. In addition, it can also be a regular polygon such as an equilateral triangle, a square, a regular pentagon, or a polygon other than a regular polygon. In addition, when the opening 20a is a concave polygon such as a star-shaped polygon, in which at least one internal angle exceeds 180 degrees, the channel width can be increased. In addition, an ellipse, a polygon with rounded corners, a closed curve combining a straight line and a curve, etc. can also be used.

[0096] The shape of opening 20a is not limited; it can be any shape as long as opening 20b and opening 20c are located inside opening 20a. However, when the shapes of openings 20b and 20c are similar to or close to the shape of opening 20a, the difference in area between opening 20a and openings 20b or 20c can be reduced, and as a result, the area of opening 20a itself can be reduced, which is preferred.

[0097] Since the semiconductor layer 21 and the insulating layer 22 are formed along the inner wall of the opening 20a of the insulating layer 41b, the thickness of this part is sometimes thinned depending on the deposition method. For example, in deposition methods such as sputtering or plasma CVD, the thickness of the film deposited on a surface inclined or perpendicular to the substrate surface tends to be thinner than the thickness of the film deposited on a surface parallel to the substrate surface. On the other hand, when a deposition method such as atomic layer deposition (ALD) or thermal CVD is used, a film of uniform thickness can be deposited regardless of the angle of the formed surface. For example, when the angle θ of the side wall of the opening 20a of the insulating layer 41b is greater than 75 degrees, greater than 80 degrees, or greater than 85 degrees, it is preferable to form the semiconductor layer 21 and the insulating layer 22 using the ALD method.

[0098] [Components]

[0099] <Substrate>

[0100] As a substrate for forming a transistor, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used. Examples of insulator substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Furthermore, examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or gallium nitride. Furthermore, examples include semiconductor substrates having an insulator region within the above-mentioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductor substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Furthermore, examples include insulator substrates provided with a conductive layer or semiconductor layer, semiconductor substrates provided with a conductive layer or insulating layer, and conductor substrates provided with a semiconductor layer or insulating layer. Alternatively, substrates having elements provided on these substrates can be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element (including a transistor), a light-emitting element, and a memory element.

[0101] <Semiconductor Layer>

[0102] The semiconductor layer 21 preferably includes a metal oxide (oxide semiconductor).

[0103] As metal oxides that can be used for the semiconductor layer 21, for example, In oxide, Ga oxide and Zn oxide can be mentioned. The metal oxide preferably contains at least In or Zn. In addition, the metal oxide preferably contains two or three selected from In, element M and Zn. Note that element M is a metal element or semi-metal element with a high bond energy with oxygen, for example, a metal element or semi-metal element with a higher bond energy with oxygen than In. As element M, specifically Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge and Sb can be mentioned. The element M contained in the metal oxide is preferably any one or more of the above elements, and is particularly preferably one or more selected from Al, Ga, Y and Sn, among which Ga is more preferred. Note that the metal oxide containing In, M and Zn is sometimes referred to as In-M-Zn oxide below. Note that in this specification and the like, metal elements and semi-metal elements may be collectively referred to as "metal elements", and the "metal elements" described in this specification and the like may include semi-metal elements.

[0104] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably greater than or equal to the atomic ratio of M. For example, the atomic ratio of the metal elements in such an In-M-Zn oxide includes In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, or compositions close thereto. The close composition range includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of In in the metal oxide, the on-state current and field-effect mobility of the transistor can be improved.

[0105] The atomic ratio of In in the In-M-Zn oxide may be smaller than the atomic ratio of the element M. For example, the atomic ratio of the metal elements in such an In-M-Zn oxide includes In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, or compositions thereabouts. Increasing the atomic ratio of M in the metal oxide can suppress the formation of oxygen vacancies.

[0106] The semiconductor layer 21 can be made of, for example, In oxide, In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-Ga-Sn-Zn oxide, In-Ga-Al-Zn oxide, or the like. Furthermore, Ga-Zn oxide can also be used. Using a material that does not contain Zn, such as indium oxide, is preferred because it improves compatibility with the LSI manufacturing process. On the other hand, using a material that contains Zn is preferred because it facilitates improved crystallinity.

[0107] Metal oxides can also replace In or contain one or more metal elements with a large period number in addition to In. The greater the overlap of the orbits of the metal elements in the metal oxide, the greater the tendency of carrier conduction in the metal oxide. Therefore, by including a metal element with a large period number, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large period number, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm and Eu can be cited. Note that La, Ce, Pr, Nd, Pm, Sm and Eu are called light rare earth elements.

[0108] The metal oxide may also contain one or more non-metallic elements. The inclusion of non-metallic elements in the metal oxide may sometimes improve the field-effect mobility of the transistor. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0109] Metal oxides can be formed using sputtering or atomic layer deposition (ALD) as appropriate. ALD deposition is particularly preferred due to its excellent coverage. Note that when forming metal oxides using sputtering, the composition of the deposited metal oxide may differ from that of the target. In particular, the zinc content of the deposited metal oxide may be reduced to approximately 50% of the zinc content in the target.

[0110] In this specification, etc., the content rate of a certain metal oxide in a metal element refers to the ratio of the number of atoms of the element to the total number of atoms of the metal element contained in the metal oxide. For example, a metal oxide contains metal element X, metal element Y, and metal element Z, and the number of atoms of metal element X, metal element Y, and metal element Z contained in the metal oxide is A, respectively. X 、A Y 、A Z When the content of metal element X is expressed as A X / (A X +A Y +A Z ). In addition, when the ratio of the number of atoms of metal element X, metal element Y, and metal element Z in the metal oxide (atomic ratio) is expressed as B X :B Y :B Z When the content of metal element X is expressed as B X / (B X +B Y +B Z ).

[0111] For example, when a metal oxide containing In is used, a transistor with a large on-state current can be realized by increasing the In content.

[0112] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability in response to positive bias can be realized. In other words, a transistor with minimal fluctuation in threshold voltage during a PBTS (Positive Bias Temperature Stress) test can be realized. Furthermore, when using a metal oxide containing Ga, the Ga content is preferably lower than the In content. This allows for the realization of a transistor with high mobility and reliability.

[0113] On the other hand, increasing the Ga content can achieve transistors with high reliability against light. Specifically, it can achieve transistors with minimal fluctuation in threshold voltage during NBTIS (Negative Bias Temperature Illumination Stress) testing. Specifically, metal oxides with a Ga atomic ratio greater than that of In have a larger band gap, which can reduce the fluctuation in threshold voltage during NBTIS testing of transistors.

[0114] Furthermore, by increasing the zinc content, a highly crystalline metal oxide is formed, which can suppress the diffusion of impurities in the metal oxide. This suppresses variations in the electrical characteristics of the transistor and improves reliability.

[0115] The semiconductor layer 21 may also have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer 21 may also be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form the structure, thereby reducing manufacturing costs. Note that a stacked structure of two or more oxide semiconductor layers with different stacked compositions may also be adopted. In addition, by utilizing the ALD method, a metal oxide layer whose composition continuously changes in the thickness direction may be formed. Thus, compared with the case of using a film with a predetermined composition, not only can the range of design options be expanded, but the generation of interface states, etc., generated between two layers with different compositions can also be prevented, thereby improving electrical properties and reliability.

[0116] In the case where the semiconductor layer 21 has a two-layer structure, it is preferred to use a material (a material with high conductivity) whose mobility is higher than that of the first layer in the second layer, that is, the layer close to the gate electrode. Thus, a transistor that is normally off and has a large on-state current can be formed. Therefore, low power consumption and high performance can be achieved. In addition, a material whose mobility is higher than that of the second layer can be used in the first layer, that is, the layer on the side in contact with the source electrode and the drain electrode. Thus, the contact resistance between the semiconductor layer 21 and the source electrode or the drain electrode can be reduced, thereby reducing the parasitic resistance and forming a transistor with a large on-state current.

[0117] When the semiconductor layer 21 has a three-layer structure, it is preferable to use a material having higher mobility than the first and third layers for the second layer. This can realize a transistor with high on-state current and high reliability.

[0118] For example, the mobility or conductivity can be replaced by the indium content. In addition, the following factors also affect mobility and conductivity: the presence or absence of elements other than indium that help improve conductivity or the content of such elements. As an example of a high mobility material, for example, materials having an atomic ratio of In:Ga:Zn=4:3:2 and nearby, materials having an atomic ratio of In:Zn=1:1 and nearby, materials having an atomic ratio of In:Zn=4:1 and nearby, materials having an atomic ratio of In:Sn:Zn=40:X:10 (atomic ratio of X is greater than 0.1 and less than 5, typically X=1) and nearby, etc. can be cited. On the other hand, as materials whose mobility or conductivity is lower than the above-mentioned materials, there can be mentioned materials such as In:Ga:Zn=1:3:2 [atomic ratio] and nearby materials, materials such as In:Ga:Zn=1:3:4 [atomic ratio] and nearby materials, materials such as In:Ga:Zn=2:2:1 [atomic ratio] and nearby materials, materials such as In:Ga:Zn=1:1:1 [atomic ratio] and nearby materials, materials such as In:Ga:Zn=1:1:2 [atomic ratio] and nearby materials, etc.

[0119] A crystalline metal oxide layer is preferably used as the semiconductor layer 21. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, or a nanocrystalline (nc) structure, as described later, can be used. Using a crystalline metal oxide layer for the semiconductor layer 21 reduces the defect state density in the semiconductor layer 21, thereby achieving a highly reliable semiconductor device.

[0120] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 21, the lower the defect state density in the semiconductor layer 21. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0121] Compared to transistors using amorphous silicon, transistors using oxide semiconductors (hereinafter referred to as OS transistors) have significantly higher field-effect mobility. Furthermore, the leakage current between the source and drain of an OS transistor in the off state (hereinafter also referred to as off-state current) is extremely low, allowing the charge accumulated in a capacitor connected in series with the transistor to be retained for a long period of time. Furthermore, the use of OS transistors can reduce the power consumption of semiconductor devices.

[0122] A semiconductor device according to one embodiment of the present invention can be applied to a display device, for example. When increasing the brightness of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To this end, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Because the source-drain withstand voltage of an OS transistor is higher than that of a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Thus, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be increased, thereby improving the brightness of the light-emitting device.

[0123] When the transistor operates in the saturation region, the OS transistor can make the change in source-drain current smaller than that of the Si transistor in response to changes in gate-source voltage. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, the amount of current flowing through the light-emitting device can be tightly controlled. As a result, the grayscale of the pixel circuit can be increased. In addition, even if the electrical characteristics (such as resistance) of the light-emitting device fluctuate or the electrical characteristics are uneven, a stable current can be passed.

[0124] As described above, by using an OS transistor as a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black blur," "increase in luminance of emitted light," "multi-gradation," and "suppression of the influence of manufacturing unevenness of light-emitting devices."

[0125] OS transistors have little change in electrical characteristics due to exposure to radiation, that is, they have high tolerance to radiation, so they can be appropriately used in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be appropriately used as pixel circuits for flat-panel detectors of X-rays. In addition, OS transistors can be appropriately used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton radiation, and neutron radiation).

[0126] Note that the semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, a semiconductor composed of a single element or a compound semiconductor can be used. Examples of semiconductors composed of a single element include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) or germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. Note that these semiconductor materials may also contain impurities as dopants.

[0127] Alternatively, the semiconductor layer 21 may also include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked together through bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. The layered material has high conductivity per unit layer, that is, high two-dimensional conductivity. By using a material that functions as a semiconductor and has high two-dimensional conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0128] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing oxygen group elements (elements belonging to Group 16). In addition, examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0129] There are no particular restrictions on the crystallinity of the semiconductor material used for the semiconductor layer 21. An amorphous semiconductor, a single crystal semiconductor, or a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part thereof) can be used. Using a crystalline semiconductor is preferred because it can suppress degradation of transistor characteristics.

[0130] <Gate Insulation Layer>

[0131] The insulating layer 22 is used as a gate insulating layer of a transistor and can also be used as a dielectric layer of a capacitor. When an oxide semiconductor is used for the semiconductor layer 21, an oxide insulating film is preferably used as a film in the insulating layer 22 that is at least in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride and Ga-Zn oxide can be used. In addition, as the insulating layer 22, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide and the like can also be used. In addition, the insulating layer 22 can also have a stacked structure, for example, it can also have a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0132] In this specification, etc., an oxynitride refers to a material containing more oxygen than nitrogen, and a nitride oxide refers to a material containing more nitrogen than oxygen.

[0133] In addition, the insulating layer 22 is preferably a laminated insulating material composed of a high-k material, preferably a laminated structure of a high relative dielectric constant (high-k) material and a material with a dielectric strength greater than that of the high-k material. For example, as the insulating layer 22, an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in sequence can be used. In addition, for example, an insulating film (also referred to as ZAZA) in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in sequence can be used. In addition, for example, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in sequence can be used. By laminating an insulator with a relatively high dielectric strength such as aluminum oxide, the dielectric strength can be increased and the electrostatic breakdown of the capacitor can be suppressed.

[0134] In addition, a material exhibiting ferroelectricity may be used as the insulating layer 22. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0) and other metal oxides.

[0135] <Conductive Layer>

[0136] The conductive layer 24 and the conductive layer 25 are in contact with the semiconductor layer 21. When an oxide semiconductor is used as the semiconductor layer 21, if a metal that is easily oxidized, such as aluminum, is used in the portion of the conductive layer 24 or the conductive layer 25 that contacts the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 24 or the conductive layer 25 and the semiconductor layer 21, potentially hindering electrical conduction therebetween. Therefore, for at least the portion of the conductive layer 24 or the conductive layer 25 that contacts the semiconductor layer 21, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low resistance even if oxidized, or an oxide conductive material.

[0137] As the conductive layer 24 and the conductive layer 25, for example, titanium, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. These are conductive materials that are not easily oxidized or materials that maintain conductivity even if oxidized.

[0138] Alternatively, conductive oxides such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide, and Ga-Zn oxide can be used. In particular, conductive oxides containing indium are preferably used because they have high conductivity. Furthermore, oxide materials such as In-Ga-Zn oxide, which can be used in the semiconductor layer 21, can also be used in the conductive layer by increasing the carrier concentration.

[0139] For example, the conductive layers 24 and 25 may have the following structures: a single-layer structure of the aforementioned conductive oxide film; a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked in this order; a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on tungsten; a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the aforementioned conductive oxide film; a two-layer structure in which the aforementioned conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film; etc. Note that ruthenium is not easily etched, so when using this material, the thinner the better; for example, the thickness is preferably not less than 0.1 nm and not more than 2 nm.

[0140] Conductive layer 23 serves as a gate electrode and can be made of various conductive materials. For example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, or the like, or an alloy containing such a metal element, is preferably used as conductive layer 23. Furthermore, nitrides or oxides of the aforementioned metals or alloys may also be used. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferably used. Furthermore, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0141] Alternatively, the conductive layer 23 may also use the nitrides and oxides that can be used for the conductive layers 24 and 25 .

[0142] Since conductive layers 23, 24, and 25 also function as wiring, it is preferable to use a stack of low-resistance conductive materials. For example, the lower layers of conductive layers 24 and 25 may also use the same low-resistance conductive material as that used for conductive layer 23.

[0143] <Insulation layer>

[0144] The insulating layer 41b can function as an interlayer insulating film. For example, it is preferably formed by a deposition method such as sputtering or plasma CVD. In particular, by utilizing sputtering to deposit the film without using hydrogen as the deposition gas, a film containing an extremely low amount of hydrogen can be deposited. This suppresses the supply of hydrogen to the semiconductor layer 21, thereby stabilizing the electrical characteristics of the transistor 10.

[0145] Since the insulating layer 41b is in contact with the channel formation region of the semiconductor layer 21, an oxide insulating film is preferably used. In particular, an oxide insulating film that releases oxygen when heated is preferably used. As the insulating layer 41b, an oxide insulating film that can be used for the gate insulating layer described above can be used.

[0146] Furthermore, because insulating layer 41b serves as an interlayer insulating layer, it is preferable to use a deposition method that allows for a higher deposition rate than other insulating layers. For example, a TEOS (Tetra-Ethyl-Ortho-Silicate; chemical formula: Si(OC2H5)4) film formed using plasma CVD can be used as insulating layer 41. This can improve productivity.

[0147] The insulating layers 41a and 41c are preferably films that are not easily diffused by hydrogen. By sandwiching the insulating layer 41b above and below with the insulating layers 41a and 41c, which are not easily diffused by hydrogen, hydrogen can be prevented from entering the insulating layer 41b in contact with the semiconductor layer 21 from outside.

[0148] As the insulating layer 41a and the insulating layer 41c, for example, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. In particular, silicon nitride and silicon nitride oxide are particularly suitable for the insulating layer 41a and the insulating layer 41c because they rarely release impurities (such as water and hydrogen) and do not easily allow oxygen and hydrogen to pass through.

[0149] The insulating layer 11 serves as an interlayer insulating layer. As the insulating layer 11, the insulating material that can be used for the insulating layer 41b described above or the insulating material that can be used for the insulating layer 41a and the insulating layer 41c described above can be used as appropriate.

[0150] The above is the description of the components.

[0151] [Deformation example]

[0152] The following describes an example in which some parts differ from the above-mentioned configuration example. Note that the description of parts that overlap with the above-mentioned contents may be omitted.

[0153] <Deformation Example 1>

[0154] Figure 4A 2 is a schematic cross-sectional view of a transistor 10 a shown below. The transistor 10 a mainly differs from the transistor 10 described above in that the shape of the semiconductor layer 21 is different.

[0155] In the portion of the semiconductor layer 21 located above the conductive layer 25, the ends of the semiconductor layer 21 and the conductive layer 25 are substantially aligned. This structure allows the conductive layer 25 and the semiconductor layer 21 to be processed in the same process, simplifying the process. Furthermore, since the conductive layer 25 is covered by the semiconductor layer 21, damage to the conductive layer 25, which could reduce its conductivity, can be prevented during processes such as etching the semiconductor layer 21 and depositing the insulating layer 22.

[0156] <Deformation Example 2>

[0157] Figure 4B The transistor 10 b shown differs from the transistor 10 described above primarily in the structures of the conductive layer 24 and the semiconductor layer 21 .

[0158] Inside opening 20a, the end of conductive layer 24 has a portion that protrudes beyond the end of semiconductor layer 21. Furthermore, the top surface of conductive layer 24 has a portion in contact with semiconductor layer 21 and a portion in contact with insulating layer 22. Furthermore, diameter R2 of opening 20b is smaller than diameter R3 of opening 20c. This structure reduces the step at these ends compared to a case where the ends of semiconductor layer 21 and conductive layer 24 are substantially aligned, thereby preventing poor coverage of insulating layer 22.

[0159] <Deformation Example 3>

[0160] Figure 5A The transistor 10 c shown differs from the transistor 10 described above primarily in the shape of the conductive layer 24 .

[0161] The thickness of the portion of the conductive layer 24 overlapping the opening 20a is thinner than the portion overlapping the insulating layer 41. For example, when a portion of the conductive layer 24 is etched and thinned when forming the opening 20a, the above-described shape may be obtained.

[0162] in addition, Figure 5B The transistor 10 d shown is an example in which the conductive layer 24 is also etched when the opening 20 a is formed.

[0163] By adopting the above structure, the step in the opening 20 a is reduced, and the occurrence of poor coverage of the insulating layer 22 can be more effectively suppressed.

[0164] <Deformation Example 4>

[0165] Figure 5C The transistor 10 e shown is an example in which the semiconductor layer 21 is provided in the opening 20 a so as to cover the end portion of the conductive layer 24 .

[0166] In the transistor 10e, the opening 20c is located inside the opening 20b when viewed from a planar perspective. Therefore, the diameter R3 of the opening 20c is smaller than the diameter R2 of the opening 20b.

[0167] By adopting such a structure, the step in the opening 20 a can also be reduced, so the occurrence of poor coverage of the insulating layer 22 can be more effectively suppressed.

[0168] <Variation Example 5>

[0169] exist Figure 6 , a cross section of the transistor 10 and a cross section of the transistor 15 that can be formed through the same process as the transistor 10 are shown side by side on the same plane.

[0170] Transistor 15 is a transistor in which openings 20b and 20c are not provided in conductive layer 24 and semiconductor layer 21. Transistor 15 includes semiconductor layer 21, insulating layer 22, conductive layer 23, conductive layer 24, and conductive layer 25. In transistor 15, insulating layer 22 is in contact with semiconductor layer 21 within opening 20a, but is not in contact with conductive layer 24 or insulating layer 11.

[0171] In transistor 15, by not providing openings 20b and 20c, the diameter of opening 20a provided in insulating layer 41 can be made smaller than that of transistor 10. In other words, transistor 15 can be made even more compact than transistor 10. They can be used separately as required; for example, transistor 10 can be used for transistors requiring small parasitic capacitance, while transistor 15 can be used for transistors requiring a small footprint, and so on.

[0172] <Variation Example 6>

[0173] Next, a structural example of a transistor having a structure suitable for miniaturization using an LSI process will be described.

[0174] Figure 7A The transistor 10f shown is mainly different from the above-mentioned transistor 10 and the like in that the ends of the layers are processed to be substantially vertical.

[0175] Conductive layer 24 is embedded in insulating layer 44. Insulating layer 41 is provided to cover conductive layer 24 and insulating layer 44. Conductive layer 25 is embedded in insulating layer 45. Insulating layer 22 is provided to cover insulating layer 45, conductive layer 25, semiconductor layer 21, and the like. The top surfaces of insulating layer 44 and conductive layer 24 are planarized to approximately the same height, and the top surfaces of insulating layer 45 and conductive layer 25 are planarized to approximately the same height.

[0176] Insulating layers 41a, 41b, and 41c have substantially vertical cross-sections. That is, the angle θ of the sidewalls of opening 20a in insulating layer 41 is approximately 90 degrees. Furthermore, within opening 20a, the ends of semiconductor layer 21 and conductive layer 24 are substantially aligned, so the diameter of opening 20c is substantially aligned with the outline of opening 20b.

[0177] The semiconductor layer 21 , the insulating layer 22 , and the conductive layer 23 are provided along the substantially vertical inner wall of the opening 20 a of the insulating layer 41 , and therefore are preferably formed using a deposition method with high coverage such as ALD.

[0178] Figure 7B The transistor 10 g shown is an example in which the conductive layer 23 is provided so as to fill the opening 20 a .

[0179] An insulating layer 42 is provided on the insulating layer 22. An opening 20d is provided in the insulating layer 42, overlapping the opening 20a and reaching the insulating layer 22. A conductive layer 23 is provided so as to fill the opening 20d and the opening 20a. Furthermore, the top surfaces of the conductive layer 23 and the insulating layer 42 are flattened. A conductive layer 32 is provided on the insulating layer 42, in contact with the top surface of the conductive layer 23. The conductive layer 32 serves as a gate wiring.

[0180] in addition, Figure 7C The transistor 10h shown is an example in which the insulating layer 22 is provided along the inner wall of the opening 20d.

[0181] An opening 20d is provided so as to reach the semiconductor layer 21, and an insulating layer 22 is provided so as to cover the sidewall of the opening 20d and the semiconductor layer 21. Furthermore, a conductive layer 23 is provided so as to fill the opening 20d and the opening 20a.

[0182] By adopting 7A to 7C The structure shown can realize extremely micro transistors. For example, by forming transistors with this structure on a semiconductor substrate such as a silicon wafer, a display panel with a resolution exceeding 3000ppi or even exceeding 5000ppi can be realized.

[0183] The above is the description of the modified example.

[0184] [Manufacturing method example]

[0185] Next, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Here, an example of a method for manufacturing the transistor 10 will be described.

[0186] Note that thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and atomic layer deposition (ALD). Examples of CVD methods include plasma-enhanced chemical vapor deposition (PECVD) and thermal CVD. Furthermore, one thermal CVD method includes metal organic chemical vapor deposition (MOCVD).

[0187] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using methods such as spin coating, dipping, spraying, inkjet, dispenser, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and blade coating.

[0188] Sputtering methods include RF sputtering, which uses a high-frequency power supply, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is primarily used for depositing insulating films, while DC sputtering is primarily used for depositing metallic conductive films. Furthermore, pulsed DC sputtering is primarily used for depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0189] CVD methods can be categorized into plasma-enhanced CVD (PECVD) using plasma, thermal CVD (TCVD) using heat, and photo CVD (photo CVD) using light. Furthermore, based on the source gas used, they can be further categorized into metal CVD (MCVD) and metal organic CVD (MOCVD).

[0190] Plasma-enhanced CVD allows for the production of high-quality films at relatively low temperatures. Furthermore, because thermal CVD does not utilize plasma, plasma damage to the substrate is minimized. Furthermore, thermal CVD eliminates plasma damage during deposition, resulting in films with fewer defects.

[0191] As the ALD method, a thermal ALD method in which a precursor and a reactant react using only thermal energy, a PEALD method using a reactant excited by plasma, or the like can be used.

[0192] Unlike sputtering, CVD and ALD are deposition methods that offer excellent step coverage and are less susceptible to the shape of the substrate being processed. ALD, in particular, offers excellent step coverage and thickness uniformity, making it suitable for forming films that cover surfaces with openings with high aspect ratios. However, ALD has a relatively slow deposition rate, making it sometimes preferable to combine it with other deposition methods, such as CVD, which have faster deposition rates.

[0193] When using the CVD method, films of arbitrary compositions can be deposited by adjusting the flow ratio of the source gases. For example, by changing the flow ratio of the source gases while deposition is being performed, a film with a continuously varying composition can be deposited. When deposition is performed while changing the flow ratio of the source gases, the deposition time can be shortened compared to deposition using multiple deposition chambers because the time required for transfer or pressure adjustment is not required. Consequently, the productivity of semiconductor devices can sometimes be improved.

[0194] When using ALD, films of arbitrary composition can be deposited by simultaneously introducing multiple different precursors. Alternatively, when introducing multiple different precursors, films of arbitrary composition can be deposited by controlling the number of cycles for each precursor. Furthermore, similar to CVD, films with continuously varying compositions can be deposited.

[0195] Furthermore, when thin films constituting semiconductor devices are processed, photolithography or the like can be used. In addition to the aforementioned methods, thin films can also be processed using nanoimprinting, sandblasting, lift-off, and the like. Furthermore, island-shaped thin films can be directly formed using a deposition method using a shadow mask such as a metal mask.

[0196] Photolithography typically involves two methods: one involves forming a resist mask on the film to be processed, processing the film by etching, etc., and then removing the resist mask. The other involves depositing a photosensitive film, then exposing and developing the film to the desired shape.

[0197] In the photolithography method, as the light used for exposure, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm) or light mixed with these rays can be used. In addition, ultraviolet light, KrF laser or ArF laser, etc. can also be used. In addition, exposure can also be performed using liquid immersion exposure technology. In addition, as the light used for exposure, extreme ultraviolet (EUV: Extreme Ultra-Violet) light and X-rays can also be used. In addition, an electron beam can also be used instead of the light used for exposure. When extreme ultraviolet light, X-rays or electron beams are used, extremely fine processing can be performed, so it is preferred. Note that when exposure is performed by scanning with a light beam such as an electron beam, a photomask is not required.

[0198] As a method for etching the thin film, dry etching, wet etching, sand blasting, or the like can be used.

[0199] Figures 8A to 8D These are perspective views of each step in the semiconductor device manufacturing process described below.

[0200] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate.

[0201] As the substrate, a substrate having heat resistance at least sufficient to withstand the subsequent heat treatment can be used. When using an insulating substrate as the substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, an organic resin substrate, or the like can be used. Alternatively, a semiconductor substrate such as a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate such as silicon germanium or silicon nitride, or an SOI substrate can be used.

[0202] As the insulating layer 11, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used. The insulating layer 11 can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like. If the surface on which the insulating layer 11 is to be formed is uneven, a planarization process may be performed after the insulating layer 11 is deposited to make the top surface of the insulating layer 11 flat.

[0203] Next, a conductive film is deposited on the insulating layer 11 , a resist mask is formed on the conductive film, and unnecessary portions of the conductive film are removed by etching, thereby forming the conductive layer 24 .

[0204] As the conductive film to be the conductive layer 24 , a deposition method such as sputtering, CVD, or ALD can be used.

[0205] Next, insulating layers 41a, 41b, and 41c are formed on conductive layer 24 and insulating layer 11. Insulating layers 41a, 41b, and 41c can be formed by sputtering, CVD, MBE, PLD, ALD, or the like as appropriate.

[0206] Here, it is preferable to use an insulating film having a composition or constituent elements different from those of the insulating layer 41 b as the insulating layer 41 a and the insulating layer 41 c.

[0207] Furthermore, since the thicknesses of the insulating layers 41a, 41b, and 41c affect the channel length of the transistor, it is important to prevent the thicknesses of the insulating layers 41a, 41b, and 41c from being uneven.

[0208] The insulating layer 41b is a film that will later come into contact with the semiconductor layer 21, so it is preferable to use an oxide film that contains a large amount of oxygen, enough to release oxygen when heated, and has a low hydrogen content. The insulating layer 41b can be deposited using a deposition method such as PECVD, sputtering, or ALD, with sputtering being particularly preferred. In particular, by using a gas containing oxygen instead of a gas containing hydrogen as the deposition gas, it is possible to deposit an insulating layer 41b that has an extremely low hydrogen content and contains excess oxygen. In this way, by depositing the insulating layer 41b, oxygen is supplied from the insulating layer 41b to the channel formation region of the semiconductor layer 21, thereby reducing oxygen vacancies.

[0209] Next, a conductive film is deposited on the insulating layer 41c, and unnecessary portions are removed by etching, thereby forming the conductive layer 25 ( Figure 8A ). The conductive film can be deposited by a deposition method such as sputtering, CVD, MBE, PLD, or ALD.

[0210] Next, an opening 20a ( 20b ) reaching the conductive layer 24 is formed in the conductive layer 25 , the insulating layer 41c , the insulating layer 41b , and the insulating layer 41a . Figure 8B ).

[0211] When forming opening 20a, conductive layer 25 can also be used as a hard mask. In this case, an opening is first formed in conductive layer 25 using a resist mask. Then, insulating layer 41c, insulating layer 41b, and insulating layer 41a are sequentially etched using conductive layer 25 as a mask, thereby forming opening 20a. The resist mask can be removed after etching conductive layer 25, during etching of insulating layers 41c, 41b, and 41a, or after forming opening 20a.

[0212] By using dry etching for etching the conductive layer 25, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a, a fine opening 20a can be formed. Note that this is not limiting and wet etching and dry etching may be combined, or processing may be performed by wet etching.

[0213] When the sidewalls of the opening 20a have a shape perpendicular to the top surface of the conductive layer 24, the area of the opening 20a can be reduced, which is preferred. By adopting this structure, a transistor with a small footprint can be manufactured. Alternatively, the sidewalls of the opening 20a can also have a tapered shape. By having a tapered shape, the coverage of the film formed inside the opening 20a can be improved.

[0214] The maximum width of the opening 20a (the maximum diameter of the opening 20a when viewed from above, if the opening 20a is circular) is preferably as small as possible. For example, the maximum width of the opening 20a is preferably 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 150 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less and 5 nm or more. In particular, to perform extremely fine processing on the opening 20a, photolithography using short-wavelength light such as EUV light or electron beams is preferably used.

[0215] Next, heat treatment may also be performed. The heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. In addition, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas or an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. For example, when heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of oxygen gas may be set to about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher to compensate for the oxygen that has been released. By performing the above-mentioned heat treatment, impurities such as water and hydrogen contained in the insulating layer 41 or the like may be reduced before the oxide semiconductor film that becomes the semiconductor layer is deposited.

[0216] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the gas used in the heat treatment may contain a moisture content of 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. Using highly purified gas for the heat treatment minimizes absorption of moisture and the like by the insulating layer 41 and the like.

[0217] Next, a semiconductor film that will become the semiconductor layer 21 is deposited so as to cover the conductive layer 25, the insulating layer 41c, the opening 20a, and the like. Unnecessary portions of the semiconductor film are then removed by etching to form the semiconductor layer 21. Note that the opening 20c does not need to be formed in the semiconductor layer 21 at this stage.

[0218] Next, the semiconductor layer 21 and the conductive layer 24 in the region overlapping with the opening 20a are partially etched to form an opening 20c in the semiconductor layer 21 and an opening 20b in the conductive layer 24. Figure 8C ).

[0219] The opening 20 b and the opening 20 c are preferably formed using the same resist mask. This allows the ends of the semiconductor layer 21 and the conductive layer 24 to be substantially aligned.

[0220] Note that the formation of openings 20b and 20c is not limited to this, and they can also be formed using different resist masks. Alternatively, openings 20c and 20b can be formed simultaneously with the processing of semiconductor layer 21. Alternatively, opening 20b can be formed before the semiconductor film is deposited, and opening 20c can be formed separately after the semiconductor film is deposited. Alternatively, opening 20b can be formed simultaneously with the formation of opening 20a.

[0221] As a semiconductor film, an oxide semiconductor film can be used. The oxide semiconductor film can be appropriately deposited using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, the oxide semiconductor film is preferably formed in a manner that contacts the bottom and sidewalls of the opening 20a with a high aspect ratio. Therefore, when depositing the oxide semiconductor film, it is preferred to use a deposition method with good coverage, more preferably a CVD method or an ALD method. For example, as the oxide semiconductor film, In-Ga-Zn oxide can be deposited using an ALD method. In addition, when the opening 20a is conical, the oxide semiconductor film can be deposited using a sputtering method.

[0222] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere during or after deposition of the oxide semiconductor film to reduce the impurity concentration in the oxide semiconductor film. Examples of impurities include hydrogen and carbon. Microwave treatment can also improve the crystallinity of the oxide semiconductor film. Microwave treatment, for example, refers to treatment using an apparatus that includes a power source for generating high-density plasma using microwaves.

[0223] By performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be plasmatized using microwaves or high frequencies such as RF, and the oxygen plasma can be allowed to act. In addition, as oxygen acting on the oxide semiconductor, there are various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen free radicals (also known as O radicals, which are atoms, molecules, or ions with unpaired electrons). In addition, the oxygen acting on the oxide semiconductor can be any one or more of the above forms, and oxygen free radicals are particularly preferred.

[0224] Furthermore, heating the substrate during the microwave treatment in the oxygen-containing atmosphere is preferred because it can further reduce the impurity concentration in the oxide semiconductor film. The substrate can be heated at a temperature of 100°C to 650°C, preferably 200°C to 600°C, and more preferably 300°C to 450°C.

[0225] By heating the substrate during the microwave treatment in the oxygen-containing atmosphere as described above, the carbon concentration in the oxide semiconductor film measured by SIMS can be reduced to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 1×10 18 atoms / cm 3 .

[0226] Note that while the above illustrates a structure in which the oxide semiconductor film is microwave-treated in an oxygen-containing atmosphere, the present invention is not limited thereto. For example, microwave treatment can also be performed on an insulating film located near the oxide semiconductor film, more specifically, on a silicon oxide film, in an oxygen-containing atmosphere. This allows hydrogen contained in the silicon oxide film to be released to the outside as H2O. By releasing hydrogen from the silicon oxide film located near the oxide semiconductor film, a highly reliable semiconductor device can be provided. For example, microwave treatment can also be performed on the insulating layer 22 to be formed later in an oxygen-containing atmosphere.

[0227] In addition, when the semiconductor layer 21 has a stacked structure, the deposition methods of each layer may be the same or different. For example, when the semiconductor layer 21 has a two-layer stacked structure, the lower oxide semiconductor film may be deposited by sputtering and the upper oxide semiconductor film may be deposited by ALD. The oxide semiconductor film deposited by sputtering can easily have crystallinity. Thus, by providing a crystalline oxide semiconductor film as the lower oxide semiconductor film, the crystallinity of the upper oxide semiconductor film can be improved. In addition, even if pinholes or breaks are formed in the lower oxide semiconductor film deposited by sputtering, the portion overlapping with the pinholes or breaks can be blocked by the upper oxide semiconductor film deposited by ALD with good coverage.

[0228] The semiconductor film is preferably formed by, for example, a sputtering method using a metal oxide target.

[0229] The semiconductor film is preferably a dense film with as few defects as possible. Furthermore, the semiconductor film is preferably a high-purity film with as few impurities as possible, such as hydrogen and water. In particular, a crystalline metal oxide film is preferably used as the semiconductor film.

[0230] When forming a metal oxide film, an oxygen gas and an inert gas (e.g., helium, argon, xenon, etc.) may be mixed. Note that the higher the proportion of oxygen gas in the total deposition gas during metal oxide film deposition (hereinafter also referred to as the oxygen flow rate), the higher the crystallinity of the metal oxide film can be, and a transistor with high reliability can be realized. On the other hand, the lower the oxygen flow rate, the lower the crystallinity of the metal oxide film, and a transistor with high on-state current can be realized.

[0231] When the substrate temperature is high during deposition of the metal oxide film, a denser metal oxide film with higher crystallinity can be formed. On the other hand, as the substrate temperature decreases, a metal oxide film with lower crystallinity and higher conductivity can be formed.

[0232] The metal oxide film is formed under conditions where the substrate temperature is between room temperature and 250°C, preferably between room temperature and 200°C, and more preferably between room temperature and 140°C. For example, the substrate temperature is preferably between room temperature and below 140°C, thereby improving productivity. Forming the metal oxide film at room temperature or without intentional heating can reduce crystallinity.

[0233] When using ALD, thermal ALD (Atomic Layer Deposition) or PEALD (Plasma Enhanced ALD) deposition methods are preferred. Thermal ALD is preferred due to its extremely high step coverage. PEALD is also preferred due to its high step coverage and low-temperature deposition capabilities.

[0234] For example, when a metal oxide is used for the semiconductor layer 21 , it can be deposited by the ALD method using a precursor containing a metal element constituting the metal oxide and an oxidizing agent.

[0235] For example, when depositing In—Ga—Zn oxide, three precursors may be used: a precursor containing indium, a precursor containing gallium, and a precursor containing zinc. Alternatively, two precursors may be used: a precursor containing indium and a precursor containing gallium and zinc.

[0236] As the precursor containing indium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedione)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, or the like can be used.

[0237] In addition, as a precursor containing gallium, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamide)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedione)gallium, dimethylchlorogallium, diethylchlorogallium, gallium(III) chloride, etc. can be used.

[0238] Furthermore, as a precursor containing zinc, dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedione)zinc, zinc chloride, or the like can be used.

[0239] As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used.

[0240] Methods for controlling the composition of the resulting film include adjusting the source gas flow ratio, source gas flow time, and source gas flow order. By adjusting these methods, it is possible to deposit a film with a continuously varying composition. Furthermore, it is possible to continuously deposit two or more films with different compositions.

[0241] After the oxide semiconductor film is formed, heat treatment is preferably performed. The heat treatment can be performed within a temperature range in which the oxide semiconductor film does not undergo polycrystallization, and can be performed at a temperature of 250°C or higher and 650°C or lower, preferably 400°C or higher and 600°C or lower. In addition, the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas or an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. For example, when heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of oxygen gas can be set to about 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in an atmosphere of nitrogen gas or an inert gas, and then in order to compensate for the detached oxygen, the heat treatment is performed in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher.

[0242] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the gas used in the heat treatment may contain a moisture content of 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. Using highly purified gas for the heat treatment minimizes absorption of moisture and the like by the oxide semiconductor film and the like.

[0243] Next, the insulating layer 22 is formed to cover the semiconductor layer 21, the conductive layer 25, the insulating layer 41c, the conductive layer 24, the insulating layer 11, etc. The insulating layer 22 can be deposited by sputtering, CVD, MBE, PLD, ALD, etc. as appropriate.

[0244] It is preferable to provide an insulating layer 22 with the most uniform thickness possible on the side surfaces of the semiconductor layer 21 within the opening 20a. For this purpose, it is particularly preferable to form the insulating layer 22 using the ALD method, which is a deposition method with excellent coverage. Note that when the sidewalls of the opening 20a are tapered, the insulating layer 22 can be deposited using a deposition method such as sputtering.

[0245] Next, a conductive film is deposited over the insulating layer 22, and unnecessary portions are removed by etching, thereby forming a conductive layer 23 ( Figure 8D ).

[0246] Through the above steps, the transistor 10 can be manufactured.

[0247] The above is the description of the example of the manufacturing method.

[0248] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0249] (Implementation Method 2)

[0250] One embodiment of the present invention has a structure for reducing the capacitance between the gate electrode and the first electrode at the bottom of the opening (first opening) in the insulating layer serving as a spacer. In the above-described first embodiment, a structure for reducing capacitance by providing openings in the lower first electrode and the semiconductor layer was described. This embodiment describes an example structure that partially differs from that in the first embodiment. The following description may sometimes omit portions that overlap with the above description.

[0251] More specifically, for example, the gate electrode includes an opening located inside the opening (first opening) of the insulating layer serving as a spacer when viewed from above. Thus, even if one or both of the semiconductor layer and the first electrode do not include an opening, a portion of the gate electrode that does not overlap with the first electrode and the semiconductor layer can be provided. This reduces the capacitance between the gate electrode and the first electrode.

[0252] Next, a more specific configuration example will be described with reference to the drawings.

[0253] [Structure example]

[0254] Figure 9A and Figure 9B A schematic perspective view of a transistor 50 is shown. Figure 9A is a perspective view including a cross section cut along the XZ plane, Figure 9B It is a perspective view including a cross section taken along the YZ plane.

[0255] in addition, Figure 10A shows a plan view of transistor 50, Figure 10B Shown corresponding to Figure 10A A schematic cross-sectional view of the cutoff line A1-A2 in FIG. Figure 10C Shown corresponding to Figure 10A Schematic cross-sectional view of the cutoff line B1-B2 in FIG.

[0256] Like the transistor 10 , the transistor 50 is provided in the opening 20 a in the insulating layer 41 and its surroundings, and includes a semiconductor layer 21 , an insulating layer 22 , a conductive layer 23 , a conductive layer 24 , and a conductive layer 25 .

[0257] Conductive layer 24 is provided on insulating layer 11. Insulating layer 41 is provided to cover conductive layer 24 and includes an opening that reaches conductive layer 24. Conductive layer 25 is provided on insulating layer 41. Semiconductor layer 21 includes a portion that contacts the top surface of conductive layer 25, the top surface of conductive layer 24, and the side surfaces of insulating layer 41. Insulating layer 22 covers semiconductor layer 21, and conductive layer 23 covers insulating layer 22.

[0258] Here, the conductive layer 23 includes an opening 20e that reaches the insulating layer 22. When viewed from above, the opening 20e is located inside the opening 20a. Here, the shape of the opening 20a of the insulating layer 41 and the shape of the opening 20e of the conductive layer 23 are both circular.

[0259] For the channel length L, channel width W, and the like of the transistor 50 , reference can be made to the description of Embodiment 1. Figure 11A is with Figure 10B The same cross-sectional view of transistor 50, Figure 11B From the Z direction, along Figure 11A A plan view of a cross section taken along a cutting line C1 - C2 at a height where the insulating layer 41 b is provided.

[0260] like Figure 11A As shown, the diameter of opening 20e in conductive layer 23 is R4. In this case, diameter R4 of opening 20e is smaller than diameter R1 of opening 20a. A larger R4 increases the area of the portion of conductive layer 23 that does not overlap with conductive layer 24 and semiconductor layer 21, thereby enhancing the parasitic capacitance reduction effect. For example, diameter R4 of opening 20e is at least 50% of diameter R1 of opening 20a, preferably at least 60%, more preferably at least 70%, even more preferably at least 80%, and even more preferably at least 90%, and is less than 100%.

[0261] The shape of opening 20a is not limited, and any shape is acceptable as long as opening 20e is located inside opening 20a. However, it is preferred that the shape of opening 20e is similar to or close to the shape of opening 20a because the difference in area between opening 20a and opening 20e can be reduced.

[0262] The above is the description of the structural example.

[0263] [Deformation example]

[0264] The following describes an example of a transistor structure having a partially different structure from the above.

[0265] <Deformation Example 1>

[0266] Figure 12 A cross-sectional view is shown in which the transistor 50 and the transistor 15 described as an example in Embodiment 1 are separately formed on the same surface.

[0267] Because transistor 15 does not require opening 20e inside opening 20a, opening 20a can be processed with the minimum processing size. Therefore, the area occupied by transistor 15 can be made smaller than that of transistor 50. In addition, the diameter of opening 20a of transistor 15 and transistor 50 can be appropriately changed according to the design.

[0268] In this way, the transistor 15 that can reduce the occupied area and the transistor 50 that can reduce the parasitic capacitance can be used separately according to the application.

[0269] By using different mask patterns for processing the conductive layer 23 , the opening 20 a and other layers, the transistor 50 and the transistor 15 can be formed separately without increasing the number of steps.

[0270] <Deformation Example 2>

[0271] Figure 13A A structural example of the transistor 50a having a structure suitable for miniaturization by applying an LSI process is shown.

[0272] The main difference between transistor 50a and transistor 50 is that the ends of each layer are processed to be substantially vertical. In addition, conductive layer 24 is embedded in insulating layer 44, and conductive layer 25 is embedded in insulating layer 45, and their top surfaces are flattened so that their heights are consistent.

[0273] Since the sidewalls of the opening 20 a are processed to be substantially vertical, the semiconductor layer 21 , the insulating layer 22 , and the conductive layer 23 are preferably formed by a deposition method having high coverage.

[0274] Figure 13B The transistor 50b shown is an example including the insulating layer 42 on the insulating layer 22. The conductive layer 23 includes a portion provided along the sidewall of the opening 20d of the insulating layer 42.

[0275] Figure 13C The transistor 50c shown differs from the transistor 50b in the position of the insulating layer 22. The insulating layer 22 and the conductive layer 23 have portions provided along the sidewalls of the opening 20d of the insulating layer 42.

[0276] In addition, if Figure 7B and Figure 7C As shown, the conductive layer 23 may also have a shape that fills the opening 20a. 13A to 13C As shown, forming the conductive layer 23 into a thin film is preferable because the process for forming the opening 20e in the conductive layer 23 becomes easier.

[0277] Figure 14A The transistor 50d shown is an example in which the conductive layer 32 is included to function as a gate wiring.

[0278] An insulating layer 46 is provided to cover the insulating layer 22 and the conductive layer 23, and the conductive layer 32 is provided on the insulating layer 46. The top surface of the insulating layer 46 is flattened to match the top surface of the conductive layer 23. The conductive layer 32 is provided to contact the top surface of the conductive layer 23 exposed from the insulating layer 46. The insulating layer 46 is also embedded in the opening 20a.

[0279] in addition, Figure 14B The transistor 50e is shown in Figure 13B The transistor 50b shown is an example in which the insulating layer 46 and the conductive layer 32 are further used. The insulating layer 46 is provided so as to fill the opening 20d.

[0280] In addition, you can also Figure 13C Insulating layer 46 and conductive layer 32 are also used in transistor 50c shown.

[0281] The above is the description of the modified example.

[0282] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0283] (Implementation 3)

[0284] In this embodiment, a display device using a semiconductor device according to one embodiment of the present invention is described with reference to the drawings.

[0285] The display device of this embodiment mode can be a high-resolution display device or a large display device. Therefore, for example, the display device of this embodiment mode can be used as a display portion of electronic devices with large screens, such as televisions, desktop or notebook personal computers, monitors for computers, digital signage, large-scale game consoles such as pinball machines, etc.; digital cameras; digital video cameras; digital photo frames; mobile phones; portable game consoles; portable information terminals; and audio reproduction devices.

[0286] Furthermore, the display device of this embodiment can be a high-definition display device. Therefore, for example, the display device of this embodiment can be used as a display portion of information terminal devices (wearable devices) such as watches and bracelets, as well as a display portion of wearable devices such as head-mounted displays (HMDs) for VR devices and glasses-type AR devices that can be worn on the head.

[0287] A semiconductor device according to one embodiment of the present invention can be used in a display device or a module including the display device. Examples of modules including the display device include a module in which a connector such as a flexible printed circuit (FPC) or a TCP (Tape Carrier Package) is mounted on the display device, and a module in which an integrated circuit (IC) is mounted using a COG (Chip On Glass) or COF (Chip On Film) method.

[0288] Figure 15 A perspective view of the display device 100A is shown.

[0289] The display device 100A has a structure in which a substrate 152 and a substrate 151 are bonded together. Figure 15 , the substrate 152 is indicated by a dotted line.

[0290] The display device 100A includes a display portion 162 , a connection portion 140 , a circuit portion 164 , wiring 165 , and the like. Figure 15 The example in which the display device 100A is mounted with IC 173 and FPC 172 is shown. Figure 15 The structure shown is called a display module including the display device 100A, an IC, and an FPC.

[0291] The connection portion 140 is disposed outside the display portion 162. The connection portion 140 may be disposed along one side or multiple sides of the display portion 162. The number of the connection portions 140 may also be one or more. Figure 15 In the illustrated example, the connection portion 140 is provided so as to surround the four sides of the display portion 162. In the connection portion 140, the common electrode of the display element is electrically connected to the conductive layer, and a potential can be supplied to the common electrode.

[0292] The circuit portion 164 includes, for example, a scanning line driver circuit (also referred to as a gate driver). Alternatively, the circuit portion 164 may include both a scanning line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0293] The wiring 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164. The signals and power are input to the wiring 165 from the outside through the FPC 172 or from the IC 173.

[0294] Figure 15The following illustrates an example in which an IC 173 is provided on a substrate 151 using a COG method or a COF method. For example, an IC including one or both of a scan line driver circuit and a signal line driver circuit can be used as the IC 173. Note that the display device 100A and the display module do not necessarily need to include an IC. Alternatively, the IC can be mounted on an FPC using a COF method or the like.

[0295] For example, the semiconductor device of one embodiment of the present invention can be used for one or both of the display portion 162 and the circuit portion 164 of the display device 100A. Furthermore, the semiconductor device of one embodiment of the present invention can also be used for the IC 173 .

[0296] For example, when a semiconductor device according to one embodiment of the present invention is used in a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, thereby realizing a high-definition display device. Furthermore, for example, when a semiconductor device according to one embodiment of the present invention is used in a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, thereby realizing a display device with a narrow frame. Furthermore, a semiconductor device according to one embodiment of the present invention has excellent electrical characteristics, and by using the semiconductor device in a display device, the reliability of the display device can be improved.

[0297] The display portion 162 is a region in the display device 100A that displays an image, and includes a plurality of periodically arranged pixels 210 . Figure 15 An enlarged view of one pixel 210 is shown in FIG.

[0298] There are no particular limitations on the arrangement of pixels in the display device of this embodiment, and various methods can be employed. Examples of pixel arrangements include stripe arrangement, S-stripe arrangement, matrix arrangement, Delta arrangement, Bayer arrangement, and Pentile arrangement.

[0299] Figure 15 The pixel 210 shown includes a sub-pixel 210R that emits red light, a sub-pixel 210G that emits green light, and a sub-pixel 210B that emits blue light.

[0300] Various elements can be used as display elements, for example, liquid crystal elements and light-emitting elements. In addition, MEMS (Micro Electro Mechanical Systems) elements using shutter or optical interference methods, display elements using microcapsules, electrophoresis, electrowetting, or electronic powder fluid (registered trademark) methods, etc. can also be used. Furthermore, QLEDs (Quantum-dot LEDs) using light sources and color conversion technology using quantum dot materials can also be used.

[0301] Examples of the liquid crystal element include a transmissive liquid crystal element, a reflective liquid crystal element, and a semi-transmissive liquid crystal element.

[0302] Examples of the light emitting element include self-luminous light emitting elements such as LED (Light Emitting Diode), OLED (Organic LED), and semiconductor lasers. Examples of the LED include miniature LEDs and micro LEDs.

[0303] Examples of the light-emitting substance contained in the light-emitting element include substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.).

[0304] The light emitting element may emit light of infrared, red, green, blue, cyan, magenta, yellow or white, etc. In addition, when the light emitting element has a microcavity structure, the color purity can be further improved.

[0305] In a pair of electrodes included in a light-emitting element, one electrode serves as an anode and the other electrode serves as a cathode. A display device according to one embodiment of the present invention may employ any of the following structures: a top emission type that emits light in a direction opposite to the substrate on which the light-emitting element is formed, a bottom emission type that emits light toward one side of the substrate on which the light-emitting element is formed, or a dual emission type that emits light toward both sides of the substrate.

[0306] Figure 16 An example of a cross section of the display device 100A including a portion of the region including the FPC 172 , a portion of the circuit portion 164 , a portion of the display portion 162 , a portion of the connection portion 140 , and a portion of the region including the end portion is shown.

[0307] Figure 16 Display device 100A shown includes transistors 205D, 205R, 205G, and 205B, light-emitting elements 130R, 130G, and 130B, between substrates 151 and 152. Light-emitting element 130R is a display element included in sub-pixel 210R that emits red light, light-emitting element 130G is a display element included in sub-pixel 210G that emits green light, and light-emitting element 130B is a display element included in sub-pixel 210B that emits blue light.

[0308] The display device 100A adopts an SBS structure. The SBS structure allows for optimization of the material and structure of each light-emitting element, thus increasing the freedom of material and structure selection and making it easier to improve brightness and reliability.

[0309] The display device 100A adopts a top emission type. In a top emission type, transistors and the like can be arranged so as to overlap with the light-emitting region of a light-emitting element, thereby further improving the pixel aperture ratio compared to a bottom emission type.

[0310] The transistors 205D, 205R, 205G, and 205B are all formed over the substrate 151. These transistors can be manufactured using the same process.

[0311] This embodiment shows an example of using transistors according to one embodiment of the present invention, in which parasitic capacitance is reduced by using an oxide semiconductor as a semiconductor, as transistors 205D, 205R, 205G, and 205B. For example, transistors 205R, 205G, and 205B are used as driver transistors for controlling the current flowing through a light-emitting element. Transistor 205D provided in circuit portion 164 is a transistor that constitutes part of the driver circuit.

[0312] Specifically, transistors 205D, 205R, 205G, and 205B each include a conductive layer 104 serving as a gate electrode, an insulating layer 106 serving as a gate insulator, a conductive layer 109 serving as one of a source electrode and a drain electrode, a conductive layer 107 serving as the other, a semiconductor layer 108, and an insulating layer 110. Conductive layer 109 and conductive layer 107 are in contact with semiconductor layer 108. Furthermore, conductive layer 112a in contact with conductive layer 107 and conductive layer 112b in contact with conductive layer 109 are provided. Conductive layers 112a and 112b both contain a conductive material having a lower resistance than conductive layers 107 and 109 and serve as wiring. Multiple layers formed by processing the same film are shaded identically.

[0313] In this way, the display device 100A includes a transistor of one embodiment of the present invention in both the display portion 162 and the circuit portion 164. By using a transistor of one embodiment of the present invention in the display portion 162, the pixel size can be reduced and high definition can be achieved. In addition, by using a transistor of one embodiment of the present invention in the circuit portion 164, the area occupied by the circuit portion 164 can be reduced and a narrow frame can be achieved. In addition, by using a transistor of one embodiment of the present invention in one or both of the display portion 162 and the circuit portion 164, the load on the wiring can be reduced, thereby realizing a display device capable of high-speed operation, a large display device, or a display device with high resolution (a large number of pixels). For the transistor of one embodiment of the present invention, reference can be made to the description of the above embodiment.

[0314] Note that the transistor included in the display device of this embodiment is not limited to the transistor of one embodiment of the present invention. For example, the transistor of one embodiment of the present invention may be combined with a transistor of another structure.

[0315] The display device of this embodiment mode may include, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor. The transistors included in the display device of this embodiment mode may have either a top-gate structure or a bottom-gate structure. Alternatively, gate electrodes may be provided above and below the semiconductor layer forming the channel.

[0316] The display device of this embodiment may also include a transistor using silicon for the channel formation region (Si transistor). Examples of silicon include single crystal silicon, polycrystalline silicon, amorphous silicon, and the like. In particular, a transistor containing LTPS in the semiconductor layer (hereinafter also referred to as an LTPS transistor) can be used. The LTPS transistor has high field effect mobility and good frequency characteristics. In addition, since the transistor containing amorphous silicon in the semiconductor layer can be uniformly deposited on a large area of glass substrate, high productivity can be achieved.

[0317] Furthermore, the display device of this embodiment may include a transistor (OS transistor) using an oxide semiconductor (OS) such as In-Ga-Zn oxide (also referred to as IGZO) for the channel formation region. For example, a display device may also include a transistor using silicon as the channel-forming semiconductor and a transistor using an oxide semiconductor as the channel-forming semiconductor.

[0318] The transistors included in the circuit portion 164 and the transistors included in the display portion 162 may have the same structure or different structures. The multiple transistors included in the circuit portion 164 may have the same structure or two or more different structures. Similarly, the multiple transistors included in the display portion 162 may have the same structure or two or more different structures.

[0319] All transistors included in the display portion 162 may be OS transistors, all transistors included in the display portion 162 may be Si transistors, or some transistors included in the display portion 162 may be OS transistors and the remaining transistors may be Si transistors.

[0320] For example, by using both LTPS transistors and OS transistors in the display portion 162, a display device with low power consumption and high driving capability can be realized. Furthermore, a structure combining LTPS transistors and OS transistors is sometimes referred to as LTPO. A more preferred example is a structure in which an OS transistor is used as a transistor used as a switch to control conduction / non-conduction between wirings, and an LTPS transistor is used as a transistor to control current flow.

[0321] For example, one of the transistors included in the display portion 162 is used as a transistor for controlling current flowing through the light-emitting element and may also be called a drive transistor. One of the source and drain of the drive transistor is electrically connected to the pixel electrode of the light-emitting element.

[0322] On the other hand, one of the other transistors included in the display unit 162 is used as a switch for controlling the selection and non-selection of pixels, and may also be referred to as a selection transistor. The gate of the selection transistor is electrically connected to the gate line, and one of the source and drain is electrically connected to the source line (signal line). An OS transistor is preferably used as the selection transistor. Therefore, even if the frame rate is significantly reduced (for example, below 1 fps), the grayscale of the pixel can be maintained, thereby reducing power consumption by stopping the driver when displaying a static image.

[0323] An insulating layer 218 is provided to cover the transistors 205D, 205R, 205G, and 205B, and an insulating layer 235 is provided over the insulating layer 218 .

[0324] The insulating layer 218 preferably serves as a protective layer for the transistor. A material that does not readily diffuse impurities such as water and hydrogen is preferably used for the insulating layer 218. This allows the insulating layer 218 to function as a barrier layer. This structure effectively prevents impurities from diffusing into the transistor from the outside, thereby improving the reliability of the display device.

[0325] The insulating layer 218 preferably includes one or more inorganic insulating films. Examples of the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Specific examples of the materials of these inorganic insulating films are as described above.

[0326] The insulating layer 235 is preferably used as a planarization layer, and an organic insulating film is suitable. Examples of materials that can be used for the organic insulating film include acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimide amide resins, siloxane resins, benzocyclobutene resins, phenolic resins, and precursors of these resins. In addition, the insulating layer 235 may also have a stacked structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 235 is preferably used as an etching protection layer. As a result, when processing the pixel electrodes 111R, 111G, 111B, etc., the formation of recesses in the insulating layer 235 can be suppressed. Alternatively, recesses may be provided in the insulating layer 235 when processing the pixel electrodes 111R, 111G, 111B, etc.

[0327] The light emitting elements 130R, 130G, and 130B are provided on the insulating layer 235 .

[0328] The light emitting element 130R includes a pixel electrode 111R on the insulating layer 235 , an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. Figure 16 The light emitting element 130R shown emits red light (R). The EL layer 113R includes a light emitting layer that emits red light.

[0329] Similarly, the light-emitting element 130G includes a pixel electrode 111G, an EL layer 113G, and a common electrode 115. The light-emitting element 130G emits green light (G), and the EL layer 113G includes a light-emitting layer that emits green light.

[0330] Similarly, the light-emitting element 130B includes a pixel electrode 111B, an EL layer 113B, and a common electrode 115. The light-emitting element 130B emits blue light (B), and the EL layer 113B includes a light-emitting layer that emits blue light.

[0331] Note that in Figure 16 EL layers 113R, 113G, and 113B are shown as having the same thickness, but this is not limiting. EL layers 113R, 113G, and 113B may have different thicknesses. For example, the thicknesses of EL layers 113R, 113G, and 113B are preferably set to enhance the optical path length of light emitted by each layer. This allows for a microcavity structure to be implemented, thereby improving the color purity of light emitted from each light-emitting element.

[0332] Pixel electrode 111R is electrically connected to conductive layer 112b included in transistor 205R via openings provided in insulating layer 106, insulating layer 218, and insulating layer 235. Similarly, pixel electrode 111G is electrically connected to conductive layer 112b included in transistor 205G, and pixel electrode 111B is electrically connected to conductive layer 112b included in transistor 205B.

[0333] Each end of the pixel electrodes 111R, 111G, and 111B is covered by an insulating layer 237. The insulating layer 237 serves as a partition wall (also known as a bank, dam, or spacer). The insulating layer 237 can be formed using one or both of an inorganic insulating material and an organic insulating material to form a single-layer structure or a stacked-layer structure. For example, the insulating layer 237 can use the material that can be used for the insulating layer 218 and the material that can be used for the insulating layer 235. The insulating layer 237 can electrically insulate the pixel electrode from the common electrode. In addition, the insulating layer 237 can electrically insulate adjacent light-emitting elements.

[0334] Common electrode 115 is a continuous film shared by light-emitting elements 130R, 130G, and 130B. Common electrode 115, shared by multiple light-emitting elements, is electrically connected to conductive layer 123 provided in connection portion 140. Conductive layer 123 is preferably formed using the same material and process as pixel electrodes 111R, 111G, and 111B.

[0335] In a display device according to one embodiment of the present invention, a conductive film that transmits visible light is used as the electrode on the light extraction side of the pixel electrode and the common electrode. A conductive film that reflects visible light is preferably used as the electrode on the side that does not extract light.

[0336] Alternatively, a conductive film that transmits visible light can be used as the electrode on the side that does not extract light. In this case, it is preferably placed between the reflective layer and the EL layer. In other words, the light emitted by the EL layer can also be reflected by the reflective layer and extracted from the display device.

[0337] As the material for forming a pair of electrodes of the light-emitting element, metals, alloys, conductive compounds and mixtures thereof can be appropriately used. As such materials, specifically, metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium and neodymium and alloys thereof as well as alloys appropriately combined can be cited. In addition, as such materials, indium tin oxide (also referred to as In-Sn oxide, ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide) and In-W-Zn oxide can be cited. In addition, as such materials, alloys containing aluminum (aluminum alloys) such as alloys of aluminum, nickel and lanthanum (Al-Ni-La), alloys of silver and magnesium (Mg-Ag) and alloys of silver, palladium and copper (Ag-Pd-Cu, also recorded as APC) can be cited. In addition, examples of the material include elements belonging to Group 1 or Group 2 of the periodic table (e.g., lithium, cesium, calcium, strontium) not listed above, rare earth metals such as europium and ytterbium, alloys of appropriately combined elements, and graphene.

[0338] The light-emitting element preferably employs a microcavity resonator (microcavity) structure. Therefore, one of the pair of electrodes included in the light-emitting element preferably comprises an electrode that is both transmissive and reflective to visible light (a semi-transmissive / semi-reflective electrode), while the other preferably comprises an electrode that is reflective to visible light (a reflective electrode). When the light-emitting element has a microcavity structure, the light emitted from the light-emitting layer can resonate between the two electrodes, thereby enhancing the light emitted from the light-emitting element.

[0339] The light transmittance of the transparent electrode is 40% or more. For example, an electrode having a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more is preferably used as a transparent electrode of a light-emitting element. The reflectivity of the semi-transmissive-semi-reflective electrode to visible light is 10% or more and 95% or less, preferably 30% or more and 80% or less. The reflectivity of the reflective electrode to visible light is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the resistivity of these electrodes is preferably 1×10 -2 Ωcm or less.

[0340] The EL layers 113R, 113G, and 113B are all arranged in an island shape. Figure 16 In the embodiment, the end of the adjacent EL layer 113R overlaps with the end of the EL layer 113G, the end of the adjacent EL layer 113G overlaps with the end of the EL layer 113B, and the end of the adjacent EL layer 113R overlaps with the end of the EL layer 113B. Figure 16 As shown in FIG. 1 , when depositing island-shaped EL layers using a high-definition metal mask, the ends of adjacent EL layers may overlap. However, the present invention is not limited to this. In other words, adjacent EL layers may be separated without overlapping. Furthermore, a display device may have both overlapping and separated portions of adjacent EL layers.

[0341] EL layers 113R, 113G, and 113B each include at least a light-emitting layer. The light-emitting layer contains one or more light-emitting substances. As the light-emitting substance, a substance that emits light in a color such as blue, purple, bluish-purple, green, yellow-green, yellow, orange, or red is suitably used. Alternatively, a substance that emits near-infrared light may be used.

[0342] Examples of the light-emitting substance include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0343] The light-emitting layer may further comprise one or more organic compounds (host material, auxiliary material, etc.) in addition to the light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole transport properties (hole transport material) and a substance with high electron transport properties (electron transport material) may be used. In addition, as the one or more organic compounds, a bipolar substance (a substance with high electron transport properties and hole transport properties, also referred to as a bipolar material) or a TADF material may also be used.

[0344] For example, the light-emitting layer preferably comprises a combination of a phosphorescent material, a hole transport material that easily forms an exciplex, and an electron transport material. By adopting such a structure, it is possible to efficiently obtain light emission by ExTET (Exciplex-Triplet Energy Transfer) that utilizes energy transfer from the exciplex to the luminescent substance (phosphorescent material). By selecting a combination of exciplexes that emit light with a wavelength overlapping with the absorption band on the lowest energy side of the luminescent substance, energy transfer can be smoothed, thereby efficiently obtaining light emission. By adopting the above structure, high efficiency, low voltage drive, and long life of the light-emitting element can be achieved at the same time.

[0345] In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole-injecting properties (hole-injection layer), a layer containing a hole-transporting material (hole-transport layer), a layer containing a substance with high electron-blocking properties (electron-blocking layer), a layer containing a substance with high electron-injecting properties (electron-injection layer), a layer containing an electron-transporting material (electron-transport layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer). Furthermore, the EL layer may include one or both of a bipolar material and a TADF material.

[0346] The light-emitting element may use a low molecular weight compound or a high molecular weight compound, and may also contain an inorganic compound. The layers constituting the light-emitting element may be formed by methods such as vapor deposition (including vacuum vapor deposition), transfer, printing, inkjet, and coating.

[0347] The light-emitting element can adopt a single structure (including a structure with only one light-emitting unit) or a series structure (including a structure with multiple light-emitting units). The light-emitting unit includes at least one light-emitting layer. The series structure has a structure in which multiple light-emitting units are connected in series through a charge generation layer. The charge generation layer has the function of injecting electrons into one of the two light-emitting units and injecting holes into the other when a voltage is applied between a pair of electrodes. By adopting a series structure, a light-emitting element that can emit light with high brightness can be realized. In addition, the series structure can improve reliability because it can reduce the current required to obtain the same brightness compared to the single structure. In addition, the series structure can also be called a stacked structure.

[0348] exist Figure 16 When a tandem-structured light-emitting element is used, it is preferable that the EL layer 113R include multiple light-emitting units emitting red light, the EL layer 113G include multiple light-emitting units emitting green light, and the EL layer 113B include multiple light-emitting units emitting blue light.

[0349] A protective layer 131 is provided on the light emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded by an adhesive layer 142. The substrate 152 is provided with a light shielding layer 117. As a seal for the light emitting element, for example, a solid sealing structure or a hollow sealing structure can be used. Figure 16 In the embodiment, the space between substrate 152 and substrate 151 is filled with adhesive layer 142, i.e., a solid sealing structure is adopted. Alternatively, a hollow sealing structure can be adopted in which the space is filled with an inert gas (nitrogen or argon, etc.). In this case, adhesive layer 142 can also be arranged in a manner that does not overlap with the light-emitting element. In addition, a resin different from the adhesive layer 142 arranged in a frame shape can also be used to fill the space.

[0350] Protective layer 131 is provided at least within display portion 162, preferably covering the entire display portion 162. Providing protective layer 131 over light-emitting elements 130R, 130G, and 130B improves the reliability of the light-emitting elements. Protective layer 131 is preferably provided to cover not only display portion 162 but also connection portion 140 and circuit portion 164. Furthermore, protective layer 131 preferably extends to the ends of display device 100A. Meanwhile, in order to electrically connect FPC 172 to conductive layer 166, a portion of connection portion 204 is provided without protective layer 131.

[0351] The protective layer 131 can be either a single-layer structure or a stacked structure with more than two layers. In addition, there is no restriction on the conductivity of the protective layer 131. As the protective layer 131, at least one of an insulating film, a semiconductor film and a conductive film can be used. When the protective layer 131 includes an inorganic film, the degradation of the light-emitting element can be suppressed, such as preventing the oxidation of the common electrode 115, suppressing the entry of impurities (moisture, oxygen, etc.) into the light-emitting element, etc., thereby improving the reliability of the display device. As the protective layer 131, for example, inorganic insulating films such as oxide insulating films, nitride insulating films, oxynitride insulating films and nitride oxide insulating films can be used. Specific examples of the materials of these inorganic insulating films are as described above. In particular, the protective layer 131 preferably includes a nitride insulating film or a nitride oxide insulating film, and more preferably includes a nitride insulating film.

[0352] Alternatively, an inorganic film including ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, or IGZO may be used as the protective layer 131. The inorganic film preferably has a high resistance, and more specifically, preferably has a resistance higher than that of the common electrode 115. The inorganic film may further contain nitrogen.

[0353] When light emitted from the light-emitting element is extracted through the protective layer 131, the protective layer 131 preferably has high visible light transmittance. For example, ITO, IGZO, and alumina are inorganic materials with high visible light transmittance and are therefore preferred.

[0354] For example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used as the protective layer 131. This stacked structure can suppress the intrusion of impurities (such as water and oxygen) into the EL layer.

[0355] Furthermore, the protective layer 131 may include an organic film. For example, the protective layer 131 may include both an organic film and an inorganic film. Examples of organic films that can be used for the protective layer 131 include organic insulating films that can be used for the insulating layer 235.

[0356] Connecting portion 204 is provided in a region where substrate 151 and substrate 152 do not overlap. In connecting portion 204, wiring 165 is electrically connected to FPC 172 via conductive layer 166 and connecting layer 242. An example of a single-layer structure in which wiring 165 is formed by processing the same conductive film as conductive layer 112b is shown. An example of a single-layer structure in which conductive layer 166 is formed by processing the same conductive film as pixel electrodes 111R, 111G, and 111B is shown. Conductive layer 166 is exposed on the top surface of connecting portion 204. Therefore, connecting portion 204 and FPC 172 can be electrically connected via connecting layer 242.

[0357] The display device 100A employs a top-emission design. Light emitted by the light-emitting element is emitted toward the substrate 152. Substrate 152 is preferably made of a material that has high visible light transmittance. Pixel electrodes 111R, 111G, and 111B are made of a material that reflects visible light, while the counter electrode (common electrode 115) is made of a material that transmits visible light.

[0358] A light-shielding layer 117 is preferably provided on the surface of the substrate 152 on the substrate 151 side. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection portion 140, the circuit portion 164, and the like.

[0359] Alternatively, a colored layer such as a color filter may be provided on the substrate 151 side surface of the substrate 152 or on the protective layer 131. When the color filter is provided so as to overlap with the light-emitting element, the color purity of light emitted from the pixel can be improved.

[0360] In addition, various optical components can be configured on the outside of the substrate 152 (the surface on the opposite side of the substrate 151). As optical components, for example, a polarizer, a phase difference plate, a light diffusion layer (diffusion film, etc.), an anti-reflection layer and a light-concentrating film (condensing film) can be cited. In addition, an antistatic film that suppresses the adhesion of dust, a water-repellent film that is not easily soiled, a hard coating film that suppresses damage during use, an impact absorbing layer and other surface protection layers can also be configured on the outside of the substrate 152. For example, by providing a glass layer or a silicon dioxide layer (SiO x Layer), which can prevent the surface from being soiled or damaged, is preferred. In addition, DLC (diamond-like carbon), aluminum oxide (AlO x ), polyester materials or polycarbonate materials, etc. In addition, as the surface protection layer, preferably a material with high transmittance to visible light is used. In addition, the surface protection layer preferably uses a material with high hardness.

[0361] Glass, quartz, ceramic, sapphire, resin, metal, alloy, semiconductor, or the like can be used for each of substrates 151 and 152. The substrate on the side that extracts light from the light-emitting element uses a material that transmits that light. By using flexible materials for substrates 151 and 152, the flexibility of the display device can be increased, thereby realizing a flexible display. A polarizing plate may also be used as at least one of substrates 151 and 152.

[0362] The following materials can be used for substrate 151 and substrate 152, respectively: polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resins, acrylic resins, polyimide resins, polymethyl methacrylate resins, polycarbonate (PC) resins, polyethersulfone (PES) resins, polyamide resins (such as nylon and aramid), polysiloxane resins, cycloolefin resins, polystyrene resins, polyamide-imide resins, polyurethane resins, polyvinyl chloride resins, polyvinylidene chloride resins, polypropylene resins, polytetrafluoroethylene (PTFE) resins, ABS resins, and cellulose nanofibers. Furthermore, glass having a thickness sufficient to provide flexibility can be used for at least one of substrate 151 and substrate 152.

[0363] When a circular polarizer is superimposed on a display device, it is preferred that a substrate with high optical isotropy be used as the substrate included in the display device. A substrate with high optical isotropy has low birefringence (or, in other words, low birefringence). Examples of films with high optical isotropy include triacetyl cellulose (TAC, also known as triacetyl cellulose) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic resin films.

[0364] As the adhesive layer 142, various curing adhesives such as light-curing adhesives such as ultraviolet curing adhesives, reaction-curing adhesives, heat-curing adhesives, and anaerobic adhesives can be used. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. In particular, materials with low moisture permeability such as epoxy resins are preferably used. In addition, two-liquid mixed resins can also be used. In addition, adhesive sheets can also be used.

[0365] As the connection layer 242 , an anisotropic conductive film (ACF), anisotropic conductive paste (ACP), or the like can be used.

[0366] [Display device 100B]

[0367] Figure 17 The main difference between the display device 100B shown and the display device 100A is that the display device 100B uses a light-emitting element and a coloring layer (color filter, etc.) having an EL layer 113 shared by sub-pixels of different colors, and is a bottom-emission display device. Note that in the following description of the display device, descriptions of parts that are identical to those of the previously described display device may be omitted.

[0368] Light emitted by the light-emitting element is emitted toward the substrate 151. A material having high visible light transmittance is preferably used for the substrate 151. On the other hand, there is no limitation on the light transmittance of the material used for the substrate 152.

[0369] Figure 17 The display device 100B shown includes transistors 205D, 205R, 205G, 205B (not shown), light-emitting elements 130R, 130G, 130B, a coloring layer 132R that transmits red light, a coloring layer 132G that transmits green light, and a coloring layer 132B that transmits blue light, etc. between the substrate 151 and the substrate 152.

[0370] The light emitting element 130R includes a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. Light emitted from the light emitting element 130R is extracted as red light to the outside of the display device 100B through the colored layer 132R.

[0371] The light-emitting element 130G includes a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. Light emitted from the light-emitting element 130G is extracted as green light to the outside of the display device 100B through the colored layer 132G.

[0372] The light-emitting element 130B includes a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. Light emitted from the light-emitting element 130B is extracted as blue light to the outside of the display device 100B through the colored layer 132B.

[0373] The light-emitting elements 130R, 130G, and 130B share the EL layer 113 and the common electrode 115. Compared with a structure in which each sub-pixel of each color has a different EL layer, a structure in which each sub-pixel of each color shares the EL layer 113 can reduce the number of manufacturing steps.

[0374] For example, Figure 17 The light emitting elements 130R, 130G, and 130B shown emit white light. The white light emitted by the light emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of a desired color.

[0375] A light shielding layer 117 is preferably formed between the substrate 151 and the transistor. Figure 17 In the illustrated example, a light-shielding layer 117 is provided over a substrate 151, an insulating layer 153 is provided over the light-shielding layer 117, and transistors 205D, 205R, 205G, and 205B (not shown) are provided over the insulating layer 153. Furthermore, colored layers 132R, 132G, and 132B are provided over an insulating layer 218, and an insulating layer 235 is provided over the colored layers 132R, 132G, and 132B.

[0376] Pixel electrodes 111R, 111G, and 111B are each made of a material with high visible light transmittance. Common electrode 115 is preferably made of a material that reflects visible light. Because low-resistance metals, etc., can be used for common electrode 115 in bottom-emission display devices, voltage drops caused by the resistance of common electrode 115 can be suppressed, achieving high display quality.

[0377] The transistor of one embodiment of the present invention can be miniaturized and have a smaller occupied area, thereby enabling an increase in the aperture ratio of pixels or a reduction in the size of pixels in a bottom emission display device.

[0378] When light-emitting elements 130R, 130G, and 130B employ microcavities, they each emit light having a specific wavelength enhanced within the white light emitted by the EL layer 113. Here, even light-emitting elements employing microcavities are referred to as white-light-emitting elements when employing an EL layer that emits white light.

[0379] The white light-emitting element preferably includes two or more light-emitting layers. In the case of using two light-emitting layers to obtain white light, the light-emitting layers can be selected in such a way that the light-emitting colors of the two light-emitting layers are in a complementary color relationship. For example, by making the light-emitting colors of the first light-emitting layer and the light-emitting colors of the second light-emitting layer complementary colors, a structure in which the light-emitting element as a whole emits white light can be obtained. In addition, in the case of using three or more light-emitting layers to obtain white light, the light-emitting colors of the three or more light-emitting layers can be combined to obtain a structure in which the light-emitting element as a whole emits white light.

[0380] The EL layer 113 preferably includes, for example, a light-emitting layer containing a light-emitting substance that emits blue light and a light-emitting layer containing a light-emitting substance that emits visible light having a wavelength longer than blue. The EL layer 113 preferably includes, for example, a light-emitting layer that emits yellow light and a light-emitting layer that emits blue light. Alternatively, the EL layer 113 preferably includes, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.

[0381] Light-emitting elements emitting white light preferably adopt a series structure. Specifically, the following can be adopted: a two-stage series structure including a light-emitting unit emitting yellow light and a light-emitting unit emitting blue light; a two-stage series structure including a light-emitting unit emitting red and green light, and a light-emitting unit emitting blue light; a three-stage series structure including, in sequence, a light-emitting unit emitting blue light, a light-emitting unit emitting yellow light, yellow-green light, or green light, and a light-emitting unit emitting blue light; or a three-stage series structure including, in sequence, a light-emitting unit emitting blue light, a light-emitting unit emitting yellow light, yellow-green light, or green light, and red light, and a light-emitting unit emitting blue light. For example, examples of the number of layers stacked and the color sequence of the light-emitting unit include a two-stage structure in which B and Y are stacked from the anode side, a two-stage structure in which B and the light-emitting unit X are stacked, a three-stage structure in which B, Y, and B are stacked, and a three-stage structure in which B, X, and B are stacked. Examples of the number of layers stacked and the color sequence of the light-emitting layer in the light-emitting unit X include a two-stage structure in which R and Y are stacked from the anode side, a two-stage structure in which R and G are stacked, a two-stage structure in which G and R are stacked, a three-stage structure in which G, R, and G are stacked, and a three-stage structure in which R, G, and R are stacked. Furthermore, other layers may be provided between the two light-emitting layers.

[0382] Or, for example, Figure 17The illustrated light-emitting elements 130R, 130G, and 130B can also emit blue light. In this case, the EL layer 113 includes one or more light-emitting layers that emit blue light. In sub-pixel 210B emitting blue light, the blue light emitted by light-emitting element 130B can be extracted. Furthermore, in sub-pixel 210R emitting red light and sub-pixel 210G emitting green light, a color conversion layer is provided between light-emitting element 130R or 130G and substrate 151. This converts the blue light emitted by light-emitting element 130R or 130G into light with a longer wavelength, thereby allowing the extraction of red or green light. Furthermore, it is preferable to provide a colored layer 132R between the color conversion layer and substrate 151 in the optical path of light emitted by light-emitting element 130R, and to provide a colored layer 132G between the color conversion layer and substrate 151 in the optical path of light emitted by light-emitting element 130G. In some cases, a portion of the light emitted by a light-emitting element is transmitted through the color conversion layer without being converted by the color conversion layer. By extracting the light that has passed through the color conversion layer through the colored layer, the colored layer absorbs light other than the desired color light, thereby improving the color purity of the light presented by the sub-pixel.

[0383] [Display device 100C]

[0384] Figure 18 Display device 100C shown in the figure is an example of a display device employing an MML (Metal Mask Less) structure. That is, display device 100C includes a light-emitting element manufactured without using a high-definition metal mask. Note that the stacked structure from substrate 151 to insulating layer 235 and the stacked structure from protective layer 131 to substrate 152 are identical to those of display device 100A, and therefore their description will be omitted.

[0385] exist Figure 18 In the embodiment, light emitting elements 130R, 130G, and 130B are provided on the insulating layer 235 .

[0386] The light emitting element 130R includes a conductive layer 124R on the insulating layer 235 , a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114 . Figure 18 Light-emitting element 130R shown emits red light (R). Layer 133R includes a light-emitting layer that emits red light. In light-emitting element 130R, layer 133R and common layer 114 can be collectively referred to as an EL layer. One or both of conductive layer 124R and conductive layer 126R can be referred to as a pixel electrode.

[0387] Likewise, light emitting element 130G includes conductive layer 124G on insulating layer 235 , conductive layer 126G on conductive layer 124G, layer 133G on conductive layer 126G, common layer 114 on layer 133G, and common electrode 115 on common layer 114 . Figure 18 The light emitting element 130G shown emits green light (G). Layer 133G includes a light emitting layer that emits green light.

[0388] Likewise, light emitting element 130B includes conductive layer 124B on insulating layer 235 , conductive layer 126B on conductive layer 124B, layer 133B on conductive layer 126B, common layer 114 on layer 133B, and common electrode 115 on common layer 114 . Figure 18 The light emitting element 130B shown emits blue light (B). Layer 133B includes a light emitting layer that emits blue light.

[0389] In this specification and other documents, an island-shaped layer provided for each light-emitting element in the EL layer included in a light-emitting element is referred to as layer 133R, layer 133G, or layer 133B, and a layer shared by a plurality of light-emitting elements is referred to as common layer 114. Furthermore, in this specification and other documents, layers 133R, 133G, and 133B excluding common layer 114 may be referred to as island-shaped EL layers, EL layers formed in an island shape, or the like.

[0390] Layers 133R, 133G, and 133B are separated from each other. Providing island-shaped EL layers in each light-emitting element suppresses leakage current between adjacent light-emitting elements. This reduces crosstalk caused by unintended light emission, enabling the realization of a display device with a very high contrast ratio.

[0391] Note that in Figure 18 In the figure, the layers 133R, 133G, and 133B are shown to have the same thickness, but the present invention is not limited thereto and the thicknesses of the layers 133R, 133G, and 133B may be different.

[0392] Conductive layer 124R is electrically connected to conductive layer 112b included in transistor 205R via openings provided in insulating layer 106, insulating layer 218, and insulating layer 235. Similarly, conductive layer 124G is electrically connected to conductive layer 112b in transistor 205G, and conductive layer 124B is electrically connected to conductive layer 112b in transistor 205B.

[0393] Conductive layers 124R, 124G, and 124B are formed to cover the openings provided in insulating layer 235. The recessed portions of conductive layers 124R, 124G, and 124B are filled with layer 128, respectively.

[0394] Layer 128 flattens the concave portions of conductive layers 124R, 124G, and 124B. Conductive layers 126R, 126G, and 126B are provided on conductive layers 124R, 124G, and 124B, and electrically connected to conductive layers 124R, 124G, and 124B. Therefore, the areas overlapping the concave portions of conductive layers 124R, 124G, and 124B can also be used as light-emitting areas, thereby increasing the pixel aperture ratio. Conductive layers 124R and 126R are preferably conductive layers that function as reflective electrodes.

[0395] Layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for layer 128. In particular, layer 128 is preferably formed of an insulating material, and an organic insulating material is particularly preferred. For example, the organic insulating material used for insulating layer 237 described above can be used for layer 128.

[0396] Although Figure 18 , the top surface of the layer 128 has a flat portion, but there is no particular limitation on the shape of the layer 128. The top surface of the layer 128 may have at least one of a convex curved surface, a concave curved surface, and a flat surface.

[0397] Furthermore, the height of the top surface of layer 128 may be the same as or substantially the same as the height of the top surface of conductive layer 124R, or may be different from each other. For example, the height of the top surface of layer 128 may be lower or higher than the height of the top surface of conductive layer 124R.

[0398] The ends of conductive layer 126R may also be aligned with the ends of conductive layer 124R, and may also cover the side surfaces of the ends of conductive layer 124R. Each end of conductive layer 124R and conductive layer 126R preferably has a tapered shape. Specifically, each end of conductive layer 124R and conductive layer 126R preferably has a tapered shape with a taper angle of less than 90°. When the ends of the pixel electrode have a tapered shape, layer 133R disposed along the side surfaces of the pixel electrode has an inclined portion. By providing the side surfaces of the pixel electrode with a tapered shape, the EL layer disposed along the side surfaces of the pixel electrode can provide good coverage.

[0399] Since the conductive layers 124G and 126G and the conductive layers 124B and 126B are the same as the conductive layers 124R and 126R, detailed description thereof will be omitted.

[0400] The top and side surfaces of conductive layer 126R are covered by layer 133R. Similarly, the top and side surfaces of conductive layer 126G are covered by layer 133G, and the top and side surfaces of conductive layer 126B are covered by layer 133B. Therefore, the entire area where conductive layers 126R, 126G, and 126B are provided can be used as the light-emitting area of light-emitting elements 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixel.

[0401] Part of the top surface and side surfaces of layers 133R, 133G, and 133B are covered by insulating layers 125 and 127. A common layer 114 is provided on layers 133R, 133G, 133B, and insulating layers 125 and 127, and a common electrode 115 is provided on common layer 114. Both common layer 114 and common electrode 115 are continuous films shared by multiple light-emitting elements.

[0402] exist Figure 18 There is no arrangement between the conductive layer 126R and the layer 133R. Figure 16 In other words, the display device 100C does not have an insulating layer (also known as a partition wall, dam, spacer, etc.) that contacts the pixel electrode and covers the top end of the pixel electrode. Therefore, the spacing between adjacent light-emitting elements can be made very small. Therefore, a high-definition or high-resolution display device can be achieved. In addition, there is no need for a mask for forming the insulating layer, thereby reducing the manufacturing cost of the display device.

[0403] As described above, layer 133R, layer 133G, and layer 133B all include a light-emitting layer. Layer 133R, layer 133G, and layer 133B preferably include a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. In addition, layer 133R, layer 133G, and layer 133B preferably include a light-emitting layer and a carrier blocking layer (hole blocking layer or electron blocking layer) on the light-emitting layer. In addition, layer 133R, layer 133G, and layer 133B may also include a light-emitting layer, a carrier blocking layer on the light-emitting layer, and a carrier transport layer on the carrier blocking layer. The surfaces of layer 133R, layer 133G, and layer 133B are exposed during the manufacturing process of the display device. Therefore, by providing one or both of the carrier transport layer and the carrier blocking layer on the light-emitting layer, the light-emitting layer can be prevented from being exposed to the outermost surface and damage to the light-emitting layer can be reduced. As a result, the reliability of the light-emitting element can be improved.

[0404] The common layer 114 may include, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may include a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. The light-emitting elements 130R, 130G, and 130B share the common layer 114.

[0405] The side surfaces of the layers 133R, 133G, and 133B are covered with the insulating layer 125. The insulating layer 127 covers the side surfaces of the layers 133R, 133G, and 133B via the insulating layer 125.

[0406] By covering the side surfaces of the layers 133R, 133G, and 133B (or even covering a portion of their top surfaces) with at least one of the insulating layer 125 and the insulating layer 127, the common layer 114 (or the common electrode 115) can be prevented from contacting the pixel electrode and the side surfaces of the layers 133R, 133G, and 133B, thereby preventing short circuits in the light-emitting elements. This improves the reliability of the light-emitting elements.

[0407] The insulating layer 125 is preferably in contact with the side surfaces of the layers 133R, 133G, and 133B. The structure in which the insulating layer 125 is in contact with the layers 133R, 133G, and 133B can prevent the layers 133R, 133G, and 133B from peeling off, thereby improving the reliability of the light-emitting element.

[0408] The insulating layer 127 is provided on the insulating layer 125 so as to fill the recessed portion of the insulating layer 125. The insulating layer 127 preferably covers at least a portion of the side surface of the insulating layer 125.

[0409] By providing the insulating layers 125 and 127, the spaces between adjacent island-shaped layers can be filled. This can reduce the unevenness of the formed surface of layers (e.g., carrier injection layers, common electrodes, etc.) disposed on the island-shaped layers, thereby further flattening the surface. This improves the coverage of the carrier injection layers and common electrodes.

[0410] The common layer 114 and the common electrode 115 are provided on the layer 133R, the layer 133G, the layer 133B, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are provided, steps are generated due to the region where the pixel electrode and the island EL layer are provided and the region where the pixel electrode and the island EL layer are not provided (the region between the light-emitting elements). The display device of one embodiment of the present invention can flatten the steps by including the insulating layer 125 and the insulating layer 127, thereby improving the coverage of the common layer 114 and the common electrode 115. Therefore, poor connection caused by disconnection can be suppressed. Alternatively, the increase in resistance caused by local thinning of the common electrode 115 due to the steps can be suppressed.

[0411] The top surface of insulating layer 127 preferably has a highly flat shape. The top surface of insulating layer 127 may also have at least one of a flat surface, a convex surface, and a concave surface. For example, the top surface of insulating layer 127 preferably has a highly flat, smoothly convex surface.

[0412] The insulating layer 125 may be an insulating layer composed of an inorganic material. For example, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used as the insulating layer 125. Specific examples of the materials for these inorganic insulating films are described above. The insulating layer 125 may have a single-layer structure or a stacked-layer structure. Aluminum oxide is particularly preferred because it has a high selectivity with the EL layer during etching and protects the EL layer during the formation of the insulating layer 127. In particular, using an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by ALD for the insulating layer 125 allows for a structure with fewer pinholes and excellent EL layer protection. Alternatively, the insulating layer 125 may have a stacked-layer structure of a film formed by ALD and a film formed by sputtering. For example, the insulating layer 125 may have a stacked-layer structure of an aluminum oxide film formed by ALD and a silicon nitride film formed by sputtering.

[0413] The insulating layer 125 preferably functions as a barrier insulating layer against at least one of water and oxygen. Furthermore, the insulating layer 125 preferably functions to suppress the diffusion of at least one of water and oxygen. Furthermore, the insulating layer 125 preferably functions to capture or immobilize (also known as gettering) at least one of water and oxygen.

[0414] In this specification, etc., a barrier insulating layer refers to an insulating layer having barrier properties. Furthermore, in this specification, etc., barrier properties refer to the ability to inhibit the diffusion of the corresponding substance (also referred to as low permeability). Alternatively, they refer to the ability to capture or immobilize the corresponding substance (also known as gettering).

[0415] When the insulating layer 125 is used as a blocking insulating layer or an insulating layer having a gettering function, it can have a structure that suppresses the entry of impurities (typically, at least one of water and oxygen) that might diffuse from the outside into each light-emitting element. This structure enables a highly reliable light-emitting element and a highly reliable display device to be provided.

[0416] Furthermore, the impurity concentration of the insulating layer 125 is preferably low. This can prevent impurities from entering the EL layer from the insulating layer 125 and degrading the EL layer. Furthermore, by reducing the impurity concentration in the insulating layer 125, the barrier properties against at least one of water and oxygen can be improved. For example, it is preferable that either the hydrogen concentration or the carbon concentration in the insulating layer 125 be sufficiently low, and preferably both the hydrogen concentration and the carbon concentration be sufficiently low.

[0417] The insulating layer 127 provided on the insulating layer 125 has the function of flattening the large unevenness of the insulating layer 125 formed between adjacent light-emitting elements. In other words, the inclusion of the insulating layer 127 improves the flatness of the surface on which the common electrode 115 is formed.

[0418] An insulating layer composed of an organic material can be suitably used as the insulating layer 127. A photosensitive organic resin is preferably used as the organic material, and for example, a photosensitive resin composition containing an acrylic resin is preferably used. Note that in this specification, etc., the term "acrylic resin" may refer to a broad range of acrylic polymers, rather than just polymethacrylate or methacrylic resin.

[0419] In addition, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin and precursors of the above resins can also be used as the insulating layer 127. In addition, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinyl pyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose or alcohol-soluble polyamide resin can also be used as the insulating layer 127. In addition, photoresist can also be used as the photosensitive organic resin. As the photosensitive organic resin, a positive material or a negative material can be used.

[0420] A material that absorbs visible light can also be used as the insulating layer 127. By absorbing the light emitted by the light-emitting element, the insulating layer 127 can suppress light leakage from the light-emitting element to adjacent light-emitting elements through the insulating layer 127 (stray light). Therefore, the display quality of the display device can be improved. In addition, the display quality can be improved even without using a polarizing plate in the display device, thereby achieving a lighter and thinner display device.

[0421] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, resin materials with light absorption properties (e.g., polyimide), and resin materials that can be used for color filters (color filter materials). In particular, the use of resin materials that are formed by mixing or laminating two or more color filter materials is preferred because they can enhance the visible light shielding effect. In particular, by mixing three or more color filter materials, a black or nearly black resin layer can be achieved.

[0422] [Display device 100D]

[0423] An example in which a light-emitting element is used as a display element has been described above. Now, a liquid crystal display device in which a liquid crystal element is used as a display element will be described.

[0424] Liquid crystal elements included in the display device can use elements of various structures. Typically, transmissive liquid crystal elements employing VA (Vertical Alignment) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane-Switching) mode, etc. can be used. Furthermore, the liquid crystal element can be not only a transmissive liquid crystal element but also a reflective or semi-transmissive liquid crystal element. Furthermore, the display device is preferably a normally black liquid crystal display device.

[0425] For example, as the VA mode, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, or the like can be used.

[0426] Liquid crystal elements using various modes can be used. For example, in addition to the VA mode, FFS mode, and IPS mode, liquid crystal elements using the TN (Twisted Nematic) mode, the ASM (Axially Symmetrically Aligned Microcell) mode, the OCB (Optically Compensated Birefringence) mode, the FLC (Ferroelectric Liquid Crystal) mode, the AFLC (Antiferroelectric Liquid Crystal) mode, the ECB (Electrically Controlled Birefringence) mode, and the guest-host mode can also be used.

[0427] Here, a liquid crystal display device is a display device that uses polarization and the optical modulation effect of liquid crystals to control the transmission or non-transmission of light. The optical modulation effect of liquid crystals is controlled by the electric field (horizontal electric field, vertical electric field, or tilted electric field) applied to the liquid crystals. Liquid crystals that can be used in liquid crystal elements include thermotropic liquid crystals, low molecular liquid crystals, high molecular liquid crystals, polymer dispersed liquid crystals (PDLC: Polymer Dispersed Liquid Crystal), polymer network liquid crystals (PNLC: Polymer Network Liquid Crystal), ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, homogeneous phases, etc. depending on the conditions. In addition, as the liquid crystal material, either positive liquid crystals or negative liquid crystals can be used, and the appropriate liquid crystal material can be selected according to the mode or design used.

[0428] Figure 19 The display device 100D shown is an FFS mode liquid crystal display device.

[0429] The substrate 151 and the substrate 152 are bonded together using an adhesive layer 144. Liquid crystal 262 is sealed in the area surrounded by the substrate 151, the substrate 152, and the adhesive layer 144. A polarizing plate 260a is located on the outer surface of the substrate 152, and a polarizing plate 260b is located on the outer surface of the substrate 151. Although not shown, a backlight may be provided outside the polarizing plate 260a or outside the polarizing plate 260b.

[0430] Transistors 205D, 205R, 205G, and 205B (not shown), a connection portion 204, a spacer 224, and the like are provided on the substrate 151. Transistor 205D is provided in the circuit portion 164, while transistors 205R and 205G are provided in the display portion 162. The conductive layer 112b included in transistors 205R and 205G is electrically connected to the pixel electrode 111 of the liquid crystal element 60.

[0431] The substrate 152 is provided with colored layers 132R and 132G, a light-shielding layer 117, an insulating layer 225, and the like.

[0432] Each of the transistors 205D, 205R, and 205G includes a conductive layer 112a, a conductive layer 112b, a semiconductor layer 108, a conductive layer 107, a conductive layer 109, an insulating layer 106, and a conductive layer 104. The conductive layer 112a serves as a source electrode or a drain electrode, and the conductive layer 112b serves as the other. The conductive layer 107 serves as a source electrode or a drain electrode, and the conductive layer 109 serves as the other. The conductive layer 104 serves as a gate electrode. A portion of the insulating layer 106 serves as a gate insulating layer.

[0433] Furthermore, the transistors 205D, 205R, and 205G are covered with an insulating layer 218. The insulating layer 218 serves as a protective layer for the transistors 205D, 205R, and 205G.

[0434] The subpixels included in the display unit 162 include transistors, a liquid crystal element 60, and a colored layer. For example, a subpixel that emits red light includes a transistor 205R, a liquid crystal element 60, and a colored layer 132R that transmits red light. Furthermore, a subpixel that emits green light includes a transistor 205G, a liquid crystal element 60, and a colored layer 132G that transmits green light. Although not shown, a subpixel that emits blue light similarly includes a transistor, a liquid crystal element 60, and a colored layer that transmits blue light.

[0435] The liquid crystal element 60 includes a common electrode 115, a pixel electrode 111, and liquid crystal 262. The common electrode 115 is disposed on the insulating layer 218, and the insulating layer 214 is disposed on the common electrode 115. In addition, the pixel electrode 111 is disposed on the insulating layer 214.

[0436] The pixel electrode 111 and the common electrode 115 allow visible light to pass through. In other words, the liquid crystal element 60 can be a transmissive liquid crystal element. For example, when the backlight source is arranged on one side of the substrate 151, light from the backlight source polarized by the polarizer 260b passes through the substrate 151, the liquid crystal element 60, and the substrate 152 to reach the polarizer 260a. At this time, the orientation of the liquid crystal 262 can be controlled by the voltage applied between the pixel electrode 111 and the common electrode 115, thereby controlling the optical modulation of the light. In other words, the intensity of the light emitted by the polarizer 260a can be controlled. In addition, because light outside the specified wavelength range of the incident light is absorbed by the coloring layer, the extracted light becomes, for example, red light.

[0437] Here, as the polarizer 260a, a linear polarizer or a circular polarizer can be used. For example, a polarizer formed by laminating a linear polarizer and a quarter-wave phase difference plate can be used. By using a circular polarizer as the polarizer 260a, external light reflection can be suppressed.

[0438] When a circular polarizer is used as polarizer 260a, a circular polarizer or a conventional linear polarizer may be used as polarizer 260b. A desired contrast ratio can be achieved by adjusting the cell gap, alignment, and drive voltage of the liquid crystal element used in liquid crystal element 60 according to the type of polarizer used for polarizers 260a and 260b.

[0439] A connection portion 204 is provided in a region near the end of the substrate 151. In the connection portion 204, the wiring 165 is electrically connected to the FPC 172 through the conductive layer 166 and the connection layer 242. The wiring 165 is connected to the wiring 165 through an opening provided in the insulating layer 110. Figure 19 In the illustrated structure, an example is shown in which the wiring 165 is formed using the same material and process as the conductive layer 112a and the conductive layer 107, and the conductive layer 166 is formed using the same material and process as the conductive layer 112b.

[0440] The pixel electrode 111 has a comb-like shape or a shape with slits in a plan view. The pixel electrode 111 overlaps with the common electrode 115. The region overlapping with the colored layer includes a portion of the common electrode 115 where the pixel electrode 111 is not disposed.

[0441] In addition, in the liquid crystal element 60, both the pixel electrode 111 and the common electrode 115 can have a comb-tooth-like top surface. Alternatively, as shown in the display device 100D, in the liquid crystal element 60, by providing only one of the pixel electrode 111 and the common electrode 115 with a comb-tooth-like top surface, a structure can be formed in which the pixel electrode 111 and the common electrode 115 partially overlap. This allows the capacitance between the pixel electrode 111 and the common electrode 115 to be used as a storage capacitor, eliminating the need for a separate capacitor element and thereby increasing the aperture ratio of the display device.

[0442] An insulating layer 225 is provided on the substrate 152 side to cover the colored layers 132R and 132G and the light-shielding layer 117. The insulating layer 225 serves as a protective layer to prevent components contained in the colored layers 132R and 132G from diffusing into the liquid crystal 262. The insulating layer 225 can also function as a planarizing film. The insulating layer 225 can be formed using a light-transmitting organic resin.

[0443] Furthermore, an alignment film for controlling the alignment of the liquid crystal 262 may be provided on the surfaces of the pixel electrode 111 , the insulating layer 214 , the insulating layer 225 , and the like that are in contact with the liquid crystal 262 .

[0444] The structural examples of the display device have been described above.

[0445] [Example of a method for manufacturing a display device]

[0446] Next, we will describe a method for manufacturing a display device using an MML (Metal Mask Less) structure. Here, we will detail the steps for manufacturing light-emitting elements without using a high-definition metal mask. Figure 20 shows cross-sectional views of the three light-emitting elements and the connector 140 included in the display portion 162 during various steps.

[0447] When manufacturing a light-emitting element, a vacuum process such as an evaporation method and a solution process such as a spin coating method and an inkjet method can be utilized. As an evaporation method, physical evaporation methods (PVD methods) such as sputtering, ion plating, ion beam evaporation, molecular beam evaporation, and vacuum evaporation methods and chemical vapor deposition methods (CVD methods) can be cited. In particular, a functional layer (hole injection layer, hole transport layer, hole blocking layer, light-emitting layer, electron blocking layer, electron transport layer, electron injection layer, charge generation layer, etc.) included in the EL layer can be formed using evaporation (vacuum evaporation method), coating method (dip coating method, dye coating method, rod coating method, spin coating method, spray coating method), printing method (inkjet method, screen printing (porous plate printing) method, offset printing (lithography) method, flexographic printing (letterpress printing) method, gravure printing method or micro-contact printing method, etc.) and other methods.

[0448] The island-shaped layers (including the light-emitting layer) produced in the display device manufacturing method described below are not formed using a high-precision metal mask, but are formed by depositing the light-emitting layer on the entire surface and then processing it using photolithography. Therefore, it is possible to realize a high-definition display device or a display device with a high aperture ratio, which has been difficult to achieve so far. Furthermore, since the light-emitting layer can be formed separately for each color, a display device with extremely clear, high-contrast, and high display quality can be realized. In addition, by providing a sacrificial layer on the light-emitting layer, it is possible to reduce damage to the light-emitting layer during the manufacturing process of the display device, thereby improving the reliability of the light-emitting element.

[0449] For example, when a display device is composed of three light-emitting elements: a light-emitting element emitting blue light, a light-emitting element emitting green light, and a light-emitting element emitting red light, three island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer three times and using photolithography processing.

[0450] First, pixel electrodes 111R, 111G, 111B and a conductive layer 123 are formed on a substrate 151 on which transistors 205R, 205G, 205B, etc. (not shown) are provided. Figure 20A ).

[0451] The conductive film that will become the pixel electrodes can be formed by, for example, sputtering or vacuum evaporation. A resist mask is formed on the conductive film using a photolithography process, and then the conductive film is processed to form the pixel electrodes 111R, 111G, and 111B and the conductive layer 123. The conductive film can be processed using either wet etching or dry etching, or both.

[0452] Next, a film 133Bf (which will later become the layer 133B) is formed on the pixel electrodes 111R, 111G, and 111B. Figure 20A ). The film 133Bf (latter layer 133B) includes a light-emitting layer that emits blue light.

[0453] This embodiment shows an example in which an island-shaped EL layer is first formed in a light-emitting element that emits blue light, and then island-shaped EL layers are formed in light-emitting elements that emit light of other colors.

[0454] During the process of forming the island-shaped EL layer, the pixel electrodes in the second and subsequent color light-emitting elements may be damaged in the previous process. As a result, the driving voltage of the second and subsequent color light-emitting elements may increase.

[0455] Therefore, when manufacturing a display device according to one embodiment of the present invention, it is preferable to start manufacturing the island-shaped EL layer from the light-emitting element emitting light with the shortest wavelength (e.g., a blue light-emitting element). For example, it is preferable to manufacture the island-shaped EL layers in the order of blue, green, and red, or blue, red, and green.

[0456] This allows the interface between the pixel electrode and the EL layer in the blue light-emitting element to be well maintained, thereby suppressing the increase in the driving voltage of the blue light-emitting element. Furthermore, the lifespan of the blue light-emitting element can be extended, and reliability can be improved. Note that compared to the blue light-emitting element, the red and green light-emitting elements are less affected by the increase in driving voltage, thereby reducing the driving voltage and improving the reliability of the display device as a whole.

[0457] Note that the order of manufacturing the island-shaped EL layers is not limited to the above order, and for example, the island-shaped EL layers may be manufactured in the order of red, green, and blue.

[0458] like Figure 20A As shown, film 133Bf is not formed on conductive layer 123. For example, film 133Bf can be deposited only in desired areas using a range mask. By employing a deposition process using a range mask and a processing process using a resist mask, a light-emitting element can be manufactured using a relatively simple process.

[0459] The heat-resistant temperature of the compound contained in film 133Bf is preferably 100°C to 180°C, more preferably 120°C to 180°C, and even more preferably 140°C to 180°C. This improves the reliability of the light-emitting element. Furthermore, the upper temperature limit allowed during the display device manufacturing process can be increased. This broadens the range of materials and formation methods available for display devices, thereby increasing yield and reliability.

[0460] As the heat-resistant temperature, for example, any of the glass transition temperature, softening point, melting point, thermal decomposition temperature and 5% weight loss temperature may be used, but the lowest temperature among these temperatures is preferably used.

[0461] The film 133Bf can be formed by, for example, vapor deposition, specifically, vacuum deposition, or by transfer, printing, inkjet, or coating.

[0462] Next, a sacrificial layer 118B ( Figure 20A ) The sacrificial layer 118B can be formed by forming a resist mask on a film that will later become the sacrificial layer 118B using a photolithography process and then processing the film.

[0463] By providing the sacrificial layer 118B on the film 133Bf, damage to the film 133Bf during the manufacturing process of the display device can be reduced, and the reliability of the light-emitting element can be improved.

[0464] The sacrificial layer 118B is preferably provided so as to cover the ends of the pixel electrodes 111R, 111G, and 111B. Thus, the ends of the layer 133B to be formed in a subsequent step are located outside the ends of the pixel electrode 111B. Since the entire top surface of the pixel electrode 111B can be used as a light-emitting area, the aperture ratio of the pixel can be increased. Furthermore, the ends of the layer 133B may be damaged in the steps after forming the layer 133B. Therefore, it is preferably located outside the ends of the pixel electrode 111B, i.e., it is preferably not used as a light-emitting area. This can suppress uneven characteristics of the light-emitting element and improve reliability.

[0465] Furthermore, by covering the top and side surfaces of pixel electrode 111B with layer 133B, subsequent steps after forming layer 133B can be performed without exposing pixel electrode 111B. Exposing the end of pixel electrode 111B may cause corrosion during etching or other processes. Suppressing corrosion of pixel electrode 111B can improve the yield and characteristics of light-emitting elements.

[0466] Furthermore, it is preferable that the sacrificial layer 118B is further provided at a position overlapping with the conductive layer 123. This can prevent the conductive layer 123 from being damaged during the manufacturing process of the display device.

[0467] The sacrificial layer 118B is made of a film that is highly resistant to the processing conditions of the film 133Bf, and more specifically, a film that can increase the etching selectivity with the film 133Bf.

[0468] Sacrificial layer 118B is formed at a temperature lower than the heat resistance temperature of each compound included in film 133Bf. The substrate temperature during formation of sacrificial layer 118B is typically 200°C or lower, preferably 150°C or lower, more preferably 120°C or lower, further preferably 100°C or lower, and even more preferably 80°C or lower.

[0469] When the heat-resistant temperature of the compound contained in film 133Bf is high, the deposition temperature of sacrificial layer 118B can be increased, which is preferable. For example, the substrate temperature during formation of sacrificial layer 118B can be set to 100°C or higher, 120°C or higher, or 140°C or higher. A higher deposition temperature allows for the formation of a denser inorganic insulating film with higher barrier properties. Therefore, by depositing the sacrificial layer at these temperatures, damage to film 133Bf can be further reduced, thereby improving the reliability of the light-emitting element.

[0470] The deposition temperature of other layers (eg, insulating film 125 f ) formed on the film 133Bf is the same as described above.

[0471] The sacrificial layer 118B can be formed by, for example, sputtering, ALD (including thermal ALD and PEALD), CVD, or vacuum evaporation, or by the aforementioned wet deposition method.

[0472] The sacrificial layer 118B (a layer provided in contact with the film 133Bf when the sacrificial layer 118B has a stacked structure) is preferably formed using a formation method that causes less damage to the film 133Bf. For example, ALD or vacuum evaporation is more preferable than sputtering.

[0473] The sacrificial layer 118B can be processed by wet etching or dry etching. The sacrificial layer 118B is preferably processed by anisotropic etching.

[0474] By using a wet etching method, damage to the film 133Bf during processing of the sacrificial layer 118B can be reduced compared to dry etching methods. When using a wet etching method, for example, a developer, a tetramethylammonium hydroxide (TMAH) aqueous solution, dilute hydrofluoric acid, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a mixed solution containing two or more of the above is preferably used. In addition, when using a wet etching method, a mixed acid solution containing water, phosphoric acid, dilute hydrofluoric acid, and nitric acid can also be used. Note that the solution used for the wet etching process can be alkaline or acidic.

[0475] As the sacrificial layer 118B, for example, one or more of a metal film, an alloy film, a metal oxide film, a semiconductor film, an inorganic insulating film, and an organic insulating film can be used.

[0476] As the sacrificial layer 118B, for example, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, titanium, aluminum, yttrium, zirconium, and tantalum, or alloy materials containing these metal materials can be used.

[0477] The sacrificial layer 118B can use metal oxides such as In-Ga-Zn oxide, indium oxide, In-Zn oxide, In-Sn oxide, indium titanium oxide (In-Ti oxide), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide), and indium tin oxide containing silicon.

[0478] Note that element M (M is one or more of aluminum, silicon, boron, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) may be used instead of gallium.

[0479] For example, semiconductor materials such as silicon or germanium are preferably used as materials that are well suited for semiconductor manufacturing processes. Alternatively, oxides or nitrides of the aforementioned semiconductor materials may be used. Alternatively, non-metallic materials such as carbon or compounds thereof may be used. Alternatively, metals such as titanium, tantalum, tungsten, chromium, and aluminum, or alloys containing one or more of these, may be used. Alternatively, oxides of the aforementioned metals such as titanium oxide or chromium oxide, or nitrides such as titanium nitride, chromium nitride, or tantalum nitride may be used.

[0480] Alternatively, various inorganic insulating films that can be used for the protective layer 131 can be used as the sacrificial layer 118B. In particular, an oxide insulating film is preferred because its adhesion to the film 133Bf is higher than that of a nitride insulating film. For example, inorganic insulating materials such as aluminum oxide, hafnium oxide, and silicon oxide can be used for the sacrificial layer 118B. For example, an aluminum oxide film can be formed using the ALD method as the sacrificial layer 118B. Using the ALD method is preferred because it reduces damage to the substrate (particularly the film 133Bf).

[0481] For example, the sacrificial layer 118B may have a stacked structure of an inorganic insulating film (e.g., an aluminum oxide film) formed using ALD and an inorganic film (e.g., an In—Ga—Zn oxide film, a silicon film, or a tungsten film) formed using sputtering.

[0482] In addition, the same inorganic insulating film can be used for both the sacrificial layer 118B and the insulating layer 125 formed later. For example, an aluminum oxide film formed using the ALD method can be used for both the sacrificial layer 118B and the insulating layer 125. Here, the sacrificial layer 118B and the insulating layer 125 can be deposited under the same deposition conditions or different deposition conditions. For example, by depositing the sacrificial layer 118B under the same conditions as the insulating layer 125, the sacrificial layer 118B can be formed as an insulating layer with high barrier properties against at least one of water and oxygen. On the other hand, the sacrificial layer 118B is a layer that is mostly or entirely removed in a subsequent step, so it is preferably easy to process. Therefore, the sacrificial layer 118B is preferably deposited under conditions where the substrate temperature is lower than that of the insulating layer 125 during deposition.

[0483] An organic material can also be used as sacrificial layer 118B. For example, a material that is soluble in a solvent that is chemically stable at least to the film located at the top of film 133Bf can be used as the organic material. In particular, a material that is soluble in water or alcohol can be suitably used. When depositing the above-mentioned material, it is preferable to apply the material by the above-mentioned wet deposition method while it is dissolved in a solvent such as water or alcohol, and then perform a heat treatment to evaporate the solvent. In this case, by performing the heat treatment in a reduced pressure atmosphere, the solvent can be removed at a low temperature and in a short time, thereby reducing thermal damage to film 133Bf, which is preferable.

[0484] Alternatively, the sacrificial layer 118B may be made of an organic resin such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinyl pyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, alcohol-soluble polyamide resin, or fluororesin such as perfluoropolymer.

[0485] For example, the sacrificial layer 118B may have a stacked structure of an organic film (eg, a PVA film) formed by evaporation or the aforementioned wet deposition method and an inorganic film (eg, a silicon nitride film) formed by sputtering.

[0486] Note that a portion of the sacrificial film may remain as a sacrificial layer in the display device of one embodiment of the present invention.

[0487] Next, the sacrificial layer 118B is used as a hard mask processing film 133Bf to form a layer 133B ( Figure 20B ).

[0488] Therefore, if Figure 20B As shown, the stacked structure of layer 133B and sacrificial layer 118B remains on pixel electrode 111B. Pixel electrodes 111R and 111G are exposed. Furthermore, sacrificial layer 118B remains on conductive layer 123 in a region corresponding to connection portion 140 .

[0489] The film 133Bf is preferably processed by anisotropic etching. Anisotropic dry etching is particularly preferred. Alternatively, wet etching may be used.

[0490] Then, the same steps as the step of forming the film 133Bf, the step of forming the sacrificial layer 118B, and the step of forming the layer 133B are repeated twice by changing at least the light-emitting material, thereby forming a stacked structure of the layer 133R and the sacrificial layer 118R on the pixel electrode 111R and a stacked structure of the layer 133G and the sacrificial layer 118G on the pixel electrode 111G ( Figure 20C Specifically, layer 133R is formed to include a light-emitting layer that emits red light, and layer 133G is formed to include a light-emitting layer that emits green light. Sacrificial layers 118R and 118G can use the same material as that used for sacrificial layer 118B, and can use different materials.

[0491] Note that the side surfaces of the layers 133B, 133G, and 133R are preferably perpendicular or substantially perpendicular to the surface on which they are formed. For example, the angle formed between the surface on which they are formed and these side surfaces is preferably not less than 60 degrees and not more than 90 degrees.

[0492] As described above, the distance between two adjacent layers among layers 133B, 133G, and 133R formed using photolithography can be reduced to 8 μm or less, 5 μm or less, 3 μm or less, 2 μm or less, or 1 μm or less. This distance can be defined, for example, by the distance between two adjacent opposing ends of layers 133B, 133G, and 133R. By reducing the distance between island-shaped EL layers as described above, a display device with high definition and a high aperture ratio can be provided.

[0493] Next, an insulating film 125f, which will later become the insulating layer 125, is formed to cover the pixel electrode, the layer 133B, the layer 133G, the layer 133R, the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R, and an insulating layer 127 ( Figure 20D ).

[0494] The insulating film 125f is preferably formed to have a thickness of 3 nm or more, 5 nm or more, or 10 nm or more and 200 nm or less, 150 nm or less, 100 nm or less, or 50 nm or less.

[0495] The insulating film 125f is preferably formed by, for example, ALD. Using ALD is preferred because it reduces deposition damage and allows for deposition of a film with high coverage. For example, an aluminum oxide film is preferably formed by ALD as the insulating film 125f.

[0496] Alternatively, the insulating film 125f may be formed by sputtering, CVD, or plasma CVD, which have a deposition rate faster than that of ALD. This allows a highly reliable display device to be manufactured with high productivity.

[0497] The insulating film to be the insulating layer 127 is preferably formed by the above-mentioned wet deposition method (e.g., spin coating) using a photosensitive resin composition containing an acrylic resin. Preferably, a heat treatment (also called pre-baking) is performed after deposition to remove the solvent in the insulating film. Then, a portion of the insulating film is irradiated with visible light or ultraviolet light to make a portion of the insulating film photosensitive. Then, development is performed to remove the exposed area in the insulating film. Then, a heat treatment (also called post-baking) is performed. Thus, a Figure 20D The insulating layer 127 is shown. Note that the shape of the insulating layer 127 is not limited to Figure 20D For example, the top surface of the insulating layer 127 may have one or more of a convex curved surface, a concave curved surface, and a flat surface. In addition, the insulating layer 127 may also cover the side surface of at least one end of the insulating layer 125, the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R.

[0498] Then, if Figure 20E As shown, etching is performed using insulating layer 127 as a mask to remove insulating film 125f and portions of sacrificial layers 118B, 118G, and 118R. This results in openings being formed in sacrificial layers 118B, 118G, and 118R, respectively, exposing the top surfaces of layers 133G, 133G, and 133R, as well as conductive layer 123. Note that portions of sacrificial layers 118B, 118G, and 118R may remain at locations overlapping with insulating layer 127 and insulating layer 125 (see sacrificial layers 119B, 119G, and 119R).

[0499] The etching process can be performed by dry etching or wet etching. In addition, when the insulating film 125f is deposited using the same material as the sacrificial layers 118B, 118G, and 118R, the etching process can be performed at once, which is preferable.

[0500] As described above, by providing insulating layer 127, insulating layer 125, sacrificial layer 118B, sacrificial layer 118G, and sacrificial layer 118R, it is possible to suppress poor connection due to disconnected portions between the light-emitting elements and increased resistance due to locally thin portions in common layer 114 and common electrode 115. Consequently, the display device according to one embodiment of the present invention can improve display quality.

[0501] Next, a common layer 114 and a common electrode 115 are sequentially formed on the insulating layer 127, the layer 133B, the layer 133G, and the layer 133R. Figure 20F ).

[0502] The common layer 114 can be formed by evaporation (including vacuum evaporation), transfer, printing, inkjet, coating, or the like.

[0503] The common electrode 115 can be formed by, for example, sputtering or vacuum deposition, or by laminating a film formed by vapor deposition and a film formed by sputtering.

[0504] As described above, in a method for manufacturing a display device according to one embodiment of the present invention, the island-shaped layer 133B, the island-shaped layer 133G, and the island-shaped layer 133R are not formed using a high-precision metal mask but are formed by depositing a film on one surface and then processing it, so that the island-shaped layer can be formed with a uniform thickness. In addition, a high-definition display device or a display device with a high aperture ratio can be realized. In addition, even if the clarity or aperture ratio is high and the distance between sub-pixels is extremely small, the contact between the layers 133B, 133G, and 133R in adjacent sub-pixels can be suppressed. Thus, leakage current between sub-pixels can be suppressed. Therefore, crosstalk caused by unintentional light emission can be suppressed, thereby realizing a display device with a very high contrast ratio.

[0505] Furthermore, by providing an insulating layer 127 having tapered ends between adjacent island-shaped EL layers, disconnection during formation of the common electrode 115 can be suppressed, and locally thin portions of the common electrode 115 can be prevented from forming. This prevents connection failures caused by disconnected portions and increases in resistance caused by locally thin portions in the common layer 114 and the common electrode 115. Consequently, a display device according to one embodiment of the present invention can achieve both high definition and high display quality.

[0506] The above is the description of an example of a method for manufacturing a display device.

[0507] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0508] (Implementation 4)

[0509] In this embodiment, an electronic device according to one embodiment of the present invention is described with reference to FIG. 21 to FIG. 23 .

[0510] The electronic device of this embodiment includes a display device according to one embodiment of the present invention in its display portion. The display device according to one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, it can be used in the display portions of various electronic devices.

[0511] Furthermore, the semiconductor device of one embodiment of the present invention can be used in parts other than the display portion of an electronic device. For example, using the semiconductor device of one embodiment of the present invention in a control portion of an electronic device is preferred because it can achieve low power consumption.

[0512] Examples of electronic devices include televisions, desktop or notebook personal computers, displays for computers, digital signage, large-scale game consoles such as pinball machines, and other electronic devices with relatively large screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices.

[0513] In particular, because the display device according to one embodiment of the present invention can improve clarity, it can be suitably used in electronic devices with smaller display units. Examples of such electronic devices include watch-type and bracelet-type information terminals (wearable devices), wearable devices that can be worn on the head, VR devices such as head-mounted displays, and glasses-type AR and MR devices.

[0514] The display device of one embodiment of the present invention preferably has an extremely high resolution such as HD (pixel number is 1280×720), FHD (pixel number is 1920×1080), WQHD (pixel number is 2560×1440), WQXGA (pixel number is 2560×1600), 4K (pixel number is 3840×2160), 8K (pixel number is 7680×4320), etc. In particular, it is preferably set to a resolution of 4K, 8K or above. In addition, the pixel density (clarity) of the display device of one embodiment of the present invention is preferably 100ppi or more, preferably 300ppi or more, more preferably 500ppi or more, further preferably 1000ppi or more, further preferably 2000ppi or more, further preferably 3000ppi or more, further preferably 5000ppi or more, further preferably 7000ppi or more. By using a display device with either or both high resolution and high definition, the sense of realism and depth can be further enhanced. Furthermore, there are no particular limitations on the screen ratio (aspect ratio) of the display device according to one embodiment of the present invention. For example, the display device can accommodate various screen ratios, such as 1:1 (square), 4:3, 16:9, and 16:10.

[0515] The electronic device of this embodiment may also include a sensor (the sensor has the function of detecting, detecting or measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, smell or infrared).

[0516] The electronic device of this embodiment can have various functions. For example, it can have the following functions: the function of displaying various information (static images, dynamic images, text images, etc.) on the display unit; the function of using a touch panel; the function of displaying a calendar, date, or time; the function of executing various software (programs); the function of conducting wireless communications; the function of reading programs or data stored in a storage medium; etc.

[0517] use 21A to 21D This article describes an example of a wearable device that can be worn on the head. These wearable devices can display at least one of AR content, VR content, SR content, and MR content. Electronic devices that display at least one of AR, VR, SR, and MR content can enhance the user's sense of immersion.

[0518] Figure 21A The electronic device 700A shown and Figure 21B The electronic devices 700B shown include a pair of display panels 751, a pair of frames 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical components 753, a frame 757 and a pair of nose pads 758.

[0519] The display device of one embodiment of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of displaying extremely high definition can be realized.

[0520] Both electronic devices 700A and 700B can project the image displayed by display panel 751 onto display area 756 in optical member 753. Because optical member 753 is light-transmissive, the user can see the image displayed in the display area superimposed on the transmitted image seen through optical member 753. Therefore, both electronic devices 700A and 700B are capable of AR display.

[0521] The electronic devices 700A and 700B may also be provided with a camera capable of photographing the front as an imaging unit. In addition, by providing an acceleration sensor such as a gyroscope sensor on the electronic devices 700A and 700B, the user's head orientation can be detected and an image corresponding to that orientation can be displayed on the display area 756.

[0522] The communication unit includes a wireless communication device, through which a video signal, etc. can be supplied. Alternatively, or in addition to the wireless communication device, a connector to which a cable for supplying video signals and power supply potential can be connected may be included.

[0523] Electronic devices 700A and 700B are provided with batteries, and can be charged wirelessly, wired, or both.

[0524] The frame 721 may also be provided with a touch sensor module. The touch sensor module has the function of detecting whether the outer surface of the frame 721 is touched. The touch sensor module can detect user tapping or sliding operations and perform various operations. For example, a tapping operation can temporarily pause or replay a dynamic image, while a sliding operation can fast forward or rewind the image. In addition, by providing a touch sensor module on each of the two frames 721, the operating range can be expanded.

[0525] A variety of touch sensors can be used in the touch sensor module. For example, various touch sensors can be used, such as capacitance, resistive film, infrared, electromagnetic induction, surface acoustic wave, and optical. Capacitive or optical sensors are particularly preferred for use in the touch sensor module.

[0526] When an optical touch sensor is used, a photoelectric conversion element can be used as a light-receiving element. The active layer of the photoelectric conversion element can use one or both of an inorganic semiconductor and an organic semiconductor.

[0527] Figure 21C The electronic device 800A shown and Figure 21D Each of the electronic devices 800B shown includes a pair of display portions 820 , a housing 821 , a communication portion 822 , a pair of mounting portions 823 , a control portion 824 , a pair of imaging portions 825 , and a pair of lenses 832 .

[0528] The display unit 820 can be applied to a display device according to one embodiment of the present invention. This makes it possible to realize an electronic device capable of displaying extremely high definition, thereby allowing the user to experience a high sense of immersion.

[0529] The display unit 820 is provided at a position inside the housing 821 that can be viewed through the lens 832. In addition, by displaying different images on each of the pair of display units 820, three-dimensional display utilizing parallax can be performed.

[0530] Both electronic device 800A and electronic device 800B can be referred to as VR-compatible electronic devices. A user wearing electronic device 800A or electronic device 800B can view an image displayed on display unit 820 through lens 832 .

[0531] Electronic devices 800A and 800B preferably include a mechanism that allows adjustment of the left and right positions of lens 832 and display unit 820 so that lens 832 and display unit 820 are optimally positioned according to the position of the user's eyes. Furthermore, they preferably include a mechanism that adjusts the focus by changing the distance between lens 832 and display unit 820.

[0532] The user can use the mounting portion 823 to mount the electronic device 800A or the electronic device 800B on the head. Figure 21C In the embodiment of the present invention, the mounting portion 823 is shaped like the temples of glasses (also referred to as temples), but the present invention is not limited thereto. As long as the user can wear it, the mounting portion 823 may have, for example, a helmet-type or belt-type shape.

[0533] The imaging unit 825 has the function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used in the imaging unit 825. In addition, multiple cameras can be provided to support various viewing angles such as telephoto and wide-angle.

[0534] Note that while this example includes the imaging unit 825, it suffices to provide a distance-measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object. In other words, the imaging unit 825 is one form of a detection unit. For example, an image sensor or a distance image sensor such as a LiDAR (Light Detection and Ranging) can be used as the detection unit. By using images acquired by a camera and an image acquired by a distance image sensor, more information can be obtained, enabling more precise gesture manipulation.

[0535] Electronic device 800A may also include a vibration mechanism for use as bone conduction headphones. For example, one or more of the display unit 820, housing 821, and mounting unit 823 may include this vibration mechanism. This eliminates the need for separate headphones, earphones, or speakers; simply attaching electronic device 800A allows for the enjoyment of video and audio.

[0536] Electronic devices 800A and 800B may both include input terminals. Cables for supplying video signals from video output devices and the like, and power for charging batteries provided in the electronic devices, may be connected to the input terminals.

[0537] The electronic device of one embodiment of the present invention may also have a function of wirelessly communicating with the earphone 750. The earphone 750 includes a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (such as sound data) from the electronic device through the wireless communication function. For example, Figure 21A The electronic device 700A shown has a function of transmitting information to the headset 750 through a wireless communication function. In addition, for example Figure 21C The electronic device 800A shown has a function of transmitting information to the headset 750 through a wireless communication function.

[0538] The electronic device may also include an earphone unit. Figure 21B The electronic device 700B shown includes an earphone unit 727. For example, a wired connection between the earphone unit 727 and the control unit may be employed. A portion of the wire connecting the earphone unit 727 and the control unit may also be disposed within the housing 721 or the mounting portion 723.

[0539] same, Figure 21D The electronic device 800B shown includes an earphone unit 827. For example, a structure in which the earphone unit 827 and the control unit 824 are connected by wire can be employed. A portion of the wiring connecting the earphone unit 827 and the control unit 824 can also be disposed within the housing 821 or the mounting portion 823. Alternatively, the earphone unit 827 and the mounting portion 823 can include magnets. This allows the earphone unit 827 to be secured to the mounting portion 823 by magnetic force, making storage easier and therefore preferred.

[0540] An electronic device may also include a sound output terminal that can be connected to earphones or headphones. Furthermore, an electronic device may include one or both of a sound input terminal and a sound input mechanism. For example, a microphone or other sound receiving device may be used as the sound input mechanism. By incorporating a sound input mechanism into an electronic device, the electronic device can be given the functionality of a so-called headset.

[0541] As described above, as electronic devices according to one embodiment of the present invention, both glasses-type (electronic devices 700A and 700B, etc.) and goggles-type (electronic devices 800A and 800B, etc.) are preferable.

[0542] An electronic device according to one embodiment of the present invention can transmit information to headphones via wired or wireless communication.

[0543] Figure 22A The electronic device 6500 shown is a portable information terminal device that can be used as a smartphone.

[0544] An electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display portion 6502 has a touch panel function.

[0545] The display portion 6502 can use the display device of one embodiment of the present invention.

[0546] Figure 22B 6506 is a schematic cross-sectional view of an end portion of the housing 6501 on the microphone 6506 side.

[0547] A light-transmitting protective component 6510 is provided on the display surface side of the frame 6501, and a display panel 6511, an optical component 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are provided in the space surrounded by the frame 6501 and the protective component 6510.

[0548] The display panel 6511 , the optical member 6512 , and the touch sensor panel 6513 are fixed to the protective member 6510 using an adhesive layer (not shown).

[0549] In a region outside the display portion 6502, a portion of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded back portion. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to terminals provided on a printed circuit board 6517.

[0550] The display panel 6511 can use a flexible display according to one embodiment of the present invention. This allows for an extremely lightweight electronic device. Furthermore, because the display panel 6511 is extremely thin, a large-capacity battery 6518 can be installed while reducing the thickness of the electronic device. Furthermore, by folding a portion of the display panel 6511 to provide a connection to the FPC 6515 on the back side of the pixel unit, an electronic device with a narrow frame can be realized.

[0551] Figure 22C An example of a television set is shown. In a television set 7100, a display portion 7000 is incorporated into a housing 7101. Here, a structure in which the housing 7101 is supported by a stand 7103 is shown.

[0552] The display device according to one embodiment of the present invention can be applied to the display portion 7000 .

[0553] The operation can be performed by using the operation switch of the frame 7101 and the remote control unit 7111 provided separately. Figure 22C Alternatively, the display unit 7000 may be provided with a touch sensor, and the television unit 7100 may be operated by touching the display unit 7000 with a finger or the like. Furthermore, the remote controller 7111 may include a display unit for displaying data output from the remote controller 7111. Using the operation keys or touch panel provided on the remote controller 7111, the channel and volume can be controlled, and the image displayed on the display unit 7000 can be manipulated.

[0554] The television set 7100 also includes a receiver and a modem. The receiver can receive standard television broadcasts. Furthermore, the modem can be connected to a wired or wireless communication network to enable one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers) information communication.

[0555] Figure 22D 1 shows an example of a notebook personal computer. The notebook personal computer 7200 includes a housing 7211 , a keyboard 7212 , a pointing device 7213 , an external connection port 7214 , and the like. A display portion 7000 is incorporated into the housing 7211 .

[0556] The display device according to one embodiment of the present invention can be applied to the display portion 7000 .

[0557] Figure 22E and Figure 22F An example of digital signage is shown.

[0558] Figure 22E The digital signage 7300 shown includes a housing 7301, a display portion 7000, a speaker 7303, etc. In addition, it may include an LED light, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, etc.

[0559] Figure 22F The digital signage 7400 is shown installed on a cylindrical pillar 7401. The digital signage 7400 includes a display unit 7000 installed along the curved surface of the pillar 7401.

[0560] exist Figure 22E and Figure 22F In this embodiment, the display device of one embodiment of the present invention can be used for the display portion 7000.

[0561] The larger the display unit 7000 is, the more information it can provide at one time. The larger the display unit 7000 is, the easier it is to attract people's attention, for example, it can improve the effectiveness of advertising.

[0562] Using a touch panel in the display unit 7000 is preferred because it allows not only still images or moving images to be displayed on the display unit 7000 but also intuitive operation by the user. Furthermore, when used to provide information such as route information or traffic information, intuitive operation can improve usability.

[0563] like Figure 22E and Figure 22FAs shown, digital signage 7300 or digital signage 7400 can preferably be linked to information terminal device 7311 or information terminal device 7411, such as a smartphone, carried by the user via wireless communication. For example, advertising information displayed on display unit 7000 can be displayed on the screen of information terminal device 7311 or information terminal device 7411. In addition, the display of display unit 7000 can be switched by operating information terminal device 7311 or information terminal device 7411.

[0564] The game can be played on the digital signage 7300 or 7400 using the screen of the information terminal device 7311 or 7411 as an operation unit (controller). This allows an unspecified number of users to participate in the game and enjoy the game at the same time.

[0565] Figures 23A to 23G The electronic device shown includes a frame 9000, a display portion 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (the sensor has the function of detecting, detecting or measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, smell or infrared), a microphone 9008, etc.

[0566] exist Figures 23A to 23G In this embodiment, the display device of one embodiment of the present invention can be used for the display portion 9001.

[0567] Figures 23A to 23G The electronic device shown has various functions. For example, it may have the following functions: a function of displaying various information (static images, dynamic images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of controlling processing by using various software (programs); a function of performing wireless communication; a function of reading out programs or data stored in a storage medium and processing them; etc. Note that the functions of the electronic device are not limited to the above functions, but may have various functions. The electronic device may also include multiple display units. In addition, a camera or the like may be provided in the electronic device so that it has the following functions: a function of taking still images or dynamic images and storing the taken images in a storage medium (an external storage medium or a storage medium built into the camera); a function of displaying the taken images on a display unit; etc.

[0568] Below, we will explain in detail Figures 23A to 23G Electronic devices shown.

[0569] Figure 23A: is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 can be used as a smartphone, for example. Note that a speaker 9003, a connection terminal 9006, a sensor 9007, etc. can also be provided in the portable information terminal 9101. In addition, as the portable information terminal 9101, text or image information can be displayed on multiple surfaces. Figure 23A 9050 is shown as an example. Information 9051, indicated by a dotted rectangle, can also be displayed on another surface of display portion 9001. Examples of information 9051 include information notifying of the receipt of an email, social media, or phone call; the title of the email or social media; the name of the sender of the email or social media; the date; the time; the remaining battery level; and the radio frequency strength. Alternatively, icon 9050 can be displayed in the location where information 9051 is displayed.

[0570] Figure 23B This is a perspective view of a portable information terminal 9102. Portable information terminal 9102 has the function of displaying information on three or more surfaces of display unit 9001. Here, an example is shown where information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, while portable information terminal 9102 is in a jacket pocket, the user can check information 9053 displayed from above. This allows the user to check this display without removing portable information terminal 9102 from their pocket, allowing them to, for example, decide whether to answer a call.

[0571] Figure 23C This is a perspective view of a tablet terminal 9103. The tablet terminal 9103 can run various application software, such as mobile phone use, reading and editing emails and articles, playing music, network communications, and computer games. The tablet terminal 9103 includes a display portion 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of a housing 9000. It also includes operation keys 9005 serving as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.

[0572] Figure 23D is a perspective view showing a watch-type portable information terminal 9200. The portable information terminal 9200 can be used, for example, as a smartwatch (registered trademark). Furthermore, the display surface of the display portion 9001 is curved, and a display can be displayed along the curved display surface. Furthermore, the portable information terminal 9200 can communicate with a headset capable of wireless communication, for example, to enable hands-free calls. Furthermore, by utilizing the connection terminal 9006, the portable information terminal 9200 can transmit data to other information terminals or be charged. Charging can also be performed by wireless power supply.

[0573] Figures 23E to 23G 1 is a perspective view showing a foldable portable information terminal 9201. Figure 23E This is a perspective view of the portable information terminal 9201 in an unfolded state. Figure 23G This is a three-dimensional diagram of the folded state. Figure 23F It is from Figure 23E Status and Figure 23G A perspective view of a state midway between transitioning from one state to another. The portable information terminal 9201 offers excellent portability when folded, while its large, seamless display area in the unfolded state provides enhanced viewing convenience. The display portion 9001 included in the portable information terminal 9201 is supported by three frames 9000 connected by hinges 9055. The display portion 9001 can be bent, for example, within a range of a curvature radius of 0.1 mm to 150 mm.

[0574] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0575] [Explanation of symbols]

[0576] 10: transistor, 10a: transistor, 10b: transistor, 10c: transistor, 10d: transistor, 10e: transistor, 10f: transistor, 10g: transistor, 10h: transistor, 11: insulating layer, 15: transistor, 20a: opening, 20b: opening, 20c: opening, 20d: opening, 20e: opening, 21: semiconductor layer, 22: insulating layer, 23: conductive layer, 24: conductive layer, 25: conductive layer, 32: conductive layer, 41: insulating layer, 41a: insulating layer, 41b: insulating layer, 41c: insulating layer, 42: insulating layer, 44: insulating layer, 45: insulating layer, 46: insulating layer, 50: transistor, 50a: transistor, 50b: transistor, 50c: transistor, 50d: transistor, 50e: transistor

Claims

1. A semiconductor device comprising: transistor; as well as The first insulating layer, The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer and a second insulating layer. The first insulating layer is located on the first conductive layer and includes a first opening, The second conductive layer is located on the first insulating layer, The semiconductor layer has a portion in contact with the first conductive layer, a portion in contact with the second conductive layer, and a portion in contact with a side surface of the first insulating layer inside the first opening. The second insulating layer covers the semiconductor layer in the first opening, The third conductive layer covers the second insulating layer in the first opening, Furthermore, in the region overlapping with the first opening, there is a portion where the first conductive layer and the third conductive layer do not overlap with each other, and the first conductive layer and the semiconductor layer do not overlap with each other.

2. A semiconductor device comprising: transistor; base insulating layer; as well as The first insulating layer, The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer and a second insulating layer. The first insulating layer is located on the first conductive layer and includes a first opening, The first conductive layer is located on the base insulating layer and includes a second opening, The second opening is located inside the first opening when viewed from a plane. The second conductive layer is located on the first insulating layer, The semiconductor layer has a portion in contact with the first conductive layer, a portion in contact with the second conductive layer, and a portion in contact with a side surface of the first insulating layer inside the first opening, and includes a third opening located inside the first opening when viewed from a plane. The second insulating layer includes a portion covering the semiconductor layer in the first opening and a portion in contact with the base insulating layer at a position overlapping with the second opening and the third opening. Furthermore, the third conductive layer covers the second insulating layer in the first opening.

3. The semiconductor device according to claim 2, wherein the second opening is smaller than the third opening, The second opening is located inside the third opening when viewed from a plane. The second insulating layer contacts the top surface of the first conductive layer and the side surface of the first conductive layer in the second opening.

4. The semiconductor device according to claim 2, wherein the third opening is smaller than the second opening, The third opening is located inside the second opening when viewed from a plane. The semiconductor layer is in contact with the top surface of the first conductive layer, the side surface of the first conductive layer in the second opening, and the base insulating layer.

5. A semiconductor device comprising: transistor; as well as The first insulating layer, The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer and a second insulating layer. The first insulating layer is located on the first conductive layer and includes a first opening, The second conductive layer is located on the first insulating layer, The semiconductor layer has a portion in contact with the first conductive layer, a portion in contact with the second conductive layer, and a portion in contact with a side surface of the first insulating layer inside the first opening. The second insulating layer covers the semiconductor layer in the first opening, Furthermore, the third conductive layer covers the second insulating layer in the first opening and includes a second opening located inside the first opening when viewed from a plane.

6. The semiconductor device according to any one of claims 1 to 5, The angle formed by the side surface of the first insulating layer in the first opening and the bottom surface of the first insulating layer is greater than or equal to 75 degrees and less than or equal to 90 degrees.

7. The semiconductor device according to any one of claims 1 to 5, wherein the semiconductor layer comprises a metal oxide, The first insulating layer comprises a first insulating film, a second insulating film and a third insulating film stacked in sequence. The first insulating film and the third insulating film include nitride, And the second insulating film includes oxide.

8. The semiconductor device according to claim 7, wherein the first insulating film and the third insulating film include silicon nitride, And the second insulating film includes silicon oxide.

9. The semiconductor device according to claim 5, The second conductive layer includes a third insulating layer, Furthermore, the third conductive layer has a portion overlapping with the second conductive layer via the third insulating layer.

10. The semiconductor device according to claim 9, wherein the third insulating layer includes a fourth conductive layer, And the fourth conductive layer is electrically connected to the third conductive layer and serves as a wiring.

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