A voltage calibration circuit, single photon avalanche diode detector and radar

Abstract

The present invention relates to the field of single-photon avalanche diode technology and is used to improve the performance stability of single-photon avalanche diodes. The voltage calibration circuit includes a quenching circuit, a sampling circuit, a sampling signal generating circuit, and a post-processing circuit. The quenching circuit includes a control circuit and a resistor circuit. The control circuit is configured to control the resistance of the resistor circuit to be greater than or equal to the first resistance when a clock signal is at a first level. The clock signal maintains the first level for a duration greater than or equal to a first preset duration. The sampling signal generating circuit is configured to output a sampling signal pulse after detecting the rising edge of an avalanche pulse. The sampling circuit is configured to sample the first end of the single-photon avalanche diode when a sampling signal pulse is received at its control end, and to send the sampling result to a post-processing circuit. The post-processing circuit is configured to adjust the bias voltage of the single-photon avalanche diode based on the sampling result.

Description

Technical Field

[0001] The present invention relates to the technical field of single-photon avalanche diodes, and in particular to a voltage calibration circuit, a single-photon avalanche diode detector and a radar. Background Art

[0002] In cutting-edge technologies such as photodetection, high-energy physics experiments, and ultra-high-speed communications, single-photon avalanche diodes (SPADs), devices based on the avalanche multiplication effect, play a crucial role. When a SPAD detects a photon, it generates an avalanche pulse. Its waveform is typically triangular, with an extremely fast rise (typically <100 ps) and a slower fall (on the order of nanoseconds). After subsequent circuitry converts this pulse into a voltage signal, its peak voltage directly reflects crucial information about the incident photon and is a key parameter for calibrating the SPAD's operating voltage.

[0003] To directly sample such narrow pulses using an analog-to-digital converter (ADC) and accurately recover their peak voltage, the Nyquist sampling theorem dictates that the ADC sampling rate must be significantly higher than the highest frequency component of the pulse. Because avalanche pulses have extremely fast rising edges, their effective bandwidth can reach several GHz, requiring an ADC sampling rate in the GHz range to avoid aliasing and accurately capture the peak value. Therefore, relying directly on high-speed ADCs for avalanche pulse sampling would significantly increase system power consumption, area, and cost, limiting the application of single-photon avalanche diodes in portable, highly integrated, or large-scale array systems.

[0004] Therefore, a method is needed to accurately measure the pulse peak value at a lower sampling rate to reduce system cost and power consumption. Summary of the Invention

[0005] The present application provides a voltage calibration circuit, a single-photon avalanche diode detector and a radar for achieving precise sampling of the single-photon avalanche diode, thereby enabling accurate calibration of the single-photon avalanche diode bias voltage and improving the performance stability of the single-photon avalanche diode.

[0006] In a first aspect, an embodiment of the present application provides a voltage calibration circuit, comprising: a quenching circuit, a sampling circuit, a sampling signal generating circuit, and a post-processing circuit; the quenching circuit comprises a control circuit and a resistance circuit, wherein the first end of the resistance circuit is connected to the first power supply end, the second end of the resistance circuit is used to connect to the first end of the single-photon avalanche diode, and the second end of the single-photon avalanche diode is connected to the second power supply end; the voltage of the first power supply end is lower than the voltage of the second power supply end; the first input end of the control circuit is connected to the third power supply end, the clock end of the control circuit is used to receive a clock signal, and the output end of the control circuit is connected to the control end of the resistance circuit; the control circuit is used to output the first voltage provided by the third power supply end to the control end of the resistance circuit when the clock signal is at a first level; the voltage of the resistance circuit at the control end is lower than the voltage of the second power supply end. The resistance value when the sampling signal is at the first voltage is greater than or equal to the first resistance value; the time length during which the clock signal maintains the first level is greater than or equal to the first preset time length; the input end of the sampling signal generating circuit is used to connect the first end of the single-photon avalanche diode, and the output end is connected to the control end of the sampling circuit, and is used to output a sampling signal pulse after detecting the rising edge of the avalanche pulse; the input end of the sampling circuit is used to connect the first end of the single-photon avalanche diode, and the output end of the sampling circuit is connected to the input end of the post-processing circuit, and the sampling circuit is used to sample the first end of the single-photon avalanche diode when its control end receives the sampling signal pulse, and send the sampling result obtained by sampling to the post-processing circuit; the post-processing circuit is used to adjust the voltage of the first power supply end and / or the voltage of the second power supply end based on the sampling result.

[0007] In the voltage calibration circuit provided in the embodiment of the present application, the quenching circuit controls the resistance of the resistor circuit based on the clock signal, so that the duration of time the resistor circuit is greater than or equal to a predetermined first resistance value is greater than or equal to the first predetermined duration. This means that during the duration of time the clock signal maintains the first level, the equivalent resistance between the first end of the single-photon avalanche diode and the first power supply end is relatively large, and the circuit characteristic is equivalent to being in an off state. In this state, when the single-photon avalanche diode generates an avalanche pulse, the sampling signal generation circuit will quickly output a sampling signal pulse as a trigger signal for the sampling circuit after detecting the rising edge of the avalanche pulse. After receiving the sampling signal pulse, the sampling circuit will sample the avalanche pulse.

[0008] It is understandable that during the time that the clock signal maintains the first level, due to the high resistance of the resistor circuit, the decline process of the avalanche pulse will become extremely slow. This slow decline process prolongs the duration of the avalanche pulse, so that the sampling circuit can sample near the peak of the avalanche pulse or in the stable decline phase, thereby ensuring the accuracy and reliability of the sampled data. It can be seen that the voltage calibration circuit provided in the embodiment of the present application can tolerate a lower sampling rate during the sampling process while still accurately capturing the peak voltage of the pulse. This reduces the requirements for the design complexity of the sampling circuit, reduces the requirements for area and power consumption resources, improves the accuracy of sampling, and reduces errors caused by insufficient sampling rate or noise interference. Therefore, when the post-processing circuit adjusts the bias voltage (the voltage of the first power supply terminal and / or the voltage of the second power supply terminal) of the single-photon avalanche diode based on the accurate sampling results, it has a more accurate adjustment basis, thereby achieving more accurate voltage calibration and improving the performance stability of the single-photon avalanche diode.

[0009] In combination with the first implementation method of the first aspect, the resistance circuit includes a transistor; the gate of the transistor is connected to the control end of the resistance circuit; the transistor is cut off when the voltage of the gate is a first voltage and is turned on when it is a second voltage; the source of the transistor is connected to the first end of the resistance circuit; and the gate of the transistor is connected to the second end of the resistance circuit.

[0010] In combination with the second implementation method of the first aspect, the clock signal periodically switches between the first level and the second level; the second input terminal of the control circuit is connected to the fourth power supply terminal, and the control circuit is also used to output the second voltage provided by the fourth power supply terminal to the control terminal of the resistance circuit when the clock signal is the second level; the resistance value of the resistance circuit when the voltage at the control terminal is the second voltage is less than or equal to the second resistance value; the first resistance value is greater than the second resistance value.

[0011] In combination with the third implementation method of the first aspect, the sampling signal generating circuit includes: a monostable trigger circuit and a delay circuit; the monostable trigger circuit is used to output a sampling signal pulse to the delay circuit after detecting the rising edge of the avalanche pulse; the delay circuit is used to send the sampling signal pulse to the sampling circuit after receiving the sampling signal pulse and delaying it for a second preset time length.

[0012] In combination with the fourth implementation method of the first aspect, the clock end of the sampling circuit is used to receive a clock signal; the sampling circuit is specifically used to output the sampling result to the post-processing circuit if the clock signal maintains the first level during sampling of the second end of the single-photon avalanche diode.

[0013] In combination with the fifth implementation manner of the first aspect, the sampling circuit is further configured to output the sampling result to the post-processing circuit when the voltage value represented by the sampling result is higher than a preset voltage threshold.

[0014] In combination with the sixth implementation method of the first aspect, the post-processing circuit is specifically used to determine the average voltage value corresponding to multiple sampling results; if the average voltage value is higher than the upper limit value of the preset voltage range, the bias voltage of the single-photon avalanche diode is reduced; the bias voltage is the voltage difference between the voltage of the second power supply end and the voltage of the first power supply end; if the average voltage value is lower than the lower limit value of the preset voltage range, the bias voltage of the single-photon avalanche diode is increased.

[0015] In combination with the seventh implementation method of the first aspect, the voltage calibration circuit also includes: a voltage divider circuit; the first end of the voltage divider circuit is connected to the first end of the single-photon avalanche diode, the second end is connected to the first power supply end, and the input end of the sampling circuit and the input end of the sampling signal generating circuit are connected to the voltage divider node of the voltage divider circuit.

[0016] The second aspect of an embodiment of the present application provides a single-photon avalanche diode detector, comprising: a single-photon avalanche diode, and a voltage calibration circuit provided by the first aspect and its possible implementation method; the first end of the resistance circuit of the voltage calibration circuit is connected to the first power supply end, the second end of the resistance circuit is connected to the first end of the single-photon avalanche diode, and the second end of the single-photon avalanche diode is connected to the second power supply end.

[0017] A third aspect of an embodiment of the present application provides a radar, including the single photon avalanche diode detector provided by the second aspect and its possible implementation methods.

[0018] Among them, the beneficial effects described in the second aspect can refer to the analysis of the beneficial effects of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present invention and do not constitute a limitation on the technical solution of the present invention.

[0020] Figure 1 A schematic diagram of an avalanche pulse provided in an embodiment of the present application;

[0021] Figure 2 A schematic diagram of a voltage calibration circuit provided in an embodiment of the present application Figure 1 ;

[0022] Figure 3 A schematic diagram of a voltage calibration circuit provided in an embodiment of the present application Figure 2 ;

[0023] Figure 4 A schematic diagram of a voltage calibration circuit provided in an embodiment of the present application Figure 3 ;

[0024] Figure 5 A signal waveform diagram provided in an embodiment of the present application Figure 1 ;

[0025] Figure 6 A schematic diagram of a voltage calibration circuit provided in an embodiment of the present application Figure 4 ;

[0026] Figure 7 A signal waveform diagram provided in an embodiment of the present application Figure 2 ;

[0027] Figure 8 A signal waveform diagram provided in an embodiment of the present application Figure 3 ;

[0028] Figure 9 A signal waveform diagram provided in an embodiment of the present application Figure 4 ;

[0029] Figure 10 A signal waveform diagram provided in an embodiment of the present application Figure 5 ;

[0030] Figure 11 A schematic diagram of a voltage calibration circuit provided in an embodiment of the present application Figure 5 . DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0032] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0033] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "connected" and "connect" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances. Furthermore, when describing pipelines, the terms "connected" and "connected" used in this application have the meaning of conducting electricity. The specific meanings need to be understood in the context.

[0034] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0035] Before explaining the embodiments of the present application in detail, some terms involved in the embodiments of the present application are first explained.

[0036] A single photon avalanche diode (SPAD) is a photodetector capable of detecting single photons. A single photon avalanche diode (SPAD) can detect single photons and possesses extremely high sensitivity. Its timing accuracy can reach tens to hundreds of picoseconds, making it suitable for applications requiring high-precision time measurement.

[0037] A metal oxide semiconductor field effect transistor (MOS) is a silicon-based electronic device that controls current through an electric field. Its equivalent resistance can be adjusted by controlling the gate voltage. MOS transistors can be either N-channel MOS (NMOS) or P-channel MOS (PMOS).

[0038] After the avalanche pulse generated by the single-photon avalanche diode is converted into a voltage signal by the subsequent circuit, its peak voltage directly reflects the key information of the photon incident event and is the core parameter for calibrating the SPAD operating voltage. The avalanche pulse generated by the single-photon avalanche diode has an extremely short rise time (usually less than 100ps) and a long fall time (nanosecond level). Figure 1As shown, the avalanche pulse waveform has time on the horizontal axis and voltage on the vertical axis, and the avalanche pulse is approximately triangular. This pulse waveform is rich in high-frequency components. Direct sampling requires an extremely high sampling rate (GHz level) to accurately restore the peak voltage Vex. This not only increases the design complexity of the sampling circuit, as well as the area and power requirements, but inaccurate sampling results also reduce the accuracy of subsequent calibration, ultimately causing the SPAD operating voltage to deviate from the optimal range, leading to systemic performance degradation such as reduced detection efficiency, increased dark count rate, and worsening timing jitter.

[0039] Based on this, an embodiment of the present application provides a voltage calibration circuit, in which the quenching circuit of the voltage calibration circuit controls the resistance of the resistor circuit based on the clock signal, so that the duration of time that the resistance is greater than or equal to a preset first resistance is greater than or equal to the first preset duration. This means that during the duration that the clock signal maintains the first level, the equivalent resistance between the first end of the single-photon avalanche diode and the first power supply end is large, and the circuit characteristics are equivalent to being in an off state. In this state, when the single-photon avalanche diode generates an avalanche pulse, the sampling signal generation circuit will quickly output a sampling signal pulse as a trigger signal for the sampling circuit after detecting the rising edge of the avalanche pulse. After receiving the sampling signal pulse, the sampling circuit will sample the avalanche pulse.

[0040] It is understandable that during the time that the clock signal maintains the first level, due to the high resistance of the resistor circuit, the decline process of the avalanche pulse will become extremely slow. This slow decline process prolongs the duration of the avalanche pulse, so that the sampling circuit can sample near the peak of the avalanche pulse or in the stable decline phase, thereby ensuring the accuracy and reliability of the sampled data. It can be seen that the voltage calibration circuit provided in the embodiment of the present application can tolerate a lower sampling rate during the sampling process while still accurately capturing the peak voltage of the pulse. This reduces the requirements for the design complexity of the sampling circuit, reduces the requirements for area and power consumption resources, improves the accuracy of sampling, and reduces errors caused by insufficient sampling rate or noise interference. Therefore, when the post-processing circuit adjusts the bias voltage (the voltage of the first power supply terminal and / or the voltage of the second power supply terminal) of the single-photon avalanche diode based on the accurate sampling results, it has a more accurate adjustment basis, thereby achieving more accurate voltage calibration and improving the performance stability of the single-photon avalanche diode.

[0041] The voltage calibration circuit provided in the embodiment of the present application is described below with reference to the accompanying drawings:

[0042] See also Figure 2 The voltage calibration circuit provided in an embodiment of the present application includes a quenching circuit 12, a sampling circuit 13, a sampling signal generating circuit 14 and a post-processing circuit 15.

[0043] like Figure 2 As shown, the quenching circuit 12 includes a resistance circuit 121, a first end of the resistance circuit 121 is connected to the first power supply terminal 21, a second end of the resistance circuit 121 is used to connect to the first end 11-1 of the single-photon avalanche diode 11, and the second end 11-2 of the single-photon avalanche diode is connected to the second power supply terminal 22; the voltage of the first power supply terminal 21 is lower than the voltage of the second power supply terminal 22.

[0044] It should be noted that the embodiment of the present application does not limit the specific form of the single-photon avalanche diode 11. The single-photon avalanche diode mentioned in the embodiment of the present application can be a single single-photon avalanche diode or a SPAD array composed of multiple single-photon avalanche diodes.

[0045] It should be understood that the two power supply terminals connected to the single-photon avalanche diode 11 are used to provide the necessary bias voltage for the single-photon avalanche diode to operate normally in Geiger mode (i.e., the reverse bias voltage exceeds the avalanche breakdown voltage). The second power supply terminal 22 generally serves as a high-potential terminal, providing a forward bias or relatively high potential for the single-photon avalanche diode. The first power supply terminal 21 serves as a low-potential terminal or ground terminal, providing a reference potential or zero potential for the single-photon avalanche diode.

[0046] For example, as a feasible implementation method, combining Figure 2 See Figure 3 The second power supply terminal 22 is Vop, which is used to provide a positive bias voltage (higher than the first power supply terminal); the first power supply terminal 21 is directly grounded as a reference zero potential.

[0047] As another feasible implementation method, combining Figure 2 See Figure 4 The second power supply terminal 22 is Vop, which is used to provide a negative bias voltage (greater than or equal to the breakdown voltage of the single-photon avalanche diode); the first power supply terminal 21 is VDD, which serves as an intermediate potential terminal and is usually the system logic power supply voltage (such as 3.3V, 5V).

[0048] The operating principle of a single-photon avalanche diode (SPAD) is that when it detects a photon and avalanche breakdown occurs, it generates a rapidly rising avalanche pulse. In the embodiment of the present application, the resistance of resistor circuit 121 is adjustable. If the resistance is too low, the avalanche pulse width is too narrow, and the sampling circuit cannot accurately sample the peak voltage of the pulse.

[0049] Therefore, please refer to the examples in this application. Figure 2The quenching circuit 12 includes a control circuit 122 , a first input terminal of the control circuit 122 is connected to the third power supply terminal 23 , a clock terminal of the control circuit is used to receive a clock signal, and an output terminal of the control circuit 122 is connected to the control terminal of the resistance circuit 121 .

[0050] The control circuit is used to output the first voltage provided by the third power supply end to the control end of the resistance circuit when the clock signal is at the first level; the resistance value of the resistance circuit when the voltage at the control end is the first voltage is greater than or equal to the first resistance value; the time length for which the clock signal maintains the first level is greater than or equal to a first preset time length.

[0051] That is, when the control circuit receives a clock signal (CLK) at a first level (high or low), the control circuit outputs the first voltage provided by the third power supply terminal to the control terminal of the resistor circuit, causing the resistance of the resistor circuit to be greater than or equal to the first resistance. Furthermore, the clock signal maintains the first level for a duration greater than or equal to a first preset duration, meaning that the resistance of the resistor circuit remains greater than or equal to the first resistance for a duration greater than or equal to the first preset duration.

[0052] It should be understood that the first preset duration is pre-set and can be determined according to actual application needs, and the embodiments of the present application do not limit this. For example, multiple periods can be pre-set, and then within each preset period, a duration greater than or equal to the first preset duration is set as the duration of the first level, and the embodiments of the present application do not limit this. It should be understood that for ease of description, the following description uses the duration of the first level as the first duration as an example.

[0053] During the first duration, the resistance of the resistor circuit 121 is controlled to be greater than or equal to the first resistance, so that after the single-photon avalanche diode generates an avalanche pulse, the high resistance will cause the avalanche pulse voltage to drop extremely slowly during the first duration. This slow decline process extends the duration of the avalanche pulse, so that the sampling circuit can perform sampling near the peak of the avalanche pulse or in the stable decline stage, thereby ensuring the accuracy and reliability of the sampled data.

[0054] For example, see Figure 5 In the voltage calibration circuit provided by the embodiment of the present application, after the single-photon avalanche diode detects a photon at time t1, the waveform of the avalanche pulse Vin rises rapidly, and then remains approximately unchanged within the first duration (t0-t2). After the first duration ends, if Figure 5 At the time t2 - t3 shown, the resistance Vq of the resistance circuit 121 is controlled to be less than or equal to the second resistance, which accelerates the recovery process of the avalanche pulse Vin, causing the avalanche pulse Vin to drop rapidly, forming a trapezoidal avalanche pulse waveform.

[0055] Depend on Figure 5 As can be seen, the voltage calibration circuit provided by the embodiment of the present application maintains the avalanche pulse voltage approximately equal to the peak voltage during the first duration and then accelerates its decline after the first duration ends. This generates a nearly trapezoidal avalanche pulse, allowing the sampling circuit more time to capture and stabilize the peak voltage of the pulse. This improves sampling accuracy and reduces errors caused by insufficient sampling rate or noise interference.

[0056] In this application, please continue to refer to Figure 2 The input end 14-1 of the sampling signal generating circuit 14 is used to connect to the second end 11-2 of the single-photon avalanche diode 11, and the output end 14-2 is connected to the control end of the sampling circuit 13, and is used to generate a sampling signal after detecting the rising edge of the avalanche pulse, and then output the sampling signal pulse Vs.

[0057] The input end of the sampling signal generating circuit 14 is directly connected to the first end (usually the cathode or signal output end) of the single photon avalanche diode 11 for real-time monitoring of the output signal of the single photon avalanche diode.

[0058] The avalanche pulse generated by the single-photon avalanche diode 11 during avalanche breakdown has a fast rising edge and high amplitude. The sampling signal generation circuit 14 is capable of detecting the rising edge (i.e., the transition from a low-level to a high-level pulse) of the avalanche pulse output by the single-photon avalanche diode 11 in real time. Upon detecting the rising edge, it generates a sampling signal pulse with a specific width and timing, which is used to control the activation of the sampling circuit 13, enabling the sampling circuit to accurately perform sampling.

[0059] As a feasible implementation, the sampling signal generation circuit 14 includes a comparator for comparing the output signal of the single-photon avalanche diode 11 with a preset threshold voltage (Vth). When the output signal of the single-photon avalanche diode exceeds Vth, the comparator outputs a high level, indicating the arrival of a rising edge.

[0060] In this application, please continue to refer to Figure 2 The input terminal 13-1 of the sampling circuit 13 is used to connect to the first terminal 11-1 of the single-photon avalanche diode 11, and the sampling signal generating circuit 14 is used to sample the first terminal 11-1 of the single-photon avalanche diode 11 when the control terminal thereof receives a sampling signal pulse.

[0061] The sampling circuit 13 can be connected to the first end 11 - 1 of the single-photon avalanche diode 11 through the input end 13 - 1 , thereby achieving accurate sampling of the single-photon avalanche diode signal when a sampling signal pulse is received.

[0062] As a feasible implementation method, Figure 5As shown, the sampling process of the sampling circuit 13 can last for a fourth preset time period (Δt s ), thereby generating a sampling signal waveform with a width of the fourth preset time length.

[0063] As a feasible implementation method, Figure 2 As shown, the sampling circuit 13 also includes an analog-to-digital converter (ADC). The control end of the sampling circuit 13 is responsible for the configuration and trigger management of the ADC. The ADC completes the sampling and digitization of the avalanche pulse under the action of the control signal.

[0064] In this application, please continue to refer to Figure 2 The output end of the sampling circuit 13 is connected to the input end of the post-processing circuit 15 . After sampling the first end 11 - 1 of the single-photon avalanche diode 11 , the sampling circuit 13 sends the sampling result to the post-processing circuit 15 .

[0065] In a voltage calibration circuit, a post-processing circuit is an essential module. Its core function is to optimize and analyze the raw sampled signals obtained by the sampling circuit to improve the overall performance of the system. In this embodiment of the application, the post-processing circuit is used to adjust the voltage of the first power supply terminal and / or the voltage of the second power supply terminal based on the sampling results.

[0066] The post-processing circuit can dynamically adjust the output voltage of the first power supply terminal and / or the second power supply terminal of the single-photon avalanche diode through precise analysis of the avalanche pulse peak voltage Vex in the sampling results. Its essence is to achieve closed-loop control of the SPAD bias voltage, thereby ensuring that the single-photon avalanche diode always operates at the optimal balance point between detection efficiency and dark count rate, thereby improving the stability and reliability of the system in complex environments.

[0067] It can be seen that in the voltage calibration circuit provided in the embodiment of the present application, the quenching circuit controls the resistance of the resistor circuit based on the clock signal, so that the duration of time when the resistance is greater than or equal to the preset first resistance is greater than or equal to the first preset duration. This means that during the duration when the clock signal maintains the first level, the equivalent resistance between the first end of the single-photon avalanche diode and the first power supply end is large, and the circuit characteristics are equivalent to being in an off state. In this state, when the single-photon avalanche diode generates an avalanche pulse, the sampling signal generation circuit will quickly output a sampling signal pulse as a trigger signal for the sampling circuit after detecting the rising edge of the avalanche pulse. After receiving the sampling signal pulse, the sampling circuit will sample the avalanche pulse.

[0068] It is understandable that during the time that the clock signal maintains the first level, due to the high resistance of the resistor circuit, the decline process of the avalanche pulse will become extremely slow. This slow decline process prolongs the duration of the avalanche pulse, so that the sampling circuit can sample near the peak of the avalanche pulse or in the stable decline phase, thereby ensuring the accuracy and reliability of the sampled data. It can be seen that the voltage calibration circuit provided in the embodiment of the present application can tolerate a lower sampling rate during the sampling process while still accurately capturing the peak voltage of the pulse. This reduces the requirements for the design complexity of the sampling circuit, reduces the requirements for area and power consumption resources, improves the accuracy of sampling, and reduces errors caused by insufficient sampling rate or noise interference. Therefore, when the post-processing circuit adjusts the bias voltage (the voltage of the first power supply terminal and / or the voltage of the second power supply terminal) of the single-photon avalanche diode based on the accurate sampling results, it has a more accurate adjustment basis, thereby achieving more accurate voltage calibration and improving the performance stability of the single-photon avalanche diode.

[0069] In some embodiments, since unstable current or oscillation may exist in the early stage of avalanche, in order to ensure the sampling accuracy of the sampling circuit, the sampling signal generating circuit can generate a sampling signal pulse after a delay after detecting the rising edge of the avalanche pulse.

[0070] As another possible implementation, combining Figure 2 , see Figure 6 The sampling signal generating circuit 14 includes a monostable trigger circuit 141 and a delay circuit 142. The monostable trigger circuit 141 is configured to output a sampling signal pulse to the delay circuit 142 after detecting the rising edge of the avalanche pulse; the delay circuit 142 is configured to delay the sampling signal pulse to the sampling circuit after receiving the sampling signal pulse for a second preset time period.

[0071] The monostable trigger circuit 141 detects the rising edge of the avalanche pulse output by the single-photon avalanche diode (i.e., a photon-triggered high-level transition) and generates a fixed-width sampling signal pulse as the initial trigger signal. This ensures that each avalanche event triggers only one sampling event, avoiding multiple false triggers caused by noise or oscillation.

[0072] After receiving the sampling pulse output by the monostable circuit, the delay circuit 142 delays the pulse for a second predetermined time period before transmitting it to the sampling circuit. Since unstable current or oscillation may exist in the early stage of avalanche, delayed sampling ensures that the signal is captured after it stabilizes.

[0073] Combine Figure 5As shown, the voltage calibration circuit provided by this embodiment controls the resistance of the resistor circuit to be greater than or equal to the first resistance at time t0, that is, the single-photon avalanche diode can output an avalanche pulse to the sampling circuit. At time t1, the photon reaches the photosensitive region of the single-photon avalanche diode and triggers an avalanche multiplication effect, generating an avalanche pulse Vin. The sampling signal generation circuit 14 is based on the rising edge of Vin and delays τ (τ>Δt rise ) and then generates a sampling signal pulse Vs. The sampling circuit ADC starts sampling at time ts based on the Vs signal edge and completes sampling after Δts. Therefore, the sampling result is approximately the pulse peak value Vex.

[0074] It can be seen that the solution provided in this embodiment is to send the sampling signal pulse to the sampling circuit after the delay circuit receives the sampling signal pulse and delays it for a second preset time. This delayed sampling mechanism can ensure that the sampling window avoids the oscillation stage of the rising edge of the pulse, thereby avoiding the pulse establishment time difference caused by factors such as process deviation and eliminating the oscillation caused by inductor / capacitor parasitic parameters.

[0075] In some embodiments, MOS transistors can adjust their equivalent resistance by controlling the gate voltage. They also have fast turn-on and turn-off characteristics and can respond to control signals within nanoseconds. Therefore, the resistance of a resistor circuit can be adjusted by using the MOS transistor as a resistor circuit.

[0076] That is to say, as a feasible implementation method, Figure 2 As shown, the resistance circuit 121 includes a transistor ( Figure 2 Taking the transistor as NMOS as an example), the control circuit can control the resistance value of the resistance circuit by controlling the gate voltage Vq of the MOS tube.

[0077] Among them, the gate of the transistor is connected to the control end of the resistance circuit; the transistor is cut off when the gate voltage is a first voltage and is turned on when it is a second voltage; the source of the transistor is connected to the first end of the resistance circuit; and the gate of the transistor is connected to the second end of the resistance circuit.

[0078] It should be understood that the MOS transistor can be an NMOS transistor or a PMOS transistor, and the embodiments of the present application do not limit this.

[0079] Taking NMOS as an example, when the gate voltage Vq of the NMOS is 0 (or below its threshold voltage), the electric field between the gate and the channel is insufficient to form a conductive channel, and the NMOS is in the off state. At this time, the resistance between the source and the drain is extremely large (up to the terahertz level), equivalent to an open circuit, and the current passing through it is extremely small.

[0080] When the NMOS is off, the avalanche current generated by a single-photon avalanche diode (SPAD) cannot be quickly discharged through the NMOS. Due to the presence of parasitic capacitance (such as junction capacitance) within the SPAD, the charge generated during the avalanche is stored in the capacitance, causing the avalanche pulse voltage to maintain a near-constant peak value within microsecond timescales, and the avalanche pulse width can be as wide as several milliseconds.

[0081] When the gate voltage Vq increases to exceed the threshold voltage, a strong electric field forms between the gate and the channel of the NMOS. The carriers (electrons) in the channel are attracted in large numbers, forming a low-impedance path, and the NMOS enters the on state. At this time, the resistance between the source and the drain is significantly reduced (ohmic level), allowing current to flow quickly.

[0082] After the NMOS is turned on, the avalanche current is rapidly discharged through a low-impedance path between the source and drain of the NMOS. This rapidly increases the bias voltage across the single-photon avalanche diode, accelerating the avalanche recovery process and causing the voltage across the resistor circuit to drop rapidly. The recovery time is determined by the on-resistance of the NMOS, the resistor circuit, the parasitic capacitance of the single-photon avalanche diode, and external circuit parameters. It can typically be shortened to nanoseconds, achieving efficient quenching recovery.

[0083] It can be seen that in this embodiment, the resistance circuit includes a MOS transistor, so that its on-resistance can be changed in real time by adjusting the gate voltage of the MOS transistor, thereby achieving dynamic optimization of the quenching recovery speed and improving the response speed and dynamic range of the detector.

[0084] In some embodiments, to ensure the normal operation of the single-photon avalanche diode, quenching must be performed after the avalanche pulse is generated. Otherwise, the single-photon avalanche diode (SPAD) will burn out the device due to excessive current caused by the continuous avalanche effect, extend the dead time, and cause baseline drift.

[0085] As a feasible implementation method, please continue to refer to Figure 2 The second input terminal of the control circuit 122 is connected to the fourth power supply terminal 24, and the control circuit is further used to output the second voltage provided by the fourth power supply terminal to the control terminal of the resistance circuit when the clock signal is at the second level; the resistance value of the resistance circuit when the voltage at the control terminal is the second voltage is less than or equal to the second resistance value; the first resistance value is greater than the second resistance value.

[0086] Specifically, the control circuit receives a clock signal (CLK) whose level switches between a first level (high or low) and a second level (low or high). When CLK is at the first level, the control circuit outputs a first voltage provided by a third power supply terminal to the resistor circuit (the gate of the transistor), causing the resistance of the resistor circuit to be greater than the first resistance, thereby turning off the transistor. When CLK is at the second level, the control circuit outputs a second voltage provided by a fourth power supply terminal to the resistor circuit (the gate of the transistor), causing the resistance of the resistor circuit to be less than the second resistance, thereby turning on the transistor.

[0087] In this way, the gate voltage of the transistor can be controlled by the level of the clock signal to realize the on and off of the transistor, thereby controlling the avalanche recovery process of the single-photon avalanche diode.

[0088] As a feasible implementation manner, the clock signal switches periodically between a first level and a second level, and the duration of the first level in each period is a first duration.

[0089] The clock signal periodically switches between a first level (high or low) and a second level (low or high). The duration of the first level in each cycle is the first duration. This periodic clock signal divides time into fixed quenching and recovery phases, ensuring that the bias recovery and quenching processes of the single-photon avalanche diode are strictly executed according to the predetermined time within each cycle.

[0090] As a feasible implementation method, the duration of the second level in each cycle can be called a third preset duration, which is not limited in the embodiment of the present application.

[0091] During the third preset time period, the clock signal is at the second level, the resistance circuit is less than the preset second resistance value, the falling speed increases rapidly, and rapid recovery is achieved, thereby forming a trapezoidal avalanche pulse waveform.

[0092] It is understood that by accurately setting the cycle length and the first duration of each cycle, the quenching time and recovery time of the single-photon avalanche diode can be optimized, ensuring the stability and reliability of the single-photon avalanche diode under high-frequency operation. For example, under strong light conditions, the first duration can be appropriately shortened, and the voltage calibration frequency can be increased while ensuring the recovery effect. Under low light conditions, the first duration can be appropriately extended to ensure that photons can be detected within each cycle.

[0093] As a possible implementation, see Figure 2 The control circuit drives two transmission gates (TG) through the clock signal CLK, ensuring that only one transmission gate is turned on at any time and the other remains closed. This mutual exclusion control enables dynamic switching of signal paths.

[0094] The control ends of the two transmission gates are respectively connected to logically opposite signals (for example, one is connected to the first level of the clock signal, and the other is connected to the second level of the clock signal), and the input ends of the two transmission gates are respectively connected to the third power supply end and the fourth power supply end, so that the control circuit can control the opening and closing of the transmission gate based on the clock signal, and then control the conduction between the second power supply end or the first power supply end and the resistance circuit.

[0095] It should be understood that the resistor circuit in the embodiment of the present application is cut off when the voltage of the gate is the first voltage provided by the third power supply terminal. Since digital signals (such as binary codes) only contain high levels (1) and low levels (0), they are more tolerant to noise, while analog signals are continuous voltage values ​​and are easily affected by noise interference, resulting in voltage fluctuations and affecting the conduction state of the transmission gate.

[0096] Therefore, as a feasible implementation method, the second power supply terminal can output a digital control signal corresponding to the first voltage. Figure 2 As shown, the first input terminal of the control circuit is connected to the third power supply terminal through a digital-to-analog converter DAC.

[0097] It should be understood that the digital-to-analog converter is used to convert the digital control signal into an analog first voltage, so that the resistance circuit can adjust its own resistance based on the first voltage, thereby enabling the control circuit to be accurately controlled.

[0098] Since signal processing (such as photon counting, time marking, and energy spectrum analysis) is based on digital domain algorithms, the voltage calibration circuit also needs to convert analog pulses into digital codes. Therefore, as another feasible implementation method, Figure 2 As shown, the sampling circuit includes an analog-to-digital converter ADC, which is used to convert the sampled signal obtained by sampling into a digital signal to facilitate subsequent processing of the digital signal.

[0099] It should be understood that the ADC can also cooperate with a time-to-digital converter (TDC) to add a timestamp to the digital signal (such as the arrival time of the photon), which is not described in detail in the embodiments of the present application.

[0100] For example, please see Figure 5 The resistance of the resistor circuit can be controlled based on the clock signal CLK. At time t0, the clock signal CLK is controlled to change from a high level to a low level, causing the gate voltage Vq of the transistor to decrease and the resistance of the resistor circuit to be greater than or equal to a first resistance value. After the first duration (time t2), the clock signal CLK is controlled to change from a low level to a high level, causing the gate voltage Vq of the transistor to increase, and the resistance of the resistor circuit to be less than the first resistance value, thereby quenching the avalanche pulse. At time t3, the clock signal CLK is controlled to change from a high level to a low level, ending the current sampling cycle and restarting the avalanche pulse detection and sampling process in the next sampling cycle.

[0101] In some embodiments, since the control circuit needs to monitor or drive the single-photon avalanche diode, the reference potential of its input terminal must be aligned with one end of the single-photon avalanche diode (usually the end connected to the power supply or ground) to maintain potential matching and ensure the effectiveness of signal detection.

[0102] As a possible implementation, see Figure 3 The cathode of the single-photon avalanche diode is the first terminal, connected to the positive high-voltage power supply Vop; the anode is the second terminal, connected to the ground after passing through the resistor circuit. At this time, the first input terminal of the control circuit is connected to the power supply terminal VQH (high-level power supply terminal), and the second input terminal is grounded. It should be understood that Figure 3 The circuit shown can drive NMOS through VQH (a high voltage close to VDD), causing it to turn on quickly and quench avalanche current quickly, making it suitable for high-frequency detection.

[0103] As another possible implementation, see Figure 4 The anode of the single-photon avalanche diode is connected to the negative high-voltage power supply Vop, and the cathode is connected to VDD. In this configuration, the first input of the control circuit is connected to the power supply VQL (low-level power supply), and the second input is connected to VDD. Figure 4 The circuit shown can drive the PMOS with VQL (a low voltage close to GND), causing it to turn on slowly, reducing power consumption and noise, and is suitable for precision detection.

[0104] Combine Figure 3 and Figure 4 It can be seen that the first power supply terminal connected to the first end (cathode or anode) of the single-photon avalanche diode is consistent with the second input terminal of the control circuit, thereby achieving potential reference consistency, otherwise it may cause level mismatch or leakage current path problems.

[0105] The first input of the control circuit is connected to VQH or VQL. It should be understood that VQH and VQL control the conduction level of the MOS transistor, thereby adjusting the quenching and recovery speed of the single-photon avalanche diode. As a feasible implementation, the voltage values ​​of VQH and VQL are neither directly connected to ground (GND, 0V) nor directly connected to the power supply (VDD, such as 3.3V or 5V), but rather to an intermediate value.

[0106] If VQH is connected directly to VDD (e.g., 5V), the NMOS transistor will be fully turned on, quenching too quickly and potentially introducing noise. If VQL is connected directly to GND (0V), the PMOS transistor will be fully turned on and quenching too quickly, potentially introducing noise. Therefore, choosing an intermediate value (e.g., VQH = 4V, VQL = 1V) allows for fine-tuning of the MOS transistor's resistance and controlling the quenching and recovery speeds.

[0107] In some embodiments, in the voltage calibration circuit, the post-processing circuit is an essential module, and its core function is to optimize and analyze the original sampling signal obtained by the sampling circuit to improve the overall performance of the system.

[0108] Specifically, as a feasible implementation method, please refer to Figure 2 The voltage calibration circuit provided in the embodiment of the present application further includes a post-processing circuit 15, the input end of the post-processing circuit 15 is connected to the output end of the sampling circuit 13; wherein the post-processing circuit 15 is used to process the sampling result of the sampling circuit.

[0109] As a feasible implementation method, Figure 2 As shown, the clock terminal of the post-processing circuit 15 is used to receive the clock signal CLK. The clock signal CLK can be used as a timestamp reference to record the precise time of arrival of the photon.

[0110] It should be understood that this embodiment does not impose specific limitations on the role of the post-processing circuit. For example, since the avalanche signal output by a single-photon avalanche diode may include: dark counts (spurious signals triggered by thermal noise in the absence of photons); afterpulsing (secondary triggering caused by residual carriers from a previous avalanche); and environmental noise, power supply fluctuations, or external electromagnetic interference. Therefore, as a feasible implementation, the post-processing circuit can eliminate invalid signals collected by the sampling circuit through digital filtering or time-correlation analysis (such as time window screening).

[0111] As another feasible implementation, single-photon avalanche diodes (SPADs) can generate massive amounts of raw data at high photon rates (e.g., millions of pulses per second), making direct transmission or storage inefficient. Therefore, as a feasible implementation, post-processing circuits can implement photon counting statistics, accumulating valid photon events in real time and outputting count rates or histograms.

[0112] In some embodiments, the voltage across the single-photon avalanche diode (SPAD) is its bias voltage (i.e., operating voltage). The increase in this voltage relative to the breakdown voltage is an overbias voltage. The operating characteristics of a SPAD are significantly affected by overbias, and the breakdown voltage of a SPAD pixel exhibits consistency issues. Therefore, a circuit is required to automatically adjust the operating voltage and precisely control the overbias voltage consistency of the pixel to ensure the stability of the pixel's photodetection rate. The peak voltage of a SPAD avalanche pulse is approximately equal to the overbias voltage of the SPAD. Therefore, the operating voltage of the SPAD can be calibrated using the peak voltage of the SPAD avalanche pulse detected in the above embodiments.

[0113] As a feasible implementation, the post-processing circuit is also used to adjust the bias voltage of the single-photon avalanche diode in the following way:

[0114] S11. Determine an average voltage value corresponding to multiple sampling results.

[0115] Because a single avalanche event has random fluctuations, such as the statistical fluctuations of the avalanche gain, the charge in each avalanche may vary slightly even with the same photon energy. Another example is transient oscillations or power supply ripple during the quenching process, which can generate circuit noise interference.

[0116] Therefore, in this embodiment, the post-processing circuit calculates the average voltage of multiple sampling signals from the same single-photon avalanche diode pixel to eliminate the random fluctuations of a single avalanche event. By calculating the average of these multiple sampling signals, the steady-state operating voltage characteristic of the pixel can be obtained, reflecting its true overbias state.

[0117] S12: If the average voltage value is higher than the upper limit of the preset voltage range, the bias voltage of the single-photon avalanche diode is reduced.

[0118] The bias voltage is a voltage difference between a voltage at the second power supply terminal and a voltage at the first power supply terminal.

[0119] If the average voltage of multiple samples of a single pixel exceeds the upper limit of the preset range, it indicates that the current over-bias voltage (V ex ) is too high, which in turn leads to excessive avalanche gain and may increase the probability of afterpulsing. Furthermore, sustained high voltage may accelerate device aging and even cause thermal runaway. Therefore, the bias voltage (Vbias) is reduced to return the overbias voltage to a reasonable range. This stabilizes the avalanche gain of the single-photon avalanche diode, extending device life while maintaining detection efficiency near the specified value.

[0120] S13. If the average voltage value is lower than the lower limit of the preset voltage range, increase the bias voltage of the single photon avalanche diode.

[0121] If the average voltage value is lower than the lower limit of the preset range, it indicates that the bias voltage is insufficient, which will cause over-bias (V ex ) is insufficient, which reduces the avalanche gain and the photon detection efficiency (PDE).

[0122] Therefore, the bias voltage is increased to increase the overbias voltage, strengthen the electric field strength, and improve the avalanche probability of all pixels. Through dynamic compensation, edge pixels (such as those with large process deviations) can also achieve the detection efficiency of the center pixel.

[0123] It is understood that the solution provided in this embodiment can be used to perform detection, comparison, and adjustment over multiple clock cycles until the average voltage corresponding to the sampling results obtained based on the adjusted bias voltage falls within a preset voltage range. This ensures that the detection efficiency of the single-photon avalanche diode is consistent at different time points, thereby improving data reliability.

[0124] This embodiment adjusts the bias voltage based on the comparison between the average voltage value corresponding to the peak voltage of the avalanche pulse and the preset voltage range, thereby achieving precise adaptive control of the bias voltage. By continuously monitoring the average voltage value, changes in the working state of the single-photon avalanche diode can be identified: when the average voltage value exceeds or falls below the preset range, it means that the actual over-bias voltage deviates from the target value. At this time, the bias voltage can be fine-tuned to keep the working point in the optimal range. The solution provided by this embodiment first uses the statistical averaging method to effectively suppress the random fluctuations of a single avalanche event, ensuring the reliability of the adjustment decision; secondly, the preset voltage range can be flexibly set according to different application requirements to achieve programmable optimization of the working point; finally, the entire adjustment process is completely based on the working characteristics of the single-photon avalanche diode itself, without the introduction of an external reference benchmark, which simplifies the system architecture and ensures the accuracy of the adjustment, so that it can be better applied to single-photon avalanche diode application scenarios that require long-term stable operation.

[0125] In some embodiments, due to the random nature of photon arrival times, the avalanche pulses output by the single-photon avalanche diode are also randomly distributed in time. To ensure that the post-processing circuit can correctly use the sampling results, the data obtained by the sampling circuit must first be validated. Only when the sampling results are confirmed to be valid will they be transmitted to the post-processing circuit for further processing.

[0126] As a possible implementation, see Figure 2 The clock end of the sampling circuit 13 is used to receive the clock signal CLK; the sampling circuit 13 is specifically used to output the sampling result to the post-processing circuit 15 if the clock signal maintains the first level during the sampling of the first end of the single-photon avalanche diode.

[0127] It should be understood that when the clock signal is at the first level, the control circuit outputs the first voltage provided by the third power supply terminal to the transistor gate, causing the transistor to enter a cutoff state. At this point, the resistor circuit assumes a high-impedance state (with a resistance greater than the first resistance), allowing the avalanche pulse signal to be fully acquired. Therefore, during the sampling process at the second terminal of the single-photon avalanche diode, if the clock signal continuously maintains the first level, the sampling is deemed valid, and the sampling result is output to the post-processing circuit for further processing.

[0128] As a feasible implementation, the first level is a low level and the second level is a high level, that is, when the sampling signal pulse is a high level and the clock signal is always a low level, the sampling result is determined to be a valid sampling.

[0129] That is, during the sampling process, if the clock signal changes, or the clock signal remains at the second level, the sampling result obtained by the sampling circuit will not be quantized, or will be marked as an invalid sample.

[0130] For example, see Figure 7 , when the clock signal changes from the first level to the second level during the sampling period, the sampling is determined to be an invalid sampling.

[0131] For another example, see Figure 8 , when the clock signal maintains the second level during the sampling period, the sampling is determined to be an invalid sampling.

[0132] It can be seen that the solution provided in this embodiment strictly interlocks the phase of the sampling signal Vs and the clock signal (CLK) (CLK is forced to remain at a low level when Vs is high), ensuring that the sampling window is completely aligned with the avalanche pulse peak, avoiding the amplitude measurement error caused by time jitter in traditional asynchronous sampling, and thus improving the measurement accuracy and stability of the voltage calibration circuit in the random photon arrival scenario.

[0133] As a feasible implementation manner, the sampling circuit is further configured to output the sampling result to the post-processing circuit when the voltage value represented by the sampling result is higher than or equal to a preset voltage threshold.

[0134] Because single-photon avalanche diodes generate wiring crosstalk during operation, a threshold is applied to the voltage represented by the sampling result to prevent it from affecting the post-processing circuit. If the voltage is greater than or equal to the preset voltage threshold, the sampling result is determined to be a true avalanche signal that meets the amplitude requirements, i.e., a valid sample, and is output to the post-processing circuit.

[0135] For example, see Figure 9 If the peak voltage of the avalanche pulse is lower than the preset voltage threshold during the sampling period, the sampling signal Vs will remain at a low level and the sampling circuit will not start voltage sampling.

[0136] For another example, see Figure 10 ,When there is no pulse response during the sampling period, the sampling signal Vs will remain at a low level and the sampling circuit will not start voltage sampling.

[0137] As can be seen, the solution provided in this embodiment filters the sampling results using a preset voltage threshold to effectively distinguish true avalanche signals (typically with higher peak voltages) from noise interference (such as low-amplitude signals like trace crosstalk). This reduces the error rate of processing invalid sampled data and significantly improves the detection reliability of weak light signals. Furthermore, this hardware-level pre-screening reduces the inefficient computational load of post-processing circuits, optimizing overall energy efficiency while maintaining single-photon detection sensitivity.

[0138] In some embodiments, a single-photon avalanche diode (SPAD) is required to have high photon detection efficiency. Therefore, an overbias voltage Vex (e.g., 5V) exceeding the logic circuit power supply voltage VDD (e.g., 3.3V) is applied to the diode to produce a high-amplitude pulse. This high-amplitude pulse exceeds the input voltage range of the sampling circuit, preventing effective peak voltage sampling and quantization and potentially damaging the device.

[0139] As a feasible implementation method, combined with Figure 2 , see Figure 11 The voltage calibration circuit provided in the embodiment of the present application also includes: a voltage divider circuit 16; the first end of the voltage divider circuit 16 is connected to the first end 11-1 of the single-photon avalanche diode 11, and the second end is connected to the first power supply end 21, and the input end of the sampling circuit and the input end of the sampling signal generating circuit are connected to the voltage dividing node of the voltage divider circuit.

[0140] The voltage divider circuit 16 is used to divide the voltage of the avalanche pulse received by the single photon avalanche diode and output the divided avalanche pulse to the sampling circuit.

[0141] For example, as an implementation method, Figure 11 As shown, the voltage divider circuit 16 can use capacitors to perform voltage division.

[0142] The voltage divider circuit proportionally reduces the high-amplitude avalanche pulse output by the single-photon avalanche diode to a voltage range acceptable to the sampling circuit. By limiting the input voltage, it ensures the normal operation of the sampling circuit while preventing damage to the sampling circuit (such as the ADC and comparator) due to overvoltage. By properly configuring the voltage divider circuit, the amplitude of the divided pulse can be matched to the dynamic range of the sampling circuit, thereby improving sampling accuracy and signal-to-noise ratio.

[0143] In an exemplary embodiment, the present application also provides a single-photon avalanche diode detector, comprising: a single-photon avalanche diode, and a voltage calibration circuit according to any of the above embodiments. A first end of a resistor circuit of the voltage calibration circuit is connected to a first power supply terminal, a second end of the resistor circuit is connected to a first end of the single-photon avalanche diode, and a second end of the single-photon avalanche diode is connected to a second power supply terminal.

[0144] In an exemplary embodiment, the present application also provides a radar including the single-photon avalanche diode detector provided in the above embodiment. It should be understood that the radar may include additional components, such as an antenna, a processor, a display, etc., which are not described in detail in the present embodiment.

[0145] The above are only specific embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any changes or replacements within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A voltage calibration circuit, characterized in that: include: Quenching circuit, sampling circuit, sampling signal generating circuit and post-processing circuit; The quenching circuit includes a control circuit and a resistor circuit, wherein a first end of the resistor circuit is connected to a first power supply terminal, a second end of the resistor circuit is used to connect to a first end of a single-photon avalanche diode, and a second end of the single-photon avalanche diode is connected to a second power supply terminal; a voltage at the first power supply terminal is lower than a voltage at the second power supply terminal; The first input terminal of the control circuit is connected to the third power supply terminal, the clock terminal of the control circuit is used to receive a clock signal, and the output terminal of the control circuit is connected to the control terminal of the resistance circuit; The control circuit is configured to output the first voltage provided by the third power supply terminal to the control terminal of the resistance circuit when the clock signal is at the first level; the resistance value of the resistance circuit when the voltage at the control terminal is the first voltage is greater than or equal to the first resistance value; and the duration for which the clock signal maintains the first level is greater than or equal to a first preset duration; The input end of the sampling signal generating circuit is used to be connected to the first end of the single photon avalanche diode, and the output end is connected to the control end of the sampling circuit, and is used to output a sampling signal pulse after detecting the rising edge of the avalanche pulse; The input end of the sampling circuit is used to connect to the first end of the single-photon avalanche diode, and the output end of the sampling circuit is connected to the input end of the post-processing circuit. The sampling circuit is used to sample the first end of the single-photon avalanche diode when the control end thereof receives the sampling signal pulse, and send the sampling result obtained by sampling to the post-processing circuit; The post-processing circuit is used to adjust the voltage of the first power supply terminal and / or the voltage of the second power supply terminal based on the sampling result.

2. The voltage calibration circuit according to claim 1, wherein: The resistance circuit includes a transistor; The gate of the transistor is connected to the control end of the resistance circuit; the source of the transistor is connected to the first end of the resistance circuit; the drain of the transistor is connected to the second end of the resistance circuit; the transistor is cut off when the gate voltage is the first voltage and is turned on when the gate voltage is the second voltage.

3. The voltage calibration circuit according to claim 1 or 2, characterized in that: The clock signal periodically switches between the first level and the second level; The second input terminal of the control circuit is connected to the fourth power supply terminal, and the control circuit is further used to output the second voltage provided by the fourth power supply terminal to the control terminal of the resistance circuit when the clock signal is at the second level; the resistance value of the resistance circuit when the voltage at the control terminal is the second voltage is less than or equal to the second resistance value; the first resistance value is greater than the second resistance value.

4. The voltage calibration circuit according to claim 1, wherein: The sampling signal generating circuit includes: a monostable trigger circuit and a delay circuit; the monostable trigger circuit is used to output the sampling signal pulse to the delay circuit after detecting the rising edge of the avalanche pulse; The delay circuit is used for sending the sampling signal pulse to the sampling circuit after delaying for a second preset time after receiving the sampling signal pulse.

5. The voltage calibration circuit according to claim 1, wherein: The clock terminal of the sampling circuit is used to receive a clock signal; The sampling circuit is specifically configured to output a sampling result to the post-processing circuit if the clock signal maintains a first level during sampling of the second end of the single-photon avalanche diode.

6. The voltage calibration circuit according to claim 1, wherein: The sampling circuit is further configured to output the sampling result to the post-processing circuit when a voltage value represented by the sampling result is higher than a preset voltage threshold.

7. The voltage calibration circuit according to claim 1, wherein: The post-processing circuit is specifically used to: Determining an average voltage value corresponding to a plurality of the sampling results; If the average voltage value is higher than an upper limit of a preset voltage range, reducing the bias voltage of the single photon avalanche diode; The bias voltage is a voltage difference between a voltage at the second power supply terminal and a voltage at the first power supply terminal; If the average voltage value is lower than the lower limit of the preset voltage range, the bias voltage of the single photon avalanche diode is increased.

8. The voltage calibration circuit according to claim 1, wherein: The voltage calibration circuit further includes: a voltage divider circuit; The first end of the voltage divider circuit is connected to the first end of the single photon avalanche diode, and the second end is connected to the first power supply end. The input end of the sampling circuit and the input end of the sampling signal generating circuit are connected to the voltage dividing node of the voltage divider circuit.

9. A single photon avalanche diode detector, characterized in that: include: A single photon avalanche diode, and a voltage calibration circuit according to any one of claims 1 to 8; The first end of the resistance circuit of the voltage calibration circuit is connected to the first power supply end, the second end of the resistance circuit is connected to the first end of the single photon avalanche diode, and the second end of the single photon avalanche diode is connected to the second power supply end.

10. A radar, characterized in that: include: The single photon avalanche diode detector according to claim 9.

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