Self-bias and temperature compensation band-gap reference power supply

Abstract

The invention relates to a self-biasing and temperature compensation band-gap reference power supply which comprises a PTAT current generation circuit, a temperature coefficient elimination circuit, a divider resistance network and a resistance network current generation circuit. The power supply circuit is powered by VDD, and the PTAT current generating circuit generates PTAT current through a positive feedback loop. In a temperature coefficient elimination circuit, a self-biased reference current is adopted to provide a bias current for a Zener diode, and a bias current with a zero temperature coefficient is designed to provide a path of bias current for the Zener diode. A negative feedback circuit is introduced into the resistance network current generation circuit to provide another path of configuration current for the Zener diode, and it is ensured that the Zener diode works in a reverse breakdown region and operates stably. And the output precision is improved while positive and negative temperature coefficients are eliminated. The circuit provided by the invention has the advantages of high cost performance, high output precision and good temperature drift characteristic, the circuit is simplified, the integrated manufacturing is easy, the output noise is low, and the reliability is also remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, in particular to a self-biased and temperature-compensated bandgap reference power supply. Technical Background

[0002] like Figure 1 As shown, existing bandgap voltage references provide stable reference voltage outputs for control circuits. These output voltages must be unaffected by the manufacturing process, input voltage, and ambient temperature. They are widely used in circuits such as power management and ADCs. These high-precision, low-temperature drift, and low-noise bandgap references are indispensable components of analog circuits. Traditional bandgap reference circuits are compatible with CMOS processes. While high-order compensation or segmented compensation can reduce the reference voltage's temperature drift, manufacturing process and cost factors hinder cost-effective temperature drift performance. Furthermore, the output noise is high, requiring external capacitors to reduce it. Furthermore, the output voltage is susceptible to package stress, resulting in post-operation performance that generally fails to meet the requirements of high-precision and high-stability circuits. Long-term reliability issues can also hinder sustained high performance. Consequently, numerous designers have been diligently working to design and manufacture high-performance, cost-effective bandgap references. Summary of the Invention

[0003] The purpose of the present invention is to solve the defects of the prior art, such as high output noise, output voltage being easily affected by package stress, and difficulty in meeting high precision and high stability, and to provide a self-biased and temperature-compensated bandgap reference power supply.

[0004] The technical solution adopted in the present invention is as follows:

[0005] A self-biased and temperature-compensated bandgap reference power supply includes a PTAT current generating circuit, a temperature coefficient elimination circuit, a voltage divider resistor network, and a bias current circuit, wherein the bias current circuit is connected to a Zener diode, and is characterized in that:

[0006] (1) The temperature coefficient elimination circuit is composed of PMOS tubes MP3 and MP4, NMOS tubes MN3 and MN4, PMOS tube MP5, PNP transistor Q3, Zener diode D1 and resistor R3. The temperature coefficient elimination circuit provides a bias current with zero temperature coefficient for Zener diode D1.

[0007] (2) A resistor network current generating circuit consisting of a PMOS transistor MP6, an NMOS transistor MN5, an operational amplifier A1, and a resistor R2 is set up to play a negative feedback role; when the output reference voltage drifts, the circuit generates another bias current to correct the working state of the Zener diode in real time.

[0008] On the basis of the above technical solutions, there are the following further technical solutions:

[0009] The PTAT current generating circuit is composed of PMOS transistors MP1 and MP2, NMOS transistors MN1 and MN2, PNP transistors Q1 and Q2, and resistor R1. The sources of the PMOS transistors MP1 and MP2 are connected to the input power supply VDD, and the gates of the PMOS transistors MP1 and MP2 are connected to the drains of the PMOS transistor MP2 and the NMOS transistor MN2. The drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1, the gates of MN1, and the gates of MN2. The source of the NMOS transistor MN1 is connected to the emitter of the transistor Q1. The source of the NMOS transistor MN2 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the emitter of the transistor Q2. The base and collector of the transistor Q1 are connected to the power supply 0V. The base and collector of the transistor Q2 are also connected to the power supply 0V.

[0010] The temperature coefficient elimination circuit is composed of PMOS tubes MP3 and MP4, NMOS tubes MN3 and MN4, PMOS tube MP5, PNP triode Q3, Zener diode D1 and resistor R3; the source of PMOS tube MP3 and MP4 are connected to the input power supply VDD; the gate of PMOS tube MP3 is connected to the drain of MP3, the gate of MP4 and the drain of NMOS tube MN3; the drain of MP4 is connected to one end of resistor R3, the drain of PMOS tube MP5 and the cathode of Zener diode D1; the source of PMOS tube MP5 is connected to the input power supply VDD; the other end of resistor R3 is connected to NM The source of the OS transistor MN4 is connected to one end of the resistor R4; the gates of the NMOS transistors MN3 and MN4 are connected to the gates of the NMOS transistors MN1 and MN2 in the PTAT current generating circuit; the sources of MN3 and MN4 are connected to the emitter of the transistor Q3; the base and collector of the transistor Q3 are connected to the input power supply 0V; the temperature coefficient elimination circuit generates a self-biased reference current to provide a bias current for the Zener diode D1, while the PMOS transistor MP5 provides another bias current for the Zener diode. The current generates positive and negative voltage drops in the resistor network and the resistor voltage divider network that vary with temperature, thereby achieving positive and negative temperature coefficient elimination.

[0011] The resistor network current generating circuit comprises a PMOS transistor MP6, an NMOS transistor MN5, an operational amplifier A1, and a resistor R2. The source of the PMOS transistor MP6 is connected to the input power supply VDD; the drain of the PMOS transistor MP6 is connected to the gate of MP6, the gate of MP5, and the drain of the NMOS transistor MN5; the gate of MN5 is connected to the output terminal of the operational amplifier A1; the source of MN5 is connected to one end of the resistor R2 and the negative input terminal of the operational amplifier; and the other end of the resistor R2 is connected to the power supply 0V. The negative feedback circuit formed by the operational amplifier A1, the resistor R2, the PMOS transistor MP6, and the NMOS transistor MN5 is such that when R2=R5 and the gain of the operational amplifier A1 is ignored, the current flowing through the resistor R2 is equivalent to the current flowing through the voltage divider resistor network R4 and R5. Due to the mirror characteristics of the PMOS transistors MP5 and MP6, the PMOS transistor MP5 provides another bias current to the Zener diode D1.

[0012] The voltage divider resistor network is composed of resistors R4, R5, and capacitor C1; one end of resistor R4 is connected to the other end of resistor R3 and the drain of NMOS transistor MN4; the other end of resistor R4 is connected to one end of resistor R5, one end of capacitor C1, the positive input terminal of the operational amplifier, and the output terminal Vout of this circuit; the other end of noise reduction capacitor C1 and the other end of resistor R5 are connected to the input power supply 0V. Noise reduction capacitor C1 is a built-in capacitor on the chip and is used to eliminate high-frequency noise on the chip.

[0013] Due to the adoption of the above technical solution, the PTAT current is replicated through a current mirror to drive a temperature coefficient cancellation circuit. In the temperature coefficient cancellation circuit, a self-bias current with a zero temperature coefficient is designed to provide a bias current for the Zener diode. A negative feedback circuit is introduced into the resistor network current generation circuit to provide another configuration current for the Zener diode to correct the Zener diode's operating state in real time, ensuring that the Zener diode operates in the reverse breakdown region and operates stably, achieving positive and negative temperature coefficient cancellation while improving output accuracy and stability. The circuit of the present invention not only has highly cost-effective output accuracy and good temperature drift characteristics, but also simplifies the circuit, facilitates integrated manufacturing, reduces output noise, and significantly improves reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Attachment Figure 1 FIG. 1 is a block diagram showing the principle of a conventional bandgap reference power supply according to the present invention;

[0015] Attachment Figure 2 FIG2 is a schematic diagram of a self-biased and temperature-compensated bandgap reference power supply according to the present invention;

[0016] Attachment Figure 3 The figure shows the simulation results of the self-biased and temperature-compensated bandgap reference power supply according to the present invention as the temperature changes;

[0017] Attachment Figure 4 Shown are the output noise simulation results of a self-biased and temperature-compensated bandgap reference power supply according to the present invention.

[0018] Specific implementation:

[0019] 1. The present invention provides a self-biased and temperature-compensated bandgap reference power supply, the circuit schematic diagram of which is as follows: Figure 2 As shown, it includes a PTAT current generating circuit, a temperature coefficient elimination circuit, a voltage divider resistor network, and a resistor network current generating circuit; the circuit is powered by VDD, and the PTAT current generating circuit is composed of PMOS tubes MP1 and MP2, NMOS tubes MN1 and MN2, PNP transistors Q1 and Q2, and resistor R1. The PTAT current generating circuit generates a PTAT current through a positive feedback loop to provide a driving signal for the temperature coefficient elimination circuit; the temperature coefficient elimination circuit is composed of PMOS tubes MP3 and MP4, NMOS tubes MN3, MN4, MN5, PNP transistor Q3, Zener diode D1, and resistor R3 and PMOS tube MP5. A self-biased reference current is used to provide bias current for the Zener diode, and a bias current with zero temperature coefficient is designed. The Zener diode operates in the reverse breakdown region. The PTAT current is replicated through a current mirror to provide bias current for the Zener diode and generate positive and negative voltage drops that vary with temperature in the resistor network, thereby eliminating the positive and negative temperature coefficients. The resistor network current generation circuit is composed of a PMOS transistor MP6, an NMOS transistor MN5, an operational amplifier A1, and a resistor R2. The voltage divider resistor network is composed of resistors R4, R5, and capacitor C1. All components of this circuit are scientifically matched through precise calculations and have the remarkable characteristics of easy integration, low temperature drift, high output accuracy, low output noise, and high reliability.

[0020] 2. Circuit diagram as follows Figure 2 As shown, the PTAT current generating circuit is composed of PMOS transistors MP1 and MP2, NMOS transistors MN1 and MN2, PNP transistors Q1 and Q2, and resistor R1. The sources of the PMOS transistors MP1 and MP2 are connected to the input power supply VDD; the gates of the PMOS transistors MP1 and MP2 are connected to the drains of the PMOS transistor MP2 and the NMOS transistor MN2; the drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1, the gates of MN1, and the gates of MN2; the source of the NMOS transistor MN1 is connected to the emitter of the transistor Q1; the source of the NMOS transistor MN2 is connected to one end of the resistor R1; the other end of the resistor R1 is connected to the emitter of the transistor Q2; the base and collector of the transistor Q1 are connected to the power supply 0V; and the base and collector of the transistor Q2 are connected to the power supply 0V. The PTAT current generating circuit generates a PTAT current through a positive feedback loop, providing a stable driving current for the temperature coefficient cancellation circuit.

[0021] 3. Circuit diagram as follows Figure 2 As shown, the temperature coefficient elimination circuit is composed of PMOS transistors MP3 and MP4, NMOS transistors MN3 and MN4, PMOS transistor MP5, PNP transistor Q3, Zener diode D1, and resistor R3; the source of PMOS transistor MP3 and MP4 are connected to the input power supply VDD; the gate of PMOS transistor MP3 is connected to the drain of MP3, the gate of MP4, and the drain of NMOS transistor MN3; the drain of MP4 is connected to one end of resistor R3, the drain of PMOS transistor MP5, and the cathode of Zener diode D1; the source of PMOS transistor MP5 is connected to the input power supply VDD; the other end of resistor R3 is connected to the source of NMOS transistor MN4 and one end of resistor R4; NMOS transistors MN3, The gate of MN4 is connected to the gates of NMOS tubes MN1 and MN2 in the PTAT current generating circuit; the sources of MN3 and MN4 are connected to the emitter of transistor Q3; the base of transistor Q3 is connected to the collector and the input power supply 0V; in this circuit, a self-biased reference current is used to provide a bias current for Zener diode D1, and a bias current with a zero temperature coefficient is designed. The Zener diode operates in the reverse breakdown region, and the PTAT current is copied through the current mirror to provide a bias current for the Zener diode. At the same time, the PMOS tube MP5 provides another bias current for the Zener diode. The current generates positive and negative voltage drops that change with temperature in the resistor network and the resistor voltage divider network, realizing the elimination of positive and negative temperature coefficients and ensuring Figure 2 The voltage of node A in the circuit eliminates the influence of ambient temperature and does not require a bias current source to be connected outside the chip.

[0022] 4. Circuit diagram as follows Figure 2 As shown, the resistor network current generating circuit is composed of a PMOS transistor MP6, an NMOS transistor MN5, an operational amplifier A1, and a resistor R2. The source of the PMOS transistor MP6 is connected to the input power supply VDD; the drain of the PMOS transistor MP6 is connected to the gate of MP6 and the drain of the NMOS transistor MN5; the gate of MN5 is connected to the output terminal of the operational amplifier A1; the source of MN5 is connected to one end of the resistor R2 and the negative input terminal of the operational amplifier; the other end of the resistor R2 is connected to the power supply 0V. The negative feedback circuit composed of the operational amplifier A1, the resistor R2, the PMOS transistor MP6, and the NMOS transistor MN5, when R2=R5 and the gain of the operational amplifier A1 is ignored, the current flowing through the resistor R2 is equal to the current flowing through the voltage divider resistor network R4 and R5. Due to the mirror characteristics of the PMOS transistors MP5 and MP6, the PMOS transistor MP5 provides another bias current to the Zener diode D1, ensuring the stability of the static operating current of the Zener diode D1 in the reverse breakdown region, thereby ensuring Figure 2 Voltage stability at node A in the circuit.

[0023] 5. Circuit diagram as follows Figure 2As shown in the figure, the voltage divider resistor network circuit is composed of resistors R4, R5, and capacitor C1. One end of resistor R4 is connected to the other end of resistor R3 and the drain of NMOS transistor MN4. The other end of resistor R4 is connected to one end of resistor R5, one end of capacitor C1, the positive input terminal of the operational amplifier, and the output terminal Vout of this circuit. The other end of noise reduction capacitor C1 and the other end of resistor R5 are connected to the input power supply 0V. Noise reduction capacitor C1 is a built-in capacitor of the chip and is used to eliminate high-frequency noise on the chip.

[0024] 6. Circuit diagram as follows Figure 2 As shown, electronic components can be used for modular production, or bulk silicon technology can be used for overall production.

[0025] 7. Design calculation

[0026] In the operating temperature range, the base-to-emitter voltage of the transistor has a negative temperature coefficient. When the two transistors operate at different current densities, the difference between their base-to-emitter voltages is proportional to the absolute temperature. The PTAT current generated by the PTAT current generating circuit is recorded as :

[0027]

[0028] and is the base-to-emitter voltage of the PNP transistors Q1 and Q2, and the voltage difference is recorded as :

[0029]

[0030] Where k is the Boltzmann constant, q is the charge carried by the electron, and N is the ratio of the collector area of Q2 to that of Q1.

[0031] Q3, MN3 and Q1, MN1 form a current mirror, Q3, MN3 copy the PTAT current to get the current :

[0032]

[0033] The currents flowing through MN3 and MN4 are and , the current flowing through MP3 is equal to the current flowing through MN3 , MP4 proportionally copies the current on MP3 through the current mirror to obtain the current :

[0034]

[0035] The static operating current of the Zener diode D1 in the reverse breakdown region is , an additional loop is needed to stabilize its working state. The loop is composed of R2, R3, R4, R5, operational amplifier A1, NMOS transistor MN5, PMOS transistors MP5 and MP6. Let R2 = R5. Amplifier A1 and MN5 form a current series negative feedback loop. Ignoring the limited gain of the amplifier, it is easy to obtain that the current flowing through R2 and R5 is equal:

[0036]

[0037] MP5 and MP6 form a current mirror, and we get .

[0038] Current flowing through resistor R3 is the current flowing through MN4 plus the current flowing through R5:

[0039]

[0040] Current flowing through Zener diode D1 :

[0041]

[0042] By adjusting the P in the current mirror ratio of MP3 and MP4, the current flowing into D1 can be adjusted. The bias current of D1 is a positive temperature coefficient current. In the temperature range [-55℃, 125℃], the positive temperature coefficient current flows through D1. When the reverse breakdown voltage of D1 is V Z V changes with temperature T Z (T), in this interval V Z (T) monotonically increasing, V Z (T) has a positive temperature coefficient.

[0043] The voltage value of node A is V A It is V Z Subtract the voltage drop across resistor R3:

[0044]

[0045] I5 is composed of a zero temperature coefficient voltage V OUT Produced, at V A Ignore the I5 term when taking the derivative with respect to temperature T:

[0046]

[0047] By adjusting the current mirror multiple M and the resistance value of resistor R3, the zero temperature coefficient voltage V A , V A Finally, it presents first-order compensation, V A Output zero temperature coefficient voltage V through the voltage divider resistor network OUT:

[0048]

[0049] Resistor R5 in parallel with capacitor C1 is used to eliminate on-chip output noise, achieving low-noise output without the need for external capacitors. If high-frequency noise signals are present in the chip's external circuits, a noise reduction capacitor can be connected in parallel to the Vout output.

[0050] 8. Beneficial effects

[0051] (1) The present invention solves the problem that the Zener diode in the bandgap reference voltage source needs to use an external bias current.

[0052] (2) The temperature coefficient elimination circuit uses a self-biased reference current to provide bias current for the Zener diode, and designs a bias current with zero temperature coefficient. The negative feedback loop in the resistor network current generation circuit monitors the output power drift in real time to provide another configuration current for the Zener diode, and corrects the working state of the Zener diode in real time. Figure 3 Figure 4 As shown, compared with the traditional bandgap reference voltage source, the present invention further improves the output accuracy of the Zener diode bandgap reference circuit and reduces the output noise. The bias current with zero temperature coefficient minimizes the nonlinearity of the Zener diode voltage changing with temperature.

[0053] (3) The use of self-biased reference current technology reduces design complexity, modular manufacturing cost and debugging cost. At the same time, the use of self-biased reference current makes the circuit more reliable.

Claims

1. A self-biased and temperature-compensated bandgap reference power supply, comprising a PTAT current generating circuit, a temperature coefficient cancellation circuit, a voltage divider resistor network, and a bias current circuit, wherein the bias current circuit is connected to a Zener diode, characterized in that: (1) The temperature coefficient elimination circuit is composed of PMOS tubes MP3 and MP4, NMOS tubes MN3 and MN4, PMOS tube MP5, PNP transistor Q3, Zener diode D1 and resistor R3. The temperature coefficient elimination circuit provides a bias current with zero temperature coefficient for Zener diode D1. (2) A resistor network current generating circuit consisting of a PMOS transistor MP6, an NMOS transistor MN5, an operational amplifier A1, and a resistor R2 is set up to play a negative feedback role; when the output reference voltage drifts, the circuit generates another bias current to correct the working state of the Zener diode in real time.

2. The self-biased and temperature-compensated bandgap reference power supply according to claim 1, wherein: The PTAT current generating circuit is composed of PMOS transistors MP1 and MP2, NMOS transistors MN1 and MN2, PNP transistors Q1 and Q2, and resistor R1. The sources of the PMOS transistors MP1 and MP2 are connected to the input power supply VDD, and the gates of the PMOS transistors MP1 and MP2 are connected to the drains of the PMOS transistor MP2 and the NMOS transistor MN2. The drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1, the gates of MN1, and the gates of MN2. The source of the NMOS transistor MN1 is connected to the emitter of the transistor Q1. The source of the NMOS transistor MN2 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the emitter of the transistor Q2. The base and collector of the transistor Q1 are connected to the power supply 0V. The base and collector of the transistor Q2 are also connected to the power supply 0V.

3. The self-biased and temperature-compensated bandgap reference power supply according to claim 1, wherein: The temperature coefficient elimination circuit is composed of PMOS tubes MP3 and MP4, NMOS tubes MN3 and MN4, PMOS tube MP5, PNP transistor Q3, Zener diode D1 and resistor R3; the source of PMOS tube MP3 and MP4 are connected to the input power supply VDD; the gate of PMOS tube MP3 is connected to the drain of MP3, the gate of MP4 and the drain of NMOS tube MN3; the drain of MP4 is connected to one end of resistor R3, the drain of PMOS tube MP5 and the cathode of Zener diode D1; the source of PMOS tube MP5 is connected to the input power supply VDD; the other end of resistor R3 is connected to the NMOS The source of transistor MN4 is connected to one end of resistor R4; the gates of NMOS transistors MN3 and MN4 are connected to the gates of NMOS transistors MN1 and MN2 in the PTAT current generating circuit; the sources of MN3 and MN4 are connected to the emitter of transistor Q3; the base and collector of transistor Q3 are connected to the input power supply 0V; the temperature coefficient elimination circuit generates a self-biased reference current to provide a bias current for Zener diode D1, while the PMOS transistor MP5 provides another bias current for the Zener diode. The current generates positive and negative voltage drops in the resistor network and the resistor voltage divider network that vary with temperature, thereby achieving positive and negative temperature coefficient elimination.

4. The self-biased and temperature-compensated bandgap reference power supply according to claim 1, wherein: The resistor network current generating circuit consists of a PMOS transistor MP6, an NMOS transistor MN5, an operational amplifier A1, and a resistor R2. The source of the PMOS transistor MP6 is connected to the input power supply VDD; the drain of the PMOS transistor MP6 is connected to the gate of MP6, the gate of MP5, and the drain of the NMOS transistor MN5; the gate of MN5 is connected to the output terminal of the operational amplifier A1; the source of MN5 is connected to one end of the resistor R2 and the negative input terminal of the operational amplifier; and the other end of the resistor R2 is connected to the power supply 0V. The negative feedback circuit formed by the operational amplifier A1, resistor R2, PMOS transistor MP6, and NMOS transistor MN5 is such that when R2 = R5 and the gain of the operational amplifier A1 is ignored, the current flowing through resistor R2 is equivalent to the current flowing through the voltage divider resistor network R4 and R5. Due to the mirror characteristics of the PMOS transistors MP5 and MP6, the PMOS transistor MP5 provides another bias current to the Zener diode D1.

5. The self-biased and temperature-compensated bandgap reference power supply according to claim 1, wherein: The voltage-divider resistor network consists of resistors R4, R5, and capacitor C1. One end of resistor R4 is connected to the other end of resistor R3 and the drain of NMOS transistor MN4. The other end of resistor R4 is connected to one end of resistor R5, one end of capacitor C1, the positive input terminal of the operational amplifier, and the output terminal Vout of this circuit. The other end of noise reduction capacitor C1 and the other end of resistor R5 are connected to the input power supply 0V. Noise reduction capacitor C1 is a built-in capacitor on the chip and is used to eliminate high-frequency noise on the chip.

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