A storage device and a processing method of firmware exception thereof

Abstract

The application provides a storage device and a processing method for firmware exception of the storage device. The storage device comprises a flash memory and a main controller connected with the flash memory. The main controller comprises a static random storage unit and a central processing unit. The central processing unit is used for monitoring the running state of the storage device, reading part of test data from the flash memory and writing the test data into the static random storage unit when the running state of the storage device is in a firmware exception state, comparing the test data with the written data in the static random storage unit to obtain a normal detection result. The central processing unit is also used for performing bit inversion on the test data to obtain inverted data, writing the inverted data into the static random storage unit, comparing the inverted data with the written data in the static random storage unit to obtain an inverted detection result. The central processing unit is also used for generating exception detection information according to the normal detection result and the inverted detection result. The application can analyze the causes of the firmware exception of the storage device.

Description

Technical Field

[0001] This invention relates to the field of static storage technology, and in particular to a storage device and a method for handling firmware anomalies. Background Technology

[0002] When a firmware anomaly occurs in a storage device, it may be a minor fault caused by a bit flip in the static random access memory (SRAM) cell, or a serious fault caused by a controller logic error or an inability to correct the error using error correction code (ECC).

[0003] In existing technologies, when a storage device experiences a firmware anomaly, the common practice is to directly implement write protection without analyzing the cause of the anomaly. If the firmware anomaly is caused by a bit flip in the static random access memory (SRAM) cell, subsequent write protection removal requires specific vendor commands, a prolonged period of complete power failure, or returning the device to the factory for specialized tools, or may even be impossible. All of these factors affect the normal operation of the storage device. Therefore, there is room for improvement. Summary of the Invention

[0004] This invention provides a method for handling firmware anomalies in storage devices, in order to improve the technical problem in the prior art where direct write protection processing for firmware anomalies caused by bit flips in storage devices affects the normal use of the storage device.

[0005] This invention proposes a storage device, comprising:

[0006] flash memory;

[0007] A main controller, connected to the flash memory, the main controller comprising:

[0008] Static random access memory (SRAM);

[0009] The central processing unit is used to monitor the operating status of the storage device, and when the operating status of the storage device is in a firmware abnormal state, write all the data in the static random access memory unit to the flash memory and record it as test data.

[0010] The central processing unit is also used to read a portion of the test data from the flash memory and write it to the static random access memory unit, and compare the portion of the test data with the written data in the static random access memory unit to obtain a normal test result;

[0011] The central processing unit is also used to invert the bits of the partial test data to obtain inverted data, write the inverted data into the static random access memory, and compare the inverted data with the written data in the static random access memory to obtain the inverted detection result.

[0012] The central processing unit is also used to generate abnormal detection information based on normal detection results and inverted detection results.

[0013] In one embodiment of the present invention, the central processing unit is used to invert the bits of the partial test data to obtain first inverted data, write the first inverted data into the static random access memory unit, and denot it as first written data; compare the first inverted data with the first written data to obtain a first inverted detection result;

[0014] The central processing unit is further configured to invert the first inverted data bitwise to obtain the second inverted data, write the second inverted data into the static random access memory unit, and denot it as the second written data; compare the second inverted data with the second written data to obtain the second inverted detection result;

[0015] Based on the first and second inverted detection results, an inverted detection result is generated.

[0016] In one embodiment of the present invention, the central processing unit is used to divide the storage area of ​​the static random access unit according to the amount of data of the partial test data to obtain multiple storage sub-areas;

[0017] The central processing unit is also used to write the partial test data and the inverted data into each storage sub-area respectively, and obtain the corresponding normal detection results and inverted detection results;

[0018] Anomaly detection information is generated based on the normal detection results and the inverted detection results corresponding to each storage sub-region.

[0019] In one embodiment of the present invention, the storage space size of each storage sub-region is the same as the data size of the portion of test data.

[0020] In one embodiment of the present invention, the central processing unit is used to write the partial test data and the inverted data into each storage sub-region in sequence according to the arrangement order of the multiple storage sub-regions.

[0021] In one embodiment of the present invention, the central processing unit is used to generate bit-flipping anomaly detection information when the normal detection result is that the partial test data is different from the written data in the static random access unit, and / or the inverted detection result is that the inverted data is different from the written data in the static random access unit;

[0022] Otherwise, generate anomaly detection information for other faults.

[0023] In one embodiment of the present invention, the central processing unit is further configured to, after generating anomaly detection information of bit flipping, obtain the storage sub-region in the static random access memory unit where bit flipping has occurred; wherein, the storage region of the static random access memory unit includes multiple storage sub-regions.

[0024] In one embodiment of the present invention, the central processing unit is further configured to adjust the voltage of the power supply supplying power to the static random access memory unit after generating anomaly detection information of bit flipping.

[0025] The central processing unit is further configured to, after each adjustment of the voltage supplying the static random access memory unit, write the partial test data and the inverted data to the storage sub-region where bit flips have occurred, compare the partial test data with the written data in the storage sub-region where bit flips have occurred, and compare the inverted data with the written data in the storage sub-region where bit flips have occurred, until no bit flips occur in the storage sub-region where bit flips have occurred.

[0026] In one embodiment of the present invention, the central processing unit is further configured to obtain the minimum and maximum voltage values ​​for supplying power to the static random access memory unit when no bit flip occurs on the storage sub-region where a bit flip has occurred.

[0027] Calculate the average of the minimum and maximum voltage values, and use the average value as the optimal voltage value for supplying power to the static random access memory (SRAM) unit.

[0028] This invention also proposes a method for handling firmware anomalies in storage devices, comprising:

[0029] Monitor the operating status of the storage device, and when the operating status of the storage device is in a firmware abnormal state, write all the data in the static random access memory unit to the flash memory and record it as test data;

[0030] Partial test data is read from the flash memory and written to the static random access memory (SRAM). The partial test data is compared with the data written in the SRAM to obtain a normal test result.

[0031] The test data is bitwise inverted to obtain inverted data, which is then written into the static random access memory (SRAM). The inverted data is compared with the data written into the SRAM to obtain the inverted detection result.

[0032] Anomaly detection information is generated based on the normal detection results and the inverted detection results.

[0033] The beneficial effects of this invention are as follows: This invention proposes a method for handling firmware anomalies in a storage device. By monitoring the operating status of the storage device, when the device is in a firmware anomaly state, a portion of test data is written to the static random access memory (SRAM) for a first detection. Then, the portion of test data is bitwise inverted to obtain inverted data, which is then written to the SRAM for a second detection. If the portion of test data is the same as the data written to the SRAM, and the inverted data is also the same as the data written to the SRAM, it indicates that no bit offset has occurred in the SRAM, meaning the firmware anomaly is not caused by bit offset, and write protection can be applied to the storage device. Otherwise, bit offset has occurred in the SRAM, meaning the firmware anomaly is caused by bit offset, and the SRAM can be repaired, thus ensuring the normal operation of the storage device. Attached Figure Description

[0034] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0035] In the attached diagram:

[0036] Figure 1 This is a schematic diagram of the structure of a storage device provided in one embodiment of the present invention.

[0037] Figure 2 This is a schematic diagram of static random access memory (SRAM) detection of a storage device provided in one embodiment of the present invention.

[0038] Figure 3 This is a schematic diagram of static random access memory (SRAM) detection of a storage device provided in another embodiment of the present invention.

[0039] Figure 4 This is a method for handling firmware anomalies in storage devices provided in one embodiment of the present invention.

[0040] The attached figures are labeled as follows:

[0041] 10. Storage device; 20. Main controller; 21. Central processing unit; 22. Static random access memory; 30. Flash memory; 31. Block. Detailed Implementation

[0042] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0043] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0044] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0045] Please see Figures 1 to 4 This invention proposes a storage device and a method for handling firmware anomalies, applicable to the field of static storage technology, such as embedded multimedia cards (EMMC), solid-state drives (SSDs), and universal flash storage (UFS). When a firmware anomaly occurs during operation, the method analyzes the cause of the anomaly, enabling repair of the storage device in cases of non-critical firmware failures, thereby ensuring its normal operation. Detailed analysis follows with specific embodiments.

[0046] Please see Figure 1 In one embodiment of the present invention, a storage device 10 is provided, which may include a main controller 20 and flash memory 30.

[0047] The main controller 20 is a dedicated processor chip responsible for managing the overall operation of the storage device 10, interface protocol conversion, and underlying flash memory management. The flash memory 30 is a non-volatile storage medium, an array of memory cells composed of floating gate transistors, used for permanent data storage. The main controller 20 relies on the flash memory 30 for physical storage space; without the flash memory 30, data cannot be stored. The flash memory 30 depends on the main controller 20 for operability; for example, the flash memory 30 requires the main controller 20 to issue conversion instructions, manage bad blocks, and perform error correction instructions before it can be used by the host.

[0048] Specifically, the main controller 20 may include a central processing unit 21 and a static random access memory (SRAM) 22. The central processing unit 21 is the core of the storage device 10 for both computation and control, and the static random access memory 22 is the internal memory that exchanges data with the central processing unit 21.

[0049] Specifically, the central processing unit 21 is used to monitor the operating status of the storage device 10, and when the operating status of the storage device 10 is in a firmware abnormal state, it writes all the data in the static random access storage unit 22 into the flash memory 30 and records it as test data.

[0050] For example, bit errors may occur in the static random access memory (SRAM) cell 22 during use. Although the storage device 10 undergoes final testing (FT) at the packaging and testing facility to reject memory chips with bit errors before shipment, the external environment is uncontrollable during actual use. No matter how much the packaging and testing facility simulates, it cannot achieve 100% coverage. Different supply voltages, ambient temperatures, and data types can all cause bit errors in the storage device 10. Therefore, bit errors in the SRAM cell 22 are entirely possible during the use of the storage device 10, leading to firmware anomalies.

[0051] Therefore, it is evident that during the use of storage device 10, when a firmware anomaly occurs due to a 22-bit flip in the static random access memory (SRAM) cell, storage device 10 can be repaired to maintain normal operation. Thus, when a firmware anomaly occurs in storage device 10, the cause can be analyzed. If it is caused by a 22-bit flip in the SRAM cell, storage device 10 can be repaired. If it is caused by a multi-bit error, an error that error correction code (ECC) cannot correct, a logic error in the main controller 20, or other fatal firmware errors not caused by bit flips, write protection should be implemented on storage device 10.

[0052] In one embodiment of the present invention, when the storage device 10 is in a firmware abnormality state, the central processing unit 21 reads a portion of test data from the flash memory 30 and writes it to the static random access memory (SRAM) 22, compares the portion of test data with the written data in the SRAM 22, and obtains a normal detection result. A normal detection result can be that the portion of test data is the same as the written data in the SRAM 22, or it can be that the portion of test data is different from the written data in the SRAM 22; if they are different, it means that a bit offset has occurred.

[0053] The central processing unit 21 is also used to invert a portion of the test data bitwise to obtain inverted data, write the inverted data to the static random access memory (SRAM) unit 22, and compare the inverted data with the written data in the SRAM unit 22 to obtain the inversion detection result. The inversion detection result can be that the inverted data is the same as the written data in the SRAM unit 22, or it can be that the inverted data is different from the written data in the SRAM unit 22.

[0054] Subsequently, the central processing unit 21 generates anomaly detection information based on the normal detection results and the inverted detection results. The central processing unit 21 generates bit-flipped anomaly detection information when the normal detection result indicates that part of the test data differs from the data written to the static random access memory (SRAM) unit 22, and / or when the inverted detection result indicates that the inverted data differs from the data written to the SRAM unit 22. Otherwise, it generates anomaly detection information for other faults.

[0055] For example, if some test data is the same as the data written in the static random access memory (SRAM) 22, and the inverted data is the same as the data written in the SRAM 22, it indicates that the firmware malfunction of the storage device 10 is not caused by bit offset in the SRAM 22.

[0056] For example, if some test data is different from the data written in the static random access memory (SRAM) 22, and the inverted data is the same as the data written in the SRAM 22, it indicates that the firmware of the storage device 10 is abnormal because bit offset occurs in the SRAM 22.

[0057] For example, if some test data is the same as the data written in the static random access memory (SRAM) 22, and the inverted data is different from the data written in the SRAM 22, it indicates that a bit offset has occurred in the SRAM 22, causing a firmware malfunction in the storage device 10.

[0058] For example, if some test data is different from the data written in the static random access memory (SRAM) 22, and the inverted data is different from the data written in the SRAM 22, it indicates that a bit offset has occurred in the SRAM 22, causing a firmware malfunction in the storage device 10.

[0059] Please see Figure 1 In one embodiment of the present invention, the static random access storage unit 22 may include a data buffer and a table buffer. The data buffer is used to cache user read and write data, and the table buffer is used to store algorithm-related table data.

[0060] When a firmware error occurs in storage device 10, all data in the data cache area and the table cache area can be recorded into code block 31 of flash memory 30. Furthermore, the location information of the data in the data cache area and the location information of the data in the table cache area can be updated into system block 31 of flash memory 30.

[0061] Specifically, the data in the data cache is written to the code block 31 of the flash memory 30, and after all the data in the data cache is written to the code block 31 of the flash memory 30, it is determined whether the data in the table cache has been written to the code block 31 of the flash memory 30.

[0062] When the data in the table cache area has been written to the code block 31 of the flash memory 30, all the data in the static random access unit 22 has been written to the flash memory 30 to serve as a storage backup.

[0063] If the data in the table cache is not written or is not fully written to the code block 31 of the flash memory 30, the data in the table cache can be copied to the data cache first, and then the data in the table cache can be written to the code block 31 of the flash memory 30 through the data cache, thereby realizing the writing of all the data in the static random access unit 22 to the flash memory 30.

[0064] Please see Figure 1, Figure 2 and Figure 3 In one embodiment of the present invention, a portion of the test data read by the central processing unit 21 from the flash memory 30 can be cached in a cache area, and the test data can be inverted in the cache area. The cache area can be a fixed storage area in the storage device 10, or a portion of the storage area in the static random access memory unit 22.

[0065] Specifically, such as Figure 2 Specifically, position 1 in the static random access memory 22 can be used as a data buffer, and some test data can be cached in this data buffer. It is required that no bit flips occur in this data buffer. Part of the test data from the data buffer corresponding to position 1 is written to the data detection area corresponding to position 2 for data verification. That is, it is determined whether the part of the test data in the data buffer is the same as the data written in the data detection area. If they are the same, it means that no bit flip has occurred; if they are different, it means that a bit flip has occurred.

[0066] Next, in the data buffer corresponding to position 1, a portion of the test data is inverted to obtain inverted data. The inverted data in the data buffer corresponding to position 1 is written to the data detection area corresponding to position 2 for data verification. That is, it is determined whether the inverted data in the data buffer is the same as the written data in the data detection area. If they are the same, it means that no bit offset has occurred; if they are different, it means that bit offset has occurred.

[0067] Specifically, such as Figure 3 As shown, in this embodiment, a bit error occurred in the data detection area corresponding to position 2. Then, following the same method used to detect position 2, the data detection area corresponding to position 3 can be detected using partial test data and inverted data from position 1 to determine whether a bit error will occur at position 3.

[0068] Please see Figure 1 In one embodiment of the present invention, the central processing unit 21 performs bitwise inversion on a portion of the test data to obtain inverted data. The inversion operation can be performed once or twice.

[0069] For example, the central processing unit 21 performs a bitwise inversion on a portion of the test data only once to obtain inverted data. When a portion of the test data is 011010 (both 0 and 1 are binary numbers, and the test data and inverted data mentioned below are also binary numbers), the inverted data is 100101. This allows for the detection of a six-bit storage area in the static random access memory (SRAM) unit 22, with each bit being checked for both 0 and 1, preventing any missed detections. Of course, in actual testing, the number of test bits is greater, corresponding to a larger storage area in the SRAM unit 22, typically a 4KB unit.

[0070] As mentioned above, a single inversion operation is sufficient to verify the binary 0s and 1s of each bit. However, a single inversion operation only flips the value of each bit once; for example, a 0 is changed to a 1, but no 1 is changed to a 0. Therefore, in addition to verifying the binary 0s and 1s of each bit, the transformation operations from 0 to 1 and from 1 to 0 must also be considered, meaning two inversion operations are possible.

[0071] Specifically, the central processing unit 21 inverts a portion of the test data bit-by-bit to obtain first inverted data, and writes the first inverted data into the static random access memory unit 22, denoted as first written data. The first inverted data is compared with the first written data to obtain the first inverted detection result. When the first inverted data and the first written data are the same, it indicates that no bit offset has occurred; when the first inverted data and the first written data are different, it indicates that bit offset has occurred.

[0072] The central processing unit 21 is also used to invert the first inverted data bit by bit to obtain the second inverted data, and write the second inverted data into the static random access memory unit 22, denoted as the second written data. The second inverted data and the second written data are compared to obtain the second inversion detection result. When the second inverted data and the second written data are the same, it indicates that no bit offset has occurred; when the second inverted data and the second written data are different, it indicates that bit offset has occurred.

[0073] The central processing unit 21 generates an inversion detection result based on the first inversion detection result and the second inversion detection result.

[0074] Please see Figure 1 In one embodiment of the present invention, if a bit offset is detected in the static random access memory unit 22, a repair process is required. The prerequisite for the repair process is to determine the specific location where the bit offset occurs in the static random access memory unit 22.

[0075] Specifically, the central processing unit 21 is used to divide the storage area of ​​the static random access storage unit 22 into multiple storage sub-regions based on the amount of partial test data. The central processing unit 21 is also used to write partial test data and inverted data into each storage sub-region respectively, and obtain the corresponding normal detection results and inverted detection results. The central processing unit 21 is also used to generate anomaly detection information based on the normal detection results and inverted detection results corresponding to each storage sub-region.

[0076] The storage space size of each storage sub-region is the same as the data size of a portion of the test data. Furthermore, the central processing unit 21 writes a portion of the test data and the inverted data sequentially into each storage sub-region according to the arrangement order of the multiple storage sub-regions, in order to detect whether bit offset has occurred in each storage sub-region.

[0077] Please see Figure 1 In one embodiment of the present invention, the central processing unit 21 is further configured to, after generating anomaly detection information of bit flipping, obtain the storage sub-region in the static random access memory unit 22 where bit flipping has occurred. The storage region of the static random access memory unit 22 includes multiple storage sub-regions.

[0078] The central processing unit 21 is also used to adjust the voltage supplied to the static random access memory unit 22 after generating anomaly detection information of bit flipping.

[0079] The central processing unit 21 is also used to write partial test data and inverted data to the storage sub-region where bit flips have occurred after each adjustment of the voltage supply to the static random access memory unit 22, and to compare the partial test data with the written data in the storage sub-region where bit flips have occurred, and to compare the inverted data with the written data in the storage sub-region where bit flips have occurred, until no bit flips occur in the storage sub-region where bit flips have occurred.

[0080] When no bit flip occurs in the storage sub-region where a bit flip has occurred, it indicates that the voltage supplied to the static random access memory (SRAM) cell 22 is appropriate. At this time, no bit flip will occur in other normal storage sub-regions of the SRAM cell 22. Under this supply voltage, no firmware abnormality will occur in the storage device 10.

[0081] Please see Figure 1 In one embodiment of the present invention, the central processing unit 21 is further configured to obtain the minimum and maximum voltage values ​​for supplying power to the static random access memory (SRAM) unit 22 when no bit flipping occurs in the storage sub-region where bit flipping has occurred. The average value of the minimum and maximum voltage values ​​is calculated, and this average value is used as the optimal voltage value for supplying power to the SRAM unit 22.

[0082] Please see Figure 4 In one embodiment of the present invention, a method for handling firmware anomalies in a storage device is proposed, comprising the following steps.

[0083] Step S10: Monitor the operating status of the storage device, and when the operating status of the storage device is in a firmware abnormal state, write all the data in the static random access memory of the storage device to the flash memory of the storage device and record it as test data.

[0084] Step S20: Read a portion of the test data from the flash memory and write it into the static random access memory (SRAM). Compare the portion of the test data with the data written into the SRAM to obtain a normal test result.

[0085] Step S30: Invert the bits of the test data to obtain inverted data, write the inverted data into the static random access memory (SRAM), and compare the inverted data with the written data in the SRAM to obtain the inverted detection result.

[0086] Step S40: Generate abnormal detection information based on the normal detection results and the inverted detection results.

[0087] Therefore, it is evident that during the use of storage device 10, when a firmware anomaly occurs due to a 22-bit flip in the static random access memory (SRAM) cell, storage device 10 can be repaired to maintain normal operation. Thus, when a firmware anomaly occurs in storage device 10, the cause can be analyzed. If it is caused by a 22-bit flip in the SRAM cell, storage device 10 can be repaired. If it is caused by a multi-bit error, an error that error correction code (ECC) cannot correct, a logic error in the main controller 20, or other fatal firmware errors not caused by bit flips, write protection should be implemented on storage device 10.

[0088] This invention proposes a method for handling firmware anomalies in storage devices. When a firmware anomaly occurs during the operation of a storage device, the cause of the firmware anomaly can be analyzed, so that the storage device can be repaired when the firmware anomaly is not caused by a serious fault, thereby ensuring the normal use of the storage device.

[0089] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A storage device, characterized in that, include: flash memory; A main controller, connected to the flash memory, the main controller comprising: Static random access memory (SRAM); The central processing unit is used to monitor the operating status of the storage device, and when the operating status of the storage device is in a firmware abnormal state, write all the data in the static random access memory unit to the flash memory and record it as test data. The central processing unit is also used to read a portion of the test data from the flash memory and write it to the static random access memory unit, and compare the portion of the test data with the written data in the static random access memory unit to obtain a normal test result; The central processing unit is also used to invert the bits of the partial test data to obtain inverted data, write the inverted data into the static random access memory, and compare the inverted data with the written data in the static random access memory to obtain the inverted detection result. The central processing unit is also used to generate abnormal detection information based on normal detection results and inverted detection results; The central processing unit is further configured to, after generating anomaly detection information of bit flipping, obtain the storage sub-region in the static random access memory (SRAM) where bit flipping has occurred; the central processing unit is configured to adjust the voltage supplied to the SRAM; wherein, the storage area of ​​the SRAM includes multiple storage sub-regions; The central processing unit is further configured to, after each adjustment of the voltage supplying the static random access memory unit, write the partial test data and the inverted data to the storage sub-region where bit flips have occurred, compare the partial test data with the written data in the storage sub-region where bit flips have occurred, and compare the inverted data with the written data in the storage sub-region where bit flips have occurred, until no bit flips occur in the storage sub-region where bit flips have occurred.

2. The storage device according to claim 1, characterized in that, The central processing unit is used to invert the bits of the partial test data to obtain first inverted data, write the first inverted data into the static random access memory unit, and record it as first written data; compare the first inverted data with the first written data to obtain the first inverted detection result; The central processing unit is further configured to invert the first inverted data bitwise to obtain the second inverted data, and write the second inverted data into the static random access memory unit, denoted as the second written data; Compare the second inverted data with the second written data to obtain the second inverted detection result; Based on the first and second inverted detection results, an inverted detection result is generated.

3. The storage device according to claim 1, characterized in that, The central processing unit is used to divide the storage area of ​​the static random access unit into multiple storage sub-areas based on the amount of data in the partial test data. The central processing unit is also used to write the partial test data and the inverted data into each storage sub-area respectively, and obtain the corresponding normal detection results and inverted detection results; Anomaly detection information is generated based on the normal detection results and the inverted detection results corresponding to each storage sub-region.

4. The storage device according to claim 3, characterized in that, The storage space size of each storage sub-region is the same as the data size of the portion of test data.

5. The storage device according to claim 3, characterized in that, The central processing unit is used to write the partial test data and the inverted data into each storage sub-region in sequence according to the arrangement order of the multiple storage sub-regions.

6. The storage device according to claim 1, characterized in that, The central processing unit is used to generate bit-flipping anomaly detection information when the normal detection result is that the partial test data is different from the written data in the static random access unit, and / or the inverted detection result is that the inverted data is different from the written data in the static random access unit; Otherwise, generate anomaly detection information for other faults.

7. The storage device according to claim 1, characterized in that, The central processing unit is also used to obtain the minimum and maximum voltage values ​​for supplying power to the static random access memory unit when no bit flip occurs in the storage sub-region where a bit flip has occurred. Calculate the average of the minimum and maximum voltage values, and use the average value as the optimal voltage value for supplying power to the static random access memory (SRAM) unit.

8. A method for handling firmware anomalies in a storage device, characterized in that, include: Monitor the operating status of the storage device, and when the operating status of the storage device is in a firmware abnormal state, write all the data in the static random access memory of the storage device to the flash memory of the storage device and record it as test data; Partial test data is read from the flash memory and written to the static random access memory (SRAM). The partial test data is compared with the data written in the SRAM to obtain a normal test result. The test data is bitwise inverted to obtain inverted data, which is then written into the static random access memory (SRAM). The inverted data is compared with the data written into the SRAM to obtain the inverted detection result. Based on the normal detection results and the inverted detection results, abnormal detection information is generated; After generating anomaly detection information for bit flipping, the storage sub-region in the static random access memory (SRAM) where bit flipping occurred is obtained; the voltage supplying power to the SRAM is adjusted; wherein, the storage region of the SRAM includes multiple storage sub-regions; After each adjustment of the voltage supplying the static random access memory (SRAM) cell, the partial test data and the inverted data are written to the storage sub-region where bit flips occur. The partial test data is compared with the written data in the storage sub-region where bit flips occur, and the inverted data is compared with the written data in the storage sub-region where bit flips occur, until no bit flips occur in the storage sub-region where bit flips occur.

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