Chip testing method and electronic device

Abstract

The application discloses a chip testing method and electronic equipment, and belongs to the technical field of semiconductors. The method first acquires level signals of each byte channel of a measured chip, and determines level reference values of each channel through reference voltage calibration. Subsequently, byte-independent timing testing is independently performed based on the reference values: under a fixed clock period, a plurality of reading delays are configured for each byte channel in sequence, and data setup time and data hold time are measured in real time based on sampling points of a command end and a target end data selection signal. Through the combination of pre-calibration level reference values and byte-independent testing, the duty cycle imbalance and output difference problems among multiple byte channels are effectively solved, and the measurement precision of timing parameters of a storage chip is significantly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and particularly relates to a chip testing method and electronic equipment. BACKGROUND

[0002] The AC timing of a memory chip directly affects the speed binning of the chip. Currently, the industry uses a method of scanning the boundaries of a data signal (DQ / DQS) by moving a strobe point to measure key parameters such as tDQSCK (clock skew time), tDQSQ (data strobe window), etc. However, this method has two key problems: one is duty unbalance, mainly caused by manufacturing process deviation leading to asymmetric output driving capability and signal edge distortion caused by packaging parasitic parameters; the other is byte output difference, resulting from the difference in internal wiring length of the chip and the non-uniformity of the etching process.

[0003] These problems cause the existing testing method to be unable to accurately reflect the real timing characteristics of each byte channel, seriously affecting the reliability of the test results. SUMMARY

[0004] The main purpose of the present application is to provide a chip testing method and electronic equipment, aiming to solve the problem of insufficient test precision caused by duty unbalance and byte output difference in the existing AC timing test, thereby improving the accuracy of the timing parameter measurement of the memory chip.

[0005] To achieve the above purpose, the present application provides a chip testing method, which comprises:

[0006] obtaining a level signal output by each byte channel of a tested chip;

[0007] based on the level signal, performing reference voltage calibration on each byte channel to determine a level reference value of each byte channel;

[0008] based on the level reference value, independently performing byte-by-byte timing test on each byte channel, comprising:

[0009] configuring a plurality of reading delays for each byte channel in sequence under a preset clock period;

[0010] for each reading delay, measuring the data setup time and data hold time under the current configuration based on the strobe point of the command end data strobe signal and the target end data strobe signal of the byte channel.

[0011] The present application also provides a testing system for a memory chip, comprising:

[0012] The acquisition module is configured to acquire a level signal output by each byte channel of the chip under test;

[0013] The control module is configured to perform reference voltage calibration on each byte channel based on the level signal to determine a level reference value of each byte channel.

[0014] The test module is configured to independently perform byte-by-byte timing test on each byte channel based on the level reference value, including: configuring a plurality of reading delays for each byte channel in sequence under a preset clock cycle; and measuring data setup time and data hold time under the current configuration based on the gating sampling points of the command end data strobe signal and the target end data strobe signal of the byte channel for each reading delay.

[0015] The present application also provides an electronic device, including a memory, a processor and a computer program stored in the memory and running on the processor, wherein the processor implements the steps of the chip test method when executing the computer program.

[0016] The present application also provides a non-transitory computer readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the chip test method when executed by a processor.

[0017] The technical scheme of the present application aims to solve the duty cycle imbalance problem, acquires the level signal output by each byte channel of the chip in advance before testing, then performs reference voltage calibration on each byte channel based on the level signal to determine the level reference value of each byte channel, thereby providing a more accurate level reference for subsequent testing. Then, based on the level reference value, byte-by-byte timing test is independently carried out on each byte channel. For the byte output difference problem, a plurality of reading delays are configured for each byte channel in sequence under a preset clock cycle; and for each reading delay, the data setup time and data hold time under the current configuration are measured based on the gating sampling points of the command end data strobe signal and the target end data strobe signal of the byte channel. In this way, the best and most accurate AC timing parameters can be effectively measured, and in the byte test, the mode can be effectively reduced, thereby improving the accuracy of the timing parameter measurement of the storage chip.

[0018] Therefore, the present application solves the duty cycle imbalance and byte output difference problems by acquiring the level in advance and calibrating the reference value, and independently carrying out timing test operation byte by byte, thereby improving the accuracy of the timing parameter measurement of the storage chip. BRIEF DESCRIPTION OF DRAWINGS

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0020] Figure 1 A flowchart of a chip testing method provided in an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of chip signal transmission and timing provided in an embodiment of the present invention;

[0022] Figure 3 This is a flowchart of the reference voltage setting process in chip testing provided in an embodiment of the present invention;

[0023] Figure 4 A flowchart for setting gating sampling points in chip testing provided in this embodiment of the invention;

[0024] Figure 5 This is a diagram showing the relationship between the chip's AC timing parameters provided in an embodiment of the present invention.

[0025] Figure 6 Waveforms acquired by an oscilloscope as provided in an embodiment of the present invention;

[0026] Figure 7 This is a schematic diagram of the chip testing system provided in an embodiment of the present invention;

[0027] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0028] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0030] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0031] The AC timing parameters of a memory chip are timing parameters related to address, command, and control signals, including key parameters such as clock offset time (tDQSCK) and data strobe window (tDQSQ). They directly affect the chip's speed binding, determining the timing coordination and constraints between signals during AC signal transmission. Their role is to measure key performance indicators of the memory chip. Precise AC timing parameters ensure accurate and stable data transmission between the chip and external devices, preventing data errors or transmission failures due to signal timing mismatches. Furthermore, in the chip's research, development, production, and testing stages, accurate calculation of these parameters allows for the effective measurement of precise timing indicators, thereby improving chip performance and quality to meet the needs of different application scenarios.

[0032] However, current industry measurement methods suffer from duty cycle imbalances caused by manufacturing process deviations (such as asymmetrical output drive capability and signal edge distortion), as well as differences in byte output caused by internal chip routing and manufacturing etching issues. This makes it difficult for existing testing methods to accurately reflect the true timing characteristics of each byte channel, affecting the reliability of test results and highlighting the importance of accurately calculating AC timing parameters.

[0033] Based on this, the present invention provides a chip testing method and an electronic device, which are described in detail below with reference to the accompanying drawings.

[0034] Please refer to Figure 1 , Figure 1 A flowchart illustrating a chip testing method provided in an embodiment of the present invention. A chip testing method, the method comprising:

[0035] S110: Obtain the level signal output of each byte channel of the chip under test.

[0036] Specifically, using pre-set test equipment or circuits, the output level of each byte channel in the chip under test is acquired and collected. A byte channel refers to an independent channel in the chip used to transmit byte data, and the level signal indicates whether the channel outputs a high or low level. This step provides the raw data basis for subsequent reference voltage calibration. Because the output levels of different byte channels may vary due to factors such as manufacturing processes, acquiring the level signal can accurately determine the characteristics of each byte channel. Only by acquiring accurate level signals can targeted processing and calibration be performed in subsequent steps, thereby ensuring the accuracy of the entire test.

[0037] S120 performs reference voltage calibration for each byte channel based on the level signal to determine the level reference value for each byte channel.

[0038] Specifically, based on the acquired level signals output by each byte channel, a reference voltage (Voltage of High-level reference) calibration operation is performed on each byte channel. The calibration process involves analyzing the high and low voltage conditions of the level signals and adjusting the reference voltage according to a specific algorithm (e.g., taking half the difference between high and low voltages) to determine a suitable reference voltage (Voh) for each byte channel's characteristics. Because of issues such as duty cycle imbalance and byte output differences within the chip, the output characteristics of different byte channels may be inconsistent. Reference voltage calibration can reduce the impact of these differences on the test results, allowing subsequent tests based on the reference value to more accurately reflect the true situation of each byte channel, thus improving the reliability and consistency of the test results.

[0039] S130, based on the level reference value, independently performs byte-by-byte timing tests on each byte channel, including: configuring multiple levels of read delay for each byte channel in sequence under a preset clock cycle; for each read delay, measuring the data setup time and data hold time under the current configuration based on the selection sampling points of the command end data strobe signal and the target end data strobe signal of that byte channel.

[0040] Specifically, after determining the level reference value Voh for each byte channel, timing tests are performed independently for each byte channel. The specific operation is as follows:

[0041] Configuring multi-level read latency involves setting multiple different levels of read latency (RL, such as RL, RL-1, ..., RL-N, where N is the total number of byte channels of the chip under test) for each byte channel within a pre-set clock cycle (e.g., CK_c, CK_t, which provides a synchronization reference for chip operation, and chip data transmission, command execution, and other operations are all performed in an orderly manner under its control). The read latency determines the time interval from issuing a read command to the data reaching the required valid output. For example, when set to RL, after issuing a read command through the command address signal CA[5:0] (used to transmit chip command and address information, such as read command, write command, and memory address instructions), the data signal (DQ)[7:0] (used to transmit the actual data content) will start outputting valid data that meets the timing requirements only after the time delay corresponding to RL.

[0042] Measure timing parameters. For each set read delay, perform the following operations: acquire the data signal waveform at fixed sampling point positions of DQS_c and DQS_t, where the sampling point positions can be preset by the chip design specifications or the test system; analyze the setup time (tDS) of the data signal relative to the effective edge of DQS_c and the hold time (tDH) relative to the effective edge of DQS_t based on the waveform.

[0043] The measurement data setup time and data hold time are specifically defined as follows: under the current configuration, the measurement data setup time (tDS, which is the shortest time required for the data signal (DQ) to reach the corresponding byte channel level reference value Voh before the valid edge of the command end data strobe signal (DQS_c) arrives, and the data hold time (tDH, which is the shortest time for the data signal (DQ) to maintain the corresponding byte channel level reference value Voh after the valid edge of the target end data strobe signal (DQS_t) arrives).

[0044] by Figure 2 Taking the chip signal transmission and timing diagram shown below as an example, Figure 2The diagram illustrates the clock signal CK_c / CK_t, the command address signal CA[5:0], the data signal (DQ)[7:0], and multiple byte channels (such as Byte0, Byte1, ..., Byte31). Due to variations in chip manufacturing processes and trace lengths, data transmission between different byte channels differs. Therefore, independent read delay settings and testing are required to obtain the AC timing parameters for each channel. Driven by the clock signal (CK_c / CK_t), the command address signal CA[5:0] transmits the read command first. After the corresponding read delay, the data signal (DQ)[7:0] begins output. Different read delay settings (RL, RL-1, ..., RL-N) result in different data output start times. Simultaneously, the data output of each byte channel is relatively independent. By using fixed sampling points, the waveforms of the command-side data strobe signal (DQS_c) and the target-side data strobe signal (DQS_t) are acquired, and parameters such as data setup time and data hold time are measured to comprehensively and accurately evaluate the AC timing characteristics of each channel.

[0045] By performing timing tests byte-by-byte independently, precise measurements can be taken for the unique characteristics of each byte channel, avoiding interference from differences in byte outputs. Through configuring multi-level read latency and gating-based sampling points, data setup and hold times under different conditions can be measured comprehensively and meticulously, accurately obtaining the AC timing parameters of each byte channel. This effectively measures the best and most accurate timing indicators, improving the accuracy of timing parameter measurements for memory chips and better evaluating chip performance.

[0046] Therefore, steps S110 to S130 above, by combining pre-calibrated level reference values ​​with byte-by-byte independent testing, effectively solve the problems of duty cycle imbalance and output differences between multi-byte channels, and significantly improve the measurement accuracy of memory chip timing parameters (such as tDS / tDH of DDR / LPDDR).

[0047] In some embodiments, the method further includes:

[0048] S140, based on the measured data setup time and data hold time of each byte channel, independently calculate the AC timing parameters of that byte channel.

[0049] Specifically, in the field of memory chip testing, data setup time (tDS) and data hold time (tDH) are two key timing parameters. This step aims to use the measured data setup time (tDS) and data hold time (tDH) of each byte channel to obtain the complete AC timing parameters (ACtiming) of each byte channel through a pre-defined calculation method. AC timing parameters are a set of timing parameters related to address, command, and control signals, including numerous indicators reflecting the chip's signal transmission time characteristics, such as clock offset time (tDQSCK) and data strobe window (tDQSQ).

[0050] As a core set of indicators for measuring the performance of memory chips, accurate calculation of AC timing parameters is crucial for a comprehensive and detailed understanding of the chip's timing characteristics during AC signal transmission, such as signal synchronization and stability. Only by obtaining precise AC timing parameters can we determine whether the chip meets design requirements and the needs of specific application scenarios. For example, in high-speed data transmission scenarios, accurate AC timing parameters are key to ensuring accurate data transmission. Furthermore, calculating AC timing parameters using data setup time (tDS) and data hold time (tDH) can effectively avoid test errors caused by issues such as unbalanced duty cycles and byte output differences within the chip. Previous S110 to S130 test procedures have significantly reduced the impact of these issues on tDS and tDH measurements. Calculating AC timing parameters based on this foundation can more accurately reflect the true timing characteristics of each byte channel, greatly improving the reliability and consistency of test results, and thus providing a more reliable basis for chip quality assessment and speed classification.

[0051] In some embodiments, please refer to Figure 3 , Figure 3 A flowchart illustrating the reference voltage setting process during chip testing, provided for embodiments of the present invention. The process for setting the reference voltage during chip testing includes:

[0052] S310 sends a write-read instruction sequence to the chip under test.

[0053] Specifically, the purpose of sending a write-read command sequence is to prompt the chip to perform data write and read operations, thereby generating the level signals that need to be acquired subsequently. In the testing process of memory chips, by first writing specific data to the chip and then reading it back, relevant information during data transmission can be effectively obtained.

[0054] During the stable data output phase, the S320 synchronously acquires the extreme voltage values ​​of the data pins of each byte channel.

[0055] Specifically, a precision measurement unit (PMU) can be used to record high and low voltage values. A PMU is a specialized device capable of accurately measuring parameters such as voltage and current. Selecting to perform data acquisition during a stable data output phase ensures the accuracy and reliability of the acquired voltage values, avoiding the acquisition of erroneous or highly fluctuating data during periods of unstable output. By synchronously acquiring the voltage extreme values ​​of each byte channel's data pin (DQ pin), the maximum and minimum voltage extreme values ​​for each byte channel can be obtained separately.

[0056] S330 records the maximum voltage extreme value collected from each channel as a high-level signal and the minimum voltage extreme value collected as a low-level signal.

[0057] Specifically, the maximum voltage extreme value collected from each channel is recorded as a high-level signal, and the minimum voltage extreme value collected is recorded as a low-level signal. This step provides basic data support for subsequent calculation of the level reference value.

[0058] S340 calculates the arithmetic mean of the high-level signal and the low-level signal for each byte channel, and uses the calculation result as the level reference value.

[0059] Specifically, the calculation method is Voh = (high - low voltage) / 2, where high represents the high-level signal determined in step S330, and low voltage represents the low-level signal. This calculation method is used to calculate a suitable level reference value for each byte channel. Since the high and low level signals of different byte channels may vary due to factors such as manufacturing process deviations and wiring differences within the chip, independent calculations are necessary to ensure that each byte channel has a level reference value suitable for its own characteristics. This provides a strong guarantee for subsequent accurate timing tests and other operations.

[0060] Understandable Figure 3 The illustrated process revolves around acquiring voltage level signals from the chip and determining the voltage level reference value, which is a crucial step in the preparatory work for chip testing. By sending write-read commands to induce data output from the chip, and using the PMU to acquire the voltage extreme values ​​during the stable phase to determine the high and low voltage levels, the average value is calculated to obtain the voltage level reference value for each byte channel. This series of operations lays the foundation for subsequent precise timing tests on each byte channel of the chip, helping to more accurately evaluate chip performance and effectively addressing the impact of factors such as duty cycle imbalance and byte output differences on test results.

[0061] In some embodiments, please refer to Figure 4 , Figure 4This is a flowchart illustrating the selection and sampling point setting in chip testing according to an embodiment of the present invention. After configuring the read latency, the testing process for the chip under test is as follows:

[0062] S410, set test data mode.

[0063] Specifically, a pre-defined test data pattern is written to the chip under test. This test data pattern contains feature sequences that can identify byte boundaries, such as specific binary sequences. Writing this test data pattern is to accurately determine the starting position of the first byte of each byte channel in subsequent operations. These feature sequences that can identify byte boundaries act like special markers in the data, facilitating location during subsequent data reading.

[0064] S420, write-read operation and start position determination.

[0065] In this step, a read command is sent, prompting the chip under test to output response data containing the aforementioned characteristic sequence. The starting position of the first byte of each byte channel is determined by detecting the position of the characteristic signal appearing in the response data. During data transmission, the data strobe signal DQS (including DQS_c and DQS_t) can be generated internally by the chip and output synchronously with the data signal (DQ). The test system uses a high-precision sampling circuit to acquire the DQ signal at preset fixed time points to analyze its timing relationship with the DQS signal.

[0066] This method can accurately locate the starting position of each byte channel data output, which plays an important role in the subsequent correct interpretation and processing of the chip output data.

[0067] S430, repeated write-read operations and testing.

[0068] After determining the starting position, based on the read latency (RL) configuration determined in step S420, the write-read operation is re-executed. This means writing the same test data pattern (feature sequence from S410) to the chip under test again, and then performing a read operation at a preset fixed sampling point. This step aims to test whether the chip under test can correctly complete the write-read operation under the current read latency setting, thereby verifying whether the chip functions normally under the current read latency configuration and ensuring that the chip can accurately write and read data as expected.

[0069] It should be noted that if the write-read operation in step S430 fails, it is necessary to return to step S420 to remeasure the timing parameters and calculate the new RL configuration value.

[0070] S440, output result.

[0071] If the test passes, the results can be printed out, including information such as whether the test was successful and relevant parameters, which can provide an important basis for subsequent evaluation of chip performance.

[0072] In some embodiments, after the write-read data operation is completed, dynamic timing calibration needs to be further performed, specifically including:

[0073] With a preset time step, the data signal waveforms of the corresponding byte channels are collected near the effective clock edges of the data strobe signals at the command end and the target end, respectively, based on fixed sampling points.

[0074] Based on the acquired data signal waveform of the corresponding byte channel, measure the data setup time and data hold time of that byte channel.

[0075] Specifically, with a preset time step (e.g., ±5ps), the data signal (DQ) waveforms of the corresponding byte channel are acquired using a high-precision sampling device near the effective clock edges of the command-side data strobe signal (DQS_c) and the target-side data strobe signal (DQS_t), based on fixed sampling points, covering the complete time domain of the signal's effective window. Based on waveform analysis, the data setup time (tDS) and data hold time (tDH) are quantized and measured. Through these measurements, the boundary of the effective data window (the interval between tDS and tDH) is determined. Finally, the read delay (RL) is configured to the delay value corresponding to the center of the window to maximize timing margin and avoid sampling errors caused by clock jitter, signal offset, and other factors.

[0076] In some embodiments, please refer to Figure 5 , Figure 5 This diagram illustrates the timing parameters of the chip's communication circuitry (AC) according to an embodiment of the present invention. The diagram shows the command-side clock signal (CK_c) and the target-side clock signal (CK_t). The command-side clock signal (CK_c) provides a time reference for command-side operations, coordinating the timing of the command-side data strobe signal (DQS_c). For example, when the chip transmits data, the times when the command is issued and received are closely related to the command-side clock signal (CK_c). The target-side clock signal (CK_t), as the target-side clock signal, provides a time reference for the target-side data processing operations. It works in conjunction with CK_c to ensure precise coordination between the operations of the command-side and the target-side during chip data transmission. For example, when data is transmitted from the command-side to the target-side, the operations at both ends need to be performed in an orderly manner under the coordination of their respective clock signals.

[0077] tDQSCK represents both the first phase difference between the command-side data strobe signal (DQS_c) and the clock signal (CK_c), and the second phase difference between the target-side data strobe signal (DQS_t) and the clock signal (CK_t). These two phase differences reflect the time offset of the data strobe signal relative to the clock signal, and this offset plays a crucial role in determining the data sampling time. Specifically, the command-side data strobe signal (DQS_c) determines the sampling time of the data signal (DQ) at the command end. Its phase relationship with CK_c and its own effective edge (rising or falling edge) together determine the specific time of data acquisition at the command end. For example, the data signal (DQ) should be in a stable state near the effective edge of the command-side data strobe signal (DQS_c) to ensure accurate sampling. The target-side data strobe signal (DQS_t) plays a similar role at the target end as the command-side data strobe signal (DQS_c), used to determine the sampling time of the data signal (DQ) at the target end. Its relationship with CK_t and its own characteristics are crucial for the target end to correctly receive and process data. The data signal (DQ) carries the actual data information transmitted by the chip. In different byte channels (such as Byte0-Byte31), the DQ signal is transmitted and sampled under the control of the DQS_c and DQS_t signals. Changes in its signal state, such as high level or low level, represent different data values.

[0078] tDQSCK(MAX), tDQSCK center, and tDQSCK(MIN) represent the maximum, center, and minimum phase difference values, respectively. Determining these values ​​defines a range that delineates the boundaries of a single-channel sampling window (e.g., a rising strobe region window). For example, tDQSCK(MAX) and tDQSCK(MIN) determine the maximum and minimum boundaries of the sampling window in the phase difference dimension, while tDQSCK center serves as a reference center position. Furthermore, the timing parameters of the byte channel can be determined based on the first and second phase differences.

[0079] For example, for each byte channel, based on the measured data setup time (tDS) and data hold time (tDH), the basic timing margin parameters for that channel are calculated as follows:

[0080] Minimum setup time margin: tDS_margin = tDS - tDS_spec;

[0081] Minimum hold time margin: tDH_margin = tDH - tDH_spec;

[0082] Among them, tDS_spec and tDH_spec are the minimum allowed values ​​specified by the protocol.

[0083] The timing test for each byte channel also includes a sampling window definition step:

[0084] a) Phase difference measurement:

[0085] The first phase difference Δt1 between the data strobe signal (DQS_c) at the command terminal and the clock signal (CK_c) at the command terminal is measured.

[0086] The second phase difference Δt2 between the target end data strobe signal (DQS_t) and the target end clock signal (CK_t) is measured.

[0087] b) Window boundary calculation:

[0088] Based on Δt1, Δt2, and the tDS_margin and tDH_margin calculated above, the effective sampling window for this byte channel is determined, which includes the window start boundary and the window end boundary.

[0089] Window start boundary: tW_start = max(Δt1,Δt2) + tDS_margin;

[0090] Window end boundary: tW_end=min(Δt1+tCK / 2,Δt2+tCK / 2)-tDH_margin; where tCK is the clock cycle.

[0091] Define the above tW_start and tW_end as the timing relationship parameters of this byte channel.

[0092] Figure 5 The diagram illustrates the relationship between the command-side data strobe signal (DQS_c), the target-side data strobe signal (DQS_t), and the data signal (DQ). Here, tDSH / DQS_c represents the setup / hold time of the data strobe signal at the command end, and tDSH / DQS_t represents the setup / hold time of the data strobe signal at the target end. These are related to the effective edge characteristics of the data strobe signal and affect the timing of data sampling and the effective time range of the data. They are important parameters for constructing the sampling window and determining data validity. tQH is a parameter related to the data hold time (relative to the data strobe signal). It determines the length of time the data signal needs to remain stable after sampling, which is crucial for determining the validity of data within a single-channel sampling window. tDQSQ represents the time relationship between the data strobe signal and the data. It defines the effective time interval of the data strobe signal, which is related to the single-channel sampling window because valid data can only be sampled within the data strobe window.

[0093] Based on the data setup time and data hold time of each byte channel, a globally effective sampling window can be calculated and calibrated according to timing parameters. The globally effective sampling window is the smallest common time interval that covers the timing requirements of all byte channels. Its existence ensures that, in the case of multiple byte channels, the data acquisition and processing requirements of all channels can be met, guaranteeing the accuracy and stability of the chip's overall data transmission.

[0094] In summary, the relevant signals, such as CK_c, CK_t, DQS_c, DQS_t, DQ, and CA[5:0], and the relevant parameters, such as tDQSCK, tDQSCK(MAX), tDQSCK center, tDQSCK(MIN), tDSH / DQS_c, tDSH / DQS_t, tQH, tDQSQ, and RL, are interconnected and interact with each other to jointly construct a complete chip AC timing model. This model is used to describe the timing relationships and operating specifications of the chip during data transmission, ensuring that the chip can accurately and stably perform data reading and writing operations.

[0095] In some embodiments, the method further includes:

[0096] Based on the data setup time and data hold time of each byte channel, a globally effective sampling window is calculated and calibrated according to timing parameters. The globally effective sampling window is the smallest common time interval covering the timing requirements of all byte channels of the chip.

[0097] Specifically, the chip contains multiple byte channels, such as Byte0-Byte31, each with its own independent data setup and hold times. When calculating the global effective sampling window, the data setup and hold times of all byte channels must be considered comprehensively. For example, if there are three byte channels with data setup and hold times corresponding to time intervals of [1-5], [3-7], and [2-6] respectively, then through analysis and calculation, a minimum common time interval that satisfies the timing requirements of these three channels must be found. This interval is the global effective sampling window.

[0098] The determination of timing parameters depends on the measurement of the first phase difference between the command-side data strobe signal and the clock signal, and the second phase difference between the target-side data strobe signal and the clock signal. These timing parameters define the boundaries of the single-channel sampling window, thereby constraining the range of effective data acquisition during dynamic sampling.

[0099] Calibrate the global effective sampling window based on timing parameters. This involves adjusting and optimizing the global effective sampling window using these parameters. This is because timing parameters accurately reflect the time relationship between the data strobe signal and the clock signal, and the accuracy of the global effective sampling window depends precisely on these accurate time relationships. For example, if the timing parameters of a channel show a phase difference between its data strobe signal and clock signal, the global effective sampling window needs to be adjusted accordingly to ensure that data from all byte channels is correctly sampled within the accurate time interval.

[0100] In summary, by calculating the globally effective sampling window based on the data establishment and hold times of each byte channel, and calibrating it according to timing relationship parameters, the timing differences between different byte channels of the chip can be effectively coordinated, ensuring that data is sampled within an accurate and uniform time interval. This not only provides key indicators for chip testing and performance evaluation, but also helps improve the accuracy of chip data sampling, as well as overall performance and reliability.

[0101] Please refer to Figure 6 , Figure 6 The figure shows waveforms acquired by an oscilloscope according to an embodiment of the present invention. Two waveform curves are shown: the DQS_t waveform represents the target data strobe signal (DQS_t), and the DQ_c waveform represents the command data signal (DQ_c). These two waveforms exhibit periodic changes, indicating that they are electrical signals that change regularly over time. Both the DQS_t and DQ_c waveforms have obvious sinusoidal characteristics. Within each cycle, the waveform rises from a trough to a peak, and then falls from a peak to a trough, completing a full cycle. Multiple complete cycles can be observed in the figure. The time interval between adjacent cycles is relatively stable, but there are slight differences in the time interval of some cycles, indicating a duty cycle unbalance.

[0102] Duty cycle imbalance means that the ratio of high to low signal durations is not the ideal 50%. This imbalance can affect signal transmission quality and subsequent circuitry's sampling and processing of the signal. Therefore, in such cases, it is necessary to first configure a level reference value (voh) and then perform testing. By setting an appropriate output reference voltage, signal quality can be optimized, the effects of duty cycle imbalance can be mitigated, and the system can be ensured to operate stably and accurately.

[0103] Because a chip has multiple byte channels (such as Byte0-Byte31), the signals transmitted by different byte channels may differ due to hardware variations, wiring lengths, and other factors. For example, the signal amplitude, phase, rise time, or fall time of different byte channels may not be exactly the same. This byte-level difference can affect the accurate transmission and processing of data, so byte-by-byte testing is necessary.

[0104] Figure 6 The waveforms acquired by the oscilloscope show two waveforms: the target data strobe signal (DQS_t) and the command data signal (DQ_c). There are signs of duty cycle imbalance and byte-level differences. It is necessary to configure the level reference value to achieve duty cycle calibration and to perform byte-level timing analysis by testing byte by byte.

[0105] The chip testing system provided by the present invention is described below. The chip testing system described below can be referred to in correspondence with the chip testing method described above.

[0106] Please refer to Figure 7 , Figure 7 This is a schematic diagram of the structure of a chip testing system provided in an embodiment of the present invention. A chip testing system 700 includes a data acquisition module 710, a control module 720, and a testing module 730.

[0107] For example, the acquisition module 710 is used to acquire the level signals output by each byte channel of the chip under test.

[0108] For example, the control module 720 performs a reference voltage calibration on each byte channel based on the said level signal to determine the level reference value for each byte channel.

[0109] For example, the test module 730 is used to perform byte-by-byte timing tests independently on each byte channel based on the level reference value, including: configuring multiple levels of read delay for each byte channel in sequence under a preset clock cycle; and for each read delay, measuring the data setup time and data hold time under the current configuration based on the selection sampling points of the command end data strobe signal and the target end data strobe signal of the byte channel.

[0110] For example, the acquisition module 710 is also used for:

[0111] Send a write-read instruction sequence to the chip under test;

[0112] During the stable data output phase, the extreme voltage values ​​of the data pins of each byte channel are collected synchronously.

[0113] The maximum voltage extreme value collected from each channel is recorded as a high-level signal, and the minimum voltage extreme value collected is recorded as a low-level signal.

[0114] For example, the control module 720 is also used for:

[0115] For each byte channel, the arithmetic mean of the high-level signal and the low-level signal is calculated, and the calculation result is used as the level reference value.

[0116] For example, the test module 730 is also used for:

[0117] Under a preset clock cycle, the corresponding delay configuration values ​​are written to the chip under test in the order from the first level read delay to the Nth level read delay (N represents the total number of byte channels of the chip under test), so that the chip under test can output data according to the delay time interval corresponding to each byte channel after receiving the read command.

[0118] Write a preset test data pattern (the test data pattern contains a feature sequence that can identify byte boundaries) to the chip under test, send a read command to make the chip under test output response data containing the feature sequence, and determine the starting position of the first byte of each byte channel by detecting the occurrence position of the feature signal in the response data. After determining the starting position of the first byte of each byte channel, re-execute the write-read operation to test whether the chip under test can correctly complete the write-read operation of data under the current read latency setting.

[0119] With a preset time step, the data signal waveforms of the corresponding byte channel are acquired near the effective clock edges of the command-side data strobe signal and the target-side data strobe signal, respectively, based on fixed sampling points. According to the acquired data signal waveforms of the corresponding byte channel, the data setup time (the shortest time required for the data signal to reach the corresponding byte channel level reference value before the effective edge of the command-side data strobe signal arrives) and the data hold time (the shortest time for the data signal to maintain the corresponding byte channel level reference value after the effective edge of the target-side data strobe signal arrives) of the byte channel are measured. Based on the measured data setup time and data hold time of each byte channel, the AC timing parameters of the byte channel are calculated independently.

[0120] The first phase difference between the data strobe signal and the clock signal at the command end is measured, and the second phase difference between the data strobe signal and the clock signal at the target end is measured. Based on the first phase difference and the second phase difference, the timing relationship parameters of the byte channel are determined (used to define the single-channel sampling window boundary of the byte channel to constrain the effective data capture range during dynamic sampling).

[0121] Based on the data setup time and data hold time of each byte channel, calculate the global effective sampling window (the minimum common time interval covering the timing requirements of all byte channels), and calibrate the global effective sampling window according to the timing relationship parameters.

[0122] It should be noted that the chip testing system provided in this embodiment of the invention can implement all the method steps implemented in the above method embodiment and can achieve the same technical effect. Therefore, the parts that are the same as those in the method embodiment and the beneficial effects will not be described in detail here.

[0123] Figure 8 This is a schematic diagram of the structure of the electronic device provided in the embodiment of the present invention, such as... Figure 8 As shown, the electronic device may include a processor 810, a communications interface 820, a memory 830, and a communication bus 840, wherein the processor 810, the communications interface 820, and the memory 830 communicate with each other through the communication bus 840. The processor 810 can call logical instructions in the memory 830 to execute the chip testing method.

[0124] Furthermore, the logical instructions in the aforementioned memory 830 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to ensure that a computer device (which may be a personal computer, server, or network device, etc.) executes all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0125] On the other hand, the present invention also provides a computer program product, the computer program product including a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions, and when the program instructions are executed by a computer, the computer is able to execute the chip testing method provided by the above methods.

[0126] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the chip testing methods provided above.

[0127] The present invention provides an electronic device, a computer program product, and a processor-readable storage medium, wherein the computer program stored thereon enables the processor to implement all the method steps implemented in the above method embodiments and achieve the same technical effect. Here, the parts that are the same as those in the method embodiments and the beneficial effects will not be described in detail.

[0128] The device embodiments described above are merely illustrative examples; the units may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any inventive effort.

[0129] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to ensure that a computer device (which may be a personal computer, server, or network device, etc.) executes the methods described in the various embodiments or some parts of the embodiments.

[0130] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip testing method, characterized in that, The method includes: Acquire the level signals output by each byte channel of the chip under test; Based on the level signal, a reference voltage calibration is performed on each byte channel to determine the level reference value for each byte channel; Based on the aforementioned level reference value, byte-by-byte timing tests are performed independently on each byte channel, including: Under a preset clock cycle, configuring multiple levels of read delay for each byte channel sequentially includes: writing the corresponding delay configuration values ​​to the chip under test sequentially in order from the first level of read delay to the Nth level of read delay, so that the chip under test outputs data according to the delay time interval corresponding to each byte channel after receiving the read command, where N represents the total number of byte channels of the chip under test; For each read latency, the data setup time and data hold time under the current configuration are measured based on the gating sampling points of the command-side data strobe signal and the target-side data strobe signal of that byte channel.

2. The chip testing method according to claim 1, characterized in that, The data setup time refers to the shortest time required for the data signal to reach the corresponding byte channel level reference value before the valid edge of the data strobe signal arrives at the command end; the data hold time refers to the shortest time for the data signal to maintain the corresponding byte channel level reference value after the valid edge of the data strobe signal arrives at the target end. The method further includes: Based on the measured data setup time and data hold time of each byte channel, the AC timing parameters of that byte channel are calculated independently.

3. The chip testing method according to claim 1, characterized in that, The level signal includes a high level signal and a low level signal, and the acquisition of the level signal output by each byte channel of the chip under test includes: Send a write-read instruction sequence to the chip under test; During the stable data output phase, the extreme voltage values ​​of the data pins of each byte channel are collected synchronously. The maximum voltage extreme value collected from each channel is recorded as a high-level signal, and the minimum voltage extreme value collected is recorded as a low-level signal.

4. The chip testing method according to claim 3, characterized in that, The step of performing reference voltage calibration on each byte channel based on the level signal to determine the level reference value for each byte channel includes: For each byte channel, the arithmetic mean of the high-level signal and the low-level signal is calculated, and the calculation result is used as the level reference value.

5. The chip testing method according to claim 1, characterized in that, After configuring multi-level read delays sequentially for each byte channel, the method further includes: A preset test data pattern is written to the chip under test, the test data pattern containing a feature sequence that can identify byte boundaries; Sending a read command causes the chip under test to output response data containing the feature sequence. By detecting the occurrence position of the feature signal in the response data, the starting position of the first byte of each byte channel is determined. After determining the starting position of the first byte of each byte channel, the write-read operation is re-executed to test whether the chip under test can correctly complete the data write-read operation under the current read latency setting.

6. The chip testing method according to claim 5, characterized in that, After performing the write-read data operation, the method further includes: With a preset time step, the data signal waveforms of the corresponding byte channels are collected near the effective clock edges of the data strobe signals at the command end and the target end, respectively, based on fixed sampling points. Based on the acquired data signal waveform of the corresponding byte channel, measure the data setup time and data hold time of that byte channel.

7. The chip testing method according to claim 1, characterized in that, For each byte channel, the method further includes: The first phase difference between the data strobe signal and the clock signal at the measurement command terminal; The second phase difference between the target data gating signal and the clock signal is measured. The timing parameters of the byte channel are determined based on the first phase difference and the second phase difference.

8. The chip testing method according to claim 7, characterized in that, The method further includes: Calculate the global effective sampling window based on the data setup time and data hold time of each byte channel; The global effective sampling window is calibrated based on the time-series relationship parameters; The global effective sampling window is the smallest common time interval that covers the timing requirements of all byte channels.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the chip testing method as described in any one of claims 1 to 8.

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