Multi-channel DC source asynchronous write-in and synchronous refresh system and method

Abstract

The invention discloses a multichannel DC source asynchronous write-in and synchronous refresh system and method, and relates to the technical field of quantum computers, the multichannel DC source asynchronous write-in and synchronous refresh system comprises an FPGA mother board used for outputting output parameters of each channel of a DC source, and at least two DAC daughter boards used for executing the output parameters; the FPGA mother board is used for writing an output parameter into each DAC daughter board and controlling the receiving time of the DAC output channel of each DAC daughter board for receiving the output parameter to be before the starting time of the next refresh cycle; the FPGA mother board is also used for sending a refreshing instruction to each DAC daughter board in parallel at the starting time; after each DAC daughter board receives the refreshing instruction, the DAC output channel of the DAC daughter board is controlled to execute the received output parameters; all working time sequences of all DAC output channels have a minimum common divisor, the minimum common divisor is equal to X times of a refresh cycle, and X is a positive integer greater than or equal to 1, so that the synchronism of multi-channel output is ensured.

Description

Technical Field

[0001] The present invention relates to the field of quantum computer technology, and in particular to a multi-channel direct current source asynchronous writing and synchronous refreshing system and method. Background Art

[0002] In a trapped ion quantum computer, each ion must independently control its quantum state, using a dedicated electrode combination to create a localized electric field to achieve high-fidelity single-qubit gates. To achieve ion movement and separation / combination, adjacent electrode groups must coordinately apply a gradual voltage gradient to ensure submicron positioning accuracy during ion migration.

[0003] Furthermore, to overcome the limitations of traditional linear ion chains, a honeycomb electrode array was constructed in the XY plane to support two-dimensional ion confinement. Each ion requires six adjacent electrodes to form a three-dimensional confinement field. To suppress micromotion caused by the radio frequency electric field, a compensation electrode array is deployed at the bottom of the chip. Phase synchronization technology is used to control ion displacement within λ / 20 (λ is the laser wavelength).

[0004] Furthermore, the generation of a microwave standing wave field by a distributed electrode array enables consistent coupling strength between different ions, supporting high-fidelity two-qubit gate operations. Redundant electrodes are configured to compensate for ambient magnetic field drift in real time, helping to reduce frequency drift in ion hyperfine level transitions.

[0005] Based on the above reasons, the dense electrode architecture enables the ion trap system to simultaneously meet multiple requirements such as high-precision quantum manipulation, large-scale quantum bit expansion, and dynamic reconstruction, supporting its quantum computing breakthroughs under large-scale ion matrices. For example, the current advanced 512-bit ion chip requires the integration of more than 1,500 electrodes.

[0006] The multi-channel DC source used to control the DC electrodes of the ion trap quantum computing chip has different output voltages and different output timings for different channels. For the hundreds or thousands of DC source channels mentioned above, it is obviously impossible to write the output parameters in parallel at the same time. In this case, how to ensure the synchronization of multi-channel outputs is an urgent problem to be solved. Summary of the Invention

[0007] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, one object of the present invention is to provide a multi-channel DC source asynchronous writing and synchronous refreshing system and method to ensure the synchronization of multi-channel output.

[0008] According to a first aspect of an embodiment of the present invention, a multi-channel DC source asynchronous write and synchronous refresh system is provided, the system comprising an FPGA motherboard for outputting output parameters of each channel of the DC source, and at least two DAC daughterboards for executing the output parameters; each DAC daughterboard is provided with a plurality of DAC output channels; The FPGA motherboard is used to write output parameters to each DAC daughter board and control the DAC output channel of each DAC daughter board to receive the output parameters before the start time of the next refresh cycle; The FPGA motherboard is further configured to send a refresh instruction to each DAC daughter board in parallel at the start time; After receiving the refresh instruction, each DAC sub-board controls the DAC output channel of the DAC sub-board to execute the received output parameter; All operating timings of all DAC output channels have a lowest common denominator, where the lowest common denominator is equal to X times the refresh period, where X is a positive integer greater than or equal to 1.

[0009] Optionally, the refresh cycle satisfies the following setting condition: the FPGA motherboard writes output parameters to each DAC daughter board in parallel.

[0010] Optionally, the refresh cycle meets the following setting conditions:

[0011] The maximum number of DAC output channels on each DAC daughter board is N, the time for the FPGA mother board to write output parameters to each DAC output channel is t, and the refresh period is T.

[0012] Optionally, writing output parameters to each DAC sub-board in parallel includes: For each DAC daughter board, determining whether a historical output parameter received by each DAC output channel of the DAC daughter board is different from the output parameter; If there is a first DAC output channel whose output parameter is different from the historical output parameter, the output parameter is written to the first DAC output channel.

[0013] Optionally, the refresh cycle meets the following setting conditions:

[0014] The maximum number of the first DAC output channels in each DAC daughter board is m, the time for the FPGA mother board to write output parameters to each DAC output channel is t, and the refresh period is T.

[0015] Optionally, the DC electrodes of the DC source are grouped according to the voltage regulation frequency, and the DC electrodes included in each group are evenly distributed to the DAC output channels of each DAC sub-board.

[0016] Optionally, each DC electrode of the DC source is distributed to a DAC output channel of each DAC sub-board, including: Determine the moment when the DC electrode voltage adjustment is the largest according to the working sequence of each DC electrode; Evenly distribute the DC electrodes that need voltage adjustment at the moment to each DAC sub-board, and obtain the number M of the first DAC output channels of each DAC sub-board at the moment; m is determined according to the working sequence of each DC electrode; Adjust the distribution of each DC electrode in each DAC sub-board so that mM is less than the set threshold.

[0017] Optionally, each DAC sub-board is also provided with a voltage reference chip.

[0018] Optionally, there are wirings of equal length between the FPGA motherboard and the DAC modules of each DAC daughter board, and there are wirings of equal length between each DAC output channel of each DAC daughter board and the DC electrode of the DC source corresponding to the DAC output channel; wherein, the DAC output channel of each DAC daughter board is arranged in the DAC module of the DAC daughter board.

[0019] Optionally, the refresh period is set to be less than or equal to 100 us.

[0020] Optionally, the system includes a system clock chip, and the refresh period is generated based on a local clock signal provided by the system clock chip; The FPGA motherboard controls the local clock signal and the external clock signal to be coherent.

[0021] According to a second aspect of an embodiment of the present invention, a multi-channel DC source asynchronous writing and synchronous refreshing method is provided, which is applied to an FPGA motherboard of a multi-channel DC source asynchronous writing and synchronous refreshing system. The method comprises: Writing output parameters to each DAC sub-board, and controlling the DAC output channel of each DAC sub-board to receive the output parameters before the start time of the next refresh cycle; Sending a refresh instruction to each DAC sub-board in parallel at the start time, so that after each DAC sub-board receives the refresh instruction, it controls the DAC output channel of the DAC sub-board to execute the received output parameter; All operating timings of all DAC output channels have a lowest common denominator, where the lowest common denominator is equal to X times the refresh period, where X is a positive integer greater than or equal to 1.

[0022] According to a third aspect of an embodiment of the present invention, an ion trap quantum computing DC electrode system is provided, comprising any of the multi-channel DC source asynchronous writing and synchronous refreshing systems described above.

[0023] According to a fourth aspect of an embodiment of the present invention, an ion trap quantum computing system is provided, comprising any one of the multi-channel DC source asynchronous writing and synchronous refreshing systems described above.

[0024] As can be seen from the above, in the solution provided by the embodiment of the present invention, the output parameters can be written to each DAC sub-board in parallel through the FPGA motherboard, so that the time when each DAC sub-board obtains the output parameters is close, and refresh instructions are sent at a certain period to refresh the output parameters of the DAC output channel of each DAC sub-board. Before the refresh start time of each cycle arrives, the output parameters to be refreshed are first written, so that a unified refresh can be performed according to the refresh instruction at the beginning of the next cycle, thereby ensuring the synchronization of multi-channel outputs, reducing the output timing error of each channel of the DC source and even the occurrence of timing misalignment. This solution is suitable for the timing-sensitive application scenario of ion trap quantum computing and can meet the timing requirements of high-precision systems.

[0025] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a structural diagram of a multi-channel DC source asynchronous writing and synchronous refreshing system provided by an embodiment of the present invention; Figure 2 1 is a schematic structural diagram of a multi-channel DAC provided by an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of an FPGA development board provided by an embodiment of the present invention; Figure 4 The present invention provides a flow chart of a multi-channel DC source asynchronous writing and synchronous refreshing method. DETAILED DESCRIPTION

[0027] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0028] In one embodiment of the present invention, see Figure 1, provides a multi-channel DC source asynchronous write and synchronous refresh system, including an FPGA (Field Programmable Gate Array) motherboard for outputting output parameters of each DC source channel, and at least two DAC (Digital-to-Analog Converter) daughterboards for executing the output parameters; each DAC daughterboard is equipped with multiple DAC output channels; The FPGA motherboard is used to write output parameters to each DAC daughter board and control the DAC output channel of each DAC daughter board to receive the output parameters before the start time of the next refresh cycle; The FPGA motherboard is also used to send refresh instructions to each DAC daughter board in parallel at the start time; After receiving the refresh instruction, each DAC sub-board controls the DAC output channel of the DAC sub-board to execute the received output parameter; All operating timings of all DAC output channels have a lowest common denominator, which is equal to X times the refresh period, where X is a positive integer greater than or equal to 1.

[0029] In the above system, the FPGA motherboard refers to a circuit board developed based on FPGA, and the DAC daughterboard refers to a circuit board connected to the motherboard and including a DAC module. Figure 1 As an example, only two DAC daughter boards are connected to the motherboard. When there are more than two DAC daughter boards, each DAC daughter board is connected according to Figure 1 The method shown is to connect to the FPGA motherboard and the multi-channel DC source.

[0030] The above-mentioned output parameters include output voltage, which is sent in the form of voltage encoding. Specifically, each DAC output channel receives an output parameter. Through the conversion function of the DAC module arranged on the DAC daughter board, the output parameter is converted from a digital signal to an analog signal, which can control the voltage value of a DC electrode.

[0031] In one embodiment, the DAC daughterboard can be a multi-channel DAC of models such as AD5370, AD5371, and AD5770R. After using a high-speed serial interface such as SPI (Serial Peripheral Interface) to transmit output parameters, a Load signal is used as a refresh instruction to uniformly trigger the output parameters to take effect, which can reduce timing errors. This is suitable for ion trap quantum computing, an application scenario that is sensitive to timing, and can meet the timing requirements of high-precision systems.

[0032] A DAC output channel can control one or more DC electrodes according to the voltage specified by the output parameters.

[0033] After receiving the refresh instruction, all DAC output channels may be refreshed, or only some DAC output channels may be refreshed as shown in subsequent embodiments.

[0034] The operating sequence refers to the single output duration or single output interval duration of any DAC output channel. For example, the operating sequence of the first channel is (a1, a2, a3, ... aa), where odd-numbered elements such as a1 and a3 are output durations, and even-numbered elements such as a2 and a4 are output interval durations—that is, in a non-output state. Conversely, if a1, a3, etc. are output interval durations, then a2, a4, etc. are output durations. The operating sequence of the second channel is (b1, b2, b3, ... bb), where b1, b3, etc. are output durations, then b2, b4, etc. are output interval durations. Conversely, if b1, b3, etc. are output interval durations, then b2, b4, etc. are output durations. The operating sequence of the third channel is (c1, c2, c3, ... cc), where c1, c3, etc. are output durations, then c2, c4, etc. are output interval durations. Conversely, if c1, c3, etc. are output interval durations, then c2, c4, etc. are output durations. The lowest common denominator of all working timings of all DAC output channels is the lowest common denominator of a1, a2, a3, ... aa, b1, b2, b3, ... bb, c1, c2, c3, ... cc; only in this way can it be guaranteed that each refresh is aligned with the output rising edge or falling edge of each DAC output channel.

[0035] As can be seen from the above, in the solution provided by the embodiment of the present invention, the output parameters can be written to each DAC sub-board in parallel through the FPGA motherboard, so that the time when each DAC sub-board obtains the output parameters is close. In addition, refresh instructions are sent at a certain period to refresh the output parameters of the DAC output channels of each DAC sub-board. Before the refresh start time of each cycle arrives, the output parameters to be refreshed are first written, so that a unified refresh can be performed according to the refresh instruction at the beginning of the next cycle. This ensures the synchronization of multi-channel outputs, reduces the output timing errors of each channel of the DC source, and even reduces the occurrence of timing misalignment. This is suitable for the timing-sensitive application scenario of ion trap quantum computing and can meet the timing requirements of high-precision systems.

[0036] The structure of the DAC daughter board is as follows Figure 2 The multi-channel DAC refers to a DAC daughterboard. The FPGA motherboard and DAC daughterboard can be connected through the motherboard connector. The motherboard connector integrates various communication interfaces, such as digital power supply, analog power supply interface, and SPI (Serial Peripheral Interface).

[0037] In one embodiment of the present invention, each DAC daughter board is further provided with a voltage reference chip. Figure 2In the DAC, the voltage reference chip can provide a reference voltage signal to the multi-channel DAC, and the output form is an analog signal.

[0038] Through the D-Sub connector, ~ 39 represents 40 DAC output channels, which correspondingly control the 40 output voltages of the multi-channel DC source. Before refreshing the output parameters, the voltage reference chip outputs a voltage reference signal to control the output voltage of the DAC output channel.

[0039] In one embodiment of the present invention, the refresh cycle satisfies the following setting conditions: the FPGA motherboard writes output parameters to each DAC daughter board in parallel.

[0040] In one embodiment of the present invention, the refresh period is set to be less than or equal to 100 μs.

[0041] Specifically, the refresh cycle can be set to 1-20µs. The FPGA motherboard can send output parameters to the multi-channel DACs on each daughterboard simultaneously, but within the multi-channel DAC, control parameters cannot be written to multiple channels in parallel within the same DAC. A control refresh cycle of at least 1µs allows ample time for the DAC daughterboards to write the output parameters to each DAC channel to be refreshed after receiving them. Avoiding excessively long refresh cycles can better accommodate high-resolution operations in output voltage control timing.

[0042] In one embodiment, the above period is set to be smaller than the shortest variation interval of the output parameters of the DAC output channels of all DAC sub-boards.

[0043] For example, the influencing factor of the shortest change interval is: the shortest operation cycle or the preset working period.

[0044] For output channels with output voltage operations with high time resolution, the control period is less than the shortest operation period, where the operation period refers to the execution period of the output voltage operation, and each output voltage operation adjusts the voltage value of the output current of the output channel once.

[0045] In one embodiment of the present invention, the refresh period satisfies the following setting conditions:

[0046] The maximum number of DAC output channels on each DAC daughter board is N, the time for the FPGA motherboard to write output parameters to each DAC output channel is t, and the refresh period is T.

[0047] Specifically, each DAC daughter board may be provided with N DAC output channels to achieve even distribution.

[0048] In one embodiment of the present invention, the output parameters may be written to the DAC daughter board in the following manner: for each DAC daughter board, determining whether the historical output parameters received by each DAC output channel of the DAC daughter board are different from the output parameters; If there is a first DAC output channel whose output parameter is different from the historical output parameter, the output parameter is written to the first DAC output channel.

[0049] Historical output parameters refer to the output parameters used during the last refresh relative to the current output parameters. This allows you to select only the DAC channels whose output parameters have changed and write the output parameters to them during the refresh. For DAC channels whose output parameters haven't changed, no operation is performed, retaining the original output parameters. This simplifies the parameter refresh process.

[0050] When refreshing only the DAC channels whose output parameters have changed, the refresh cycle meets the following setting conditions:

[0051] The maximum number of first DAC output channels in each DAC daughter board is m, the time for the FPGA mother board to write output parameters to each DAC output channel is t, and the refresh period is T.

[0052] Specifically, all DAC output channels are equipped with registers. After completing one output parameter refresh and before the next output parameter refresh, the motherboard writes the output parameters to be executed in the next cycle to the output channel registers of the multi-channel DACs on each daughter board via SPI. The writing method can be serial or parallel.

[0053] There are equal-length wirings between the FPGA motherboard and the DAC modules of each DAC daughterboard, and there are equal-length wirings between each DAC output channel of each DAC daughterboard and the DC electrode of the DC source corresponding to the DAC output channel; wherein, the DAC output channel of each DAC daughterboard is arranged in the DAC module of the DAC daughterboard.

[0054] In this way, by controlling the wiring length, the transmission time of the output parameters in the line transmission is made as consistent as possible, thereby further improving the synchronization.

[0055] The DC electrode of the DC source corresponding to the DAC output channel refers to the output parameter of the DAC output channel, that is, the voltage value of the output voltage of the DC electrode controlled by the voltage coding.

[0056] In one embodiment, this correspondence is set in the following manner: the DC electrodes of the DC source are grouped according to the voltage regulation frequency, and the DC electrodes included in each group are evenly distributed to the DAC output channels of each DAC sub-board.

[0057] Specifically, the operating sequence of each DC electrode of each ion trap can be obtained, and the DC electrodes can be divided into at least two groups according to the voltage regulation frequency based on the operating characteristics of each DC electrode.

[0058] For example, some DC electrodes are refreshed every 100us, while others are refreshed every 10us. These electrodes are then divided into two groups and refreshed uniformly. After grouping, the corresponding DAC output channels are evenly distributed among the groups. For example, if a group of DC electrodes requires 40 DAC output channels to execute the output parameters, and each daughterboard has 8 DAC output channels, the DC electrodes are evenly distributed among the five DAC daughterboards, allowing each DAC output channel to control one DC electrode, rather than having one DAC daughterboard control 40 outputs.

[0059] The above optimization can reduce the total time for writing control parameters to the DAC output channels of each DAC sub-board, and can make the total time for writing the output parameters of each DAC sub-board relatively average, thereby further reducing the refresh cycle. This is equivalent to T being less than Nt in the above formula, thereby adapting to the improvement of quantum manipulation efficiency of ion trap quantum computing.

[0060] In one embodiment of the present invention, each DC electrode of the DC source is allocated to a DAC output channel of each DAC daughter board, including: Determine the moment when the DC electrode voltage adjustment is the largest according to the working sequence of each DC electrode; Evenly distribute the DC electrodes that need voltage adjustment at this moment to each DAC sub-board, and obtain the number M of first DAC output channels of each DAC sub-board at this moment; m is determined according to the working sequence of each DC electrode; Adjust the distribution of each DC electrode in each DAC sub-board so that mM is less than the set threshold.

[0061] By counting the number of DC electrodes with voltage regulation at each timing node according to a preset resolution, the moment with the largest number of DC electrode voltage regulation can be determined.

[0062] The maximum number m is determined according to the working timing of each DC electrode, that is, the number of first DAC output channels at each timing node is counted, thereby obtaining the maximum number m of first DAC output channels of each sub-board.

[0063] The smaller the threshold is set, the better. The ideal situation is to make mM reach 0 or the minimum. If M is not an integer, it needs to be rounded up - that is, if M is 30.2, it needs to be rounded up to 31.

[0064] When m or M exceeds a set threshold, part of the DC electrodes allocated on the corresponding DAC sub-board may be reallocated to other DAC sub-boards with smaller m or M values.

[0065] The above system includes a system clock chip, and the refresh cycle is generated based on a local clock signal provided by the system clock chip; The FPGA motherboard controls the local clock signal and the external clock signal to be coherent.

[0066] The following embodiments describe how an FPGA motherboard controls the coherence of a local clock signal and an external clock signal.

[0067] In one embodiment of the present invention, a clock control system is provided. Figure 3 , FPGA motherboard, synchronous sampling source and system clock chip for quantum measurement and control. The FPGA motherboard includes a time interval measurement module and a PID control module; System clock chip, used to provide local clock signal to the time interval measurement module; A synchronous sampling source, used for providing a measurement clock signal to the time interval measurement module; a time interval measurement module, configured to obtain frequency and / or phase information of an external clock signal and a local clock signal based on a measurement clock signal; A PID control module, configured to output a clock adjustment signal based on frequency and / or phase information of an external clock signal and a local clock signal; The system clock chip is further configured to adjust the frequency and / or phase of the local clock signal according to the clock adjustment signal.

[0068] The quantum measurement and control process includes multi-channel DC source control based on ion trap quantum computing. The FPGA motherboard is used to output the output parameters of each channel of the DC source. The system also includes a DAC daughterboard for executing the output parameters. The local clock signal is used to control the timing of the output parameters of each channel of the DC source.

[0069] Figure 3 In the figure, FPGA refers to the FPGA motherboard, which is connected to the DAC daughterboard through the motherboard connector. The motherboard connector also connects to the power supply.

[0070] A clock signal is a periodically changing electrical signal that can be expressed as alternating high and low levels. In the above system, the local clock signal and the measurement clock signal are clock signals provided by the system clock chip and the synchronous sampling source, respectively.

[0071] The refresh period is set to be smaller than the shortest change interval of the output parameters in each channel of the DC source.

[0072] The external clock signal refers to the clock signal of the ion trap monitoring or signal detection related system.

[0073] When a measurement clock signal and a local clock signal are obtained, the phase information can include the phase difference between the two. This phase difference reflects the timing deviation between the local and measurement clock signals. The phase difference between the two clock signals can be measured using Digital Dual-Mixing Time-to-Digital Converter (DDDMTD). DDMTD utilizes fully digital processing, enabling algorithms such as Kalman filtering to be implemented on an FPGA motherboard to suppress burst noise. DDMTD supports real-time phase adjustment at the nanosecond level, such as temperature drift compensation. DDMTD can simultaneously measure the phase difference of multiple clocks, enabling cluster device synchronization. Therefore, this architecture is particularly suitable for boards in quantum manipulation systems.

[0074] The phase difference can be specifically obtained by calculating the delay time of the local clock signal edge relative to the measured clock signal. Once the phase difference is obtained, the frequency of the local clock signal can be derived based on the phase difference and the frequency of the measured clock signal. In this embodiment, the synchronous sampling source can be configured to output a fixed-frequency clock signal, thereby calculating the frequency and / or phase information of the local clock signal and the frequency and / or phase information of the external clock signal using a unified standard.

[0075] The calculation method of the frequency and phase information of the external clock signal is similar to that of the frequency and phase information of the local clock signal. The only difference is the replacement of the names of the external clock signal and the local clock signal.

[0076] Figure 3 This is a schematic diagram of the overall structure of the FPGA motherboard in the solution provided by an embodiment of the present invention, wherein the synchronous sampling source directly outputs a measurement clock signal to the time interval measurement module.

[0077] The system also includes a frequency synthesizer that outputs an external clock signal to the time interval measurement module. The frequency synthesizer is used to receive and adjust the external clock signal to make it have the same frequency as the local clock signal, thereby outputting an external clock signal with the same frequency as the local clock signal.

[0078] A frequency synthesizer can generate a clock signal with a target frequency through PLL (Phase-Locked Loop) feedback regulation or DDS (Direct Digital Synthesizer) phase accumulation. By setting the target frequency to the frequency of the local clock signal, an external clock signal with the same frequency as the local clock signal can be output.

[0079] The core of DDMTD is to measure the phase difference between two clocks using a dual-mixer structure. However, this technology requires that the two input signals have strictly identical frequencies. If the external clock signal and the local clock signal have different frequencies, mixing will produce a difference frequency signal, making it impossible to directly quantify the phase difference. A frequency synthesizer converts the external clock to the local clock frequency domain—that is, to the same frequency—so that the two signals meet the phase difference detection requirements.

[0080] Figure 3 The PID in the figure represents the PID control module. According to the requirements of quantum measurement and control, if the local clock signal needs to be adjusted to be in phase with the external clock signal, the phase information of the external clock signal and the local clock signal is used. Specifically, the phase difference between the local clock signal and the external clock signal can be calculated through the phase information of the external clock signal and the phase information of the local clock signal. The clock adjustment signal is a PID control signal output according to the phase difference. By constructing a PID formula of the phase difference and the output and performing parameter adjustment to control the relationship between the output and the phase difference, the PID control signal is obtained, and then the PID control signal is converted into a reference clock signal.

[0081] Alternatively, if the local clock signal needs to be adjusted to have the same frequency and phase as the external clock signal, the phase information of the external clock signal and the local clock signal, as well as the frequency of the external clock signal and the local clock signal are used as inputs for PID control, thereby outputting a PID control signal.

[0082] In this way, the two clock signals can have the same frequency and a constant phase difference, or the two clock signals can have different frequencies and the change in phase difference conforms to a trigonometric function relationship or other function relationship, thereby achieving coherence between the local clock signal and the external clock signal.

[0083] The system clock chip can choose a high-performance clock generator chip such as LMK04828 or HMC7044. By setting up an additional system clock chip, it is avoided to develop a module that provides a local clock signal on the FPGA motherboard, thereby reducing development costs.

[0084] In the above embodiment, the specific implementation of the PID control module controlling the system clock chip is as follows: the PID control module outputs a PID control signal as a clock adjustment signal to control the voltage-controlled crystal oscillator. Figure 3 , the clock control system further includes: a second DAC and a voltage-controlled crystal oscillator; The voltage-controlled crystal oscillator is used to provide a reference clock signal for the system clock chip to control the system clock chip to adjust the frequency and / or phase of the local clock signal; The second DAC is used to convert the clock adjustment signal into an analog signal to control the voltage-controlled crystal oscillator to output a reference clock signal.

[0085] The second described in the second DAC is only used to distinguish it from the DAC sub-board in the aforementioned embodiment, so as to indicate that it is a different DAC device.

[0086] The frequency and / or phase information of the local clock signal output by the system clock chip is controlled by a voltage-controlled crystal oscillator, which is in turn controlled by a clock adjustment signal. Since the voltage-controlled crystal oscillator is controlled by an analog signal, and the PID control module, as part of the FPGA, outputs a digital signal, a DAC is required to convert the digital signal into an analog signal.

[0087] In one embodiment of the present invention, the clock control system further comprises a first crystal oscillator; The first crystal oscillator is used to provide a system configuration clock signal to the FPGA motherboard, so that the FPGA motherboard starts running and establishes an SPI connection with the system clock chip to obtain a local clock signal.

[0088] The FPGA circuit board refers to the FPGA motherboard in the above-mentioned embodiments. The system configuration clock signal is a clock signal with a preset frequency. Providing the system configuration clock signal to the FPGA circuit board and providing the same system configuration clock signal to the system clock chip allows the FPGA circuit board and the system clock chip to communicate with each other according to consistent timing.

[0089] The clock control system includes a synchronous sampling source and a first crystal oscillator. The reason for setting up independent clock signal sources is that the DDMTD achieves high-precision alignment by measuring the phase difference between the two clocks. If the first crystal oscillator is used directly as the sampling clock, internal logic noise in the first crystal oscillator, such as power supply jitter and cross-clock domain interference, will contaminate the measurement results and degrade phase noise. Setting up an independent synchronous sampling source prevents FPGA digital noise from entering the measurement chain. Furthermore, the first crystal oscillator, which serves as the system configuration clock, has a large clock path delay and is susceptible to temperature and voltage drift, making it unable to meet the DDMTD's stringent sampling clock phase consistency requirements.

[0090] In one embodiment of the present invention, the clock control system further includes a DDR (Double Data Rate Synchronous Dynamic Random Access Memory) for storing quantum measurement and control instructions received by the communication module; The system clock chip is also used to provide a local clock signal to the DDR so that the DDR performs data processing operations based on the local clock signal.

[0091] In one embodiment, the clock control system further comprises: FLASH used to store system firmware. After the system is powered on, the system firmware is loaded from FLASH to the FPGA motherboard; The clock control system also includes an EEPROM for storing the version number and factory number of the software and hardware.

[0092] like Figure 3 As shown, the FPGA motherboard is connected to FLASH (flash memory), DDR, and EEPROM (Electrically Erasable Programmable Read-Only Memory). FLASH can be NAND FLASH (Not AND Flash, a flash memory with a NAND logic gate array structure), used as a large-capacity storage device. DDR can be any RAM (Random Access Memory) device, used as a system operation cache. EEPROM can be any ROM device or NOR FLASH (or NOR flash memory with a NOR logic gate array structure), used as a system firmware device. Specifically, FLASH can store system firmware, which is loaded from FLASH to the FPGA motherboard after the system is powered on. DDR can store the timing information for sending the output voltage of the multi-channel DC source.

[0093] The instructions issued by DDR storage directly serve quantum computing tasks. The DDR controller uses the local clock signal provided by the system clock chip for control, ensuring that the data read and write operations of DDR are synchronized with the quantum measurement and control core. Using the same clock domain can ensure low-latency synchronization of instruction reading and quantum measurement and control, avoiding data errors or performance bottlenecks caused by clock switching, and reducing the timing risks brought by cross-clock domains; it also simplifies the data path design inside the FPGA, such as the depth control of the FIFO buffer, thereby improving the overall efficiency of the system.

[0094] In one embodiment, the local clock signal provided by the system clock chip includes a parallel coherent measurement signal, a system global signal, and a DDR control signal; The coherent measurement signal is provided to the time interval measurement module; The system's global signals are used to control quantum measurement and control operations; DDR control signals are used to provide DDR.

[0095] Figure 3 In the example, the system clock chip provides four line connections, among which the SPI connection is used to connect to the FPGA. The measurement line sends a coherent measurement signal to measure whether the local clock signal is coherent with the external clock signal. If not, the PID control module is used to adjust the local clock signal until coherence is achieved as shown in the above embodiment. The Global connection represents the system global signal.

[0096] The coherent measurement signal is parallel and isolated from other signals, so that the measurement process can be as free from interference from other signals as possible.

[0097] DDR stands for DDR control signal, which is used to: Output processing operations performed by the DDR interface, including read / write operations, require strict alignment of the clock and data. Due to path delay differences, the global clock signal cannot directly meet the setup / hold time requirements of the DDR interface, and its phase must be independently adjusted through a dedicated clock network. The DDR clock duty cycle must be close to 50%, but the global clock may cause waveform distortion due to load changes during long-distance transmission. In contrast, providing a separate local clock signal can reduce such distortion by setting up a local clock buffer (such as BUFR). In addition, the independent DDR clock path can reduce crosstalk from high-speed switching signals on the global clock network, improving system stability.

[0098] In one embodiment of the present invention, the clock control system further includes a communication module; The first crystal oscillator is also used to provide a system configuration clock signal to the communication module.

[0099] The communication module includes an Ethernet port and a serial transceiver connected to the Ethernet port based on a communication protocol, and a system configuration clock signal is provided to the serial transceiver.

[0100] The communication module can be Figure 3 The serial transceiver and Ethernet port communicate based on the SGMII (Serial Gigabit Media Independent Interface) communication protocol.

[0101] The system configures the clock for SPI connections and Ethernet serial transceiver-to-physical layer operations, which are lower-priority or asynchronous communication tasks. Because data communication typically has a low correlation with the timing of DC power supply output operations, and the clock signal provided by the crystal oscillator does not require coherent adjustment, its frequency and phase are relatively stable, ensuring stable and smooth data communication.

[0102] like Figure 3 ,The first crystal oscillator divides the system configuration clock signal into two ,paths through the clock distribution module, one path is provided to the FPGA motherboard and ,the other path is provided to the serial transceiver.

[0103] Corresponding to the above system embodiment, an embodiment of the present invention further provides a multi-channel DC source asynchronous writing and synchronous refreshing method, see Figure 4, applied to an FPGA motherboard of a multi-channel DC source asynchronous writing and synchronous refreshing system, the method includes steps S401-S402.

[0104] S401: writing output parameters to each DAC sub-board, and controlling the DAC output channel of each DAC sub-board to receive the output parameters before the start time of the next refresh cycle; S402: Sending a refresh instruction to each DAC sub-board in parallel at the start time, so that after each DAC sub-board receives the refresh instruction, it controls the DAC output channel of the DAC sub-board to execute the received output parameter.

[0105] Among them, all operating timings of all DAC output channels have a lowest common denominator, and the lowest common denominator is equal to X times the refresh period, where X is a positive integer greater than or equal to 1.

[0106] In one embodiment of the present invention, an ion trap quantum computing DC electrode system is also provided, comprising the multi-channel DC source asynchronous writing and synchronous refreshing system of any of the above embodiments.

[0107] In one embodiment of the present invention, an ion trap quantum computing system is provided, comprising the multi-channel DC source asynchronous writing and synchronous refreshing system according to any one of the above embodiments.

[0108] It should be noted that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic device), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0109] It should be understood that various components of the present invention may be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods may be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof may be used: a discrete logic circuit having logic gate circuits for implementing logic functions on data signals, an application-specific integrated circuit having suitable combinational logic gate circuits, a programmable gate array (PGA), a field-programmable gate array (FPGA), etc.

[0110] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0111] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0112] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0113] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0114] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0115] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A multi-channel DC source asynchronous writing and synchronous refreshing system, characterized in that: The system includes an FPGA motherboard for outputting output parameters of each channel of a DC source, and at least two DAC daughterboards for executing the output parameters; each DAC daughterboard is provided with a plurality of DAC output channels; The FPGA motherboard is used to write output parameters to each DAC daughter board and control the DAC output channel of each DAC daughter board to receive the output parameters before the start time of the next refresh cycle; The FPGA motherboard is further configured to send a refresh instruction to each DAC daughter board in parallel at the start time; After receiving the refresh instruction, each DAC sub-board controls the DAC output channel of the DAC sub-board to execute the received output parameter; All operating timings of all DAC output channels have a lowest common denominator, where the lowest common denominator is equal to X times the refresh period, where X is a positive integer greater than or equal to 1.

2. The system according to claim 1, wherein: The refresh cycle meets the following setting conditions: the FPGA motherboard writes output parameters to each DAC daughter board in parallel.

3. The system according to claim 2, characterized in that The refresh cycle meets the following setting conditions: The maximum number of DAC output channels on each DAC daughter board is N, the time for the FPGA mother board to write output parameters to each DAC output channel is t, and the refresh period is T.

4. The system according to claim 2, wherein: Writing output parameters to each DAC sub-board in parallel includes: For each DAC daughter board, determining whether a historical output parameter received by each DAC output channel of the DAC daughter board is different from the output parameter; If there is a first DAC output channel whose output parameter is different from the historical output parameter, the output parameter is written to the first DAC output channel.

5. The system according to claim 4, characterized in that The refresh cycle meets the following setting conditions: The maximum number of the first DAC output channels in each DAC daughter board is m, the time for the FPGA mother board to write output parameters to each DAC output channel is t, and the refresh period is T.

6. The system according to claim 5, characterized in that The DC electrodes of the DC source are grouped according to the voltage regulation frequency, and the DC electrodes included in each group are evenly distributed to the DAC output channels of each DAC sub-board.

7. The system according to claim 5, characterized in that Each DC electrode of the DC source is distributed to a DAC output channel of each DAC sub-board, including: Determine the moment when the DC electrode voltage adjustment is the largest according to the working sequence of each DC electrode; Evenly distribute the DC electrodes that need voltage adjustment at the moment to each DAC sub-board, and obtain the number M of the first DAC output channels of each DAC sub-board at the moment; m is determined according to the working sequence of each DC electrode; Adjust the distribution of each DC electrode in each DAC sub-board so that mM is less than the set threshold.

8. The system according to claim 1, wherein: Each DAC daughter board is also equipped with a voltage reference chip.

9. The system according to claim 1, wherein: There is wiring of equal length between the FPGA motherboard and the DAC modules of each DAC daughter board, and there is wiring of equal length between each DAC output channel of each DAC daughter board and the DC electrode of the DC source corresponding to the DAC output channel; wherein, the DAC output channel of each DAC daughter board is arranged in the DAC module of the DAC daughter board.

10. The system according to claim 1, wherein: The refresh period is set to be less than or equal to 100 μs.

11. The system according to any one of claims 1 to 10, characterized in that The system includes a system clock chip, and the refresh cycle is generated based on a local clock signal provided by the system clock chip; The FPGA motherboard controls the local clock signal and the external clock signal to be coherent.

12. A multi-channel DC source asynchronous writing and synchronous refreshing method, characterized in that: An FPGA motherboard applied to a multi-channel DC source asynchronous writing and synchronous refreshing system, the method comprising: Writing output parameters to each DAC sub-board, and controlling the DAC output channel of each DAC sub-board to receive the output parameters before the start time of the next refresh cycle; Sending a refresh instruction to each DAC sub-board in parallel at the start time, so that after each DAC sub-board receives the refresh instruction, it controls the DAC output channel of the DAC sub-board to execute the received output parameter; All operating timings of all DAC output channels have a lowest common denominator, where the lowest common denominator is equal to X times the refresh period, where X is a positive integer greater than or equal to 1.

13. An ion trap quantum computing DC electrode system, characterized in that: A multi-channel DC source asynchronous writing and synchronous refreshing system comprising any one of claims 1-11.

14. An ion trap quantum computing system, characterized in that: A multi-channel DC source asynchronous writing and synchronous refreshing system comprising any one of claims 1-11.

Images